Skip to content

A
AIDA-2020 TLU - Hardware
Commit a648eb8d authored by David Cussans's avatar David Cussans
Browse files
Options

Comitting updated schematics for fmc vc . Adding a diagram illustrating… 

Comitting updated schematics for fmc vc . Adding a diagram illustrating coincidence logic. Adding simulation scripts
parent 5ab3f84e
Show whitespace changes
Inline Side-by-side
Showing with 66517 additions and 54262 deletions
Cadence/adw/shoppingCart.xml
View file @ a648eb8d
......@@ -56,4 +56,38 @@
<property name="PACK_TYPE" value="SC88"/>
<property name="TYPE" value="PRTR5V0U4Y"/>
</component>
<component cell="con19p" library="cnconnector" partname="CON19P" partno="HDMI-19-01-X-SM" quantity="1" >
<property name="TYPE" value="HDMI-19-01-X-SM"/>
</component>
<component cell="common_mode_line_filter" library="cndiscrete" partname="COMMON_MODE_LINE_FILTER" partno="744231091" quantity="1" >
<property name="PACK_TYPE" value="4312"/>
<property name="TYPE" value="744231091"/>
<property name="VALUE" value="90ohm"/>
</component>
<component cell="res_array_x4" library="cnpassive" partname="RES_ARRAY_X4" partno="TC164-FR-##47RL" quantity="1" >
<property name="PACK_TYPE" value="1206_TC164"/>
<property name="TOL" value="1%"/>
<property name="VALUE" value="47"/>
</component>
<component cell="capn4i" library="cnpassive" partname="CAPN4I" partno="GNM214B11C105MA01D" quantity="1" >
<property name="DIELECTRIC" value="X5R"/>
<property name="TYPE" value="GNM21"/>
<property name="VALUE" value="1uF"/>
<property name="VOLTAGE" value="16V"/>
</component>
<component cell="tps786xx" library="cnlinear" partname="TPS786XX" partno="TPS78633DCQ" quantity="1" >
<property name="PACK_TYPE" value="SOT223"/>
<property name="TYPE" value="TPS78633DCQ"/>
</component>
<component cell="plemo2ci" library="cnconnector" partname="PLEMO2CI" partno="EPG.00.302.NLN" quantity="1" >
<property name="TYPE" value="EPG.00.302.NLN"/>
</component>
<component cell="24aa025e48" library="cnmemory" partname="24AA025E48" partno="24AA025E48T-I/SN" quantity="1" >
<property name="PACK_TYPE" value="SOIC"/>
<property name="TYPE" value="24AA025E48T-I/SN"/>
</component>
<component cell="zener" library="cndiscrete" partname="ZENER" partno="BZT52-C3V6" quantity="1" >
<property name="PACK_TYPE" value="SOD123-CA"/>
<property name="TYPE" value="BZT52-C3V6"/>
</component>
</sc:shoppingCart>
Cadence/fmc_tlu_diode_clamp_b.cpm 0 → 100644
View file @ a648eb8d
{ Machine generated file created by SPI }
{ Last modified was 15:25:40 Wednesday, May 18, 2016 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
START_GLOBAL
view_pcb './worklib/fmc_tlu_diode_clamp_b/physical'
design_name 'fmc_tlu_diode_clamp_b'
design_library 'fmc_tlu_v1_lib'
library 'fmc_tlu_v1_lib' 'bris_cds_analogue' 'bris_cds_connectors' 'bris_cds_logic' 'bris_cds_memory' 'bris_cds_special' 'bris_cds_standard' 'bris_cds_switches' 'cnconnector' 'cninterface' 'cnpower' 'cnlinear' 'cnpassive' 'cndiscrete' 'standard' 'cds_analogue' 'cn100e' 'cn74lv' 'cn74tiac' 'cn75als' 'cncmos' 'cnfast' 'cnmemory' 'uob_hep_pc036a_lib' 'cds_connectors' 'cds_special' 'cnmech' 'cnspecial'
temp_dir 'temp'
cpm_version '16.3'
ppt '$BRIS_CDSLIB/cds_analogue/cds_analogue.ptf' '$BRIS_CDSLIB/cds_connectors/cds_connectors.ptf' '$BRIS_CDSLIB/cds_logic/cds_logic.ptf' '$BRIS_CDSLIB/cds_pld/cds_pld.ptf' '$BRIS_CDSLIB/cds_special/cds_special.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnconnector.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cndiscrete.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnpassive.ptf'
cdsprop_file ''
physical_path './worklib/fmc_tlu_diode_clamp_b/physical'
trapezoidal_angle_in_degree '90.000000'
session_name 'ProjectMgr8446'
END_GLOBAL
START_CONCEPTHDL
LOGIC_GRID_TOGGLE 'ON'
LOGIC_GRID_SIZE '0.0500'
SYMBOL_GRID_TOGGLE 'ON'
DOC_GRID_TOGGLE 'ON'
DOC_GRID_SIZE '0.0500'
CHECK_VOLTAGE_ON_HDL 'OFF'
PLOT_FIT_TO_PAGE 'ON'
PAPER_SIZE '9'
PAPER_ORIENTATION '2'
PAPER_SOURCE '15'
WPLOTTER_NAME 'Generic PostScript Printer'
PLOTTER_FACILITY 'DEVICE'
PLOT_EDGE_TO_EDGE 'ON'
END_CONCEPTHDL
START_PKGRXL
regenerate_physical_net_name 'OFF'
electrical_constraints 'ON'
overwrite_constraints 'OFF'
GEN_SUBDESIGN
force_subdesign 'fmc_tlu_cfd' 'fmc_tlu_vsupply5v'
END_PKGRXL
START_DESIGNSYNC
replace_symbol '0'
etch_removal 'NO'
ignore_fixed 'NO'
create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'fmc_tlu_v1a_66_gloss4a.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'NO'
END_DESIGNSYNC
START_BOMHDL
last_output_file './worklib/fmc_tlu_toplevel_b/bom/fmc_tlu_v1a.csv'
last_template_file '/projects/HEP_Instrumentation/cad/tools/cadence_templates/spreadsheet-format.bom'
last_standard_option '1'
last_what_to_output '0'
last_variant_file ''
last_ss_delimiter 'Colon :'
use_filters '0'
last_callout_file ''
last_variant ''
END_BOMHDL
START_PDF
CURRENTPDFVIEWER '0'
CURRENTPDFVIEWERPATH 'Default'
END_PDF
START_CONSTRAINT_MGR
EDIT_PHYSICAL_SPACING_CONSTRAINTS 'ON'
END_CONSTRAINT_MGR
Cadence/fmc_tlu_v1c.cpm
View file @ a648eb8d
{ Machine generated file created by SPI }
{ Last modified was 14:45:25 Thursday, April 21, 2016 }
{ Last modified was 15:16:35 Friday, May 20, 2016 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
......@@ -40,6 +40,7 @@ electrical_constraints 'ON'
overwrite_constraints 'OFF'
GEN_SUBDESIGN
force_subdesign 'fmc_tlu_cfd' 'fmc_tlu_vsupply5v'
f2b_overwrite_constraints 'ON'
END_PKGRXL
START_DESIGNSYNC
......@@ -50,10 +51,11 @@ create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'fmc_tlu_v1a_66_gloss4a.brd'
last_board_file 'fmc_tlu_v1c_67.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'NO'
show_report 'NO'
END_DESIGNSYNC
START_BOMHDL
......
Cadence/worklib/fmc_tlu_diode_clamp_b/sch_1/fmc_tlu_diode_clamp_b.dcf
View file @ a648eb8d
......@@ -7,7 +7,7 @@
( 16.6 )
)
( revisionNumber
( logicalViewRevNum 2 )
( logicalViewRevNum 4 )
( physicalViewRevNum 0 )
( otherViewRevNum 0 )
)
......@@ -544,32 +544,38 @@
( objectFlag fObjectAlias )
( objectStatus "page1_gnd_signal" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig0"
( objectStatus "sig0" )
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig4_p"
( objectStatus "sig4_p" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig1"
( objectStatus "sig1" )
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig4_n"
( objectStatus "sig4_n" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig2"
( objectStatus "sig2" )
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):vclamp"
( objectStatus "vclamp" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig3"
( objectStatus "sig3" )
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig0_n"
( objectStatus "sig0_n" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig4"
( objectStatus "sig4" )
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig0_p"
( objectStatus "sig0_p" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig5"
( objectStatus "sig5" )
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig1_n"
( objectStatus "sig1_n" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig6"
( objectStatus "sig6" )
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig1_p"
( objectStatus "sig1_p" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig7"
( objectStatus "sig7" )
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig2_n"
( objectStatus "sig2_n" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):vclamp"
( objectStatus "vclamp" )
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig2_p"
( objectStatus "sig2_p" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig3_n"
( objectStatus "sig3_n" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig3_p"
( objectStatus "sig3_p" )
)
( gate "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):page1_i9"
( attribute "CDS_LIB" "cnpassive"
......@@ -702,6 +708,145 @@
( pin "vcc"
)
)
( gate "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):page1_i58"
( attribute "CDS_LIB" "cnpassive"
( Origin gPackager )
)
( attribute "PACK_TYPE" "0603"
( Origin gFrontEnd )
)
( attribute "PHYS_PAGE" "1"
( Origin gFrontEnd )
)
( attribute "ROT" "1"
( Origin gFrontEnd )
)
( attribute "SIZE" "1"
( Origin gFrontEnd )
)
( attribute "VALUE" "100NF"
( Origin gFrontEnd )
)
( attribute "VER" "1"
( Origin gFrontEnd )
)
( attribute "VOLTAGE" "16V"
( Units "uVoltage" "V" 1.000000)
( Origin gFrontEnd )
)
( attribute "XY" "(2575,-1875)"
( Origin gFrontEnd )
)
( attribute "CHIPS_PART_NAME" "CAPCERSMDCL2"
( Origin gPackager )
)
( attribute "CDS_PART_NAME" "CAPCERSMDCL2_0603-100NF,16V"
( Origin gPackager )
)
( objectStatus "PAGE1_I58" )
( pin "a(0)"
( attribute "PN" "#"
( Origin gPackager )
)
)
( pin "b(0)"
( attribute "PN" "#"
( Origin gPackager )
)
)
)
( gate "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):page1_i70"
( attribute "CDS_LIB" "cndiscrete"
( Origin gPackager )
)
( attribute "LOCATION" "D3"
( Origin gPackager )
)
( attribute "PACK_TYPE" "SOT23"
( Origin gFrontEnd )
)
( attribute "PHYS_PAGE" "1"
( Origin gFrontEnd )
)
( attribute "ROT" "0"
( Origin gFrontEnd )
)
( attribute "TYPE" "USBLC6-2SC6"
( Origin gFrontEnd )
)
( attribute "VER" "1"
( Origin gFrontEnd )
)
( attribute "XY" "(5025,175)"
( Origin gFrontEnd )
)
( attribute "CHIPS_PART_NAME" "USBLC6-2"
( Origin gPackager )
)
( attribute "CDS_PART_NAME" "USBLC6-2SC6"
( Origin gPackager )
)
( objectStatus "PAGE1_I70" )
( pin "gnd"
)
( pin "\i/o1\(0)"
)
( pin "\i/o1\(1)"
)
( pin "\i/o2\(0)"
)
( pin "\i/o2\(1)"
)
( pin "vbus"
)
)
( gate "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):page1_i67"
( attribute "CDS_LIB" "cnpassive"
( Origin gPackager )
)
( attribute "PACK_TYPE" "0603"
( Origin gFrontEnd )
)
( attribute "PHYS_PAGE" "1"
( Origin gFrontEnd )
)
( attribute "ROT" "1"
( Origin gFrontEnd )
)
( attribute "SIZE" "1"
( Origin gFrontEnd )
)
( attribute "VALUE" "100NF"
( Origin gFrontEnd )
)
( attribute "VER" "1"
( Origin gFrontEnd )
)
( attribute "VOLTAGE" "16V"
( Units "uVoltage" "V" 1.000000)
( Origin gFrontEnd )
)
( attribute "XY" "(5975,0)"
( Origin gFrontEnd )
)
( attribute "CHIPS_PART_NAME" "CAPCERSMDCL2"
( Origin gPackager )
)
( attribute "CDS_PART_NAME" "CAPCERSMDCL2_0603-100NF,16V"
( Origin gPackager )
)
( objectStatus "PAGE1_I67" )
( pin "a(0)"
( attribute "PN" "#"
( Origin gPackager )
)
)
( pin "b(0)"
( attribute "PN" "#"
( Origin gPackager )
)
)
)
)
)
)
Cadence/worklib/fmc_tlu_diode_clamp_b/sch_1/fmc_tlu_diode_clamp_b.dcf,1
View file @ a648eb8d
......@@ -7,7 +7,7 @@
( 16.6 )
)
( revisionNumber
( logicalViewRevNum 0 )
( logicalViewRevNum 1 )
( physicalViewRevNum 0 )
( otherViewRevNum 0 )
)
......
Cadence/worklib/fmc_tlu_diode_clamp_b/sch_1/fmc_tlu_diode_clamp_b.dcf,2
View file @ a648eb8d
......@@ -7,7 +7,7 @@
( 16.6 )
)
( revisionNumber
( logicalViewRevNum 1 )
( logicalViewRevNum 2 )
( physicalViewRevNum 0 )
( otherViewRevNum 0 )
)
......@@ -536,6 +536,172 @@
( allRules )
( design "fmc_tlu_diode_clamp_b"
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):gnd_signal"
( alias ( signalRef "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):page1_gnd_signal") )
( objectStatus "gnd_signal" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):page1_gnd_signal"
( objectFlag fObjectAlias )
( objectStatus "page1_gnd_signal" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig0"
( objectStatus "sig0" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig1"
( objectStatus "sig1" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig2"
( objectStatus "sig2" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig3"
( objectStatus "sig3" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig4"
( objectStatus "sig4" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig5"
( objectStatus "sig5" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig6"
( objectStatus "sig6" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):sig7"
( objectStatus "sig7" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):vclamp"
( objectStatus "vclamp" )
)
( gate "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):page1_i9"
( attribute "CDS_LIB" "cnpassive"
( Origin gPackager )
)
( attribute "PACK_TYPE" "0603"
( Origin gFrontEnd )
)
( attribute "PHYS_PAGE" "1"
( Origin gFrontEnd )
)
( attribute "ROT" "1"
( Origin gFrontEnd )
)
( attribute "SIZE" "1"
( Origin gFrontEnd )
)
( attribute "VALUE" "100NF"
( Origin gFrontEnd )
)
( attribute "VER" "1"
( Origin gFrontEnd )
)
( attribute "VOLTAGE" "16V"
( Units "uVoltage" "V" 1.000000)
( Origin gFrontEnd )
)
( attribute "XY" "(2175,-1875)"
( Origin gFrontEnd )
)
( attribute "CHIPS_PART_NAME" "CAPCERSMDCL2"
( Origin gPackager )
)
( attribute "CDS_PART_NAME" "CAPCERSMDCL2_0603-100NF,16V"
( Origin gPackager )
)
( objectStatus "PAGE1_I9" )
( pin "a(0)"
( attribute "PN" "#"
( Origin gPackager )
)
)
( pin "b(0)"
( attribute "PN" "#"
( Origin gPackager )
)
)
)
( gate "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):page1_i55"
( attribute "CDS_LIB" "cndiscrete"
( Origin gPackager )
)
( attribute "PACK_TYPE" "SC88"
( Origin gFrontEnd )
)
( attribute "PHYS_PAGE" "1"
( Origin gFrontEnd )
)
( attribute "ROT" "0"
( Origin gFrontEnd )
)
( attribute "TYPE" "PRTR5V0U4Y"
( Origin gFrontEnd )
)
( attribute "VER" "1"
( Origin gFrontEnd )
)
( attribute "XY" "(1025,-250)"
( Origin gFrontEnd )
)
( attribute "CHIPS_PART_NAME" "PRTR5V0U4Y"
( Origin gPackager )
)
( attribute "CDS_PART_NAME" "PRTR5V0U4Y"
( Origin gPackager )
)
( objectStatus "PAGE1_I55" )
( pin "esd1"
)
( pin "esd2"
)
( pin "esd3"
)
( pin "esd4"
)
( pin "gnd"
)
( pin "vcc"
)
)
( gate "@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1):page1_i56"
( attribute "CDS_LIB" "cndiscrete"
( Origin gPackager )
)
( attribute "PACK_TYPE" "SC88"
( Origin gFrontEnd )
)
( attribute "PHYS_PAGE" "1"
( Origin gFrontEnd )
)
( attribute "ROT" "0"
( Origin gFrontEnd )
)
( attribute "TYPE" "PRTR5V0U4Y"
( Origin gFrontEnd )
)
( attribute "VER" "1"
( Origin gFrontEnd )
)
( attribute "XY" "(1050,-2450)"
( Origin gFrontEnd )
)
( attribute "CHIPS_PART_NAME" "PRTR5V0U4Y"
( Origin gPackager )
)
( attribute "CDS_PART_NAME" "PRTR5V0U4Y"
( Origin gPackager )
)
( objectStatus "PAGE1_I56" )
( pin "esd1"
)
( pin "esd2"
)
( pin "esd3"
)
( pin "esd4"
)
( pin "gnd"
)
( pin "vcc"
)
)
)
)
)
Cadence/worklib/fmc_tlu_diode_clamp_b/sch_1/fmc_tlu_diode_clamp_b.xcon
View file @ a648eb8d
......@@ -5,15 +5,15 @@
<schemaVersion>16.6</schemaVersion>
<creatorTool>concepthdl</creatorTool>
<modifierTool>concepthdl</modifierTool>
<modificationTime>2016-04-22T09:05:35</modificationTime>
<modificationTime>2016-05-18T10:06:29</modificationTime>
<savedLibrary>fmc_tlu_v1_lib</savedLibrary>
</header>
<designs>
<design schemaType="nameBased" name="fmc_tlu_diode_clamp_b" view="sch_1">
<lastids>
<instanceid>3</instanceid>
<netid>11</netid>
<insttermid>14</insttermid>
<instanceid>7</instanceid>
<netid>21</netid>
<insttermid>28</insttermid>
</lastids>
<cells>
<cell>
......@@ -80,6 +80,40 @@
</term>
</terms>
</cell>
<cell>
<id>S4</id>
<library>cndiscrete</library>
<name>usblc6-2</name>
<view>sym_1</view>
<parameters>
</parameters>
<terms>
<term>
<id>T39</id>
<name>gnd</name>
<direction>input</direction>
</term>
<term>
<id>T40</id>
<name>i/o1</name>
<direction>inout</direction>
<msb>1</msb>
<lsb>0</lsb>
</term>
<term>
<id>T41</id>
<name>i/o2</name>
<direction>inout</direction>
<msb>1</msb>
<lsb>0</lsb>
</term>
<term>
<id>T42</id>
<name>vbus</name>
<direction>input</direction>
</term>
</terms>
</cell>
</cells>
<nets>
<net>
......@@ -87,58 +121,70 @@
<name>page1_gnd_signal</name>
</net>
<net>
<id>N3</id>
<name>sig0</name>
<id>N11</id>
<name>vclamp</name>
<scope>interface</scope>
<direction>inout</direction>
</net>
<net>
<id>N12</id>
<name>sig0_n</name>
<scope>interface</scope>
<direction>input</direction>
</net>
<net>
<id>N4</id>
<name>sig1</name>
<id>N13</id>
<name>sig0_p</name>
<scope>interface</scope>
<direction>input</direction>
</net>
<net>
<id>N5</id>
<name>sig2</name>
<id>N14</id>
<name>sig1_n</name>
<scope>interface</scope>
<direction>input</direction>
</net>
<net>
<id>N6</id>
<name>sig3</name>
<id>N15</id>
<name>sig1_p</name>
<scope>interface</scope>
<direction>input</direction>
</net>
<net>
<id>N7</id>
<name>sig4</name>
<id>N16</id>
<name>sig2_n</name>
<scope>interface</scope>
<direction>input</direction>
</net>
<net>
<id>N8</id>
<name>sig5</name>
<id>N17</id>
<name>sig2_p</name>
<scope>interface</scope>
<direction>input</direction>
</net>
<net>
<id>N9</id>
<name>sig6</name>
<id>N18</id>
<name>sig3_n</name>
<scope>interface</scope>
<direction>input</direction>
</net>
<net>
<id>N10</id>
<name>sig7</name>
<id>N19</id>
<name>sig3_p</name>
<scope>interface</scope>
<direction>input</direction>
</net>
<net>
<id>N11</id>
<name>vclamp</name>
<id>N20</id>
<name>sig4_n</name>
<scope>interface</scope>
<direction>inout</direction>
<direction>input</direction>
</net>
<net>
<id>N21</id>
<name>sig4_p</name>
<scope>interface</scope>
<direction>input</direction>
</net>
<net>
<id>N1</id>
......@@ -212,28 +258,28 @@
<id>M3</id>
<termid>T13</termid>
<connections>
<connection net="N4" />
<connection net="N12" />
</connections>
</pin>
<pin>
<id>M4</id>
<termid>T14</termid>
<connections>
<connection net="N5" />
<connection net="N15" />
</connections>
</pin>
<pin>
<id>M5</id>
<termid>T15</termid>
<connections>
<connection net="N6" />
<connection net="N14" />
</connections>
</pin>
<pin>
<id>M6</id>
<termid>T16</termid>
<connections>
<connection net="N3" />
<connection net="N13" />
</connections>
</pin>
<pin>
......@@ -275,28 +321,28 @@
<id>M9</id>
<termid>T13</termid>
<connections>
<connection net="N8" />
<connection net="N16" />
</connections>
</pin>
<pin>
<id>M10</id>
<termid>T14</termid>
<connections>
<connection net="N9" />
<connection net="N19" />
</connections>
</pin>
<pin>
<id>M11</id>
<termid>T15</termid>
<connections>
<connection net="N10" />
<connection net="N18" />
</connections>
</pin>
<pin>
<id>M12</id>
<termid>T16</termid>
<connections>
<connection net="N7" />
<connection net="N17" />
</connections>
</pin>
<pin>
......@@ -323,6 +369,139 @@
<portinterfaces>
</portinterfaces>
</instance>
<instance>
<id>I4</id>
<cellid>S2</cellid>
<name>page1_i58</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
<pin>
<id>M15</id>
<termid>T11</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N1" />
</connections>
</pin>
<pin>
<id>M16</id>
<termid>T12</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N11" />
</connections>
</pin>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
<instance>
<id>I6</id>
<cellid>S2</cellid>
<name>page1_i67</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
<pin>
<id>M23</id>
<termid>T11</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N1" />
</connections>
</pin>
<pin>
<id>M24</id>
<termid>T12</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N11" />
</connections>
</pin>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
<instance>
<id>I7</id>
<cellid>S4</cellid>
<name>page1_i70</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
<pin>
<id>M25</id>
<termid>T39</termid>
<connections>
<connection net="N1" />
</connections>
</pin>
<pin>
<id>M26</id>
<termid>T40</termid>
<msb>1</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="1" pinlsb="1" net="N21" />
<connection pinmsb="0" pinlsb="0" net="N21" />
</connections>
</pin>
<pin>
<id>M27</id>
<termid>T41</termid>
<msb>1</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="1" pinlsb="1" net="N20" />
<connection pinmsb="0" pinlsb="0" net="N20" />
</connections>
</pin>
<pin>
<id>M28</id>
<termid>T42</termid>
<connections>
<connection net="N11" />
</connections>
</pin>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
</instances>
<templateresolutions>
</templateresolutions>
......@@ -337,49 +516,61 @@
<scope>global</scope>
</pageScope>
</netScope>
<netScope ref="sig0">
<netScope ref="sig0_n">
<pageScope number="1">
<scope>interface</scope>
<direction>input</direction>
</pageScope>
</netScope>
<netScope ref="sig0_p">
<pageScope number="1">
<scope>interface</scope>
<direction>input</direction>
</pageScope>
</netScope>
<netScope ref="sig1_n">
<pageScope number="1">
<scope>interface</scope>
<direction>input</direction>
</pageScope>
</netScope>
<netScope ref="sig1">
<netScope ref="sig1_p">
<pageScope number="1">
<scope>interface</scope>
<direction>input</direction>
</pageScope>
</netScope>
<netScope ref="sig2">
<netScope ref="sig2_n">
<pageScope number="1">
<scope>interface</scope>
<direction>input</direction>
</pageScope>
</netScope>
<netScope ref="sig3">
<netScope ref="sig2_p">
<pageScope number="1">
<scope>interface</scope>
<direction>input</direction>
</pageScope>
</netScope>
<netScope ref="sig4">
<netScope ref="sig3_n">
<pageScope number="1">
<scope>interface</scope>
<direction>input</direction>
</pageScope>
</netScope>
<netScope ref="sig5">
<netScope ref="sig3_p">
<pageScope number="1">
<scope>interface</scope>
<direction>input</direction>
</pageScope>
</netScope>
<netScope ref="sig6">
<netScope ref="sig4_n">
<pageScope number="1">
<scope>interface</scope>
<direction>input</direction>
</pageScope>
</netScope>
<netScope ref="sig7">
<netScope ref="sig4_p">
<pageScope number="1">
<scope>interface</scope>
<direction>input</direction>
......@@ -398,20 +589,25 @@
<errorStatus>false</errorStatus>
<nets>
<net ref="gnd_signal"></net>
<net ref="sig0"></net>
<net ref="sig1"></net>
<net ref="sig2"></net>
<net ref="sig3"></net>
<net ref="sig4"></net>
<net ref="sig5"></net>
<net ref="sig6"></net>
<net ref="sig7"></net>
<net ref="sig0_n"></net>
<net ref="sig0_p"></net>
<net ref="sig1_n"></net>
<net ref="sig1_p"></net>
<net ref="sig2_n"></net>
<net ref="sig2_p"></net>
<net ref="sig3_n"></net>
<net ref="sig3_p"></net>
<net ref="sig4_n"></net>
<net ref="sig4_p"></net>
<net ref="vclamp"></net>
</nets>
<instances>
<instance ref="i9"></instance>
<instance ref="i55"></instance>
<instance ref="i56"></instance>
<instance ref="i58"></instance>
<instance ref="i67"></instance>
<instance ref="i70"></instance>
</instances>
</page>
</pages>
......
Cadence/worklib/fmc_tlu_diode_clamp_b/sch_1/page1.cpc
View file @ a648eb8d
......@@ -43,6 +43,30 @@
#ISCELL
standard gnd_signal *
page1_i57
#CELL
cnpassive capcersmdcl2 *
page1_i58
#ISCELL
standard gnd_signal *
page1_i59
#ISCELL
standard inport *
page1_i64
#ISCELL
standard inport *
page1_i65
#CELL
cnpassive capcersmdcl2 *
page1_i67
#ISCELL
standard gnd_signal *
page1_i68
#CELL
cndiscrete usblc6-2 *
page1_i70
#ISCELL
standard gnd_signal *
page1_i71
#CELL
cnpassive capcersmdcl2 *
page1_i9
Cadence/worklib/fmc_tlu_diode_clamp_b/sch_1/page1.csa
View file @ a648eb8d
......@@ -9,228 +9,228 @@ SET PROP_DISPLAY VALUE;
SET PAGE_NUMBER P1;
FORCEADD INPORT..1
(-850 550);
FORCEPROP 2 LAST CDS_LIB standard
FORCEPROP 1 LAST OFFPAGE TRUE
J 0
(-850 550);
DISPLAY INVISIBLE (-850 550);
FORCEPROP 1 LAST PATH I24
(-525 425);
DISPLAY 0.872340 (-525 425);
DISPLAY INVISIBLE (-525 425);
FORCEPROP 1 LASTPIN (-800 550) HDL_PORT IN
J 0
(-875 600);
DISPLAY 0.872340 (-875 600);
PAINT PINK (-875 600);
DISPLAY INVISIBLE (-875 600);
(-525 425);
DISPLAY 0.872340 (-525 425);
DISPLAY INVISIBLE (-525 425);
FORCEPROP 1 LASTPIN (-800 550) VHDL_PORT IN
J 0
(-785 480);
DISPLAY 0.872340 (-785 480);
PAINT PINK (-785 480);
DISPLAY INVISIBLE (-785 480);
FORCEPROP 1 LASTPIN (-800 550) HDL_PORT IN
FORCEPROP 1 LAST PATH I24
J 0
(-525 425);
DISPLAY 0.872340 (-525 425);
DISPLAY INVISIBLE (-525 425);
FORCEPROP 1 LAST OFFPAGE TRUE
(-875 600);
DISPLAY 0.872340 (-875 600);
PAINT PINK (-875 600);
DISPLAY INVISIBLE (-875 600);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(-525 425);
DISPLAY 0.872340 (-525 425);
DISPLAY INVISIBLE (-525 425);
(-850 550);
DISPLAY INVISIBLE (-850 550);
FORCEADD INPORT..1
(-850 0);
FORCEPROP 2 LAST CDS_LIB standard
FORCEPROP 1 LAST OFFPAGE TRUE
J 0
(-850 0);
DISPLAY INVISIBLE (-850 0);
FORCEPROP 1 LAST PATH I25
(-525 -125);
DISPLAY 0.872340 (-525 -125);
DISPLAY INVISIBLE (-525 -125);
FORCEPROP 1 LASTPIN (-800 0) HDL_PORT IN
J 0
(-875 50);
DISPLAY 0.872340 (-875 50);
PAINT PINK (-875 50);
DISPLAY INVISIBLE (-875 50);
(-525 -125);
DISPLAY 0.872340 (-525 -125);
DISPLAY INVISIBLE (-525 -125);
FORCEPROP 1 LASTPIN (-800 0) VHDL_PORT IN
J 0
(-785 -70);
DISPLAY 0.872340 (-785 -70);
PAINT PINK (-785 -70);
DISPLAY INVISIBLE (-785 -70);
FORCEPROP 1 LASTPIN (-800 0) HDL_PORT IN
FORCEPROP 1 LAST PATH I25
J 0
(-525 -125);
DISPLAY 0.872340 (-525 -125);
DISPLAY INVISIBLE (-525 -125);
FORCEPROP 1 LAST OFFPAGE TRUE
(-875 50);
DISPLAY 0.872340 (-875 50);
PAINT PINK (-875 50);
DISPLAY INVISIBLE (-875 50);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(-525 -125);
DISPLAY 0.872340 (-525 -125);
DISPLAY INVISIBLE (-525 -125);
(-850 0);
DISPLAY INVISIBLE (-850 0);
FORCEADD INPORT..1
(-850 -550);
FORCEPROP 2 LAST CDS_LIB standard
FORCEPROP 1 LAST OFFPAGE TRUE
J 0
(-850 -550);
DISPLAY INVISIBLE (-850 -550);
FORCEPROP 1 LAST PATH I26
(-525 -675);
DISPLAY 0.872340 (-525 -675);
DISPLAY INVISIBLE (-525 -675);
FORCEPROP 1 LASTPIN (-800 -550) HDL_PORT IN
J 0
(-875 -500);
DISPLAY 0.872340 (-875 -500);
PAINT PINK (-875 -500);
DISPLAY INVISIBLE (-875 -500);
(-525 -675);
DISPLAY 0.872340 (-525 -675);
DISPLAY INVISIBLE (-525 -675);
FORCEPROP 1 LASTPIN (-800 -550) VHDL_PORT IN
J 0
(-785 -620);
DISPLAY 0.872340 (-785 -620);
PAINT PINK (-785 -620);
DISPLAY INVISIBLE (-785 -620);
FORCEPROP 1 LASTPIN (-800 -550) HDL_PORT IN
FORCEPROP 1 LAST PATH I26
J 0
(-525 -675);
DISPLAY 0.872340 (-525 -675);
DISPLAY INVISIBLE (-525 -675);
FORCEPROP 1 LAST OFFPAGE TRUE
(-875 -500);
DISPLAY 0.872340 (-875 -500);
PAINT PINK (-875 -500);
DISPLAY INVISIBLE (-875 -500);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(-525 -675);
DISPLAY 0.872340 (-525 -675);
DISPLAY INVISIBLE (-525 -675);
(-850 -550);
DISPLAY INVISIBLE (-850 -550);
FORCEADD INPORT..1
(-850 -1100);
FORCEPROP 2 LAST CDS_LIB standard
FORCEPROP 1 LAST OFFPAGE TRUE
J 0
(-850 -1100);
DISPLAY INVISIBLE (-850 -1100);
FORCEPROP 1 LAST PATH I27
(-525 -1225);
DISPLAY 0.872340 (-525 -1225);
DISPLAY INVISIBLE (-525 -1225);
FORCEPROP 1 LASTPIN (-800 -1100) HDL_PORT IN
J 0
(-875 -1050);
DISPLAY 0.872340 (-875 -1050);
PAINT PINK (-875 -1050);
DISPLAY INVISIBLE (-875 -1050);
(-525 -1225);
DISPLAY 0.872340 (-525 -1225);
DISPLAY INVISIBLE (-525 -1225);
FORCEPROP 1 LASTPIN (-800 -1100) VHDL_PORT IN
J 0
(-785 -1170);
DISPLAY 0.872340 (-785 -1170);
PAINT PINK (-785 -1170);
DISPLAY INVISIBLE (-785 -1170);
FORCEPROP 1 LASTPIN (-800 -1100) HDL_PORT IN
FORCEPROP 1 LAST PATH I27
J 0
(-525 -1225);
DISPLAY 0.872340 (-525 -1225);
DISPLAY INVISIBLE (-525 -1225);
FORCEPROP 1 LAST OFFPAGE TRUE
(-875 -1050);
DISPLAY 0.872340 (-875 -1050);
PAINT PINK (-875 -1050);
DISPLAY INVISIBLE (-875 -1050);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(-525 -1225);
DISPLAY 0.872340 (-525 -1225);
DISPLAY INVISIBLE (-525 -1225);
(-850 -1100);
DISPLAY INVISIBLE (-850 -1100);
FORCEADD INPORT..1
(-850 -1650);
FORCEPROP 2 LAST CDS_LIB standard
FORCEPROP 1 LAST OFFPAGE TRUE
J 0
(-850 -1650);
DISPLAY INVISIBLE (-850 -1650);
FORCEPROP 1 LAST PATH I28
(-525 -1775);
DISPLAY 0.872340 (-525 -1775);
DISPLAY INVISIBLE (-525 -1775);
FORCEPROP 1 LASTPIN (-800 -1650) HDL_PORT IN
J 0
(-875 -1600);
DISPLAY 0.872340 (-875 -1600);
PAINT PINK (-875 -1600);
DISPLAY INVISIBLE (-875 -1600);
(-525 -1775);
DISPLAY 0.872340 (-525 -1775);
DISPLAY INVISIBLE (-525 -1775);
FORCEPROP 1 LASTPIN (-800 -1650) VHDL_PORT IN
J 0
(-785 -1720);
DISPLAY 0.872340 (-785 -1720);
PAINT PINK (-785 -1720);
DISPLAY INVISIBLE (-785 -1720);
FORCEPROP 1 LASTPIN (-800 -1650) HDL_PORT IN
FORCEPROP 1 LAST PATH I28
J 0
(-525 -1775);
DISPLAY 0.872340 (-525 -1775);
DISPLAY INVISIBLE (-525 -1775);
FORCEPROP 1 LAST OFFPAGE TRUE
(-875 -1600);
DISPLAY 0.872340 (-875 -1600);
PAINT PINK (-875 -1600);
DISPLAY INVISIBLE (-875 -1600);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(-525 -1775);
DISPLAY 0.872340 (-525 -1775);
DISPLAY INVISIBLE (-525 -1775);
(-850 -1650);
DISPLAY INVISIBLE (-850 -1650);
FORCEADD INPORT..1
(-850 -2200);
FORCEPROP 2 LAST CDS_LIB standard
FORCEPROP 1 LAST OFFPAGE TRUE
J 0
(-850 -2200);
DISPLAY INVISIBLE (-850 -2200);
FORCEPROP 1 LAST PATH I29
(-525 -2325);
DISPLAY 0.872340 (-525 -2325);
DISPLAY INVISIBLE (-525 -2325);
FORCEPROP 1 LASTPIN (-800 -2200) HDL_PORT IN
J 0
(-875 -2150);
DISPLAY 0.872340 (-875 -2150);
PAINT PINK (-875 -2150);
DISPLAY INVISIBLE (-875 -2150);
(-525 -2325);
DISPLAY 0.872340 (-525 -2325);
DISPLAY INVISIBLE (-525 -2325);
FORCEPROP 1 LASTPIN (-800 -2200) VHDL_PORT IN
J 0
(-785 -2270);
DISPLAY 0.872340 (-785 -2270);
PAINT PINK (-785 -2270);
DISPLAY INVISIBLE (-785 -2270);
FORCEPROP 1 LASTPIN (-800 -2200) HDL_PORT IN
FORCEPROP 1 LAST PATH I29
J 0
(-525 -2325);
DISPLAY 0.872340 (-525 -2325);
DISPLAY INVISIBLE (-525 -2325);
FORCEPROP 1 LAST OFFPAGE TRUE
(-875 -2150);
DISPLAY 0.872340 (-875 -2150);
PAINT PINK (-875 -2150);
DISPLAY INVISIBLE (-875 -2150);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(-525 -2325);
DISPLAY 0.872340 (-525 -2325);
DISPLAY INVISIBLE (-525 -2325);
(-850 -2200);
DISPLAY INVISIBLE (-850 -2200);
FORCEADD INPORT..1
(-850 -2750);
FORCEPROP 2 LAST CDS_LIB standard
FORCEPROP 1 LAST OFFPAGE TRUE
J 0
(-850 -2750);
DISPLAY INVISIBLE (-850 -2750);
FORCEPROP 1 LAST PATH I30
(-525 -2875);
DISPLAY 0.872340 (-525 -2875);
DISPLAY INVISIBLE (-525 -2875);
FORCEPROP 1 LASTPIN (-800 -2750) HDL_PORT IN
J 0
(-875 -2700);
DISPLAY 0.872340 (-875 -2700);
PAINT PINK (-875 -2700);
DISPLAY INVISIBLE (-875 -2700);
(-525 -2875);
DISPLAY 0.872340 (-525 -2875);
DISPLAY INVISIBLE (-525 -2875);
FORCEPROP 1 LASTPIN (-800 -2750) VHDL_PORT IN
J 0
(-785 -2820);
DISPLAY 0.872340 (-785 -2820);
PAINT PINK (-785 -2820);
DISPLAY INVISIBLE (-785 -2820);
FORCEPROP 1 LASTPIN (-800 -2750) HDL_PORT IN
FORCEPROP 1 LAST PATH I30
J 0
(-525 -2875);
DISPLAY 0.872340 (-525 -2875);
DISPLAY INVISIBLE (-525 -2875);
FORCEPROP 1 LAST OFFPAGE TRUE
(-875 -2700);
DISPLAY 0.872340 (-875 -2700);
PAINT PINK (-875 -2700);
DISPLAY INVISIBLE (-875 -2700);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(-525 -2875);
DISPLAY 0.872340 (-525 -2875);
DISPLAY INVISIBLE (-525 -2875);
(-850 -2750);
DISPLAY INVISIBLE (-850 -2750);
FORCEADD INPORT..1
(-850 -3300);
FORCEPROP 2 LAST CDS_LIB standard
FORCEPROP 1 LAST OFFPAGE TRUE
J 0
(-850 -3300);
DISPLAY INVISIBLE (-850 -3300);
FORCEPROP 1 LAST PATH I31
(-525 -3425);
DISPLAY 0.872340 (-525 -3425);
DISPLAY INVISIBLE (-525 -3425);
FORCEPROP 1 LASTPIN (-800 -3300) HDL_PORT IN
J 0
(-875 -3250);
DISPLAY 0.872340 (-875 -3250);
PAINT PINK (-875 -3250);
DISPLAY INVISIBLE (-875 -3250);
(-525 -3425);
DISPLAY 0.872340 (-525 -3425);
DISPLAY INVISIBLE (-525 -3425);
FORCEPROP 1 LASTPIN (-800 -3300) VHDL_PORT IN
J 0
(-785 -3370);
DISPLAY 0.872340 (-785 -3370);
PAINT PINK (-785 -3370);
DISPLAY INVISIBLE (-785 -3370);
FORCEPROP 1 LASTPIN (-800 -3300) HDL_PORT IN
FORCEPROP 1 LAST PATH I31
J 0
(-525 -3425);
DISPLAY 0.872340 (-525 -3425);
DISPLAY INVISIBLE (-525 -3425);
FORCEPROP 1 LAST OFFPAGE TRUE
(-875 -3250);
DISPLAY 0.872340 (-875 -3250);
PAINT PINK (-875 -3250);
DISPLAY INVISIBLE (-875 -3250);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(-525 -3425);
DISPLAY 0.872340 (-525 -3425);
DISPLAY INVISIBLE (-525 -3425);
(-850 -3300);
DISPLAY INVISIBLE (-850 -3300);
FORCEADD GND_SIGNAL..1
(2125 -2175);
FORCEPROP 3 LASTPIN (2175 -2125) SIG_NAME GND_SIGNAL\g
......@@ -239,24 +239,24 @@ J 0
DISPLAY 0.659574 (2185 -2115);
PAINT MONO (2185 -2115);
DISPLAY INVISIBLE (2185 -2115);
FORCEPROP 1 LAST HDL_POWER GND_SIGNAL
FORCEPROP 2 LAST PATH I42
J 0
(2125 -2125);
DISPLAY 0.978723 (2125 -2125);
DISPLAY INVISIBLE (2125 -2125);
(2075 -2075);
DISPLAY 1.021277 (2075 -2075);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(2125 -2175);
DISPLAY INVISIBLE (2125 -2175);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(2125 -2025);
DISPLAY 0.978723 (2125 -2025);
DISPLAY INVISIBLE (2125 -2025);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(2125 -2175);
DISPLAY INVISIBLE (2125 -2175);
FORCEPROP 2 LAST PATH I42
FORCEPROP 1 LAST HDL_POWER GND_SIGNAL
J 0
(2075 -2075);
DISPLAY 1.021277 (2075 -2075);
(2125 -2125);
DISPLAY 0.978723 (2125 -2125);
DISPLAY INVISIBLE (2125 -2125);
FORCEADD GND_SIGNAL..1
(575 -525);
FORCEPROP 3 LASTPIN (625 -475) SIG_NAME GND_SIGNAL\g
......@@ -265,6 +265,10 @@ J 0
DISPLAY 0.659574 (635 -465);
PAINT MONO (635 -465);
DISPLAY INVISIBLE (635 -465);
FORCEPROP 2 LAST PATH I53
J 0
(525 -450);
DISPLAY 1.021277 (525 -450);
FORCEPROP 1 LAST HDL_POWER GND_SIGNAL
J 0
(575 -475);
......@@ -279,88 +283,84 @@ FORCEPROP 2 LAST CDS_LIB standard
J 0
(575 -525);
DISPLAY INVISIBLE (575 -525);
FORCEPROP 2 LAST PATH I53
J 0
(525 -450);
DISPLAY 1.021277 (525 -450);
FORCEADD IOPORT..1
(2850 -1450);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(2850 -1450);
DISPLAY INVISIBLE (2850 -1450);
FORCEPROP 1 LAST PATH I54
J 0
(2850 -1400);
DISPLAY 0.872340 (2850 -1400);
PAINT PINK (2850 -1400);
DISPLAY INVISIBLE (2850 -1400);
FORCEPROP 1 LAST OFFPAGE TRUE
FORCEPROP 1 LASTPIN (2800 -1450) VHDL_PORT INOUT
J 0
(2875 -1350);
DISPLAY INVISIBLE (2875 -1350);
(2815 -1520);
DISPLAY 0.872340 (2815 -1520);
PAINT MONO (2815 -1520);
DISPLAY INVISIBLE (2815 -1520);
FORCEPROP 1 LASTPIN (2800 -1450) HDL_PORT INOUT
J 0
(3175 -1575);
DISPLAY 0.872340 (3175 -1575);
PAINT MONO (3175 -1575);
DISPLAY INVISIBLE (3175 -1575);
FORCEPROP 1 LASTPIN (2800 -1450) VHDL_PORT INOUT
FORCEPROP 1 LAST OFFPAGE TRUE
J 0
(2815 -1520);
DISPLAY 0.872340 (2815 -1520);
PAINT MONO (2815 -1520);
DISPLAY INVISIBLE (2815 -1520);
FORCEADD PRTR5V0U4Y..1
(1025 -250);
FORCEPROP 1 LAST $LOCATION D?
J 1
(1030 18);
DISPLAY 0.723404 (1030 18);
PAINT WHITE (1030 18);
FORCEPROP 1 LAST PATH I55
J 1
(1030 -267);
DISPLAY 0.723404 (1030 -267);
PAINT WHITE (1030 -267);
DISPLAY INVISIBLE (1030 -267);
FORCEPROP 2 LAST CDS_LIB cndiscrete
(2875 -1350);
DISPLAY INVISIBLE (2875 -1350);
FORCEPROP 1 LAST PATH I54
J 0
(2850 -1400);
DISPLAY 0.872340 (2850 -1400);
PAINT PINK (2850 -1400);
DISPLAY INVISIBLE (2850 -1400);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(2850 -1450);
DISPLAY INVISIBLE (2850 -1450);
FORCEADD PRTR5V0U4Y..1
(1025 -250);
DISPLAY INVISIBLE (1025 -250);
FORCEPROP 1 LAST TYPE PRTR5V0U4Y
J 1
(1030 -22);
DISPLAY 0.723404 (1030 -22);
PAINT WHITE (1030 -22);
FORCEPROP 1 LAST $LOCATION D?
J 1
(1030 18);
DISPLAY 0.723404 (1030 18);
PAINT WHITE (1030 18);
FORCEPROP 1 LAST PACK_TYPE SC88
J 1
(1030 -498);
DISPLAY 0.723404 (1030 -498);
PAINT WHITE (1030 -498);
FORCEPROP 2 LAST CDS_LIB cndiscrete
J 0
(1025 -250);
DISPLAY INVISIBLE (1025 -250);
FORCEPROP 1 LAST PATH I55
J 1
(1030 -267);
DISPLAY 0.723404 (1030 -267);
PAINT WHITE (1030 -267);
DISPLAY INVISIBLE (1030 -267);
FORCEADD PRTR5V0U4Y..1
(1050 -2450);
FORCEPROP 1 LAST PATH I56
J 1
(1055 -2467);
DISPLAY 0.723404 (1055 -2467);
PAINT WHITE (1055 -2467);
DISPLAY INVISIBLE (1055 -2467);
FORCEPROP 1 LAST $LOCATION D?
J 1
(1055 -2182);
DISPLAY 0.723404 (1055 -2182);
PAINT WHITE (1055 -2182);
FORCEPROP 1 LAST PACK_TYPE SC88
J 1
(1055 -2698);
DISPLAY 0.723404 (1055 -2698);
PAINT WHITE (1055 -2698);
FORCEPROP 1 LAST TYPE PRTR5V0U4Y
J 1
(1055 -2222);
DISPLAY 0.723404 (1055 -2222);
PAINT WHITE (1055 -2222);
FORCEPROP 1 LAST PACK_TYPE SC88
FORCEPROP 1 LAST PATH I56
J 1
(1055 -2698);
DISPLAY 0.723404 (1055 -2698);
PAINT WHITE (1055 -2698);
(1055 -2467);
DISPLAY 0.723404 (1055 -2467);
PAINT WHITE (1055 -2467);
DISPLAY INVISIBLE (1055 -2467);
FORCEPROP 2 LAST CDS_LIB cndiscrete
J 0
(1050 -2450);
......@@ -377,51 +377,305 @@ FORCEPROP 2 LAST PATH I57
J 0
(550 -2650);
DISPLAY 1.021277 (550 -2650);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(600 -2725);
DISPLAY INVISIBLE (600 -2725);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(600 -2575);
DISPLAY 0.978723 (600 -2575);
DISPLAY INVISIBLE (600 -2575);
FORCEPROP 1 LAST HDL_POWER GND_SIGNAL
J 0
(600 -2675);
DISPLAY 0.978723 (600 -2675);
DISPLAY INVISIBLE (600 -2675);
FORCEADD CAPCERSMDCL2..1
R 1
(2575 -1875);
FORCEPROP 1 LAST PATH I58
R 1
J 0
(2475 -1850);
DISPLAY 0.723404 (2475 -1850);
DISPLAY INVISIBLE (2475 -1850);
FORCEPROP 1 LAST VALUE 100NF
R 1
J 1
(2675 -1875);
DISPLAY 0.723404 (2675 -1875);
FORCEPROP 1 LAST VOLTAGE 16V
R 1
J 1
(2725 -1875);
DISPLAY 0.723404 (2725 -1875);
FORCEPROP 1 LAST $LOCATION C?
R 1
J 0
(2525 -1900);
DISPLAY 0.723404 (2525 -1900);
FORCEPROP 1 LAST SIZE 1
R 1
J 0
(2645 -1895);
DISPLAY 0.702128 (2645 -1895);
PAINT WHITE (2645 -1895);
DISPLAY INVISIBLE (2645 -1895);
FORCEPROP 2 LAST CDS_LIB cnpassive
J 0
(2575 -1875);
DISPLAY INVISIBLE (2575 -1875);
FORCEPROP 1 LAST PACK_TYPE 0603
R 1
J 1
(2775 -1875);
DISPLAY 0.723404 (2775 -1875);
DISPLAY INVISIBLE (2775 -1875);
FORCEPROP 1 LASTPIN (2575 -1975) $PN #
R 1
J 2
(2550 -1975);
DISPLAY 0.723404 (2550 -1975);
DISPLAY INVISIBLE (2550 -1975);
FORCEPROP 1 LASTPIN (2575 -1775) $PN #
R 1
J 0
(2550 -1775);
DISPLAY 0.723404 (2550 -1775);
DISPLAY INVISIBLE (2550 -1775);
FORCEADD GND_SIGNAL..1
(2525 -2175);
FORCEPROP 3 LASTPIN (2575 -2125) SIG_NAME GND_SIGNAL\g
J 0
(2585 -2115);
DISPLAY 0.659574 (2585 -2115);
PAINT MONO (2585 -2115);
DISPLAY INVISIBLE (2585 -2115);
FORCEPROP 2 LAST PATH I59
J 0
(2475 -2100);
DISPLAY 1.021277 (2475 -2100);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(2525 -2175);
DISPLAY INVISIBLE (2525 -2175);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(600 -2575);
DISPLAY 0.978723 (600 -2575);
DISPLAY INVISIBLE (600 -2575);
(2525 -2025);
DISPLAY 0.978723 (2525 -2025);
DISPLAY INVISIBLE (2525 -2025);
FORCEPROP 1 LAST HDL_POWER GND_SIGNAL
J 0
(2525 -2125);
DISPLAY 0.978723 (2525 -2125);
DISPLAY INVISIBLE (2525 -2125);
FORCEADD INPORT..1
(3200 275);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(600 -2725);
DISPLAY INVISIBLE (600 -2725);
(3200 275);
DISPLAY INVISIBLE (3200 275);
FORCEPROP 1 LASTPIN (3250 275) VHDL_PORT IN
J 0
(3265 205);
DISPLAY 0.872340 (3265 205);
PAINT PINK (3265 205);
DISPLAY INVISIBLE (3265 205);
FORCEPROP 1 LASTPIN (3250 275) HDL_PORT IN
J 0
(3525 150);
DISPLAY 0.872340 (3525 150);
DISPLAY INVISIBLE (3525 150);
FORCEPROP 1 LAST OFFPAGE TRUE
J 0
(3525 150);
DISPLAY 0.872340 (3525 150);
DISPLAY INVISIBLE (3525 150);
FORCEPROP 1 LAST PATH I64
J 0
(3175 325);
DISPLAY 0.872340 (3175 325);
PAINT PINK (3175 325);
DISPLAY INVISIBLE (3175 325);
FORCEADD INPORT..1
(3200 75);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(3200 75);
DISPLAY INVISIBLE (3200 75);
FORCEPROP 1 LASTPIN (3250 75) VHDL_PORT IN
J 0
(3265 5);
DISPLAY 0.872340 (3265 5);
PAINT PINK (3265 5);
DISPLAY INVISIBLE (3265 5);
FORCEPROP 1 LASTPIN (3250 75) HDL_PORT IN
J 0
(3525 -50);
DISPLAY 0.872340 (3525 -50);
DISPLAY INVISIBLE (3525 -50);
FORCEPROP 1 LAST OFFPAGE TRUE
J 0
(3525 -50);
DISPLAY 0.872340 (3525 -50);
DISPLAY INVISIBLE (3525 -50);
FORCEPROP 1 LAST PATH I65
J 0
(3175 125);
DISPLAY 0.872340 (3175 125);
PAINT PINK (3175 125);
DISPLAY INVISIBLE (3175 125);
FORCEADD CAPCERSMDCL2..1
R 1
(2175 -1875);
FORCEPROP 1 LASTPIN (2175 -1775) $PN #
(5975 0);
FORCEPROP 1 LASTPIN (5975 100) $PN #
R 1
J 0
(2150 -1775);
DISPLAY 0.723404 (2150 -1775);
DISPLAY INVISIBLE (2150 -1775);
FORCEPROP 1 LASTPIN (2175 -1975) $PN #
(5950 100);
DISPLAY 0.723404 (5950 100);
DISPLAY INVISIBLE (5950 100);
FORCEPROP 1 LASTPIN (5975 -100) $PN #
R 1
J 2
(2150 -1975);
DISPLAY 0.723404 (2150 -1975);
DISPLAY INVISIBLE (2150 -1975);
(5950 -100);
DISPLAY 0.723404 (5950 -100);
DISPLAY INVISIBLE (5950 -100);
FORCEPROP 1 LAST PACK_TYPE 0603
R 1
J 1
(2375 -1875);
DISPLAY 0.723404 (2375 -1875);
DISPLAY INVISIBLE (2375 -1875);
(6175 0);
DISPLAY 0.723404 (6175 0);
DISPLAY INVISIBLE (6175 0);
FORCEPROP 2 LAST CDS_LIB cnpassive
J 0
(5975 0);
DISPLAY INVISIBLE (5975 0);
FORCEPROP 1 LAST SIZE 1
R 1
J 0
(6045 -20);
DISPLAY 0.702128 (6045 -20);
PAINT WHITE (6045 -20);
DISPLAY INVISIBLE (6045 -20);
FORCEPROP 1 LAST $LOCATION C?
R 1
J 0
(5925 -25);
DISPLAY 0.723404 (5925 -25);
FORCEPROP 1 LAST VOLTAGE 16V
R 1
J 1
(6125 0);
DISPLAY 0.723404 (6125 0);
FORCEPROP 1 LAST VALUE 100NF
R 1
J 1
(6075 0);
DISPLAY 0.723404 (6075 0);
FORCEPROP 1 LAST PATH I67
R 1
J 0
(5875 25);
DISPLAY 0.723404 (5875 25);
DISPLAY INVISIBLE (5875 25);
FORCEADD GND_SIGNAL..1
(5925 -300);
FORCEPROP 3 LASTPIN (5975 -250) SIG_NAME GND_SIGNAL\g
J 0
(5985 -240);
DISPLAY 0.659574 (5985 -240);
PAINT MONO (5985 -240);
DISPLAY INVISIBLE (5985 -240);
FORCEPROP 1 LAST HDL_POWER GND_SIGNAL
J 0
(5925 -250);
DISPLAY 0.978723 (5925 -250);
DISPLAY INVISIBLE (5925 -250);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(5925 -150);
DISPLAY 0.978723 (5925 -150);
DISPLAY INVISIBLE (5925 -150);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(5925 -300);
DISPLAY INVISIBLE (5925 -300);
FORCEPROP 2 LAST PATH I68
J 0
(5875 -225);
DISPLAY 1.021277 (5875 -225);
FORCEADD USBLC6-2..1
(5025 175);
FORCEPROP 2 LAST CDS_LIB cndiscrete
J 0
(5025 175);
DISPLAY INVISIBLE (5025 175);
FORCEPROP 1 LAST $LOCATION D3
J 1
(5030 393);
DISPLAY 0.723404 (5030 393);
PAINT WHITE (5030 393);
FORCEPROP 1 LAST TYPE USBLC6-2SC6
J 1
(5030 338);
DISPLAY 0.723404 (5030 338);
PAINT WHITE (5030 338);
FORCEPROP 1 LAST PACK_TYPE SOT23
J 1
(5030 -23);
DISPLAY 0.723404 (5030 -23);
PAINT WHITE (5030 -23);
FORCEPROP 1 LAST PATH I70
J 1
(5030 158);
DISPLAY 0.723404 (5030 158);
PAINT WHITE (5030 158);
DISPLAY INVISIBLE (5030 158);
FORCEADD GND_SIGNAL..1
(4675 -75);
FORCEPROP 3 LASTPIN (4725 -25) SIG_NAME GND_SIGNAL\g
J 0
(4735 -15);
DISPLAY 0.659574 (4735 -15);
PAINT MONO (4735 -15);
DISPLAY INVISIBLE (4735 -15);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(4675 -75);
DISPLAY INVISIBLE (4675 -75);
FORCEPROP 1 LAST HDL_POWER GND_SIGNAL
J 0
(4675 -25);
DISPLAY 0.978723 (4675 -25);
DISPLAY INVISIBLE (4675 -25);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(4675 75);
DISPLAY 0.978723 (4675 75);
DISPLAY INVISIBLE (4675 75);
FORCEPROP 2 LAST PATH I71
J 0
(4625 0);
DISPLAY 1.021277 (4625 0);
FORCEADD CAPCERSMDCL2..1
R 1
(2175 -1875);
DISPLAY INVISIBLE (2175 -1875);
FORCEPROP 1 LAST PATH I9
FORCEPROP 1 LAST VALUE 100NF
R 1
J 1
(2275 -1875);
DISPLAY 0.723404 (2275 -1875);
FORCEPROP 1 LAST VOLTAGE 16V
R 1
J 1
(2325 -1875);
DISPLAY 0.723404 (2325 -1875);
FORCEPROP 1 LAST $LOCATION C?
R 1
J 0
(2075 -1850);
DISPLAY 0.723404 (2075 -1850);
DISPLAY INVISIBLE (2075 -1850);
(2125 -1900);
DISPLAY 0.723404 (2125 -1900);
FORCEPROP 1 LAST SIZE 1
R 1
J 0
......@@ -429,24 +683,37 @@ J 0
DISPLAY 0.702128 (2245 -1895);
PAINT WHITE (2245 -1895);
DISPLAY INVISIBLE (2245 -1895);
FORCEPROP 1 LAST $LOCATION C?
FORCEPROP 1 LAST PATH I9
R 1
J 0
(2125 -1900);
DISPLAY 0.723404 (2125 -1900);
FORCEPROP 1 LAST VOLTAGE 16V
(2075 -1850);
DISPLAY 0.723404 (2075 -1850);
DISPLAY INVISIBLE (2075 -1850);
FORCEPROP 2 LAST CDS_LIB cnpassive
J 0
(2175 -1875);
DISPLAY INVISIBLE (2175 -1875);
FORCEPROP 1 LAST PACK_TYPE 0603
R 1
J 1
(2325 -1875);
DISPLAY 0.723404 (2325 -1875);
FORCEPROP 1 LAST VALUE 100NF
(2375 -1875);
DISPLAY 0.723404 (2375 -1875);
DISPLAY INVISIBLE (2375 -1875);
FORCEPROP 1 LASTPIN (2175 -1975) $PN #
R 1
J 1
(2275 -1875);
DISPLAY 0.723404 (2275 -1875);
J 2
(2150 -1975);
DISPLAY 0.723404 (2150 -1975);
DISPLAY INVISIBLE (2150 -1975);
FORCEPROP 1 LASTPIN (2175 -1775) $PN #
R 1
J 0
(2150 -1775);
DISPLAY 0.723404 (2150 -1775);
DISPLAY INVISIBLE (2150 -1775);
FORCEADD A3-2000..1
(1500 350);
FORCEPROP 0 LAST CDS_CON_LAST_MODIFIED Fri Apr 22 09:05:35 2016
FORCEPROP 0 LAST CDS_CON_LAST_MODIFIED Wed May 18 10:06:29 2016
J 0
(3250 -2450);
DISPLAY INVISIBLE (3250 -2450);
......@@ -479,67 +746,103 @@ J 0
DISPLAY 0.553191 (6300 -5625);
PAINT AQUA (6300 -5625);
DISPLAY INVISIBLE (6300 -5625);
WIRE 16 -1 (2575 -2125)(2575 -1975);
WIRE 16 -1 (650 -2450)(650 -2675);
WIRE 16 -1 (650 -2450)(800 -2450);
WIRE 16 -1 (625 -250)(625 -475);
WIRE 16 -1 (625 -250)(775 -250);
WIRE 16 -1 (2175 -2125)(2175 -1975);
WIRE 16 -1 (1300 -2350)(1325 -2350);
WIRE 16 -1 (1325 -2350)(1325 -1650);
WIRE 16 -1 (-800 -1650)(1325 -1650);
FORCEPROP 2 LAST SIG_NAME SIG4
J 0
(-660 -1640);
DISPLAY 1.021277 (-660 -1640);
WIRE 16 -1 (1300 -2450)(1750 -2450);
WIRE 16 -1 (1275 -250)(1750 -250);
WIRE 16 -1 (1750 -250)(1750 -1450);
WIRE 16 -1 (1750 -2450)(1750 -1450);
WIRE 16 -1 (2800 -1450)(2175 -1450);
WIRE 16 -1 (2175 -1450)(1750 -1450);
WIRE 16 -1 (2175 -1775)(2175 -1450);
WIRE 16 -1 (5975 -250)(5975 -100);
WIRE 16 -1 (4725 175)(4725 -25);
WIRE 16 -1 (4775 175)(4725 175);
WIRE 16 -1 (5450 75)(5725 75);
WIRE 16 -1 (5275 75)(5450 75);
WIRE 16 -1 (5450 -200)(5450 75);
WIRE 16 -1 (4600 -200)(5450 -200);
WIRE 16 -1 (4775 75)(4600 75);
WIRE 16 -1 (4600 75)(4600 -200);
WIRE 16 -1 (4600 75)(3250 75);
FORCEPROP 2 LAST SIG_NAME SIG4_N
J 0
(3390 85);
DISPLAY 1.021277 (3390 85);
WIRE 16 -1 (5450 275)(5275 275);
WIRE 16 -1 (5725 275)(5450 275);
WIRE 16 -1 (5450 275)(5450 575);
WIRE 16 -1 (5450 575)(4600 575);
WIRE 16 -1 (4600 275)(3250 275);
FORCEPROP 2 LAST SIG_NAME SIG4_P
J 0
(3390 285);
DISPLAY 1.021277 (3390 285);
WIRE 16 -1 (4600 575)(4600 275);
WIRE 16 -1 (4775 275)(4600 275);
WIRE 16 -1 (5975 100)(5975 175);
WIRE 16 -1 (5975 175)(6300 175);
WIRE 16 -1 (5275 175)(5975 175);
FORCEPROP 2 LAST SIG_NAME VCLAMP
J 0
(2365 -1440);
DISPLAY 1.021277 (2365 -1440);
(5890 185);
DISPLAY 1.021277 (5890 185);
WIRE 16 -1 (1325 -2550)(1300 -2550);
WIRE 16 -1 (1325 -3300)(1325 -2550);
WIRE 16 -1 (1325 -3300)(-800 -3300);
FORCEPROP 2 LAST SIG_NAME SIG7
FORCEPROP 2 LAST SIG_NAME SIG3_N
J 0
(-660 -3290);
DISPLAY 1.021277 (-660 -3290);
WIRE 16 -1 (1300 -350)(1275 -350);
WIRE 16 -1 (1300 -1100)(1300 -350);
WIRE 16 -1 (-800 -1100)(1300 -1100);
FORCEPROP 2 LAST SIG_NAME SIG1_N
J 0
(-660 -1090);
DISPLAY 1.021277 (-660 -1090);
WIRE 16 -1 (5175 -350)(5150 -350);
WIRE 16 -1 (1275 -250)(1750 -250);
WIRE 16 -1 (1300 -2450)(1750 -2450);
WIRE 16 -1 (2800 -1450)(2575 -1450);
WIRE 16 -1 (2575 -1775)(2575 -1450);
WIRE 16 -1 (1750 -2450)(1750 -1450);
WIRE 16 -1 (1750 -250)(1750 -1450);
WIRE 16 -1 (2175 -1450)(1750 -1450);
WIRE 16 -1 (2575 -1450)(2175 -1450);
WIRE 16 -1 (2175 -1775)(2175 -1450);
FORCEPROP 2 LAST SIG_NAME VCLAMP
J 0
(2240 -1390);
DISPLAY 1.021277 (2240 -1390);
WIRE 16 -1 (250 -2550)(800 -2550);
WIRE 16 -1 (250 -2750)(-800 -2750);
FORCEPROP 2 LAST SIG_NAME SIG6
FORCEPROP 2 LAST SIG_NAME SIG3_P
J 0
(-660 -2740);
DISPLAY 1.021277 (-660 -2740);
WIRE 16 -1 (250 -2750)(250 -2550);
WIRE 16 -1 (250 -2350)(800 -2350);
WIRE 16 -1 (250 -2200)(-800 -2200);
FORCEPROP 2 LAST SIG_NAME SIG5
FORCEPROP 2 LAST SIG_NAME SIG2_N
J 0
(-660 -2190);
DISPLAY 1.021277 (-660 -2190);
WIRE 16 -1 (250 -2200)(250 -2350);
WIRE 16 -1 (1300 -350)(1275 -350);
WIRE 16 -1 (1300 -1100)(1300 -350);
WIRE 16 -1 (-800 -1100)(1300 -1100);
FORCEPROP 2 LAST SIG_NAME SIG3
WIRE 16 -1 (1300 -2350)(1325 -2350);
WIRE 16 -1 (1325 -2350)(1325 -1650);
WIRE 16 -1 (-800 -1650)(1325 -1650);
FORCEPROP 2 LAST SIG_NAME SIG2_P
J 0
(-660 -1090);
DISPLAY 1.021277 (-660 -1090);
(-660 -1640);
DISPLAY 1.021277 (-660 -1640);
WIRE 16 -1 (225 -350)(775 -350);
WIRE 16 -1 (225 -550)(-800 -550);
FORCEPROP 2 LAST SIG_NAME SIG2
FORCEPROP 2 LAST SIG_NAME SIG1_P
J 0
(-660 -540);
DISPLAY 1.021277 (-660 -540);
WIRE 16 -1 (225 -550)(225 -350);
WIRE 16 -1 (225 -150)(775 -150);
WIRE 16 -1 (225 0)(-800 0);
FORCEPROP 2 LAST SIG_NAME SIG1
FORCEPROP 2 LAST SIG_NAME SIG0_N
J 0
(-660 10);
DISPLAY 1.021277 (-660 10);
......@@ -547,20 +850,26 @@ WIRE 16 -1 (225 0)(225 -150);
WIRE 16 -1 (1275 -150)(1300 -150);
WIRE 16 -1 (1300 -150)(1300 550);
WIRE 16 -1 (-800 550)(1300 550);
FORCEPROP 2 LAST SIG_NAME SIG0
FORCEPROP 2 LAST SIG_NAME SIG0_P
J 0
(-660 560);
DISPLAY 1.021277 (-660 560);
DOT 1 (1750 -1450);
DOT 1 (5450 75);
DOT 1 (4600 75);
DOT 1 (4600 275);
DOT 1 (5450 275);
DOT 1 (5975 175);
DOT 1 (2575 -1450);
DOT 1 (2175 -1450);
FORCENOTE
LICENSED UNDER THE TAPR OPEN HARDWARE LICENSE (WWW.TAPR.ORG/OHL)
(4100 -3600) 0;
DISPLAY LEFT (4100 -3600);
DISPLAY 0.808511 (4100 -3600);
DOT 1 (1750 -1450);
FORCENOTE
11
(6200 -2850) 0;
DISPLAY LEFT (6200 -2850);
DISPLAY 1.021277 (6200 -2850);
FORCENOTE
LICENSED UNDER THE TAPR OPEN HARDWARE LICENSE (WWW.TAPR.ORG/OHL)
(4100 -3600) 0;
DISPLAY LEFT (4100 -3600);
DISPLAY 0.808511 (4100 -3600);
QUIT
Cadence/worklib/fmc_tlu_diode_clamp_b/sch_1/page1.csv
View file @ a648eb8d
......@@ -2,139 +2,181 @@ FILE_TYPE = CONNECTIVITY;
{Allegro Design Entry HDL 16.6-S055 (v16-6-112EP) 8/13/2015}
"PAGE_NUMBER" = 1;
0"NC";
1"GND_SIGNAL\g";
2"GND_SIGNAL\g";
3"GND_SIGNAL\g";
4"SIG4";
5"VCLAMP";
6"SIG7";
7"SIG6";
8"SIG5";
9"SIG3";
10"SIG2";
11"SIG1";
12"SIG0";
1"SIG4_N";
2"SIG4_P";
3"VCLAMP";
4"GND_SIGNAL\g";
5"GND_SIGNAL\g";
6"SIG3_N";
7"SIG1_N";
8"VCLAMP";
9"SIG3_P";
10"SIG2_N";
11"SIG2_P";
12"SIG1_P";
13"SIG0_N";
14"SIG0_P";
15"GND_SIGNAL\g";
16"GND_SIGNAL\g";
17"GND_SIGNAL\g";
18"GND_SIGNAL\g";
%"INPORT"
"1","(-850,550)","0","standard","I24";
;
CDS_LIB"standard"
OFFPAGE"TRUE";
OFFPAGE"TRUE"
CDS_LIB"standard";
"A"
VHDL_PORT"IN"
HDL_PORT"IN"12;
HDL_PORT"IN"
VHDL_PORT"IN"14;
%"INPORT"
"1","(-850,0)","0","standard","I25";
;
CDS_LIB"standard"
OFFPAGE"TRUE";
OFFPAGE"TRUE"
CDS_LIB"standard";
"A"
VHDL_PORT"IN"
HDL_PORT"IN"11;
HDL_PORT"IN"
VHDL_PORT"IN"13;
%"INPORT"
"1","(-850,-550)","0","standard","I26";
;
CDS_LIB"standard"
OFFPAGE"TRUE";
OFFPAGE"TRUE"
CDS_LIB"standard";
"A"
VHDL_PORT"IN"
HDL_PORT"IN"10;
HDL_PORT"IN"
VHDL_PORT"IN"12;
%"INPORT"
"1","(-850,-1100)","0","standard","I27";
;
CDS_LIB"standard"
OFFPAGE"TRUE";
OFFPAGE"TRUE"
CDS_LIB"standard";
"A"
VHDL_PORT"IN"
HDL_PORT"IN"9;
HDL_PORT"IN"
VHDL_PORT"IN"7;
%"INPORT"
"1","(-850,-1650)","0","standard","I28";
;
CDS_LIB"standard"
OFFPAGE"TRUE";
OFFPAGE"TRUE"
CDS_LIB"standard";
"A"
VHDL_PORT"IN"
HDL_PORT"IN"4;
HDL_PORT"IN"
VHDL_PORT"IN"11;
%"INPORT"
"1","(-850,-2200)","0","standard","I29";
;
CDS_LIB"standard"
OFFPAGE"TRUE";
OFFPAGE"TRUE"
CDS_LIB"standard";
"A"
VHDL_PORT"IN"
HDL_PORT"IN"8;
HDL_PORT"IN"
VHDL_PORT"IN"10;
%"INPORT"
"1","(-850,-2750)","0","standard","I30";
;
CDS_LIB"standard"
OFFPAGE"TRUE";
OFFPAGE"TRUE"
CDS_LIB"standard";
"A"
VHDL_PORT"IN"
HDL_PORT"IN"7;
HDL_PORT"IN"
VHDL_PORT"IN"9;
%"INPORT"
"1","(-850,-3300)","0","standard","I31";
;
CDS_LIB"standard"
OFFPAGE"TRUE";
OFFPAGE"TRUE"
CDS_LIB"standard";
"A"
VHDL_PORT"IN"
HDL_PORT"IN"6;
HDL_PORT"IN"
VHDL_PORT"IN"6;
%"GND_SIGNAL"
"1","(2125,-2175)","0","standard","I42";
;
HDL_POWER"GND_SIGNAL"
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"GND"3;
HDL_POWER"GND_SIGNAL";
"GND"16;
%"GND_SIGNAL"
"1","(575,-525)","0","standard","I53";
;
HDL_POWER"GND_SIGNAL"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"GND"2;
"GND"17;
%"IOPORT"
"1","(2850,-1450)","0","standard","I54";
;
CDS_LIB"standard"
OFFPAGE"TRUE";
OFFPAGE"TRUE"
CDS_LIB"standard";
"A"
HDL_PORT"INOUT"
VHDL_PORT"INOUT"5;
VHDL_PORT"INOUT"
HDL_PORT"INOUT"8;
%"PRTR5V0U4Y"
"1","(1025,-250)","0","cndiscrete","I55";
;
$LOCATION"D?"
CDS_LIB"cndiscrete"
TYPE"PRTR5V0U4Y"
PACK_TYPE"SC88";
"ESD4"12;
"ESD1"11;
"ESD2"10;
"GND"2;
"ESD3"9;
"VCC"5;
$LOCATION"D?"
PACK_TYPE"SC88"
CDS_LIB"cndiscrete";
"ESD4"14;
"ESD1"13;
"ESD2"12;
"GND"17;
"ESD3"7;
"VCC"8;
%"PRTR5V0U4Y"
"1","(1050,-2450)","0","cndiscrete","I56";
;
$LOCATION"D?"
TYPE"PRTR5V0U4Y"
PACK_TYPE"SC88"
TYPE"PRTR5V0U4Y"
CDS_LIB"cndiscrete";
"ESD4"4;
"ESD1"8;
"ESD2"7;
"GND"1;
"ESD4"11;
"ESD1"10;
"ESD2"9;
"GND"15;
"ESD3"6;
"VCC"5;
"VCC"8;
%"GND_SIGNAL"
"1","(600,-2725)","0","standard","I57";
;
HDL_POWER"GND_SIGNAL"
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"GND"1;
HDL_POWER"GND_SIGNAL";
"GND"15;
%"CAPCERSMDCL2"
"1","(2175,-1875)","1","cnpassive","I9";
"1","(2575,-1875)","1","cnpassive","I58";
;
VALUE"100NF"
VOLTAGE"16V"
$LOCATION"C?"
SIZE"1"
CDS_LIB"cnpassive"
PACK_TYPE"0603";
"A <SIZE-1..0>\NAC"
$PN"#"18;
"B <SIZE-1..0>\NAC"
$PN"#"8;
%"GND_SIGNAL"
"1","(2525,-2175)","0","standard","I59";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_POWER"GND_SIGNAL";
"GND"18;
%"INPORT"
"1","(3200,275)","0","standard","I64";
;
CDS_LIB"standard"
OFFPAGE"TRUE";
"A"
VHDL_PORT"IN"
HDL_PORT"IN"2;
%"INPORT"
"1","(3200,75)","0","standard","I65";
;
CDS_LIB"standard"
OFFPAGE"TRUE";
"A"
VHDL_PORT"IN"
HDL_PORT"IN"1;
%"CAPCERSMDCL2"
"1","(5975,0)","1","cnpassive","I67";
;
PACK_TYPE"0603"
CDS_LIB"cnpassive"
......@@ -142,8 +184,48 @@ SIZE"1"
$LOCATION"C?"
VOLTAGE"16V"
VALUE"100NF";
"B <SIZE-1..0>\NAC"
$PN"#"5;
"A <SIZE-1..0>\NAC"
$PN"#"4;
"B <SIZE-1..0>\NAC"
$PN"#"3;
%"GND_SIGNAL"
"1","(5925,-300)","0","standard","I68";
;
HDL_POWER"GND_SIGNAL"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"GND"4;
%"USBLC6-2"
"1","(5025,175)","0","cndiscrete","I70";
;
CDS_LIB"cndiscrete"
$LOCATION"D3"
TYPE"USBLC6-2SC6"
PACK_TYPE"SOT23";
"I/O1<1>"2;
"I/O1<0>"2;
"GND"5;
"I/O2<0>"1;
"I/O2<1>"1;
"VBUS"3;
%"GND_SIGNAL"
"1","(4675,-75)","0","standard","I71";
;
CDS_LIB"standard"
HDL_POWER"GND_SIGNAL"
BODY_TYPE"PLUMBING";
"GND"5;
%"CAPCERSMDCL2"
"1","(2175,-1875)","1","cnpassive","I9";
;
VALUE"100NF"
VOLTAGE"16V"
$LOCATION"C?"
SIZE"1"
CDS_LIB"cnpassive"
PACK_TYPE"0603";
"A <SIZE-1..0>\NAC"
$PN"#"16;
"B <SIZE-1..0>\NAC"
$PN"#"8;
END.
Cadence/worklib/fmc_tlu_diode_clamp_b/sch_1/pc.db
View file @ a648eb8d
-- pcdb file, Rev:1.0 written by Allegro Design Entry HDL 16.6-S055 (v16-6-112EP) 8/13/2015 on Fri Apr 22 09:05:35 2016
-- pcdb file, Rev:1.0 written by Allegro Design Entry HDL 16.6-S055 (v16-6-112EP) 8/13/2015 on Wed May 18 10:06:29 2016
#ISCELL
bris_cds_standard a3-2000 *
*
......@@ -44,6 +44,30 @@
#ISCELL
standard gnd_signal *
page1_i57
#CELL
cnpassive capcersmdcl2 *
page1_i58
#ISCELL
standard gnd_signal *
page1_i59
#ISCELL
standard inport *
page1_i64
#ISCELL
standard inport *
page1_i65
#CELL
cnpassive capcersmdcl2 *
page1_i67
#ISCELL
standard gnd_signal *
page1_i68
#CELL
cndiscrete usblc6-2 *
page1_i70
#ISCELL
standard gnd_signal *
page1_i71
#CELL
cnpassive capcersmdcl2 *
page1_i9
Cadence/worklib/fmc_tlu_toplevel_c/packaged/pxl.state
View file @ a648eb8d
This source diff could not be displayed because it is too large. You can view the blob instead.
Cadence/worklib/fmc_tlu_toplevel_c/physical/allegro.jrl
View file @ a648eb8d
\t (00:01:45) allegro 16.6 S035 (v16-6-112CR) Linux I32
\t (00:01:45) Journal start - Tue Jul 14 10:36:00 2015
\t (00:01:45) Host=voltar.phy.bris.ac.uk User=phdgc Pid=6892 CPUs=8
\t (00:01:45) CmdLine= /software/CAD/Cadence/2014_2015/SPB166/tools/pcb/bin/allegro.exe -proj /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/pc051a_toplevel.cpm -product Concept_HDL_studio -mpssession phdgc_ProjectMgr20240 -mpshost voltar.phy.bris.ac.uk
\t (00:01:45)
\d (00:01:45) Design opened: /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/physical/fmc_tlu_v1a_66_gloss4b.brd
\i (00:01:47) zoom points
\t (00:01:47) Pick 1st corner of the new window.
\i (00:01:47) pick -7.3458 46.9349
\t (00:01:47) last pick: -7.3458 46.9349
\t (00:01:47) Pick to complete the window.
\i (00:01:48) pick 11.4776 13.4710
\t (00:01:48) last pick: 11.4776 13.4710
\t (00:01:48) Grids are drawn 0.3200, 0.3200 apart for enhanced viewability.
\i (00:01:48) trapsize 2562
\i (00:01:52) setwindow form.vf_vis
\i (00:01:52) FORM vf_vis 1 all_colorvisible YES
\i (00:01:55) setwindow pcb
\i (00:01:55) zoom points
\t (00:01:55) Pick 1st corner of the new window.
\i (00:01:56) pick 10.5904 39.0429
\t (00:01:56) last pick: 10.5904 39.0429
\t (00:01:56) Pick to complete the window.
\i (00:01:57) pick 17.6624 28.3324
\t (00:01:57) last pick: 17.6624 28.3324
\t (00:01:57) Grids are drawn 0.0800, 0.0800 apart for enhanced viewability.
\i (00:01:57) trapsize 820
\i (00:01:59) roam x 96
\i (00:01:59) roam x 96
\i (00:01:59) roam x 96
\i (00:01:59) roam x 96
\i (00:01:59) roam x 96
\i (00:01:59) roam x 96
\i (00:01:59) roam x 96
\i (00:01:59) roam x 96
\i (00:01:59) roam x 96
\i (00:01:59) roam x 96
\i (00:02:00) roam x 96
\i (00:02:00) roam x 96
\i (00:02:00) roam y -96
\i (00:02:00) roam y -96
\i (00:02:00) roam y -96
\i (00:02:00) roam y -96
\i (00:02:00) roam y -96
\i (00:02:00) roam y -96
\i (00:02:00) roam y -96
\i (00:02:00) roam y -96
\i (00:02:00) roam y -96
\i (00:02:00) roam y -96
\i (00:02:00) roam y -96
\i (00:02:00) roam y -96
\i (00:02:01) roam y -96
\i (00:02:01) roam y -96
\i (00:02:01) roam y -96
\i (00:02:01) roam y -96
\i (00:02:01) roam y -96
\i (00:02:01) roam y -96
\i (00:02:01) roam y -96
\i (00:02:01) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:03) roam y -96
\i (00:02:03) roam y -96
\i (00:26:10) trapsize 819
\i (00:26:10) trapsize 809
\i (00:26:10) trapsize 721
\i (00:26:11) trapsize 697
\i (00:26:11) trapsize 690
\i (00:26:11) trapsize 688
\i (00:26:16) setwindow form.vf_vis
\i (00:26:16) FORM vf_vis 1 all_colorvisible NO
\i (00:26:17) FORM vf_vis 2 all_colorvisible YES
\i (00:26:18) setwindow pcb
\i (00:26:18) roam start
\i (00:26:18) roam x -64
\i (00:26:18) roam y 16
\i (00:26:18) roam x -16
\i (00:26:18) roam x -16
\i (00:26:18) roam x -32
\i (00:26:18) roam y -32
\i (00:26:19) roam x -16
\i (00:26:19) roam y -32
\i (00:26:19) roam x -16
\i (00:26:19) roam y -32
\i (00:26:19) roam x -16
\i (00:26:19) roam y -32
\i (00:26:19) roam x -16
\i (00:26:19) roam y -48
\i (00:26:19) roam x -16
\i (00:26:19) roam y -32
\i (00:26:19) roam x -16
\i (00:26:19) roam y -48
\i (00:26:19) roam y -32
\i (00:26:19) roam y 16
\i (00:26:19) roam y 48
\i (00:26:19) roam x -16
\i (00:26:19) roam y 48
\i (00:26:19) roam y 16
\i (00:26:19) roam x -16
\i (00:26:19) roam y 64
\i (00:26:19) roam y 48
\i (00:26:19) roam x -16
\i (00:26:19) roam y 96
\i (00:26:19) roam y 16
\i (00:26:19) roam x -16
\i (00:26:19) roam y 96
\i (00:26:19) roam x -16
\i (00:26:19) roam y 64
\i (00:26:19) roam y 64
\i (00:26:19) roam x -16
\i (00:26:19) roam y 64
\i (00:26:19) roam y 48
\i (00:26:19) roam y 48
\i (00:26:19) roam y 48
\i (00:26:19) roam y 48
\i (00:26:19) roam y 32
\i (00:26:19) roam y 32
\i (00:26:19) roam y 16
\i (00:26:19) roam y 16
\i (00:26:19) roam y 16
\i (00:26:19) roam y 16
\i (00:26:19) roam y 16
\i (00:26:19) roam x 16
\i (00:26:19) roam y 16
\i (00:26:20) roam y 16
\i (00:26:20) roam y 16
\i (00:26:20) roam y 16
\i (00:26:20) roam y 16
\i (00:26:20) roam y 16
\i (00:26:20) roam y 16
\i (00:26:20) roam y 16
\i (00:26:20) roam x 16
\i (00:26:20) roam y 32
\i (00:26:20) roam y 32
\i (00:26:20) roam y 32
\i (00:26:20) roam x 16
\i (00:26:20) roam y 32
\i (00:26:20) roam y 32
\i (00:26:20) roam y 32
\i (00:26:20) roam x 16
\i (00:26:20) roam y 48
\i (00:26:20) roam y 32
\i (00:26:20) roam y 32
\i (00:26:20) roam y 32
\i (00:26:20) roam y 32
\i (00:26:20) roam y 32
\i (00:26:20) roam y 16
\i (00:26:20) roam x 16
\i (00:26:20) roam y 32
\i (00:26:20) roam y 16
\i (00:26:20) roam y 16
\i (00:26:20) roam x 16
\i (00:26:20) roam x 16
\i (00:26:20) roam x 16
\i (00:26:20) roam y -16
\i (00:26:20) roam x 16
\i (00:26:20) roam x 16
\i (00:26:20) roam x 32
\i (00:26:20) roam y -32
\i (00:26:20) roam x 32
\i (00:26:20) roam y -16
\i (00:26:20) roam x 48
\i (00:26:20) roam y -32
\i (00:26:21) roam x 48
\i (00:26:21) roam y -32
\i (00:26:21) roam x 32
\i (00:26:21) roam y -32
\i (00:26:21) roam x 32
\i (00:26:21) roam y -16
\i (00:26:21) roam x 48
\i (00:26:21) roam y -32
\i (00:26:21) roam x 32
\i (00:26:21) roam y -32
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 32
\i (00:26:21) roam y -32
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 32
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:22) roam x 16
\i (00:26:22) roam y -16
\i (00:26:22) roam x 16
\i (00:26:22) roam y -16
\i (00:26:22) roam y -16
\i (00:26:22) roam x 16
\i (00:26:22) roam x 16
\i (00:26:22) roam y -16
\i (00:26:22) roam x 16
\i (00:26:22) roam x 16
\i (00:26:22) roam y -16
\i (00:26:22) roam x 32
\i (00:26:22) roam x 32
\i (00:26:22) roam y -16
\i (00:26:22) roam x 48
\i (00:26:22) roam y -16
\i (00:26:22) roam x 64
\i (00:26:22) roam y -16
\i (00:26:22) roam x 48
\i (00:26:22) roam x 64
\i (00:26:22) roam y -16
\i (00:26:22) roam x 80
\i (00:26:22) roam y -16
\i (00:26:22) roam x 48
\i (00:26:22) roam x 64
\i (00:26:22) roam y -16
\i (00:26:22) roam x 48
\i (00:26:22) roam x 48
\i (00:26:22) roam y -16
\i (00:26:22) roam x 32
\i (00:26:22) roam x 32
\i (00:26:22) roam y -16
\i (00:26:22) roam x 16
\i (00:26:22) roam x 16
\i (00:26:22) roam y 16
\i (00:26:22) roam y 16
\i (00:26:22) roam y 32
\i (00:26:22) roam y 32
\i (00:26:22) roam x -16
\i (00:26:22) roam y 48
\i (00:26:22) roam y 48
\i (00:26:22) roam y 48
\i (00:26:22) roam y 48
\i (00:26:22) roam y 64
\i (00:26:22) roam y 32
\i (00:26:22) roam y 16
\i (00:26:23) roam y 16
\i (00:26:23) roam y 16
\i (00:26:23) roam x -16
\i (00:26:23) roam x -16
\i (00:26:23) roam x -16
\i (00:26:23) roam x -32
\i (00:26:23) roam x -32
\i (00:26:23) roam x -16
\i (00:26:23) roam x -32
\i (00:26:23) roam x -32
\i (00:26:23) roam x -16
\i (00:26:23) roam x -32
\i (00:26:23) roam x -32
\i (00:26:23) roam x -16
\i (00:26:23) roam x -16
\i (00:26:24) roam x -16
\i (00:26:24) roam x -16
\i (00:26:24) roam x -16
\i (00:26:24) roam x -16
\i (00:26:24) roam x -16
\i (00:26:24) roam x -16
\i (00:26:24) roam x -16
\i (00:26:24) roam x -16
\i (00:26:24) roam x -16
\i (00:26:25) roam x -16
\i (00:26:25) roam end
\i (00:26:26) roam start
\i (00:26:26) roam x -16
\i (00:26:26) roam y 64
\i (00:26:26) roam x -48
\i (00:26:26) roam y 96
\i (00:26:26) roam x -32
\i (00:26:26) roam y 112
\i (00:26:26) roam x -16
\i (00:26:26) roam y 32
\i (00:26:27) roam y 48
\i (00:26:27) roam x -16
\i (00:26:27) roam y 96
\i (00:26:27) roam x -16
\i (00:26:27) roam y 112
\i (00:26:27) roam x -16
\i (00:26:27) roam y 48
\i (00:26:27) roam y 80
\i (00:26:27) roam x -16
\i (00:26:27) roam y 80
\i (00:26:27) roam x -16
\i (00:26:27) roam y 64
\i (00:26:27) roam y 80
\i (00:26:27) roam x -16
\i (00:26:27) roam y 64
\i (00:26:27) roam x -16
\i (00:26:27) roam y 64
\i (00:26:27) roam y 64
\i (00:26:27) roam x -16
\i (00:26:27) roam y 64
\i (00:26:27) roam y 48
\i (00:26:27) roam x -16
\i (00:26:27) roam y 48
\i (00:26:27) roam y 80
\i (00:26:27) roam x -16
\i (00:26:27) roam y 48
\i (00:26:27) roam y 48
\i (00:26:27) roam x -16
\i (00:26:27) roam y 48
\i (00:26:27) roam y 48
\i (00:26:27) roam y 32
\i (00:26:27) roam y 16
\i (00:26:27) roam y 16
\i (00:26:27) roam y 16
\i (00:26:27) roam y 16
\i (00:26:27) roam x -16
\i (00:26:27) roam y 16
\i (00:26:27) roam y -48
\i (00:26:27) roam x -16
\i (00:26:27) roam y 32
\i (00:26:27) roam y 16
\i (00:26:27) roam y 16
\i (00:26:28) roam y 16
\i (00:26:28) roam x 16
\i (00:26:28) roam y 16
\i (00:26:28) roam y 16
\i (00:26:28) roam x 16
\i (00:26:28) roam x 16
\i (00:26:28) roam y 32
\i (00:26:28) roam x 32
\i (00:26:28) roam y 32
\i (00:26:28) roam x 32
\i (00:26:28) roam y 48
\i (00:26:28) roam x 64
\i (00:26:28) roam y 48
\i (00:26:28) roam x 48
\i (00:26:28) roam y 80
\i (00:26:28) roam x 80
\i (00:26:28) roam y 64
\i (00:26:28) roam x 112
\i (00:26:28) roam y 96
\i (00:26:28) roam x 16
\i (00:26:28) roam y 32
\i (00:26:28) roam x 96
\i (00:26:28) roam y 112
\i (00:26:28) roam x 64
\i (00:26:28) roam y 80
\i (00:26:28) roam x 48
\i (00:26:28) roam y 64
\i (00:26:28) roam x 64
\i (00:26:28) roam y 64
\i (00:26:28) roam x 48
\i (00:26:28) roam y 64
\i (00:26:28) roam x 64
\i (00:26:28) roam y 48
\i (00:26:28) roam x 64
\i (00:26:28) roam y 48
\i (00:26:28) roam x 48
\i (00:26:28) roam y 48
\i (00:26:28) roam x 48
\i (00:26:28) roam y 48
\i (00:26:28) roam x 48
\i (00:26:28) roam y 32
\i (00:26:28) roam x 48
\i (00:26:28) roam y 16
\i (00:26:28) roam x 48
\i (00:26:28) roam y 32
\i (00:26:28) roam x 16
\i (00:26:28) roam y 16
\i (00:26:28) roam x 16
\i (00:26:28) roam y 16
\i (00:26:28) roam x -16
\i (00:26:28) roam y 16
\i (00:26:29) roam x -32
\i (00:26:29) roam y 16
\i (00:26:29) roam x -80
\i (00:26:29) roam y 48
\i (00:26:29) roam x -128
\i (00:26:29) roam y 112
\i (00:26:29) roam x -96
\i (00:26:29) roam y 80
\i (00:26:29) roam x -112
\i (00:26:29) roam y 80
\i (00:26:29) roam x -96
\i (00:26:29) roam y 96
\i (00:26:29) roam x -80
\i (00:26:29) roam y 96
\i (00:26:29) roam x -80
\i (00:26:29) roam y 96
\i (00:26:29) roam x -64
\i (00:26:29) roam y 96
\i (00:26:29) roam x -80
\i (00:26:29) roam y 144
\i (00:26:29) roam x -32
\i (00:26:29) roam y 48
\i (00:26:29) roam x -80
\i (00:26:29) roam y 144
\i (00:26:29) roam x -32
\i (00:26:29) roam y 80
\i (00:26:29) roam x -48
\i (00:26:29) roam y 80
\i (00:26:29) roam x -16
\i (00:26:29) roam y 80
\i (00:26:29) roam x -32
\i (00:26:29) roam y 64
\i (00:26:29) roam x -16
\i (00:26:29) roam y 48
\i (00:26:29) roam x -16
\i (00:26:29) roam y 32
\i (00:26:29) roam x -16
\i (00:26:29) roam y 16
\i (00:26:29) roam y 32
\i (00:26:29) roam x -16
\i (00:26:29) roam y 16
\i (00:26:29) roam x -16
\i (00:26:29) roam y 16
\i (00:26:29) roam x -16
\i (00:26:29) roam y 16
\i (00:26:29) roam x -16
\i (00:26:29) roam y -16
\i (00:26:29) roam y -16
\i (00:26:29) roam x -16
\i (00:26:29) roam y -80
\i (00:26:29) roam x -16
\i (00:26:29) roam y 16
\i (00:26:29) roam x -16
\i (00:26:30) roam x -16
\i (00:26:30) roam x -64
\i (00:26:30) roam x -48
\i (00:26:30) roam x -64
\i (00:26:30) roam x -80
\i (00:26:30) roam x -112
\i (00:26:30) roam x -112
\i (00:26:30) roam y -16
\i (00:26:30) roam x -128
\i (00:26:30) roam x -144
\i (00:26:30) roam x -144
\i (00:26:30) roam x -224
\i (00:26:30) roam x -112
\i (00:26:30) roam x -96
\i (00:26:30) roam x -80
\i (00:26:30) roam x -64
\i (00:26:30) roam x -48
\i (00:26:30) roam x -32
\i (00:26:30) roam y 16
\i (00:26:30) roam x -16
\i (00:26:30) roam x -16
\i (00:26:30) roam x -16
\i (00:26:30) roam y 16
\i (00:26:30) roam x -16
\i (00:26:30) roam x -16
\i (00:26:30) roam x -32
\i (00:26:30) roam x -48
\i (00:26:30) roam x -64
\i (00:26:30) roam x -48
\i (00:26:30) roam x -64
\i (00:26:30) roam x -64
\i (00:26:30) roam x -48
\i (00:26:30) roam x -96
\i (00:26:30) roam x -48
\i (00:26:30) roam y -16
\i (00:26:30) roam x -32
\i (00:26:30) roam x -32
\i (00:26:30) roam y -16
\i (00:26:30) roam x -48
\i (00:26:30) roam x -16
\i (00:26:30) roam x -32
\i (00:26:30) roam x -32
\i (00:26:30) roam x -16
\i (00:26:30) roam x -32
\i (00:26:30) roam x -16
\i (00:26:30) roam x -32
\i (00:26:30) roam x -32
\i (00:26:30) roam x -32
\i (00:26:30) roam x -16
\i (00:26:30) roam x -32
\i (00:26:30) roam x -32
\i (00:26:30) roam x -32
\i (00:26:30) roam x -32
\i (00:26:30) roam x -32
\i (00:26:30) roam y -16
\i (00:26:30) roam x -16
\i (00:26:30) roam x -16
\i (00:26:31) roam y -16
\i (00:26:31) roam y -16
\i (00:26:31) roam y -16
\i (00:26:31) roam y -16
\i (00:26:31) roam y -32
\i (00:26:31) roam x 16
\i (00:26:31) roam y -64
\i (00:26:31) roam x 16
\i (00:26:31) roam y -64
\i (00:26:31) roam y -64
\i (00:26:31) roam y -128
\i (00:26:31) roam y -96
\i (00:26:31) roam x 16
\i (00:26:31) roam y -80
\i (00:26:31) roam y -80
\i (00:26:31) roam y -96
\i (00:26:31) roam y -80
\i (00:26:31) roam y -64
\i (00:26:31) roam y -64
\i (00:26:31) roam x -16
\i (00:26:31) roam y -48
\i (00:26:31) roam y -48
\i (00:26:31) roam y -32
\i (00:26:31) roam y -16
\i (00:26:31) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam x 16
\i (00:26:32) roam y -32
\i (00:26:32) roam y -32
\i (00:26:32) roam y -32
\i (00:26:32) roam x 16
\i (00:26:32) roam y -48
\i (00:26:32) roam y -32
\i (00:26:32) roam y -48
\i (00:26:32) roam x 16
\i (00:26:32) roam y -32
\i (00:26:32) roam y -48
\i (00:26:32) roam y -48
\i (00:26:32) roam y -32
\i (00:26:32) roam x 16
\i (00:26:32) roam y -48
\i (00:26:32) roam y -32
\i (00:26:32) roam y -48
\i (00:26:32) roam x 16
\i (00:26:32) roam y -48
\i (00:26:32) roam y -48
\i (00:26:32) roam y -32
\i (00:26:32) roam x 16
\i (00:26:32) roam y -48
\i (00:26:32) roam y -32
\i (00:26:32) roam y -32
\i (00:26:32) roam y -16
\i (00:26:32) roam y -32
\i (00:26:32) roam y -16
\i (00:26:32) roam y -32
\i (00:26:32) roam y -16
\i (00:26:32) roam y -32
\i (00:26:32) roam y -16
\i (00:26:32) roam y -32
\i (00:26:32) roam y -32
\i (00:26:32) roam y -16
\i (00:26:32) roam x 16
\i (00:26:32) roam y -32
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam y -32
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -32
\i (00:26:33) roam x -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -32
\i (00:26:33) roam y -16
\i (00:26:33) roam y -32
\i (00:26:33) roam y -16
\i (00:26:33) roam y -32
\i (00:26:33) roam y -16
\i (00:26:33) roam y -32
\i (00:26:33) roam y -16
\i (00:26:33) roam y -32
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -32
\i (00:26:33) roam y -16
\i (00:26:33) roam x -32
\i (00:26:33) roam y -16
\i (00:26:33) roam y -32
\i (00:26:33) roam y -32
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -32
\i (00:26:34) roam y -32
\i (00:26:34) roam y -16
\i (00:26:34) roam y -32
\i (00:26:34) roam y -32
\i (00:26:34) roam x -16
\i (00:26:34) roam y -16
\i (00:26:34) roam x -32
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -32
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam x -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -32
\i (00:26:35) roam x 16
\i (00:26:35) roam y -32
\i (00:26:35) roam y -32
\i (00:26:35) roam y -32
\i (00:26:35) roam y -16
\i (00:26:35) roam x 16
\i (00:26:35) roam y -32
\i (00:26:35) roam y -16
\i (00:26:35) roam y -32
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam x 16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam x 16
\i (00:26:35) roam y -32
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam x 16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -32
\i (00:26:36) roam x 16
\i (00:26:36) roam y -32
\i (00:26:36) roam y -16
\i (00:26:36) roam y -32
\i (00:26:36) roam y -32
\i (00:26:36) roam y -32
\i (00:26:36) roam y -32
\i (00:26:36) roam x 16
\i (00:26:36) roam y -32
\i (00:26:36) roam y -16
\i (00:26:36) roam y -32
\i (00:26:36) roam y -16
\i (00:26:36) roam y -32
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:37) roam y -16
\i (00:26:37) roam end
\i (00:26:53) exit
\t (00:26:54) Journal end - Tue Jul 14 11:01:09 2015
\t (00:00:03) allegro 16.6-2015 S055 (v16-6-112EH) Linux I32
\t (00:00:03) Journal start - Fri May 20 14:54:43 2016
\t (00:00:03) Host=voltar.phy.bris.ac.uk User=phdgc Pid=12505 CPUs=8
\t (00:00:03) CmdLine= /software/CAD/Cadence/2015-16/RHELx86/SPB_16.60.055/tools/pcb/bin/allegro.exe -proj /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/fmc_tlu_v1c.cpm -product Concept_HDL_studio -mpssession phdgc_ProjectMgr1575 -mpshost voltar.phy.bris.ac.uk
\t (00:00:03)
\t (00:00:04) Opening existing design...
\d (00:00:04) Design opened: /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_c/physical/fmc_tlu_v1c_67.brd
\t (00:00:04) Grids are drawn 1.6000, 1.6000 apart for enhanced viewability.
\i (00:00:05) trapsize 13045
\i (00:00:05) trapsize 12371
\i (00:00:05) trapsize 13164
\t (00:00:05) Grids are drawn 0.8000, 0.8000 apart for enhanced viewability.
\i (00:00:05) trapsize 9433
\t (00:00:05) Grids are drawn 0.8000, 0.8000 apart for enhanced viewability.
\i (00:00:05) trapsize 9433
\i (00:00:06) ifp
\i (00:00:11) trapsize 9420
\i (00:00:11) trapsize 9335
\i (00:00:11) trapsize 6355
\i (00:00:12) trapsize 5388
\i (00:00:12) trapsize 5227
\i (00:00:14) roam start
\i (00:00:14) roam x -48
\i (00:00:14) roam y 64
\i (00:00:14) roam x -16
\i (00:00:14) roam y 80
\i (00:00:14) roam y 48
\i (00:00:14) roam y 48
\i (00:00:14) roam y 32
\i (00:00:14) roam x 16
\i (00:00:14) roam y -16
\i (00:00:14) roam x 64
\i (00:00:14) roam y -48
\i (00:00:14) roam x 64
\i (00:00:14) roam y -64
\i (00:00:14) roam x 96
\i (00:00:14) roam y -128
\i (00:00:14) roam x 112
\i (00:00:14) roam y -128
\i (00:00:14) roam x 96
\i (00:00:14) roam y -128
\i (00:00:14) roam x 80
\i (00:00:14) roam y -112
\i (00:00:14) roam x 16
\i (00:00:14) roam y -32
\i (00:00:14) roam x 16
\i (00:00:14) roam y -16
\i (00:00:15) roam x -16
\i (00:00:15) roam y 16
\i (00:00:15) roam y 16
\i (00:00:15) roam x -16
\i (00:00:15) roam y 16
\i (00:00:15) roam x -16
\i (00:00:15) roam y 16
\i (00:00:15) roam x -16
\i (00:00:15) roam y 16
\i (00:00:15) roam x -16
\i (00:00:15) roam y 16
\i (00:00:15) roam x -16
\i (00:00:15) roam y 16
\i (00:00:15) roam x -16
\i (00:00:15) roam y 16
\i (00:00:15) roam x -16
\i (00:00:15) roam y 16
\i (00:00:15) roam x -16
\i (00:00:15) roam y 16
\i (00:00:15) roam x -16
\i (00:00:15) roam y 16
\i (00:00:15) roam x -16
\i (00:00:15) roam y 16
\i (00:00:15) roam x -16
\i (00:00:15) roam y 16
\i (00:00:15) roam x -16
\i (00:00:16) roam end
\i (00:00:18) setwindow form.vf_vis
\i (00:00:18) FORM vf_vis 1 all_colorvisible NO
\i (00:00:19) FORM vf_vis 3 all_colorvisible NO
\i (00:00:23) FORM vf_vis 4 all_colorvisible NO
\i (00:00:26) FORM vf_vis 6 all_colorvisible NO
\i (00:00:29) FORM vf_vis 1 all_colorvisible YES
\i (00:00:45) setwindow pcb
\i (00:00:45) roam start
\i (00:00:45) roam x -48
\i (00:00:45) roam y -64
\i (00:00:45) roam x -80
\i (00:00:45) roam y -112
\i (00:00:45) roam x -112
\i (00:00:45) roam y -128
\i (00:00:46) roam x -64
\i (00:00:46) roam y -80
\i (00:00:46) roam x -48
\i (00:00:46) roam y -80
\i (00:00:46) roam y -64
\i (00:00:46) roam y -64
\i (00:00:46) roam y -32
\i (00:00:46) roam y -16
\i (00:00:46) roam y -16
\i (00:00:46) roam y 16
\i (00:00:46) roam y 64
\i (00:00:46) roam x 16
\i (00:00:46) roam y 48
\i (00:00:46) roam x 48
\i (00:00:46) roam y 64
\i (00:00:46) roam y 48
\i (00:00:46) roam x 16
\i (00:00:46) roam y 32
\i (00:00:47) roam x 16
\i (00:00:47) roam x 16
\i (00:00:47) roam x 32
\i (00:00:47) roam x 64
\i (00:00:47) roam x 80
\i (00:00:47) roam x 48
\i (00:00:47) roam x 16
\i (00:00:48) roam y 16
\i (00:00:48) roam y 32
\i (00:00:48) roam y 16
\i (00:00:48) roam y 32
\i (00:00:48) roam y 16
\i (00:00:48) roam y 16
\i (00:00:48) roam y 16
\i (00:00:48) roam y 16
\i (00:00:48) roam y 16
\i (00:00:48) roam y 16
\i (00:00:48) roam y 32
\i (00:00:48) roam x -16
\i (00:00:48) roam y 16
\i (00:00:48) roam y 32
\i (00:00:48) roam y 32
\i (00:00:48) roam y 32
\i (00:00:48) roam y 16
\i (00:00:48) roam y 32
\i (00:00:49) roam y -16
\i (00:00:49) roam x 16
\i (00:00:49) roam y -32
\i (00:00:49) roam x 16
\i (00:00:49) roam y -32
\i (00:00:49) roam x 16
\i (00:00:49) roam y -16
\i (00:00:50) roam x -16
\i (00:00:50) roam x -96
\i (00:00:50) roam x -64
\i (00:00:50) roam y 16
\i (00:00:50) roam x -64
\i (00:00:50) roam y 16
\i (00:00:50) roam x -32
\i (00:00:50) roam x -32
\i (00:00:50) roam x -16
\i (00:00:50) roam y 16
\i (00:00:50) roam x -32
\i (00:00:50) roam x -16
\i (00:00:51) roam x 16
\i (00:00:51) roam y 16
\i (00:00:51) roam x 16
\i (00:00:51) roam y 16
\i (00:00:51) roam y 16
\i (00:00:52) roam x 16
\i (00:00:52) roam x 16
\i (00:00:53) roam x 16
\i (00:00:53) roam x 16
\i (00:00:53) roam y -16
\i (00:00:53) roam x 16
\i (00:00:53) roam y -32
\i (00:00:53) roam x 16
\i (00:00:53) roam y -32
\i (00:00:53) roam y -16
\i (00:00:53) roam x 16
\i (00:00:53) roam y -32
\i (00:00:54) roam y -16
\i (00:00:54) roam y -16
\i (00:00:54) roam x 16
\i (00:00:54) roam y -16
\i (00:00:54) roam y -16
\i (00:00:54) roam y -16
\i (00:00:54) roam x 16
\i (00:00:54) roam y -16
\i (00:00:54) roam x 16
\i (00:00:54) roam y -16
\i (00:00:54) roam x 16
\i (00:00:54) roam x 16
\i (00:00:55) roam x -16
\i (00:00:55) roam x -32
\i (00:00:55) roam x -32
\i (00:00:55) roam x -32
\i (00:00:55) roam y 16
\i (00:00:55) roam x -16
\i (00:00:55) roam x -16
\i (00:00:55) roam y 16
\i (00:00:55) roam x -16
\i (00:00:55) roam y 16
\i (00:00:56) roam y 16
\i (00:00:56) roam y 16
\i (00:00:56) roam x 16
\i (00:00:56) roam y 32
\i (00:00:56) roam x 16
\i (00:00:56) roam y 16
\i (00:00:56) roam y 16
\i (00:00:56) roam x 16
\i (00:00:56) roam x 16
\i (00:00:56) roam y 16
\i (00:00:56) roam y 16
\i (00:00:57) roam end
\i (00:01:01) setwindow form.vf_vis
\i (00:01:01) FORM vf_vis 1 all_colorvisible NO
\i (00:01:02) FORM vf_vis 6 all_colorvisible YES
\i (00:01:09) setwindow pcb
\i (00:01:09) roam start
\i (00:01:09) roam x 48
\i (00:01:09) roam y 16
\i (00:01:09) roam x 32
\i (00:01:09) roam y 32
\i (00:01:09) roam x 16
\i (00:01:09) roam y 16
\i (00:01:09) roam y 64
\i (00:01:09) roam x 16
\i (00:01:09) roam y 32
\i (00:01:09) roam y 32
\i (00:01:10) roam x 32
\i (00:01:10) roam x 112
\i (00:01:10) roam y -48
\i (00:01:10) roam x 176
\i (00:01:10) roam y -64
\i (00:01:10) roam x 96
\i (00:01:10) roam y -32
\i (00:01:10) roam y -32
\i (00:01:11) roam y -16
\i (00:01:11) roam x -16
\i (00:01:12) roam x -16
\i (00:01:12) roam x -16
\i (00:01:12) roam x -16
\i (00:01:12) roam x -16
\i (00:01:12) roam x -16
\i (00:01:13) roam x -16
\i (00:01:13) roam x -16
\i (00:01:13) roam x -16
\i (00:01:13) roam y 16
\i (00:01:13) roam x -16
\i (00:01:13) roam x -32
\i (00:01:13) roam x -96
\i (00:01:13) roam y 32
\i (00:01:13) roam x -176
\i (00:01:13) roam y 32
\i (00:01:13) roam x -96
\i (00:01:13) roam y 16
\i (00:01:13) roam x -80
\i (00:01:13) roam x -32
\i (00:01:13) roam y 16
\i (00:01:15) roam end
\i (00:01:17) zoom points
\t (00:01:17) Pick 1st corner of the new window.
\i (00:01:18) pick 34.2105 38.5387
\t (00:01:18) last pick: 34.2105 38.5387
\t (00:01:18) Pick to complete the window.
\i (00:01:19) pick 48.0108 6.2335
\t (00:01:19) last pick: 48.0108 6.2335
\t (00:01:19) Grids are drawn 0.2000, 0.2000 apart for enhanced viewability.
\i (00:01:19) trapsize 2103
\i (00:01:19) ifp
\i (00:01:26) setwindow form.vf_vis
\i (00:01:26) FORM vf_vis 6 all_colorvisible NO
\i (00:01:27) FORM vf_vis 1 all_colorvisible YES
\i (00:01:38) setwindow pcb
\i (00:01:38) roam start
\i (00:01:38) roam x -80
\i (00:01:38) roam y 16
\i (00:01:38) roam x -240
\i (00:01:38) roam y 80
\i (00:01:39) roam x -208
\i (00:01:39) roam y 96
\i (00:01:39) roam x -112
\i (00:01:39) roam y 32
\i (00:01:39) roam x -64
\i (00:01:39) roam y 16
\i (00:01:39) roam x -64
\i (00:01:39) roam x -16
\i (00:01:39) roam x -16
\i (00:01:39) roam x -16
\i (00:01:39) roam y -16
\i (00:01:39) roam x -16
\i (00:01:39) roam y -16
\i (00:01:39) roam x -32
\i (00:01:39) roam x -32
\i (00:01:39) roam y -16
\i (00:01:39) roam x -96
\i (00:01:39) roam x -80
\i (00:01:39) roam x -64
\i (00:01:39) roam x -64
\i (00:01:39) roam y 48
\i (00:01:39) roam x -64
\i (00:01:39) roam y 64
\i (00:01:39) roam x -80
\i (00:01:39) roam y 64
\i (00:01:39) roam x -80
\i (00:01:39) roam y 80
\i (00:01:39) roam x -48
\i (00:01:39) roam y 64
\i (00:01:39) roam x -16
\i (00:01:39) roam y 32
\i (00:01:39) roam x -16
\i (00:01:39) roam y 16
\i (00:01:40) roam x 16
\i (00:01:40) roam end
\i (00:01:44) roam start
\i (00:01:44) roam x 32
\i (00:01:44) roam y -80
\i (00:01:44) roam x 48
\i (00:01:44) roam y -96
\i (00:01:44) roam x 48
\i (00:01:44) roam y -128
\i (00:01:44) roam x 64
\i (00:01:44) roam y -112
\i (00:01:44) roam x 80
\i (00:01:44) roam y -176
\i (00:01:44) roam x 64
\i (00:01:44) roam y -128
\i (00:01:44) roam x 48
\i (00:01:44) roam y -112
\i (00:01:44) roam x 16
\i (00:01:44) roam y -96
\i (00:01:44) roam x 16
\i (00:01:44) roam y -80
\i (00:01:44) roam y -64
\i (00:01:44) roam y -32
\i (00:01:44) roam x 16
\i (00:01:44) roam y -32
\i (00:01:44) roam y -16
\i (00:01:44) roam y -32
\i (00:01:45) roam y -16
\i (00:01:45) roam y -16
\i (00:01:45) roam y -32
\i (00:01:45) roam y -16
\i (00:01:45) roam y -16
\i (00:01:45) roam y -16
\i (00:01:45) roam y -16
\i (00:01:45) roam y -16
\i (00:01:45) roam y -16
\i (00:01:45) roam y -16
\i (00:01:45) roam y -16
\i (00:01:45) roam y -16
\i (00:01:45) roam y -16
\i (00:01:45) roam x 16
\i (00:01:45) roam x 16
\i (00:01:45) roam x 16
\i (00:01:45) roam x 32
\i (00:01:45) roam x 64
\i (00:01:45) roam y 16
\i (00:01:45) roam x 48
\i (00:01:45) roam y 16
\i (00:01:45) roam x 16
\i (00:01:45) roam y 16
\i (00:01:45) roam x 16
\i (00:01:45) roam y 16
\i (00:01:46) roam y 16
\i (00:01:46) roam x 16
\i (00:01:46) roam y 16
\i (00:01:47) roam y 32
\i (00:01:47) roam x 16
\i (00:01:47) roam y 32
\i (00:01:47) roam x 16
\i (00:01:47) roam y 48
\i (00:01:47) roam x 16
\i (00:01:47) roam y 48
\i (00:01:47) roam x 16
\i (00:01:47) roam y 16
\i (00:01:47) roam x 16
\i (00:01:47) roam x 16
\i (00:01:47) roam x 16
\i (00:01:48) roam x 16
\i (00:01:48) roam y -16
\i (00:01:48) roam x 32
\i (00:01:48) roam y -16
\i (00:01:48) roam x 32
\i (00:01:48) roam y -32
\i (00:01:48) roam x 48
\i (00:01:48) roam y -32
\i (00:01:48) roam x 32
\i (00:01:48) roam y -16
\i (00:01:48) roam x 16
\i (00:01:48) roam y -16
\i (00:01:48) roam y -16
\i (00:01:48) roam x 16
\i (00:01:49) roam x -16
\i (00:01:49) roam x -16
\i (00:01:49) roam x -16
\i (00:01:49) roam x -32
\i (00:01:49) roam x -16
\i (00:01:49) roam x -16
\i (00:01:49) roam x -16
\i (00:01:49) roam x -16
\i (00:01:50) roam x -16
\i (00:01:50) roam x -16
\i (00:01:50) roam x -16
\i (00:01:50) roam x -16
\i (00:01:50) roam x -16
\i (00:01:50) roam x -16
\i (00:01:50) roam x -16
\i (00:01:50) roam x -16
\i (00:01:50) roam x -16
\i (00:01:50) roam x -16
\i (00:01:50) roam end
\i (00:01:56) place manual
\i (00:12:46) setwindow form.plc_manual
\i (00:12:46) FORM plc_manual done
\i (00:12:46) setwindow pcb
\i (00:12:46) ifp
\i (00:12:52) exit
\e (00:12:52) Do you want to save the changes you made to fmc_tlu_v1c_67.brd?
\i (00:12:57) fillin menu_cancel
\i (00:12:57) ifp
\i (00:13:02) padeditlib
\i (00:16:41) fillin "C130h60o-15"
\i (00:16:44) setwindow form.padedit
\i (00:16:44) FORM padedit layers
\i (00:16:50) FORM padedit flash_th
\i (00:16:50) FORM padedit grid row begin_layer
\i (00:16:51) FORM padedit grid row default_internal
\i (00:16:58) FORM padedit grid row end_layer
\i (00:17:06) pse_exit
\i (00:17:25) fillin "C130h60o-15"
\i (00:17:28) setwindow form.padedit
\i (00:17:28) FORM padedit grid row begin_layer
\i (00:17:41) FORM padedit flash_th
\i (00:17:43) FORM padedit geometry_th Rectangle
\i (00:17:48) FORM padedit width_th 1.6
\i (00:17:50) FORM padedit height_th 1.6
\i (00:17:52) FORM padedit grid row end_layer
\i (00:17:54) FORM padedit grid row default_internal
\i (00:18:02) FORM padedit flash_th
\i (00:18:03) FORM padedit geometry_th Rectangle
\i (00:18:06) FORM padedit width_th 1.6
\i (00:18:08) FORM padedit height_th 1.6
\i (00:18:10) FORM padedit x_offset_th 0.15
\i (00:18:12) FORM padedit grid row begin_layer
\i (00:18:13) FORM padedit grid row default_internal
\i (00:18:15) FORM padedit grid row begin_layer
\i (00:18:19) FORM padedit x_offset_th 0.15
\i (00:18:21) FORM padedit grid row default_internal
\i (00:18:23) FORM padedit grid row end_layer
\i (00:18:25) FORM padedit grid row begin_layer
\i (00:18:27) FORM padedit grid row end_layer
\i (00:18:31) FORM padedit flash_th
\i (00:18:33) FORM padedit geometry_th Rectangle
\i (00:18:37) FORM padedit width_th 1.6
\i (00:18:38) FORM padedit height_th 1.6
\i (00:18:40) FORM padedit x_offset_th 0.15
\i (00:18:45) pse_update
\w (00:18:45) WARNING: If this is a via padstack, it must be added to the via list in constraints.
\i (00:18:49) pse_save
\i (00:18:52) pse_save_as
\i (00:19:03) fillin "c130h60o-15.pad"
\i (00:19:06) pse_exit
\i (00:19:12) fillin "menu_cancel"
\i (00:20:43) fillin yes
\i (00:20:43) setwindow pcb
\i (00:20:43) ifp
\i (00:20:48) exit
\e (00:20:48) Do you want to save the changes you made to fmc_tlu_v1c_67.brd?
\i (00:20:50) fillin yes
\t (00:20:51) Journal end - Fri May 20 15:15:31 2016
Cadence/worklib/fmc_tlu_toplevel_c/physical/allegro.jrl,1
View file @ a648eb8d
\t (00:00:34) allegro 16.6 S014 (v16-6-112AU) Linux I32
\t (00:00:34) Journal start - Wed May 6 14:39:49 2015
\t (00:00:34) Host=fortis.phy.bris.ac.uk User=phdgc Pid=24973 CPUs=4
\t (00:00:34)
\t (00:00:35) Opening existing design...
\d (00:00:36) Database opened: /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/physical/fmc_tlu_v1a_66_gloss4b.brd
\t (00:00:36) Grids are drawn 2.5600, 2.5600 apart for enhanced viewability.
\i (00:00:36) trapsize 13171
\i (00:00:36) trapsize 12856
\i (00:00:36) trapsize 13226
\i (00:00:37) trapsize 11342
\i (00:00:37) trapsize 14936
\i (00:00:38) ifp
\i (00:00:42) zoom points
\t (00:00:42) Pick 1st corner of the new window.
\i (00:00:43) pick -6.6217 73.7313
\t (00:00:43) last pick: -6.6217 73.7313
\t (00:00:43) Pick to complete the window.
\i (00:00:43) pick 62.0837 24.7414
\t (00:00:43) last pick: 62.0837 24.7414
\t (00:00:43) Grids are drawn 0.6400, 0.6400 apart for enhanced viewability.
\i (00:00:43) trapsize 4822
\i (00:00:43) ifp
\i (00:05:04) zoom points
\t (00:05:04) Pick 1st corner of the new window.
\i (00:05:05) pick -2.7642 66.4985
\t (00:05:05) last pick: -2.7642 66.4985
\t (00:05:05) Pick to complete the window.
\i (00:05:05) pick 68.5026 42.5822
\t (00:05:05) last pick: 68.5026 42.5822
\i (00:05:05) trapsize 2513
\i (00:05:05) ifp
\i (00:05:07) show element
\i (00:05:11) setwindow form.find
\i (00:05:11) FORM find all_off
\i (00:05:12) FORM find nets YES
\i (00:25:30) setwindow pcb
\i (00:25:30) trapsize 2233
\i (00:25:32) trapsize 2513
\i (02:45:29) pick grid 47.0924 52.5266
\t (02:45:29) last pick: 47.0900 52.5300
\i (02:45:42) pick grid 47.7458 50.0639
\t (02:45:42) last pick: 47.7500 50.0600
\i (03:36:18) zoom points
\t (03:36:18) Pick 1st corner of the new window.
\i (03:36:21) pick 20.8574 65.1918
\t (03:36:21) last pick: 20.8574 65.1918
\t (03:36:21) Pick to complete the window.
\i (03:36:22) pick 32.5676 53.6825
\t (03:36:22) last pick: 32.5676 53.6825
\t (03:36:22) Grids are drawn 0.1600, 0.1600 apart for enhanced viewability.
\i (03:36:22) trapsize 1133
\i (03:36:31) setwindow form.find
\i (03:36:31) FORM find pins YES
\i (03:36:31) FORM find nets NO
\i (03:39:20) FORM find nets YES
\i (03:39:23) setwindow pcb
\i (03:39:23) pick grid 27.5636 57.6247
\t (03:39:23) last pick: 27.5600 57.6200
\i (03:39:35) pick grid 28.3113 57.6473
\t (03:39:35) last pick: 28.3100 57.6500
\i (03:48:51) pick grid 24.3238 55.8801
\t (03:48:51) last pick: 24.3200 55.8800
\i (03:48:56) drag_start grid 23.2816 56.2200
\i (03:48:56) drag_stop 33.3636 56.4919
\i (03:48:57) roam x -96
\i (03:48:57) roam x -96
\i (03:48:58) roam x -96
\i (03:48:58) roam x -96
\i (03:48:58) roam x -96
\i (03:48:58) roam x -96
\i (03:48:58) roam x -96
\i (03:48:58) roam x -96
\i (03:48:58) roam x -96
\i (03:48:58) roam x -96
\i (03:48:58) roam x -96
\i (03:48:58) roam x -96
\i (03:48:58) roam x -96
\i (03:48:58) roam x -96
\i (03:48:58) roam x -96
\i (03:48:58) roam x -96
\i (03:49:02) pick grid 10.5162 57.2622
\t (03:49:02) last pick: 10.5200 57.2600
\i (03:49:13) pick grid 11.2639 57.4661
\t (03:49:13) last pick: 11.2600 57.4700
\i (03:50:13) zoom out
\i (03:50:13) setwindow pcb
\i (03:50:13) zoom out 19.5107 59.4145
\t (03:50:13) Grids are drawn 0.6400, 0.6400 apart for enhanced viewability.
\i (03:50:13) trapsize 2266
\i (03:50:13) zoom out
\i (03:50:13) setwindow pcb
\i (03:50:13) zoom out 19.5107 59.4145
\i (03:50:13) trapsize 4531
\i (03:50:14) roam y 96
\i (03:50:14) roam y 96
\i (03:50:14) roam y 96
\i (03:50:14) roam y 96
\i (03:50:15) roam y 96
\i (03:50:15) roam y 96
\i (03:50:15) roam y 96
\i (03:50:15) roam y 96
\i (03:50:15) roam y 96
\i (03:50:15) roam y 96
\i (03:50:15) roam y 96
\i (03:50:15) roam y 96
\i (03:50:16) roam y 96
\i (03:50:16) roam y 96
\i (03:50:16) roam y -96
\i (03:50:16) roam y -96
\i (03:50:17) roam y -96
\i (03:50:17) roam y -96
\i (03:50:17) roam y -96
\i (03:50:17) roam y -96
\i (03:50:17) roam y -96
\i (03:50:17) roam y -96
\i (03:50:17) roam y -96
\i (03:50:17) roam y -96
\i (03:50:18) roam y -96
\i (03:50:18) roam y -96
\i (03:50:21) roam x 96
\i (03:50:21) roam x 96
\i (03:50:21) roam x 96
\i (03:50:21) roam x 96
\i (03:50:21) roam x 96
\i (03:50:21) roam x 96
\i (03:50:21) roam x 96
\i (03:50:21) roam x 96
\i (03:50:21) roam x 96
\i (03:50:21) roam x 96
\i (03:50:22) roam x 96
\i (03:50:22) roam x 96
\i (03:50:22) roam x 96
\i (03:50:22) roam x 96
\i (03:50:22) roam y 96
\i (03:50:22) roam y 96
\i (03:50:22) roam y 96
\i (03:50:22) roam y 96
\i (03:50:23) roam y 96
\i (03:50:23) roam y 96
\i (03:50:23) roam y 96
\i (03:50:23) roam y 96
\i (03:50:23) roam y 96
\i (03:50:23) roam y 96
\i (03:50:26) roam y -96
\i (03:50:26) roam y -96
\i (03:50:32) setwindow form.vf_vis
\i (03:50:32) FORM vf_vis 1 all_colorvisible YES
\i (03:50:35) setwindow pcb
\i (03:50:35) pick grid 76.7401 15.3528
\t (03:50:35) last pick: 76.7400 15.3500
\i (03:50:36) roam x -96
\i (03:50:36) roam x -96
\i (03:50:36) roam x -96
\i (03:50:36) roam x -96
\i (03:50:36) roam x -96
\i (03:50:36) roam x -96
\i (03:50:36) roam x -96
\i (03:50:36) roam x -96
\i (03:50:36) roam x -96
\i (03:50:36) roam x -96
\i (03:50:36) roam x -96
\i (03:50:36) roam x -96
\i (03:50:36) roam x -96
\i (03:50:36) roam x -96
\i (03:50:37) roam y -96
\i (03:50:37) roam y -96
\i (03:50:37) roam y -96
\i (03:50:37) roam y -96
\i (03:50:37) roam y -96
\i (03:50:37) roam y -96
\i (03:50:37) roam y -96
\i (03:50:37) roam y -96
\i (03:51:27) roam y 96
\i (03:51:27) roam y 96
\i (03:51:27) roam y 96
\i (03:51:27) roam y 96
\i (03:51:28) roam y 96
\i (03:51:28) roam y 96
\i (03:51:28) roam y 96
\i (03:51:28) roam y 96
\i (03:51:28) roam y 96
\i (03:51:28) roam y 96
\i (03:51:28) roam y 96
\i (03:51:28) roam y 96
\i (03:51:28) roam x 96
\i (03:51:28) roam x 96
\i (03:51:29) roam x 96
\i (03:51:29) roam x 96
\i (03:51:29) roam x 96
\i (03:51:29) roam x 96
\i (03:51:29) roam x 96
\i (03:51:29) roam x 96
\i (03:51:29) roam x 96
\i (03:51:29) roam x 96
\i (03:51:29) roam x 96
\i (03:51:29) roam x 96
\i (03:51:29) roam x 96
\i (03:51:29) roam x 96
\i (03:51:29) roam x 96
\i (03:51:29) roam x 96
\i (03:51:29) roam x -96
\i (03:51:29) roam x -96
\i (03:51:36) setwindow form.find
\i (03:51:36) FORM find nets NO
\i (03:51:50) setwindow pcb
\i (03:51:50) zoom points
\t (03:51:50) Pick 1st corner of the new window.
\i (03:51:51) pick 90.3338 -2.0472
\t (03:51:51) last pick: 90.3338 -2.0472
\t (03:51:51) Pick to complete the window.
\i (03:51:51) pick 107.9150 -14.7347
\t (03:51:51) last pick: 107.9150 -14.7347
\t (03:51:51) Grids are drawn 0.1600, 0.1600 apart for enhanced viewability.
\i (03:51:51) trapsize 1249
\i (03:52:53) roam y -96
\i (03:52:53) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:54) roam y -96
\i (03:52:55) roam y -96
\i (03:52:55) roam y -96
\i (03:52:55) roam y -96
\i (03:52:55) roam y -96
\i (03:52:55) roam y -96
\i (03:52:55) roam y -96
\i (03:52:55) roam y -96
\i (03:52:55) roam y -96
\i (03:52:55) roam y -96
\i (03:52:55) roam y -96
\i (03:52:55) roam y -96
\i (03:52:55) roam y -96
\i (03:52:56) roam y -96
\i (03:52:56) roam y -96
\i (03:52:56) roam y -96
\i (03:52:56) roam y -96
\i (03:52:56) roam y -96
\i (03:52:56) roam y -96
\i (03:52:56) roam y -96
\i (03:52:56) roam y -96
\i (03:52:56) roam y -96
\i (03:52:56) roam y -96
\i (03:52:56) roam y -96
\i (03:52:56) roam y -96
\i (03:52:56) roam y -96
\i (03:52:56) roam y -96
\i (03:52:56) roam y -96
\i (03:52:56) roam y -96
\i (03:52:57) roam y -96
\i (03:52:57) roam y -96
\i (03:52:57) roam x -96
\i (03:52:57) roam x -96
\i (03:52:57) roam x -96
\i (03:52:57) roam x -96
\i (03:52:57) roam x -96
\i (03:52:57) roam x -96
\i (03:52:57) roam x -96
\i (03:52:57) roam x -96
\i (03:52:57) roam x -96
\i (03:52:57) roam x -96
\i (03:52:57) roam x -96
\i (03:52:57) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:58) roam x -96
\i (03:52:59) roam y 96
\i (03:52:59) roam y 96
\i (03:52:59) roam y 96
\i (03:52:59) roam y 96
\i (03:52:59) roam y 96
\i (03:52:59) roam y 96
\i (03:53:00) roam y 96
\i (03:53:00) roam y 96
\i (03:53:00) roam x -96
\i (03:53:00) roam x -96
\i (03:53:48) pick grid 23.4175 56.8451
\t (03:53:48) last pick: 23.4200 56.8500
\i (03:53:48) roam x -96
\i (03:53:48) roam x -96
\i (03:53:48) roam x -96
\i (03:53:48) roam x -96
\i (03:53:49) roam x -96
\i (03:53:49) roam x -96
\i (03:53:49) roam x -96
\i (03:53:49) roam x -96
\i (03:53:49) roam x -96
\i (03:53:49) roam x -96
\i (03:53:49) roam x -96
\i (03:53:49) roam x -96
\i (03:53:49) roam x -96
\i (03:53:49) roam x -96
\i (03:54:11) show element
\i (03:54:14) setwindow form.find
\i (03:54:14) FORM find nets YES
\i (03:54:21) setwindow pcb
\i (03:54:21) pick grid 11.4542 57.6693
\t (03:54:21) last pick: 11.4500 57.6700
\i (03:54:38) pick grid 10.5551 57.1448
\t (03:54:38) last pick: 10.5600 57.1400
\i (03:54:44) pick grid 11.3543 57.1448
\t (03:54:44) last pick: 11.3500 57.1400
\i (04:25:43) pick grid 4.5360 52.9240
\t (04:25:43) last pick: 4.5400 52.9200
\i (04:26:01) pick grid 27.1637 57.5694
\t (04:26:01) last pick: 27.1600 57.5700
\i (04:26:07) pick grid 26.2896 57.3196
\t (04:26:07) last pick: 26.2900 57.3200
\i (04:26:15) pick grid 26.9389 57.2697
\t (04:26:15) last pick: 26.9400 57.2700
\i (04:26:19) pick grid 27.1138 57.2947
\t (04:26:19) last pick: 27.1100 57.2900
\i (04:28:02) pick grid 9.3563 57.6943
\t (04:28:02) last pick: 9.3600 57.6900
\i (04:28:18) pick grid 10.1305 57.6193
\t (04:28:18) last pick: 10.1300 57.6200
\i (04:29:36) roam x 96
\i (04:29:36) roam x 96
\i (04:29:36) roam x 96
\i (04:29:36) roam x 96
\i (04:29:36) roam x 96
\i (04:29:36) roam x 96
\i (04:29:36) roam x 96
\i (04:29:36) roam x 96
\i (04:29:36) roam x 96
\i (04:29:36) roam x 96
\i (04:29:36) roam x 96
\i (04:29:36) roam x 96
\i (04:29:37) roam x 96
\i (04:29:37) roam x 96
\i (04:29:37) roam x 96
\i (04:29:37) roam x 96
\i (04:29:37) roam x 96
\i (04:29:37) roam x 96
\i (04:29:37) roam y 96
\i (04:29:37) roam y 96
\i (04:29:37) roam y 96
\i (04:29:37) roam y 96
\i (04:29:37) roam y 96
\i (04:29:37) roam y 96
\i (04:29:38) roam y 96
\i (04:29:38) roam y 96
\i (04:29:40) pick grid 47.3939 50.2016
\t (04:29:40) last pick: 47.3900 50.2000
\i (04:34:48) roam y -96
\i (04:34:48) roam y -96
\i (04:34:48) roam y -96
\i (04:34:48) roam y -96
\i (04:34:48) roam y -96
\i (04:34:48) roam y -96
\i (04:34:49) roam x -96
\i (04:34:49) roam x -96
\i (04:34:49) roam x -96
\i (04:34:49) roam x -96
\i (04:34:49) roam x -96
\i (04:34:49) roam x -96
\i (04:34:49) roam x -96
\i (04:34:49) roam x -96
\i (04:34:49) roam x -96
\i (04:34:49) roam x -96
\i (04:34:49) roam x -96
\i (04:34:49) roam x -96
\i (04:34:50) roam x -96
\i (04:34:50) roam x -96
\i (04:34:50) roam x -96
\i (04:34:50) roam x -96
\i (04:34:50) roam y -96
\i (04:34:50) roam y -96
\i (04:52:16) roam x 96
\i (04:52:16) roam x 96
\i (04:52:16) roam x 96
\i (04:52:16) roam x 96
\i (04:52:16) roam x 96
\i (04:52:16) roam x 96
\i (04:52:16) roam x 96
\i (04:52:16) roam x 96
\i (04:52:17) roam x 96
\i (04:52:17) roam x 96
\i (04:52:17) roam x 96
\i (04:52:17) roam x 96
\i (04:52:17) roam x 96
\i (04:52:17) roam x 96
\i (04:52:17) roam x 96
\i (04:52:17) roam x 96
\i (04:52:17) roam y 96
\i (04:52:17) roam y 96
\i (04:52:17) roam y 96
\i (04:52:17) roam y 96
\i (04:52:18) roam y 96
\i (04:52:18) roam y 96
\i (25:36:11) pick grid 48.1181 46.3554
\t (25:36:11) last pick: 48.1200 46.3600
\i (25:41:34) roam y -96
\i (25:41:34) roam y -96
\i (25:41:34) roam y -96
\i (25:41:34) roam y -96
\i (25:41:35) roam y -96
\i (25:41:35) roam y -96
\i (25:41:35) roam y -96
\i (25:41:35) roam y -96
\i (25:41:35) roam x -96
\i (25:41:35) roam x -96
\i (25:41:36) roam x -96
\i (25:41:36) roam x -96
\i (25:41:36) roam x -96
\i (25:41:36) roam x -96
\i (73:17:31) zoom out
\i (73:17:31) setwindow pcb
\i (73:17:31) zoom out 33.7073 61.0909
\t (73:17:31) Grids are drawn 0.6400, 0.6400 apart for enhanced viewability.
\i (73:17:31) trapsize 2498
\i (117:09:46) pick grid 48.1929 50.0018
\t (117:09:46) last pick: 48.1900 50.0000
\i (123:55:16) pick grid 7.4830 61.8901
\t (123:55:16) last pick: 7.4800 61.8900
\i (123:55:21) exit
\e (123:55:23) Do you want to save the changes you made to fmc_tlu_v1a_66_gloss4b.brd?
\i (123:55:25) fillin no
\t (123:55:26) Journal end - Mon May 11 18:34:41 2015
\t (00:01:45) allegro 16.6 S035 (v16-6-112CR) Linux I32
\t (00:01:45) Journal start - Tue Jul 14 10:36:00 2015
\t (00:01:45) Host=voltar.phy.bris.ac.uk User=phdgc Pid=6892 CPUs=8
\t (00:01:45) CmdLine= /software/CAD/Cadence/2014_2015/SPB166/tools/pcb/bin/allegro.exe -proj /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/design_files/pc051a_toplevel.cpm -product Concept_HDL_studio -mpssession phdgc_ProjectMgr20240 -mpshost voltar.phy.bris.ac.uk
\t (00:01:45)
\d (00:01:45) Design opened: /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/physical/fmc_tlu_v1a_66_gloss4b.brd
\i (00:01:47) zoom points
\t (00:01:47) Pick 1st corner of the new window.
\i (00:01:47) pick -7.3458 46.9349
\t (00:01:47) last pick: -7.3458 46.9349
\t (00:01:47) Pick to complete the window.
\i (00:01:48) pick 11.4776 13.4710
\t (00:01:48) last pick: 11.4776 13.4710
\t (00:01:48) Grids are drawn 0.3200, 0.3200 apart for enhanced viewability.
\i (00:01:48) trapsize 2562
\i (00:01:52) setwindow form.vf_vis
\i (00:01:52) FORM vf_vis 1 all_colorvisible YES
\i (00:01:55) setwindow pcb
\i (00:01:55) zoom points
\t (00:01:55) Pick 1st corner of the new window.
\i (00:01:56) pick 10.5904 39.0429
\t (00:01:56) last pick: 10.5904 39.0429
\t (00:01:56) Pick to complete the window.
\i (00:01:57) pick 17.6624 28.3324
\t (00:01:57) last pick: 17.6624 28.3324
\t (00:01:57) Grids are drawn 0.0800, 0.0800 apart for enhanced viewability.
\i (00:01:57) trapsize 820
\i (00:01:59) roam x 96
\i (00:01:59) roam x 96
\i (00:01:59) roam x 96
\i (00:01:59) roam x 96
\i (00:01:59) roam x 96
\i (00:01:59) roam x 96
\i (00:01:59) roam x 96
\i (00:01:59) roam x 96
\i (00:01:59) roam x 96
\i (00:01:59) roam x 96
\i (00:02:00) roam x 96
\i (00:02:00) roam x 96
\i (00:02:00) roam y -96
\i (00:02:00) roam y -96
\i (00:02:00) roam y -96
\i (00:02:00) roam y -96
\i (00:02:00) roam y -96
\i (00:02:00) roam y -96
\i (00:02:00) roam y -96
\i (00:02:00) roam y -96
\i (00:02:00) roam y -96
\i (00:02:00) roam y -96
\i (00:02:00) roam y -96
\i (00:02:00) roam y -96
\i (00:02:01) roam y -96
\i (00:02:01) roam y -96
\i (00:02:01) roam y -96
\i (00:02:01) roam y -96
\i (00:02:01) roam y -96
\i (00:02:01) roam y -96
\i (00:02:01) roam y -96
\i (00:02:01) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:02) roam y -96
\i (00:02:03) roam y -96
\i (00:02:03) roam y -96
\i (00:26:10) trapsize 819
\i (00:26:10) trapsize 809
\i (00:26:10) trapsize 721
\i (00:26:11) trapsize 697
\i (00:26:11) trapsize 690
\i (00:26:11) trapsize 688
\i (00:26:16) setwindow form.vf_vis
\i (00:26:16) FORM vf_vis 1 all_colorvisible NO
\i (00:26:17) FORM vf_vis 2 all_colorvisible YES
\i (00:26:18) setwindow pcb
\i (00:26:18) roam start
\i (00:26:18) roam x -64
\i (00:26:18) roam y 16
\i (00:26:18) roam x -16
\i (00:26:18) roam x -16
\i (00:26:18) roam x -32
\i (00:26:18) roam y -32
\i (00:26:19) roam x -16
\i (00:26:19) roam y -32
\i (00:26:19) roam x -16
\i (00:26:19) roam y -32
\i (00:26:19) roam x -16
\i (00:26:19) roam y -32
\i (00:26:19) roam x -16
\i (00:26:19) roam y -48
\i (00:26:19) roam x -16
\i (00:26:19) roam y -32
\i (00:26:19) roam x -16
\i (00:26:19) roam y -48
\i (00:26:19) roam y -32
\i (00:26:19) roam y 16
\i (00:26:19) roam y 48
\i (00:26:19) roam x -16
\i (00:26:19) roam y 48
\i (00:26:19) roam y 16
\i (00:26:19) roam x -16
\i (00:26:19) roam y 64
\i (00:26:19) roam y 48
\i (00:26:19) roam x -16
\i (00:26:19) roam y 96
\i (00:26:19) roam y 16
\i (00:26:19) roam x -16
\i (00:26:19) roam y 96
\i (00:26:19) roam x -16
\i (00:26:19) roam y 64
\i (00:26:19) roam y 64
\i (00:26:19) roam x -16
\i (00:26:19) roam y 64
\i (00:26:19) roam y 48
\i (00:26:19) roam y 48
\i (00:26:19) roam y 48
\i (00:26:19) roam y 48
\i (00:26:19) roam y 32
\i (00:26:19) roam y 32
\i (00:26:19) roam y 16
\i (00:26:19) roam y 16
\i (00:26:19) roam y 16
\i (00:26:19) roam y 16
\i (00:26:19) roam y 16
\i (00:26:19) roam x 16
\i (00:26:19) roam y 16
\i (00:26:20) roam y 16
\i (00:26:20) roam y 16
\i (00:26:20) roam y 16
\i (00:26:20) roam y 16
\i (00:26:20) roam y 16
\i (00:26:20) roam y 16
\i (00:26:20) roam y 16
\i (00:26:20) roam x 16
\i (00:26:20) roam y 32
\i (00:26:20) roam y 32
\i (00:26:20) roam y 32
\i (00:26:20) roam x 16
\i (00:26:20) roam y 32
\i (00:26:20) roam y 32
\i (00:26:20) roam y 32
\i (00:26:20) roam x 16
\i (00:26:20) roam y 48
\i (00:26:20) roam y 32
\i (00:26:20) roam y 32
\i (00:26:20) roam y 32
\i (00:26:20) roam y 32
\i (00:26:20) roam y 32
\i (00:26:20) roam y 16
\i (00:26:20) roam x 16
\i (00:26:20) roam y 32
\i (00:26:20) roam y 16
\i (00:26:20) roam y 16
\i (00:26:20) roam x 16
\i (00:26:20) roam x 16
\i (00:26:20) roam x 16
\i (00:26:20) roam y -16
\i (00:26:20) roam x 16
\i (00:26:20) roam x 16
\i (00:26:20) roam x 32
\i (00:26:20) roam y -32
\i (00:26:20) roam x 32
\i (00:26:20) roam y -16
\i (00:26:20) roam x 48
\i (00:26:20) roam y -32
\i (00:26:21) roam x 48
\i (00:26:21) roam y -32
\i (00:26:21) roam x 32
\i (00:26:21) roam y -32
\i (00:26:21) roam x 32
\i (00:26:21) roam y -16
\i (00:26:21) roam x 48
\i (00:26:21) roam y -32
\i (00:26:21) roam x 32
\i (00:26:21) roam y -32
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 32
\i (00:26:21) roam y -32
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 32
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:21) roam x 16
\i (00:26:21) roam y -16
\i (00:26:22) roam x 16
\i (00:26:22) roam y -16
\i (00:26:22) roam x 16
\i (00:26:22) roam y -16
\i (00:26:22) roam y -16
\i (00:26:22) roam x 16
\i (00:26:22) roam x 16
\i (00:26:22) roam y -16
\i (00:26:22) roam x 16
\i (00:26:22) roam x 16
\i (00:26:22) roam y -16
\i (00:26:22) roam x 32
\i (00:26:22) roam x 32
\i (00:26:22) roam y -16
\i (00:26:22) roam x 48
\i (00:26:22) roam y -16
\i (00:26:22) roam x 64
\i (00:26:22) roam y -16
\i (00:26:22) roam x 48
\i (00:26:22) roam x 64
\i (00:26:22) roam y -16
\i (00:26:22) roam x 80
\i (00:26:22) roam y -16
\i (00:26:22) roam x 48
\i (00:26:22) roam x 64
\i (00:26:22) roam y -16
\i (00:26:22) roam x 48
\i (00:26:22) roam x 48
\i (00:26:22) roam y -16
\i (00:26:22) roam x 32
\i (00:26:22) roam x 32
\i (00:26:22) roam y -16
\i (00:26:22) roam x 16
\i (00:26:22) roam x 16
\i (00:26:22) roam y 16
\i (00:26:22) roam y 16
\i (00:26:22) roam y 32
\i (00:26:22) roam y 32
\i (00:26:22) roam x -16
\i (00:26:22) roam y 48
\i (00:26:22) roam y 48
\i (00:26:22) roam y 48
\i (00:26:22) roam y 48
\i (00:26:22) roam y 64
\i (00:26:22) roam y 32
\i (00:26:22) roam y 16
\i (00:26:23) roam y 16
\i (00:26:23) roam y 16
\i (00:26:23) roam x -16
\i (00:26:23) roam x -16
\i (00:26:23) roam x -16
\i (00:26:23) roam x -32
\i (00:26:23) roam x -32
\i (00:26:23) roam x -16
\i (00:26:23) roam x -32
\i (00:26:23) roam x -32
\i (00:26:23) roam x -16
\i (00:26:23) roam x -32
\i (00:26:23) roam x -32
\i (00:26:23) roam x -16
\i (00:26:23) roam x -16
\i (00:26:24) roam x -16
\i (00:26:24) roam x -16
\i (00:26:24) roam x -16
\i (00:26:24) roam x -16
\i (00:26:24) roam x -16
\i (00:26:24) roam x -16
\i (00:26:24) roam x -16
\i (00:26:24) roam x -16
\i (00:26:24) roam x -16
\i (00:26:25) roam x -16
\i (00:26:25) roam end
\i (00:26:26) roam start
\i (00:26:26) roam x -16
\i (00:26:26) roam y 64
\i (00:26:26) roam x -48
\i (00:26:26) roam y 96
\i (00:26:26) roam x -32
\i (00:26:26) roam y 112
\i (00:26:26) roam x -16
\i (00:26:26) roam y 32
\i (00:26:27) roam y 48
\i (00:26:27) roam x -16
\i (00:26:27) roam y 96
\i (00:26:27) roam x -16
\i (00:26:27) roam y 112
\i (00:26:27) roam x -16
\i (00:26:27) roam y 48
\i (00:26:27) roam y 80
\i (00:26:27) roam x -16
\i (00:26:27) roam y 80
\i (00:26:27) roam x -16
\i (00:26:27) roam y 64
\i (00:26:27) roam y 80
\i (00:26:27) roam x -16
\i (00:26:27) roam y 64
\i (00:26:27) roam x -16
\i (00:26:27) roam y 64
\i (00:26:27) roam y 64
\i (00:26:27) roam x -16
\i (00:26:27) roam y 64
\i (00:26:27) roam y 48
\i (00:26:27) roam x -16
\i (00:26:27) roam y 48
\i (00:26:27) roam y 80
\i (00:26:27) roam x -16
\i (00:26:27) roam y 48
\i (00:26:27) roam y 48
\i (00:26:27) roam x -16
\i (00:26:27) roam y 48
\i (00:26:27) roam y 48
\i (00:26:27) roam y 32
\i (00:26:27) roam y 16
\i (00:26:27) roam y 16
\i (00:26:27) roam y 16
\i (00:26:27) roam y 16
\i (00:26:27) roam x -16
\i (00:26:27) roam y 16
\i (00:26:27) roam y -48
\i (00:26:27) roam x -16
\i (00:26:27) roam y 32
\i (00:26:27) roam y 16
\i (00:26:27) roam y 16
\i (00:26:28) roam y 16
\i (00:26:28) roam x 16
\i (00:26:28) roam y 16
\i (00:26:28) roam y 16
\i (00:26:28) roam x 16
\i (00:26:28) roam x 16
\i (00:26:28) roam y 32
\i (00:26:28) roam x 32
\i (00:26:28) roam y 32
\i (00:26:28) roam x 32
\i (00:26:28) roam y 48
\i (00:26:28) roam x 64
\i (00:26:28) roam y 48
\i (00:26:28) roam x 48
\i (00:26:28) roam y 80
\i (00:26:28) roam x 80
\i (00:26:28) roam y 64
\i (00:26:28) roam x 112
\i (00:26:28) roam y 96
\i (00:26:28) roam x 16
\i (00:26:28) roam y 32
\i (00:26:28) roam x 96
\i (00:26:28) roam y 112
\i (00:26:28) roam x 64
\i (00:26:28) roam y 80
\i (00:26:28) roam x 48
\i (00:26:28) roam y 64
\i (00:26:28) roam x 64
\i (00:26:28) roam y 64
\i (00:26:28) roam x 48
\i (00:26:28) roam y 64
\i (00:26:28) roam x 64
\i (00:26:28) roam y 48
\i (00:26:28) roam x 64
\i (00:26:28) roam y 48
\i (00:26:28) roam x 48
\i (00:26:28) roam y 48
\i (00:26:28) roam x 48
\i (00:26:28) roam y 48
\i (00:26:28) roam x 48
\i (00:26:28) roam y 32
\i (00:26:28) roam x 48
\i (00:26:28) roam y 16
\i (00:26:28) roam x 48
\i (00:26:28) roam y 32
\i (00:26:28) roam x 16
\i (00:26:28) roam y 16
\i (00:26:28) roam x 16
\i (00:26:28) roam y 16
\i (00:26:28) roam x -16
\i (00:26:28) roam y 16
\i (00:26:29) roam x -32
\i (00:26:29) roam y 16
\i (00:26:29) roam x -80
\i (00:26:29) roam y 48
\i (00:26:29) roam x -128
\i (00:26:29) roam y 112
\i (00:26:29) roam x -96
\i (00:26:29) roam y 80
\i (00:26:29) roam x -112
\i (00:26:29) roam y 80
\i (00:26:29) roam x -96
\i (00:26:29) roam y 96
\i (00:26:29) roam x -80
\i (00:26:29) roam y 96
\i (00:26:29) roam x -80
\i (00:26:29) roam y 96
\i (00:26:29) roam x -64
\i (00:26:29) roam y 96
\i (00:26:29) roam x -80
\i (00:26:29) roam y 144
\i (00:26:29) roam x -32
\i (00:26:29) roam y 48
\i (00:26:29) roam x -80
\i (00:26:29) roam y 144
\i (00:26:29) roam x -32
\i (00:26:29) roam y 80
\i (00:26:29) roam x -48
\i (00:26:29) roam y 80
\i (00:26:29) roam x -16
\i (00:26:29) roam y 80
\i (00:26:29) roam x -32
\i (00:26:29) roam y 64
\i (00:26:29) roam x -16
\i (00:26:29) roam y 48
\i (00:26:29) roam x -16
\i (00:26:29) roam y 32
\i (00:26:29) roam x -16
\i (00:26:29) roam y 16
\i (00:26:29) roam y 32
\i (00:26:29) roam x -16
\i (00:26:29) roam y 16
\i (00:26:29) roam x -16
\i (00:26:29) roam y 16
\i (00:26:29) roam x -16
\i (00:26:29) roam y 16
\i (00:26:29) roam x -16
\i (00:26:29) roam y -16
\i (00:26:29) roam y -16
\i (00:26:29) roam x -16
\i (00:26:29) roam y -80
\i (00:26:29) roam x -16
\i (00:26:29) roam y 16
\i (00:26:29) roam x -16
\i (00:26:30) roam x -16
\i (00:26:30) roam x -64
\i (00:26:30) roam x -48
\i (00:26:30) roam x -64
\i (00:26:30) roam x -80
\i (00:26:30) roam x -112
\i (00:26:30) roam x -112
\i (00:26:30) roam y -16
\i (00:26:30) roam x -128
\i (00:26:30) roam x -144
\i (00:26:30) roam x -144
\i (00:26:30) roam x -224
\i (00:26:30) roam x -112
\i (00:26:30) roam x -96
\i (00:26:30) roam x -80
\i (00:26:30) roam x -64
\i (00:26:30) roam x -48
\i (00:26:30) roam x -32
\i (00:26:30) roam y 16
\i (00:26:30) roam x -16
\i (00:26:30) roam x -16
\i (00:26:30) roam x -16
\i (00:26:30) roam y 16
\i (00:26:30) roam x -16
\i (00:26:30) roam x -16
\i (00:26:30) roam x -32
\i (00:26:30) roam x -48
\i (00:26:30) roam x -64
\i (00:26:30) roam x -48
\i (00:26:30) roam x -64
\i (00:26:30) roam x -64
\i (00:26:30) roam x -48
\i (00:26:30) roam x -96
\i (00:26:30) roam x -48
\i (00:26:30) roam y -16
\i (00:26:30) roam x -32
\i (00:26:30) roam x -32
\i (00:26:30) roam y -16
\i (00:26:30) roam x -48
\i (00:26:30) roam x -16
\i (00:26:30) roam x -32
\i (00:26:30) roam x -32
\i (00:26:30) roam x -16
\i (00:26:30) roam x -32
\i (00:26:30) roam x -16
\i (00:26:30) roam x -32
\i (00:26:30) roam x -32
\i (00:26:30) roam x -32
\i (00:26:30) roam x -16
\i (00:26:30) roam x -32
\i (00:26:30) roam x -32
\i (00:26:30) roam x -32
\i (00:26:30) roam x -32
\i (00:26:30) roam x -32
\i (00:26:30) roam y -16
\i (00:26:30) roam x -16
\i (00:26:30) roam x -16
\i (00:26:31) roam y -16
\i (00:26:31) roam y -16
\i (00:26:31) roam y -16
\i (00:26:31) roam y -16
\i (00:26:31) roam y -32
\i (00:26:31) roam x 16
\i (00:26:31) roam y -64
\i (00:26:31) roam x 16
\i (00:26:31) roam y -64
\i (00:26:31) roam y -64
\i (00:26:31) roam y -128
\i (00:26:31) roam y -96
\i (00:26:31) roam x 16
\i (00:26:31) roam y -80
\i (00:26:31) roam y -80
\i (00:26:31) roam y -96
\i (00:26:31) roam y -80
\i (00:26:31) roam y -64
\i (00:26:31) roam y -64
\i (00:26:31) roam x -16
\i (00:26:31) roam y -48
\i (00:26:31) roam y -48
\i (00:26:31) roam y -32
\i (00:26:31) roam y -16
\i (00:26:31) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam x 16
\i (00:26:32) roam y -32
\i (00:26:32) roam y -32
\i (00:26:32) roam y -32
\i (00:26:32) roam x 16
\i (00:26:32) roam y -48
\i (00:26:32) roam y -32
\i (00:26:32) roam y -48
\i (00:26:32) roam x 16
\i (00:26:32) roam y -32
\i (00:26:32) roam y -48
\i (00:26:32) roam y -48
\i (00:26:32) roam y -32
\i (00:26:32) roam x 16
\i (00:26:32) roam y -48
\i (00:26:32) roam y -32
\i (00:26:32) roam y -48
\i (00:26:32) roam x 16
\i (00:26:32) roam y -48
\i (00:26:32) roam y -48
\i (00:26:32) roam y -32
\i (00:26:32) roam x 16
\i (00:26:32) roam y -48
\i (00:26:32) roam y -32
\i (00:26:32) roam y -32
\i (00:26:32) roam y -16
\i (00:26:32) roam y -32
\i (00:26:32) roam y -16
\i (00:26:32) roam y -32
\i (00:26:32) roam y -16
\i (00:26:32) roam y -32
\i (00:26:32) roam y -16
\i (00:26:32) roam y -32
\i (00:26:32) roam y -32
\i (00:26:32) roam y -16
\i (00:26:32) roam x 16
\i (00:26:32) roam y -32
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam y -32
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:32) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -32
\i (00:26:33) roam x -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -32
\i (00:26:33) roam y -16
\i (00:26:33) roam y -32
\i (00:26:33) roam y -16
\i (00:26:33) roam y -32
\i (00:26:33) roam y -16
\i (00:26:33) roam y -32
\i (00:26:33) roam y -16
\i (00:26:33) roam y -32
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -32
\i (00:26:33) roam y -16
\i (00:26:33) roam x -32
\i (00:26:33) roam y -16
\i (00:26:33) roam y -32
\i (00:26:33) roam y -32
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:33) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -32
\i (00:26:34) roam y -32
\i (00:26:34) roam y -16
\i (00:26:34) roam y -32
\i (00:26:34) roam y -32
\i (00:26:34) roam x -16
\i (00:26:34) roam y -16
\i (00:26:34) roam x -32
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -32
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam x -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:34) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -32
\i (00:26:35) roam x 16
\i (00:26:35) roam y -32
\i (00:26:35) roam y -32
\i (00:26:35) roam y -32
\i (00:26:35) roam y -16
\i (00:26:35) roam x 16
\i (00:26:35) roam y -32
\i (00:26:35) roam y -16
\i (00:26:35) roam y -32
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam x 16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam x 16
\i (00:26:35) roam y -32
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam x 16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:35) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -32
\i (00:26:36) roam x 16
\i (00:26:36) roam y -32
\i (00:26:36) roam y -16
\i (00:26:36) roam y -32
\i (00:26:36) roam y -32
\i (00:26:36) roam y -32
\i (00:26:36) roam y -32
\i (00:26:36) roam x 16
\i (00:26:36) roam y -32
\i (00:26:36) roam y -16
\i (00:26:36) roam y -32
\i (00:26:36) roam y -16
\i (00:26:36) roam y -32
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:36) roam y -16
\i (00:26:37) roam y -16
\i (00:26:37) roam end
\i (00:26:53) exit
\t (00:26:54) Journal end - Tue Jul 14 11:01:09 2015
Cadence/worklib/fmc_tlu_toplevel_c/physical/eco.txt
View file @ a648eb8d
This source diff could not be displayed because it is too large. You can view the blob instead.
Cadence/worklib/fmc_tlu_toplevel_c/physical/eco.txt,1
View file @ a648eb8d
......@@ -2,19 +2,603 @@
| ECO REPORT |
| Page 1 |
|------------------------------------------------------------------------------|
| X:.../Cadence/worklib/fmc_tlu_toplevel/physical/fmc_tlu_v1_44.brd |
| Thu Dec 06 10:13:00 2012 |
| .../Cadence/worklib/fmc_tlu_toplevel_b/physical/fmc_tlu_v1a_66_gloss4.brd |
| Tue Feb 11 18:41:15 2014 |
|------------------------------------------------------------------------------|
| NET CHANGES |
| SLOT PROPERTIES added to design |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
| net name | type of change | pin_id | x | y | to net |
| slot_id | x | y | property | value |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
DUMMY8 pins MOVED FROM this net (to net name listed on right)
J4.G30 89.4241 -0.8565
FMC_LA<29>
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
FMC_LA<29> pins ADDED TO this new net
PL1.6 21.7560 4.8870
C1.2 128.601 49.4930 HARD_LOCATION
C1.2 128.601 49.4930 NO_SWAP_GATE_E
C6.2 41.8000 44.9000 HARD_LOCATION
C6.2 41.8000 44.9000 NO_SWAP_GATE_E
C29.2 43.3500 23.7000 HARD_LOCATION
C29.2 43.3500 23.7000 NO_SWAP_GATE_E
C40.2 43.9000 16.2500 HARD_LOCATION
C40.2 43.9000 16.2500 NO_SWAP_GATE_E
C42.2 44.0000 11.4000 HARD_LOCATION
C42.2 44.0000 11.4000 NO_SWAP_GATE_E
C46.2 31.6000 63.3430 HARD_LOCATION
C46.2 31.6000 63.3430 NO_SWAP_GATE_E
C47.2 25.8000 63.3430 HARD_LOCATION
C47.2 25.8000 63.3430 NO_SWAP_GATE_E
C48.2 14.4000 63.3430 HARD_LOCATION
C48.2 14.4000 63.3430 NO_SWAP_GATE_E
C49.2 9.0000 63.3430 HARD_LOCATION
C49.2 9.0000 63.3430 NO_SWAP_GATE_E
C50.2 20.9000 59.5090 HARD_LOCATION
C50.2 20.9000 59.5090 NO_SWAP_GATE_E
C51.2 37.4000 59.5040 HARD_LOCATION
C51.2 37.4000 59.5040 NO_SWAP_GATE_E
C52.2 40.5000 54.7240 HARD_LOCATION
C52.2 40.5000 54.7240 NO_SWAP_GATE_E
C53.2 53.9000 54.5000 HARD_LOCATION
C53.2 53.9000 54.5000 NO_SWAP_GATE_E
C54.2 26.4600 53.2400 HARD_LOCATION
C54.2 26.4600 53.2400 NO_SWAP_GATE_E
C55.2 10.3100 53.0200 HARD_LOCATION
C55.2 10.3100 53.0200 NO_SWAP_GATE_E
C56.2 47.8100 43.2700 HARD_LOCATION
C56.2 47.8100 43.2700 NO_SWAP_GATE_E
C65.2 49.7000 30.0000 HARD_LOCATION
C65.2 49.7000 30.0000 NO_SWAP_GATE_E
C70.2 50.3000 19.6300 HARD_LOCATION
C70.2 50.3000 19.6300 NO_SWAP_GATE_E
C71.2 47.3000 17.8040 HARD_LOCATION
C71.2 47.3000 17.8040 NO_SWAP_GATE_E
C10_1.2 62.2500 30.2000 HARD_LOCATION
C10_1.2 62.2500 30.2000 NO_SWAP_GATE_E
C10_2.2 81.2500 30.2000 HARD_LOCATION
C10_2.2 81.2500 30.2000 NO_SWAP_GATE_E
C10_3.2 100.250 30.2000 HARD_LOCATION
C10_3.2 100.250 30.2000 NO_SWAP_GATE_E
C10_4.2 119.250 30.2000 HARD_LOCATION
|------------------------------------------------------------------------------|
| ECO REPORT |
| Page 2 |
|------------------------------------------------------------------------------|
| .../Cadence/worklib/fmc_tlu_toplevel_b/physical/fmc_tlu_v1a_66_gloss4.brd |
| Tue Feb 11 18:41:15 2014 |
|------------------------------------------------------------------------------|
| SLOT PROPERTIES added to design |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
| slot_id | x | y | property | value |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
C10_4.2 119.250 30.2000 NO_SWAP_GATE_E
C10_6.2 13.8000 26.3000 HARD_LOCATION
C10_6.2 13.8000 26.3000 NO_SWAP_GATE_E
C11_6.2 13.3000 37.5000 HARD_LOCATION
C11_6.2 13.3000 37.5000 NO_SWAP_GATE_E
C12_6.2 3.6000 37.4000 HARD_LOCATION
C12_6.2 3.6000 37.4000 NO_SWAP_GATE_E
C1_1.2 65.7000 46.1000 HARD_LOCATION
C1_1.2 65.7000 46.1000 NO_SWAP_GATE_E
C1_2.2 84.7000 46.1000 HARD_LOCATION
C1_2.2 84.7000 46.1000 NO_SWAP_GATE_E
C1_3.2 103.700 46.1000 HARD_LOCATION
C1_3.2 103.700 46.1000 NO_SWAP_GATE_E
C1_4.2 122.700 46.1000 HARD_LOCATION
C1_4.2 122.700 46.1000 NO_SWAP_GATE_E
C1_6.2 -0.6000 34.4000 HARD_LOCATION
C1_6.2 -0.6000 34.4000 NO_SWAP_GATE_E
C2_1.2 60.5500 32.8000 HARD_LOCATION
C2_1.2 60.5500 32.8000 NO_SWAP_GATE_E
C2_2.2 79.5500 32.8000 HARD_LOCATION
C2_2.2 79.5500 32.8000 NO_SWAP_GATE_E
C2_3.2 98.5500 32.8000 HARD_LOCATION
C2_3.2 98.5500 32.8000 NO_SWAP_GATE_E
C2_4.2 117.550 32.8000 HARD_LOCATION
C2_4.2 117.550 32.8000 NO_SWAP_GATE_E
C2_6.2 3.1000 24.2000 HARD_LOCATION
C2_6.2 3.1000 24.2000 NO_SWAP_GATE_E
C3_1.2 74.0500 18.4000 HARD_LOCATION
C3_1.2 74.0500 18.4000 NO_SWAP_GATE_E
C3_2.2 93.0500 18.4000 HARD_LOCATION
C3_2.2 93.0500 18.4000 NO_SWAP_GATE_E
C3_3.2 112.050 18.4000 HARD_LOCATION
C3_3.2 112.050 18.4000 NO_SWAP_GATE_E
C3_4.2 131.050 18.4000 HARD_LOCATION
C3_4.2 131.050 18.4000 NO_SWAP_GATE_E
C3_6.2 -0.4000 11.9000 HARD_LOCATION
C3_6.2 -0.4000 11.9000 NO_SWAP_GATE_E
C4_1.2 72.6500 22.7000 HARD_LOCATION
C4_1.2 72.6500 22.7000 NO_SWAP_GATE_E
C4_2.2 91.6500 22.7000 HARD_LOCATION
C4_2.2 91.6500 22.7000 NO_SWAP_GATE_E
C4_3.2 110.650 22.7000 HARD_LOCATION
C4_3.2 110.650 22.7000 NO_SWAP_GATE_E
C4_4.2 129.650 22.7000 HARD_LOCATION
C4_4.2 129.650 22.7000 NO_SWAP_GATE_E
|------------------------------------------------------------------------------|
| ECO REPORT |
| Page 3 |
|------------------------------------------------------------------------------|
| .../Cadence/worklib/fmc_tlu_toplevel_b/physical/fmc_tlu_v1a_66_gloss4.brd |
| Tue Feb 11 18:41:15 2014 |
|------------------------------------------------------------------------------|
| SLOT PROPERTIES added to design |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
| slot_id | x | y | property | value |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
C4_6.2 15.2000 6.5000 HARD_LOCATION
C4_6.2 15.2000 6.5000 NO_SWAP_GATE_E
C5_1.2 71.5000 26.3000 HARD_LOCATION
C5_1.2 71.5000 26.3000 NO_SWAP_GATE_E
C5_2.2 90.5000 26.3000 HARD_LOCATION
C5_2.2 90.5000 26.3000 NO_SWAP_GATE_E
C5_3.2 109.500 26.3000 HARD_LOCATION
C5_3.2 109.500 26.3000 NO_SWAP_GATE_E
C5_4.2 128.500 26.3000 HARD_LOCATION
C5_4.2 128.500 26.3000 NO_SWAP_GATE_E
C5_6.2 -0.6000 19.1000 HARD_LOCATION
C5_6.2 -0.6000 19.1000 NO_SWAP_GATE_E
C6_1.2 59.6000 28.4000 HARD_LOCATION
C6_1.2 59.6000 28.4000 NO_SWAP_GATE_E
C6_2.2 78.6000 28.4000 HARD_LOCATION
C6_2.2 78.6000 28.4000 NO_SWAP_GATE_E
C6_3.2 97.6000 28.4000 HARD_LOCATION
C6_3.2 97.6000 28.4000 NO_SWAP_GATE_E
C6_4.2 116.600 28.4000 HARD_LOCATION
C6_4.2 116.600 28.4000 NO_SWAP_GATE_E
C6_6.2 9.2000 6.5000 HARD_LOCATION
C6_6.2 9.2000 6.5000 NO_SWAP_GATE_E
C7_1.2 67.9000 30.2000 HARD_LOCATION
C7_1.2 67.9000 30.2000 NO_SWAP_GATE_E
C7_2.2 86.9000 30.2000 HARD_LOCATION
C7_2.2 86.9000 30.2000 NO_SWAP_GATE_E
C7_3.2 105.900 30.2000 HARD_LOCATION
C7_3.2 105.900 30.2000 NO_SWAP_GATE_E
C7_4.2 124.900 30.2000 HARD_LOCATION
C7_4.2 124.900 30.2000 NO_SWAP_GATE_E
C7_6.2 2.4000 -8.4000 HARD_LOCATION
C7_6.2 2.4000 -8.4000 NO_SWAP_GATE_E
C8_1.2 59.3000 26.7000 HARD_LOCATION
C8_1.2 59.3000 26.7000 NO_SWAP_GATE_E
C8_2.2 78.3000 26.7000 HARD_LOCATION
C8_2.2 78.3000 26.7000 NO_SWAP_GATE_E
C8_3.2 97.3000 26.7000 HARD_LOCATION
C8_3.2 97.3000 26.7000 NO_SWAP_GATE_E
C8_4.2 116.300 26.7000 HARD_LOCATION
C8_4.2 116.300 26.7000 NO_SWAP_GATE_E
C8_6.2 18.7000 18.9000 HARD_LOCATION
C8_6.2 18.7000 18.9000 NO_SWAP_GATE_E
C9_1.2 67.9000 26.9000 HARD_LOCATION
C9_1.2 67.9000 26.9000 NO_SWAP_GATE_E
C9_2.2 86.9000 26.9000 HARD_LOCATION
|------------------------------------------------------------------------------|
| ECO REPORT |
| Page 4 |
|------------------------------------------------------------------------------|
| .../Cadence/worklib/fmc_tlu_toplevel_b/physical/fmc_tlu_v1a_66_gloss4.brd |
| Tue Feb 11 18:41:15 2014 |
|------------------------------------------------------------------------------|
| SLOT PROPERTIES added to design |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
| slot_id | x | y | property | value |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
C9_2.2 86.9000 26.9000 NO_SWAP_GATE_E
C9_3.2 105.900 26.9000 HARD_LOCATION
C9_3.2 105.900 26.9000 NO_SWAP_GATE_E
C9_4.2 124.900 26.9000 HARD_LOCATION
C9_4.2 124.900 26.9000 NO_SWAP_GATE_E
C9_6.2 10.3000 34.3000 HARD_LOCATION
C9_6.2 10.3000 34.3000 NO_SWAP_GATE_E
D1.5 35.8100 54.1600 HARD_LOCATION
D1.5 35.8100 54.1600 NO_SWAP_GATE_E
D2.5 18.6329 54.1139 HARD_LOCATION
D2.5 18.6329 54.1139 NO_SWAP_GATE_E
D3.5 128.671 46.6330 HARD_LOCATION
D3.5 128.671 46.6330 NO_SWAP_GATE_E
D1_1.2 62.9000 46.1000 HARD_LOCATION
D1_1.2 62.9000 46.1000 NO_SWAP_GATE_E
D1_2.2 81.9000 46.1000 HARD_LOCATION
D1_2.2 81.9000 46.1000 NO_SWAP_GATE_E
D1_3.2 100.900 46.1000 HARD_LOCATION
D1_3.2 100.900 46.1000 NO_SWAP_GATE_E
D1_4.2 119.900 46.1000 HARD_LOCATION
D1_4.2 119.900 46.1000 NO_SWAP_GATE_E
IC1.4 37.0000 58.4650 HARD_LOCATION
IC1.4 37.0000 58.4650 NO_SWAP_GATE_E
IC2.4 20.1000 58.4570 HARD_LOCATION
IC2.4 20.1000 58.4570 NO_SWAP_GATE_E
IC3.1 49.6381 30.4850 HARD_LOCATION
IC3.1 49.6381 30.4850 NO_SWAP_GATE_E
IC3.7 49.6381 30.4850 HARD_LOCATION
IC3.7 49.6381 30.4850 NO_SWAP_GATE_E
IC3.8 49.6381 30.4850 HARD_LOCATION
IC3.8 49.6381 30.4850 NO_SWAP_GATE_E
IC3.14 49.6381 30.4850 HARD_LOCATION
IC3.14 49.6381 30.4850 NO_SWAP_GATE_E
IC8.7 52.6329 19.0739 HARD_LOCATION
IC8.7 52.6329 19.0739 NO_SWAP_GATE_E
IC9.4 52.7169 13.4477 HARD_LOCATION
IC9.4 52.7169 13.4477 NO_SWAP_GATE_E
IC2_1.10 68.0000 25.1000 HARD_LOCATION
IC2_1.10 68.0000 25.1000 NO_SWAP_GATE_E
IC2_1.11 68.0000 25.1000 HARD_LOCATION
IC2_1.11 68.0000 25.1000 NO_SWAP_GATE_E
IC2_2.10 87.0000 25.1000 HARD_LOCATION
IC2_2.10 87.0000 25.1000 NO_SWAP_GATE_E
IC2_2.11 87.0000 25.1000 HARD_LOCATION
IC2_2.11 87.0000 25.1000 NO_SWAP_GATE_E
|------------------------------------------------------------------------------|
| ECO REPORT |
| Page 5 |
|------------------------------------------------------------------------------|
| .../Cadence/worklib/fmc_tlu_toplevel_b/physical/fmc_tlu_v1a_66_gloss4.brd |
| Tue Feb 11 18:41:15 2014 |
|------------------------------------------------------------------------------|
| SLOT PROPERTIES added to design |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
| slot_id | x | y | property | value |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
IC2_3.10 106.000 25.1000 HARD_LOCATION
IC2_3.10 106.000 25.1000 NO_SWAP_GATE_E
IC2_3.11 106.000 25.1000 HARD_LOCATION
IC2_3.11 106.000 25.1000 NO_SWAP_GATE_E
IC2_4.10 125.000 25.1000 HARD_LOCATION
IC2_4.10 125.000 25.1000 NO_SWAP_GATE_E
IC2_4.11 125.000 25.1000 HARD_LOCATION
IC2_4.11 125.000 25.1000 NO_SWAP_GATE_E
J1.10 11.7476 58.0700 HARD_LOCATION
J1.10 11.7476 58.0700 NO_SWAP_GATE_E
J4.D9 101.490 -2.0000 HARD_LOCATION
J4.D9 101.490 -2.0000 NO_SWAP_GATE_E
J4.H9 101.490 -2.0000 HARD_LOCATION
J4.H9 101.490 -2.0000 NO_SWAP_GATE_E
L1_6.2 -0.6000 30.0000 HARD_LOCATION
L1_6.2 -0.6000 30.0000 NO_SWAP_GATE_E
L2_6.2 6.9000 24.3000 HARD_LOCATION
L2_6.2 6.9000 24.3000 NO_SWAP_GATE_E
L3_6.2 10.2000 24.4000 HARD_LOCATION
L3_6.2 10.2000 24.4000 NO_SWAP_GATE_E
PX1_1.1 59.7000 41.2000 HARD_LOCATION
PX1_1.1 59.7000 41.2000 NO_SWAP_GATE_E
PX1_2.1 78.7000 41.2000 HARD_LOCATION
PX1_2.1 78.7000 41.2000 NO_SWAP_GATE_E
PX1_3.1 97.7000 41.2000 HARD_LOCATION
PX1_3.1 97.7000 41.2000 NO_SWAP_GATE_E
PX1_4.1 116.700 41.2000 HARD_LOCATION
PX1_4.1 116.700 41.2000 NO_SWAP_GATE_E
PX2_1.1 71.2000 41.2000 HARD_LOCATION
PX2_1.1 71.2000 41.2000 NO_SWAP_GATE_E
PX2_2.1 90.2000 41.2000 HARD_LOCATION
PX2_2.1 90.2000 41.2000 NO_SWAP_GATE_E
PX2_3.1 109.200 41.2000 HARD_LOCATION
PX2_3.1 109.200 41.2000 NO_SWAP_GATE_E
PX2_4.1 128.200 41.2000 HARD_LOCATION
PX2_4.1 128.200 41.2000 NO_SWAP_GATE_E
R1.2 20.0000 64.0690 HARD_LOCATION
R1.2 20.0000 64.0690 NO_SWAP_GATE_E
R2.2 36.8000 64.0670 HARD_LOCATION
R2.2 36.8000 64.0670 NO_SWAP_GATE_E
R3.2 47.9000 37.2000 HARD_LOCATION
R3.2 47.9000 37.2000 NO_SWAP_GATE_E
R4.2 51.4000 37.1500 HARD_LOCATION
R4.2 51.4000 37.1500 NO_SWAP_GATE_E
R5.2 52.9000 35.4500 HARD_LOCATION
|------------------------------------------------------------------------------|
| ECO REPORT |
| Page 6 |
|------------------------------------------------------------------------------|
| .../Cadence/worklib/fmc_tlu_toplevel_b/physical/fmc_tlu_v1a_66_gloss4.brd |
| Tue Feb 11 18:41:15 2014 |
|------------------------------------------------------------------------------|
| SLOT PROPERTIES added to design |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
| slot_id | x | y | property | value |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
R5.2 52.9000 35.4500 NO_SWAP_GATE_E
R6.2 46.5000 35.4000 HARD_LOCATION
R6.2 46.5000 35.4000 NO_SWAP_GATE_E
R40.2 46.3500 25.8000 HARD_LOCATION
R40.2 46.3500 25.8000 NO_SWAP_GATE_E
R41.2 52.8000 25.7000 HARD_LOCATION
R41.2 52.8000 25.7000 NO_SWAP_GATE_E
R46.2 47.1000 23.4500 HARD_LOCATION
R46.2 47.1000 23.4500 NO_SWAP_GATE_E
R47.2 52.9500 23.4000 HARD_LOCATION
R47.2 52.9500 23.4000 NO_SWAP_GATE_E
R60.2 47.3000 17.8250 HARD_LOCATION
R60.2 47.3000 17.8250 NO_SWAP_GATE_E
R61.2 47.3000 16.2450 HARD_LOCATION
R61.2 47.3000 16.2450 NO_SWAP_GATE_E
R62.2 47.3000 14.6000 HARD_LOCATION
R62.2 47.3000 14.6000 NO_SWAP_GATE_E
R63.2 47.3000 12.9110 HARD_LOCATION
R63.2 47.3000 12.9110 NO_SWAP_GATE_E
R64.2 47.3000 11.2220 HARD_LOCATION
R64.2 47.3000 11.2220 NO_SWAP_GATE_E
R65.2 47.3000 9.5120 HARD_LOCATION
R65.2 47.3000 9.5120 NO_SWAP_GATE_E
R66.2 14.4000 61.8200 HARD_LOCATION
R66.2 14.4000 61.8200 NO_SWAP_GATE_E
R67.2 9.0000 61.8200 HARD_LOCATION
R67.2 9.0000 61.8200 NO_SWAP_GATE_E
R68.2 25.8000 61.7930 HARD_LOCATION
R68.2 25.8000 61.7930 NO_SWAP_GATE_E
R69.2 31.6000 61.7650 HARD_LOCATION
R69.2 31.6000 61.7650 NO_SWAP_GATE_E
R70.2 40.5000 52.9450 HARD_LOCATION
R70.2 40.5000 52.9450 NO_SWAP_GATE_E
R71.2 54.6000 52.3000 HARD_LOCATION
R71.2 54.6000 52.3000 NO_SWAP_GATE_E
R10_1.2 73.8500 25.9000 HARD_LOCATION
R10_1.2 73.8500 25.9000 NO_SWAP_GATE_E
R10_2.2 92.8500 25.9000 HARD_LOCATION
R10_2.2 92.8500 25.9000 NO_SWAP_GATE_E
R10_3.2 111.850 25.9000 HARD_LOCATION
R10_3.2 111.850 25.9000 NO_SWAP_GATE_E
R10_4.2 130.850 25.9000 HARD_LOCATION
R10_4.2 130.850 25.9000 NO_SWAP_GATE_E
R11_1.2 58.6000 25.1000 HARD_LOCATION
R11_1.2 58.6000 25.1000 NO_SWAP_GATE_E
|------------------------------------------------------------------------------|
| ECO REPORT |
| Page 7 |
|------------------------------------------------------------------------------|
| .../Cadence/worklib/fmc_tlu_toplevel_b/physical/fmc_tlu_v1a_66_gloss4.brd |
| Tue Feb 11 18:41:15 2014 |
|------------------------------------------------------------------------------|
| SLOT PROPERTIES added to design |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
| slot_id | x | y | property | value |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
R11_2.2 77.6000 25.1000 HARD_LOCATION
R11_2.2 77.6000 25.1000 NO_SWAP_GATE_E
R11_3.2 96.6000 25.1000 HARD_LOCATION
R11_3.2 96.6000 25.1000 NO_SWAP_GATE_E
R11_4.2 115.600 25.1000 HARD_LOCATION
R11_4.2 115.600 25.1000 NO_SWAP_GATE_E
R12_1.2 63.7000 18.4500 HARD_LOCATION
R12_1.2 63.7000 18.4500 NO_SWAP_GATE_E
R12_2.2 81.5000 20.3000 HARD_LOCATION
R12_2.2 81.5000 20.3000 NO_SWAP_GATE_E
R12_3.2 100.500 20.3000 HARD_LOCATION
R12_3.2 100.500 20.3000 NO_SWAP_GATE_E
R12_4.2 119.500 20.3000 HARD_LOCATION
R12_4.2 119.500 20.3000 NO_SWAP_GATE_E
R13_1.2 59.4000 23.3000 HARD_LOCATION
R13_1.2 59.4000 23.3000 NO_SWAP_GATE_E
R13_2.2 78.4000 23.3000 HARD_LOCATION
R13_2.2 78.4000 23.3000 NO_SWAP_GATE_E
R13_3.2 97.4000 23.3000 HARD_LOCATION
R13_3.2 97.4000 23.3000 NO_SWAP_GATE_E
R13_4.2 116.400 23.3000 HARD_LOCATION
R13_4.2 116.400 23.3000 NO_SWAP_GATE_E
R14_1.2 69.4000 20.5000 HARD_LOCATION
R14_1.2 69.4000 20.5000 NO_SWAP_GATE_E
R14_2.2 88.4000 20.5000 HARD_LOCATION
R14_2.2 88.4000 20.5000 NO_SWAP_GATE_E
R14_3.2 107.400 20.5000 HARD_LOCATION
R14_3.2 107.400 20.5000 NO_SWAP_GATE_E
R14_4.2 126.400 20.5000 HARD_LOCATION
R14_4.2 126.400 20.5000 NO_SWAP_GATE_E
R1_6.2 1.7000 28.3000 HARD_LOCATION
R1_6.2 1.7000 28.3000 NO_SWAP_GATE_E
R2_1.2 64.0000 34.0000 HARD_LOCATION
R2_1.2 64.0000 34.0000 NO_SWAP_GATE_E
R2_2.2 83.0000 34.0000 HARD_LOCATION
R2_2.2 83.0000 34.0000 NO_SWAP_GATE_E
R2_3.2 102.000 34.0000 HARD_LOCATION
R2_3.2 102.000 34.0000 NO_SWAP_GATE_E
R2_4.2 121.000 34.0000 HARD_LOCATION
R2_4.2 121.000 34.0000 NO_SWAP_GATE_E
R2_6.2 8.1000 9.8500 HARD_LOCATION
R2_6.2 8.1000 9.8500 NO_SWAP_GATE_E
R3_1.2 65.8500 32.2000 HARD_LOCATION
R3_1.2 65.8500 32.2000 NO_SWAP_GATE_E
R3_2.2 84.8500 32.2000 HARD_LOCATION
|------------------------------------------------------------------------------|
| ECO REPORT |
| Page 8 |
|------------------------------------------------------------------------------|
| .../Cadence/worklib/fmc_tlu_toplevel_b/physical/fmc_tlu_v1a_66_gloss4.brd |
| Tue Feb 11 18:41:15 2014 |
|------------------------------------------------------------------------------|
| SLOT PROPERTIES added to design |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
| slot_id | x | y | property | value |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
R3_2.2 84.8500 32.2000 NO_SWAP_GATE_E
R3_3.2 103.850 32.2000 HARD_LOCATION
R3_3.2 103.850 32.2000 NO_SWAP_GATE_E
R3_4.2 122.850 32.2000 HARD_LOCATION
R3_4.2 122.850 32.2000 NO_SWAP_GATE_E
R3_6.2 7.2000 2.2000 HARD_LOCATION
R3_6.2 7.2000 2.2000 NO_SWAP_GATE_E
R5_1.2 58.4000 35.0000 HARD_LOCATION
R5_1.2 58.4000 35.0000 NO_SWAP_GATE_E
R5_2.2 77.4000 35.0000 HARD_LOCATION
R5_2.2 77.4000 35.0000 NO_SWAP_GATE_E
R5_3.2 96.4000 35.0000 HARD_LOCATION
R5_3.2 96.4000 35.0000 NO_SWAP_GATE_E
R5_4.2 115.400 35.0000 HARD_LOCATION
R5_4.2 115.400 35.0000 NO_SWAP_GATE_E
R6_1.2 71.5000 30.3000 HARD_LOCATION
R6_1.2 71.5000 30.3000 NO_SWAP_GATE_E
R6_2.2 90.5000 30.3000 HARD_LOCATION
R6_2.2 90.5000 30.3000 NO_SWAP_GATE_E
R6_3.2 109.500 30.3000 HARD_LOCATION
R6_3.2 109.500 30.3000 NO_SWAP_GATE_E
R6_4.2 128.500 30.3000 HARD_LOCATION
R6_4.2 128.500 30.3000 NO_SWAP_GATE_E
R7_1.2 67.3000 33.8000 HARD_LOCATION
R7_1.2 67.3000 33.8000 NO_SWAP_GATE_E
R7_2.2 86.3000 33.8000 HARD_LOCATION
R7_2.2 86.3000 33.8000 NO_SWAP_GATE_E
R7_3.2 105.300 33.8000 HARD_LOCATION
R7_3.2 105.300 33.8000 NO_SWAP_GATE_E
R7_4.2 124.300 33.8000 HARD_LOCATION
R7_4.2 124.300 33.8000 NO_SWAP_GATE_E
R8_1.2 71.5000 28.4000 HARD_LOCATION
R8_1.2 71.5000 28.4000 NO_SWAP_GATE_E
R8_2.2 90.5000 28.4000 HARD_LOCATION
R8_2.2 90.5000 28.4000 NO_SWAP_GATE_E
R8_3.2 109.500 28.4000 HARD_LOCATION
R8_3.2 109.500 28.4000 NO_SWAP_GATE_E
R8_4.2 128.500 28.4000 HARD_LOCATION
R8_4.2 128.500 28.4000 NO_SWAP_GATE_E
R9_1.2 59.3000 29.9000 HARD_LOCATION
R9_1.2 59.3000 29.9000 NO_SWAP_GATE_E
R9_2.2 78.3000 29.9000 HARD_LOCATION
R9_2.2 78.3000 29.9000 NO_SWAP_GATE_E
R9_3.2 97.3000 29.9000 HARD_LOCATION
R9_3.2 97.3000 29.9000 NO_SWAP_GATE_E
|------------------------------------------------------------------------------|
| ECO REPORT |
| Page 9 |
|------------------------------------------------------------------------------|
| .../Cadence/worklib/fmc_tlu_toplevel_b/physical/fmc_tlu_v1a_66_gloss4.brd |
| Tue Feb 11 18:41:15 2014 |
|------------------------------------------------------------------------------|
| SLOT PROPERTIES added to design |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
| slot_id | x | y | property | value |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
R9_4.2 116.300 29.9000 HARD_LOCATION
R9_4.2 116.300 29.9000 NO_SWAP_GATE_E
REG1_6.1 14.7000 32.2000 HARD_LOCATION
REG1_6.1 14.7000 32.2000 NO_SWAP_GATE_E
RG1_6.C7 9.1000 14.7000 HARD_LOCATION
RG1_6.C7 9.1000 14.7000 NO_SWAP_GATE_E
RG2_6.C7 11.9000 -2.8000 HARD_LOCATION
RG2_6.C7 11.9000 -2.8000 NO_SWAP_GATE_E
TP22.1 50.8000 23.3000 HARD_LOCATION
TP22.1 50.8000 23.3000 NO_SWAP_GATE_E
TP1_1.1 58.4000 32.1000 HARD_LOCATION
TP1_1.1 58.4000 32.1000 NO_SWAP_GATE_E
TP1_2.1 77.4000 32.1000 HARD_LOCATION
TP1_2.1 77.4000 32.1000 NO_SWAP_GATE_E
TP1_3.1 96.4000 32.1000 HARD_LOCATION
TP1_3.1 96.4000 32.1000 NO_SWAP_GATE_E
TP1_4.1 115.400 32.1000 HARD_LOCATION
TP1_4.1 115.400 32.1000 NO_SWAP_GATE_E
TP2_1.1 61.6000 23.4000 HARD_LOCATION
TP2_1.1 61.6000 23.4000 NO_SWAP_GATE_E
TP2_2.1 80.6000 23.4000 HARD_LOCATION
TP2_2.1 80.6000 23.4000 NO_SWAP_GATE_E
TP2_3.1 99.6000 23.4000 HARD_LOCATION
TP2_3.1 99.6000 23.4000 NO_SWAP_GATE_E
TP2_4.1 118.600 23.4000 HARD_LOCATION
TP2_4.1 118.600 23.4000 NO_SWAP_GATE_E
TP3_1.1 60.7500 21.4500 HARD_LOCATION
TP3_1.1 60.7500 21.4500 NO_SWAP_GATE_E
TP3_2.1 76.8000 20.0000 HARD_LOCATION
TP3_2.1 76.8000 20.0000 NO_SWAP_GATE_E
TP3_3.1 95.8000 20.0000 HARD_LOCATION
TP3_3.1 95.8000 20.0000 NO_SWAP_GATE_E
TP3_4.1 114.800 20.0000 HARD_LOCATION
TP3_4.1 114.800 20.0000 NO_SWAP_GATE_E
TP4_1.1 57.1000 23.2000 HARD_LOCATION
TP4_1.1 57.1000 23.2000 NO_SWAP_GATE_E
TP4_2.1 76.1000 23.2000 HARD_LOCATION
TP4_2.1 76.1000 23.2000 NO_SWAP_GATE_E
TP4_3.1 95.1000 23.2000 HARD_LOCATION
TP4_3.1 95.1000 23.2000 NO_SWAP_GATE_E
TP4_4.1 114.100 23.2000 HARD_LOCATION
TP4_4.1 114.100 23.2000 NO_SWAP_GATE_E
TP5_1.1 67.0500 20.5000 HARD_LOCATION
TP5_1.1 67.0500 20.5000 NO_SWAP_GATE_E
TP5_2.1 86.0500 20.5000 HARD_LOCATION
|------------------------------------------------------------------------------|
| ECO REPORT |
| Page 10 |
|------------------------------------------------------------------------------|
| .../Cadence/worklib/fmc_tlu_toplevel_b/physical/fmc_tlu_v1a_66_gloss4.brd |
| Tue Feb 11 18:41:15 2014 |
|------------------------------------------------------------------------------|
| SLOT PROPERTIES added to design |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
| slot_id | x | y | property | value |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
TP5_2.1 86.0500 20.5000 NO_SWAP_GATE_E
TP5_3.1 105.050 20.5000 HARD_LOCATION
TP5_3.1 105.050 20.5000 NO_SWAP_GATE_E
TP5_4.1 124.050 20.5000 HARD_LOCATION
TP5_4.1 124.050 20.5000 NO_SWAP_GATE_E
TP6_1.1 64.5500 20.5000 HARD_LOCATION
TP6_1.1 64.5500 20.5000 NO_SWAP_GATE_E
TP6_2.1 83.5500 20.5000 HARD_LOCATION
TP6_2.1 83.5500 20.5000 NO_SWAP_GATE_E
TP6_3.1 102.550 20.5000 HARD_LOCATION
TP6_3.1 102.550 20.5000 NO_SWAP_GATE_E
TP6_4.1 121.550 20.5000 HARD_LOCATION
TP6_4.1 121.550 20.5000 NO_SWAP_GATE_E
TP7_1.1 65.8500 17.9000 HARD_LOCATION
TP7_1.1 65.8500 17.9000 NO_SWAP_GATE_E
TP7_2.1 84.8500 17.9000 HARD_LOCATION
TP7_2.1 84.8500 17.9000 NO_SWAP_GATE_E
TP7_3.1 103.850 17.9000 HARD_LOCATION
TP7_3.1 103.850 17.9000 NO_SWAP_GATE_E
TP7_4.1 122.850 17.9000 HARD_LOCATION
TP7_4.1 122.850 17.9000 NO_SWAP_GATE_E
U1.1 26.5000 54.3000 HARD_LOCATION
U1.1 26.5000 54.3000 NO_SWAP_GATE_E
U1.2 26.5000 54.3000 HARD_LOCATION
U1.2 26.5000 54.3000 NO_SWAP_GATE_E
U1.4 26.5000 54.3000 HARD_LOCATION
U1.4 26.5000 54.3000 NO_SWAP_GATE_E
U1.5 26.5000 54.3000 HARD_LOCATION
U1.5 26.5000 54.3000 NO_SWAP_GATE_E
U1.6 26.5000 54.3000 HARD_LOCATION
U1.6 26.5000 54.3000 NO_SWAP_GATE_E
U1.7 26.5000 54.3000 HARD_LOCATION
U1.7 26.5000 54.3000 NO_SWAP_GATE_E
U1.9 26.5000 54.3000 HARD_LOCATION
U1.9 26.5000 54.3000 NO_SWAP_GATE_E
U1.10 26.5000 54.3000 HARD_LOCATION
U1.10 26.5000 54.3000 NO_SWAP_GATE_E
U2.1 10.2900 54.1100 HARD_LOCATION
U2.1 10.2900 54.1100 NO_SWAP_GATE_E
U2.2 10.2900 54.1100 HARD_LOCATION
U2.2 10.2900 54.1100 NO_SWAP_GATE_E
U2.4 10.2900 54.1100 HARD_LOCATION
U2.4 10.2900 54.1100 NO_SWAP_GATE_E
U2.5 10.2900 54.1100 HARD_LOCATION
U2.5 10.2900 54.1100 NO_SWAP_GATE_E
|------------------------------------------------------------------------------|
| ECO REPORT |
| Page 11 |
|------------------------------------------------------------------------------|
| .../Cadence/worklib/fmc_tlu_toplevel_b/physical/fmc_tlu_v1a_66_gloss4.brd |
| Tue Feb 11 18:41:15 2014 |
|------------------------------------------------------------------------------|
| SLOT PROPERTIES added to design |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
| slot_id | x | y | property | value |
|- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
U2.6 10.2900 54.1100 HARD_LOCATION
U2.6 10.2900 54.1100 NO_SWAP_GATE_E
U2.7 10.2900 54.1100 HARD_LOCATION
U2.7 10.2900 54.1100 NO_SWAP_GATE_E
U2.9 10.2900 54.1100 HARD_LOCATION
U2.9 10.2900 54.1100 NO_SWAP_GATE_E
U2.10 10.2900 54.1100 HARD_LOCATION
U2.10 10.2900 54.1100 NO_SWAP_GATE_E
U3.1 47.7000 44.2000 HARD_LOCATION
U3.1 47.7000 44.2000 NO_SWAP_GATE_E
U3.2 47.7000 44.2000 HARD_LOCATION
U3.2 47.7000 44.2000 NO_SWAP_GATE_E
U3.4 47.7000 44.2000 HARD_LOCATION
U3.4 47.7000 44.2000 NO_SWAP_GATE_E
U3.5 47.7000 44.2000 HARD_LOCATION
U3.5 47.7000 44.2000 NO_SWAP_GATE_E
U3.6 47.7000 44.2000 HARD_LOCATION
U3.6 47.7000 44.2000 NO_SWAP_GATE_E
U3.7 47.7000 44.2000 HARD_LOCATION
U3.7 47.7000 44.2000 NO_SWAP_GATE_E
U3.9 47.7000 44.2000 HARD_LOCATION
U3.9 47.7000 44.2000 NO_SWAP_GATE_E
U3.10 47.7000 44.2000 HARD_LOCATION
U3.10 47.7000 44.2000 NO_SWAP_GATE_E
VR1_6.3 5.9000 31.6000 HARD_LOCATION
VR1_6.3 5.9000 31.6000 NO_SWAP_GATE_E
Z1.C 29.2000 50.4500 HARD_LOCATION
Z1.C 29.2000 50.4500 NO_SWAP_GATE_E
Z4.C 132.500 35.4000 HARD_LOCATION
Z4.C 132.500 35.4000 NO_SWAP_GATE_E
|------------------------------------------------------------------------------|
| total ECO changes reported 2 |
| total ECO changes reported 480 |
|------------------------------------------------------------------------------|
Cadence/worklib/fmc_tlu_toplevel_c/physical/netrev.lst
View file @ a648eb8d
......@@ -2,59 +2,73 @@
( )
( Allegro Netrev Import Logic )
( )
( Drawing : fmc_tlu_v1a_66_gloss4.brd )
( Software Version : 16.6S014 )
( Date/Time : Tue Feb 11 18:41:14 2014 )
( Drawing : fmc_tlu_v1a_66.brd )
( Software Version : 16.6-2015S055 )
( Date/Time : Fri May 20 14:54:08 2016 )
( )
(---------------------------------------------------------------------)
------ Directives ------
------ Directives ------------
RIPUP_ETCH FALSE;
RIPUP_DELETE_FIRST_SEGMENT FALSE;
RIPUP_RETAIN_BONDWIRE FALSE;
RIPUP_SYMBOLS ALWAYS;
Missing symbol has error FALSE;
SCHEMATIC_DIRECTORY '/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged';
BOARD_DIRECTORY '';
OLD_BOARD_NAME '/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/physical/fmc_tlu_v1a_66_gloss4.brd';
NEW_BOARD_NAME 'fmc_tlu_v1a_66_gloss4a.brd';
Ripup etch: No
Ripup delete first segment: No
Ripup retain bondwire: No
Ripup symbols: Always
Missing symbol has error: No
DRC update: Yes
Schematic directory: '/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_c/packaged'
Design Directory: '.'
Old design name: '/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_c/physical/fmc_tlu_v1a_66.brd'
New design name: 'fmc_tlu_v1c_67.brd'
CmdLine: netrev -proj /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/fmc_tlu_v1a.cpm -y 1 -O /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/physical/fmc_tlu_v1a_66_gloss4.brd /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/physical/fmc_tlu_v1a_66_gloss4a.brd -$
CmdLine: netrev -proj /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/fmc_tlu_v1c.cpm -y 1 -Oo /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_c/physical/fmc_tlu_v1a_66.brd /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_c/physical/fmc_tlu_v1c_67.brd -q /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/temp/constraints_difference_report.xml -$
------ Preparing to read pst files ------
Starting to read /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstchip.dat
Finished reading /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstchip.dat (00:00:00.21)
Starting to read /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstxprt.dat
Finished reading /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstxprt.dat (00:00:00.01)
Starting to read /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstxnet.dat
Finished reading /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstxnet.dat (00:00:00.00)
Starting to read /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_c/packaged/pstchip.dat
Finished reading /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_c/packaged/pstchip.dat (00:00:00.15)
Starting to read /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_c/packaged/pstxprt.dat
Finished reading /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_c/packaged/pstxprt.dat (00:00:00.01)
Starting to read /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_c/packaged/pstxnet.dat
Finished reading /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_c/packaged/pstxnet.dat (00:00:00.00)
------ Oversights/Warnings/Errors ------
#1 WARNING(SPMHNI-192): Device/Symbol check warning detected. [help]
WARNING(SPMHNI-337): Unable to load symbol 'LEMO_EPG-00-302-NLN' used by RefDes PX1 for device 'PLEMO2CI-EPG.00.302.NLN-GND=GNA': WARNING(SPMHUT-127): Could not find padstack C130H60O-15.
due to ERROR(SPMHDB-274): Unable to load flash symbol THR_160X120X4X17 (Check PSMPATH setting for this symbo
Could not find padstack C130H60O-15.
===========================================================
Start Constraint Diff3 Import
Constraint File: /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstcmdb.dat
Allegro Baseline: /tmp/#Taaaaad01896.tmp
Schematic Baseline: /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstcmbc.dat
Start time: Tue Feb 11 18:41:15 2014
Start Constraint Override Import
Constraint File: /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_c/packaged/pstcmdb.dat
Start time: Fri May 20 14:54:08 2016
===========================================================
The constraint difference report file can be viewed using the following command:
/software/CAD/Cadence/2015-16/RHELx86/SPB_16.60.055/tools/firefox/bin/firefox -app /software/CAD/Cadence/2015-16/RHELx86/SPB_16.60.055/share/pcb/consmgr/VDD/diff3rptViewer/diff3rptViewer.ini -file file:///projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/temp/constraints_difference_report.xml
===========================================================
Finished Constraint Update Time: Tue Feb 11 18:41:16 2014
Finished Constraint Update Time: Fri May 20 14:54:09 2016
===========================================================
------ Library Paths ------
MODULEPATH = .
/cadence/psd15.1/share/local/pcb/modules
../../../modules
../../fmc_tlu_cfd/physical
../../../pc042a_lib/pc042b_vsupply5v/physical
../../fmc_tlu_vsupply5v/physical
../../ltm9007_input_filter/physical
../../ltm9007_8chan/physical
../../trenz_te0712/physical
../../pc052a_single_amplifier/physical
../../pc052b_resistive_splitter/physical
../../pc052c_splitter_array/physical
PSMPATH = .
/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/symbols
......@@ -71,14 +85,16 @@ PSMPATH = .
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/led
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/rel
/projects/HEP_Instrumentation/cad/ral_cdslib/lib_psd15.x/symbols
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/sw
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/mec
PADPATH = .
symbols
..
../symbols
/software/CAD/Cadence/SPB16.60.000/share/local/pcb/padstacks
/software/CAD/Cadence/SPB16.60.000/share/pcb/pcb_lib/symbols
/software/CAD/Cadence/SPB16.60.000/share/pcb/allegrolib/symbols
/software/CAD/Cadence/2015-16/RHELx86/SPB_16.60.055/share/local/pcb/padstacks
/software/CAD/Cadence/2015-16/RHELx86/SPB_16.60.055/share/pcb/pcb_lib/symbols
/software/CAD/Cadence/2015-16/RHELx86/SPB_16.60.055/share/pcb/allegrolib/symbols
/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/pads
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/padstacks/padstack_smd
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/padstacks/padstack3
......@@ -89,9 +105,9 @@ PADPATH = .
------ Summary Statistics ------
netrev run on Feb 11 18:41:14 2014
DESIGN NAME : 'FMC_TLU_TOPLEVEL_B'
PACKAGING ON 11-Feb-2014 AT 18:41:05
netrev run on May 20 14:54:08 2016
DESIGN NAME : 'FMC_TLU_TOPLEVEL_C'
PACKAGING ON 20-May-2016 AT 14:54:05
COMPILE 'logic'
CHECK_PIN_NAMES OFF
......@@ -121,8 +137,8 @@ netrev run on Feb 11 18:41:14 2014
No error detected
No oversight detected
No warning detected
1 warnings detected
cpu time 0:00:01
elapsed time 0:00:02
cpu time 0:00:02
elapsed time 0:00:01
Cadence/worklib/fmc_tlu_toplevel_c/physical/pstcmdb2.dat
View file @ a648eb8d
This source diff could not be displayed because it is too large. You can view the blob instead.
Cadence/worklib/fmc_tlu_toplevel_c/sch_1/fmc_tlu_toplevel_c.dcf
View file @ a648eb8d
This source diff could not be displayed because it is too large. You can view the blob instead.
Cadence/worklib/fmc_tlu_toplevel_c/sch_1/fmc_tlu_toplevel_c.dcf,1
View file @ a648eb8d
This source diff could not be displayed because it is too large. You can view the blob instead.
Cadence/worklib/fmc_tlu_toplevel_c/sch_1/fmc_tlu_toplevel_c.dcf,2
View file @ a648eb8d
This source diff could not be displayed because it is too large. You can view the blob instead.
Cadence/worklib/fmc_tlu_toplevel_c/sch_1/fmc_tlu_toplevel_c.dcf,3
View file @ a648eb8d
This source diff could not be displayed because it is too large. You can view the blob instead.
Cadence/worklib/fmc_tlu_toplevel_c/sch_1/fmc_tlu_toplevel_c.xcon
View file @ a648eb8d
This source diff could not be displayed because it is too large. You can view the blob instead.
Cadence/worklib/fmc_tlu_toplevel_c/sch_1/module_order.dat
View file @ a648eb8d
......@@ -2,17 +2,16 @@ Version 15.0
START_MODULEORDER
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1) 0 1 1 3 0
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page1_i2@fmc_tlu_v1_lib.pc036a_fmc_lpc_connector(sch_1) 0 0 4 1 0
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page4_i62@fmc_tlu_v1_lib.fmc_tlu_diode_clamp(sch_1) 0 1 5 1 0
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page4_i63@fmc_tlu_v1_lib.fmc_tlu_diode_clamp(sch_1) 0 0 6 1 1
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page4_i64@fmc_tlu_v1_lib.fmc_tlu_diode_clamp(sch_1) 0 0 7 1 1
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i35@fmc_tlu_v1_lib.fmc_tlu_cfd(sch_1) 0 0 8 1 0
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i36@fmc_tlu_v1_lib.fmc_tlu_cfd(sch_1) 0 0 9 1 1
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i37@fmc_tlu_v1_lib.fmc_tlu_cfd(sch_1) 0 0 10 1 1
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i38@fmc_tlu_v1_lib.fmc_tlu_cfd(sch_1) 0 0 11 1 1
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i5@fmc_tlu_v1_lib.pc023a_dac_vthresh(sch_1) 0 0 12 1 0
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i5@fmc_tlu_v1_lib.pc023a_dac_vthresh(sch_1):page1_i29@fmc_tlu_v1_lib.pc023a_vthresh_buffer(sch_1) 0 0 13 1 0
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i5@fmc_tlu_v1_lib.pc023a_dac_vthresh(sch_1):page1_i30@fmc_tlu_v1_lib.pc023a_vthresh_buffer(sch_1) 0 0 14 1 1
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i5@fmc_tlu_v1_lib.pc023a_dac_vthresh(sch_1):page1_i31@fmc_tlu_v1_lib.pc023a_vthresh_buffer(sch_1) 0 0 15 1 1
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i5@fmc_tlu_v1_lib.pc023a_dac_vthresh(sch_1):page1_i32@fmc_tlu_v1_lib.pc023a_vthresh_buffer(sch_1) 0 0 16 1 1
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i55@fmc_tlu_v1_lib.fmc_tlu_vsupply5v(sch_1) 0 0 17 1 0
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i35@fmc_tlu_v1_lib.fmc_tlu_cfd(sch_1) 0 0 5 1 0
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i36@fmc_tlu_v1_lib.fmc_tlu_cfd(sch_1) 0 0 6 1 1
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i37@fmc_tlu_v1_lib.fmc_tlu_cfd(sch_1) 0 0 7 1 1
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i38@fmc_tlu_v1_lib.fmc_tlu_cfd(sch_1) 0 0 8 1 1
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i5@fmc_tlu_v1_lib.pc023a_dac_vthresh(sch_1) 0 0 9 1 0
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i5@fmc_tlu_v1_lib.pc023a_dac_vthresh(sch_1):page1_i29@fmc_tlu_v1_lib.pc023a_vthresh_buffer(sch_1) 0 0 10 1 0
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i5@fmc_tlu_v1_lib.pc023a_dac_vthresh(sch_1):page1_i30@fmc_tlu_v1_lib.pc023a_vthresh_buffer(sch_1) 0 0 11 1 1
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i5@fmc_tlu_v1_lib.pc023a_dac_vthresh(sch_1):page1_i31@fmc_tlu_v1_lib.pc023a_vthresh_buffer(sch_1) 0 0 12 1 1
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i5@fmc_tlu_v1_lib.pc023a_dac_vthresh(sch_1):page1_i32@fmc_tlu_v1_lib.pc023a_vthresh_buffer(sch_1) 0 0 13 1 1
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page2_i55@fmc_tlu_v1_lib.fmc_tlu_vsupply5v(sch_1) 0 0 14 1 0
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page4_i1@fmc_tlu_v1_lib.fmc_tlu_hdmi_dut_connector(sch_1) 0 1 15 1 0
@fmc_tlu_v1_lib.fmc_tlu_toplevel_c(sch_1):page4_i1@fmc_tlu_v1_lib.fmc_tlu_hdmi_dut_connector(sch_1):page1_i78@fmc_tlu_v1_lib.fmc_tlu_diode_clamp_b(sch_1) 0 0 16 1 0
END_MODULEORDER
Cadence/worklib/fmc_tlu_toplevel_c/sch_1/page1.cpc
View file @ a648eb8d
......@@ -4,15 +4,51 @@
#ISCELL
standard gnd_signal *
page1_i10
#ISCELL
standard tap *
page1_i100
#ISCELL
standard tap *
page1_i104
#ISCELL
standard tap *
page1_i108
#CELL
cnpassive capcersmdcl2 *
page1_i11
#ISCELL
standard tap *
page1_i112
#ISCELL
standard tap *
page1_i116
#CELL
cnpassive rsmd0603 *
page1_i12
#ISCELL
standard tap *
page1_i120
#ISCELL
standard tap *
page1_i125
#ISCELL
standard tap *
page1_i126
#ISCELL
standard tap *
page1_i127
#ISCELL
standard tap *
page1_i128
#ISCELL
standard tap *
page1_i129
#CELL
cnpassive rsmd0603 *
page1_i13
#ISCELL
cnpower p3v3 *
page1_i130
#CELL
cnpassive rsmd0603 *
page1_i14
......@@ -34,30 +70,9 @@
#CELL
fmc_tlu_v1_lib pc036a_fmc_lpc_connector *
page1_i2
#ISCELL
standard tap *
page1_i20
#ISCELL
standard tap *
page1_i21
#ISCELL
standard tap *
page1_i22
#ISCELL
standard tap *
page1_i24
#ISCELL
standard tap *
page1_i28
#ISCELL
standard gnd_signal *
page1_i3
#ISCELL
standard tap *
page1_i31
#ISCELL
standard tap *
page1_i35
#ISCELL
standard tap *
page1_i36
......@@ -73,30 +88,9 @@
#ISCELL
standard tap *
page1_i40
#ISCELL
standard tap *
page1_i41
#ISCELL
standard tap *
page1_i42
#ISCELL
standard tap *
page1_i43
#ISCELL
standard tap *
page1_i44
#ISCELL
standard tap *
page1_i45
#ISCELL
standard tap *
page1_i46
#ISCELL
standard tap *
page1_i47
#ISCELL
standard tap *
page1_i48
#ISCELL
standard tap *
page1_i49
......@@ -115,30 +109,9 @@
#ISCELL
standard tap *
page1_i55
#ISCELL
standard tap *
page1_i56
#ISCELL
standard tap *
page1_i57
#ISCELL
standard tap *
page1_i58
#ISCELL
standard tap *
page1_i59
#ISCELL
standard tap *
page1_i60
#ISCELL
standard tap *
page1_i61
#ISCELL
standard tap *
page1_i62
#ISCELL
standard tap *
page1_i63
#ISCELL
standard tap *
page1_i64
......@@ -154,42 +127,12 @@
#CELL
cnconnector plemo2ci *
page1_i7
#ISCELL
standard tap *
page1_i70
#ISCELL
standard tap *
page1_i73
#ISCELL
standard tap *
page1_i76
#ISCELL
standard tap *
page1_i79
#CELL
cnmemory 24aa025e48 *
page1_i8
#ISCELL
standard tap *
page1_i81
#ISCELL
standard tap *
page1_i82
#ISCELL
standard tap *
page1_i83
#ISCELL
standard tap *
page1_i84
#ISCELL
standard tap *
page1_i85
#ISCELL
standard tap *
page1_i86
#ISCELL
cnpower p2v5 *
page1_i88
#ISCELL
standard gnd_signal *
page1_i89
......
Cadence/worklib/fmc_tlu_toplevel_c/sch_1/page1.csa
View file @ a648eb8d
......@@ -33,12 +33,92 @@ J 0
(0 -3250);
DISPLAY 0.978723 (0 -3250);
DISPLAY INVISIBLE (0 -3250);
FORCEADD TAP..1
(1750 125);
FORCEPROP 1 LASTPIN (1700 125) BN 0
J 0
(1688 133);
DISPLAY 0.680851 (1688 133);
PAINT GREEN (1688 133);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(2075 0);
DISPLAY 0.872340 (2075 0);
DISPLAY INVISIBLE (2075 0);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(1750 175);
DISPLAY 0.872340 (1750 175);
PAINT GREEN (1750 175);
DISPLAY INVISIBLE (1750 175);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(1750 125);
DISPLAY INVISIBLE (1750 125);
FORCEPROP 1 LAST PATH I100
J 0
(1748 125);
DISPLAY 0.872340 (1748 125);
PAINT GREEN (1748 125);
DISPLAY INVISIBLE (1748 125);
FORCEADD TAP..1
(150 -725);
FORCEPROP 1 LASTPIN (100 -725) BN 4
J 0
(88 -717);
DISPLAY 0.680851 (88 -717);
PAINT MONO (88 -717);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(150 -725);
DISPLAY INVISIBLE (150 -725);
FORCEPROP 1 LAST PATH I104
J 0
(148 -725);
DISPLAY 0.872340 (148 -725);
PAINT GREEN (148 -725);
DISPLAY INVISIBLE (148 -725);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(150 -675);
DISPLAY 0.872340 (150 -675);
PAINT GREEN (150 -675);
DISPLAY INVISIBLE (150 -675);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(475 -850);
DISPLAY 0.872340 (475 -850);
DISPLAY INVISIBLE (475 -850);
FORCEADD TAP..1
(150 -525);
FORCEPROP 1 LASTPIN (100 -525) BN 3
J 0
(88 -517);
DISPLAY 0.680851 (88 -517);
PAINT MONO (88 -517);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(150 -525);
DISPLAY INVISIBLE (150 -525);
FORCEPROP 1 LAST PATH I108
J 0
(148 -525);
DISPLAY 0.872340 (148 -525);
PAINT GREEN (148 -525);
DISPLAY INVISIBLE (148 -525);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(150 -475);
DISPLAY 0.872340 (150 -475);
PAINT GREEN (150 -475);
DISPLAY INVISIBLE (150 -475);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(475 -650);
DISPLAY 0.872340 (475 -650);
DISPLAY INVISIBLE (475 -650);
FORCEADD CAPCERSMDCL2..1
(-200 -3300);
FORCEPROP 1 LAST LOCATION C70
J 0
(-225 -3250);
DISPLAY 0.723404 (-225 -3250);
FORCEPROP 1 LAST VOLTAGE 16V
J 1
(-200 -3450);
......@@ -47,6 +127,10 @@ FORCEPROP 1 LAST VALUE 100NF
J 1
(-200 -3400);
DISPLAY 0.723404 (-200 -3400);
FORCEPROP 1 LAST LOCATION C70
J 0
(-225 -3250);
DISPLAY 0.723404 (-225 -3250);
FORCEPROP 1 LAST PACK_TYPE 0603
J 1
(-200 -3500);
......@@ -77,15 +161,65 @@ J 0
(-175 -3200);
DISPLAY 0.723404 (-175 -3200);
DISPLAY INVISIBLE (-175 -3200);
FORCEADD TAP..1
(150 -325);
FORCEPROP 1 LASTPIN (100 -325) BN 2
J 0
(88 -317);
DISPLAY 0.680851 (88 -317);
PAINT MONO (88 -317);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(150 -325);
DISPLAY INVISIBLE (150 -325);
FORCEPROP 1 LAST PATH I112
J 0
(148 -325);
DISPLAY 0.872340 (148 -325);
PAINT GREEN (148 -325);
DISPLAY INVISIBLE (148 -325);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(150 -275);
DISPLAY 0.872340 (150 -275);
PAINT GREEN (150 -275);
DISPLAY INVISIBLE (150 -275);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(475 -450);
DISPLAY 0.872340 (475 -450);
DISPLAY INVISIBLE (475 -450);
FORCEADD TAP..1
(150 -125);
FORCEPROP 1 LASTPIN (100 -125) BN 1
J 0
(88 -117);
DISPLAY 0.680851 (88 -117);
PAINT MONO (88 -117);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(150 -125);
DISPLAY INVISIBLE (150 -125);
FORCEPROP 1 LAST PATH I116
J 0
(148 -125);
DISPLAY 0.872340 (148 -125);
PAINT GREEN (148 -125);
DISPLAY INVISIBLE (148 -125);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(150 -75);
DISPLAY 0.872340 (150 -75);
PAINT GREEN (150 -75);
DISPLAY INVISIBLE (150 -75);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(475 -250);
DISPLAY 0.872340 (475 -250);
DISPLAY INVISIBLE (475 -250);
FORCEADD RSMD0603..2
R 1
(-1050 -3050);
FORCEPROP 1 LAST LOCATION R61
R 1
J 1
(-1087 -3045);
DISPLAY 0.723404 (-1087 -3045);
PAINT WHITE (-1087 -3045);
FORCEPROP 1 LAST VALUE XX
R 1
J 1
......@@ -98,6 +232,12 @@ J 1
(-990 -3045);
DISPLAY 0.617021 (-990 -3045);
PAINT WHITE (-990 -3045);
FORCEPROP 1 LAST LOCATION R61
R 1
J 1
(-1087 -3045);
DISPLAY 0.723404 (-1087 -3045);
PAINT WHITE (-1087 -3045);
FORCEPROP 1 LAST DIST FLAT
R 1
J 0
......@@ -193,15 +333,177 @@ J 1
DISPLAY 0.617021 (-925 -3045);
PAINT WHITE (-925 -3045);
DISPLAY INVISIBLE (-925 -3045);
FORCEADD TAP..1
(150 75);
FORCEPROP 1 LASTPIN (100 75) BN 0
J 0
(88 83);
DISPLAY 0.680851 (88 83);
PAINT MONO (88 83);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(150 75);
DISPLAY INVISIBLE (150 75);
FORCEPROP 1 LAST PATH I120
J 0
(148 75);
DISPLAY 0.872340 (148 75);
PAINT GREEN (148 75);
DISPLAY INVISIBLE (148 75);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(150 125);
DISPLAY 0.872340 (150 125);
PAINT GREEN (150 125);
DISPLAY INVISIBLE (150 125);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(475 -50);
DISPLAY 0.872340 (475 -50);
DISPLAY INVISIBLE (475 -50);
FORCEADD TAP..1
(150 -875);
FORCEPROP 1 LASTPIN (100 -875) BN 5
J 0
(88 -867);
DISPLAY 0.680851 (88 -867);
PAINT MONO (88 -867);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(475 -1000);
DISPLAY 0.872340 (475 -1000);
DISPLAY INVISIBLE (475 -1000);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(150 -825);
DISPLAY 0.872340 (150 -825);
PAINT GREEN (150 -825);
DISPLAY INVISIBLE (150 -825);
FORCEPROP 1 LAST PATH I125
J 0
(148 -875);
DISPLAY 0.872340 (148 -875);
PAINT GREEN (148 -875);
DISPLAY INVISIBLE (148 -875);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(150 -875);
DISPLAY INVISIBLE (150 -875);
FORCEADD TAP..1
(1750 -675);
FORCEPROP 1 LASTPIN (1700 -675) BN 4
J 0
(1688 -667);
DISPLAY 0.680851 (1688 -667);
PAINT MONO (1688 -667);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(1750 -675);
DISPLAY INVISIBLE (1750 -675);
FORCEPROP 1 LAST PATH I126
J 0
(1748 -675);
DISPLAY 0.872340 (1748 -675);
PAINT GREEN (1748 -675);
DISPLAY INVISIBLE (1748 -675);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(2075 -800);
DISPLAY 0.872340 (2075 -800);
DISPLAY INVISIBLE (2075 -800);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(1750 -625);
DISPLAY 0.872340 (1750 -625);
PAINT GREEN (1750 -625);
DISPLAY INVISIBLE (1750 -625);
FORCEADD TAP..1
(1750 -475);
FORCEPROP 1 LASTPIN (1700 -475) BN 3
J 0
(1688 -467);
DISPLAY 0.680851 (1688 -467);
PAINT MONO (1688 -467);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(1750 -475);
DISPLAY INVISIBLE (1750 -475);
FORCEPROP 1 LAST PATH I127
J 0
(1748 -475);
DISPLAY 0.872340 (1748 -475);
PAINT GREEN (1748 -475);
DISPLAY INVISIBLE (1748 -475);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(2075 -600);
DISPLAY 0.872340 (2075 -600);
DISPLAY INVISIBLE (2075 -600);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(1750 -425);
DISPLAY 0.872340 (1750 -425);
PAINT GREEN (1750 -425);
DISPLAY INVISIBLE (1750 -425);
FORCEADD TAP..1
(1750 -275);
FORCEPROP 1 LASTPIN (1700 -275) BN 2
J 0
(1688 -267);
DISPLAY 0.680851 (1688 -267);
PAINT MONO (1688 -267);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(1750 -275);
DISPLAY INVISIBLE (1750 -275);
FORCEPROP 1 LAST PATH I128
J 0
(1748 -275);
DISPLAY 0.872340 (1748 -275);
PAINT GREEN (1748 -275);
DISPLAY INVISIBLE (1748 -275);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(2075 -400);
DISPLAY 0.872340 (2075 -400);
DISPLAY INVISIBLE (2075 -400);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(1750 -225);
DISPLAY 0.872340 (1750 -225);
PAINT GREEN (1750 -225);
DISPLAY INVISIBLE (1750 -225);
FORCEADD TAP..1
(1750 -75);
FORCEPROP 1 LASTPIN (1700 -75) BN 1
J 0
(1688 -67);
DISPLAY 0.680851 (1688 -67);
PAINT MONO (1688 -67);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(1750 -75);
DISPLAY INVISIBLE (1750 -75);
FORCEPROP 1 LAST PATH I129
J 0
(1748 -75);
DISPLAY 0.872340 (1748 -75);
PAINT GREEN (1748 -75);
DISPLAY INVISIBLE (1748 -75);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(2075 -200);
DISPLAY 0.872340 (2075 -200);
DISPLAY INVISIBLE (2075 -200);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(1750 -25);
DISPLAY 0.872340 (1750 -25);
PAINT GREEN (1750 -25);
DISPLAY INVISIBLE (1750 -25);
FORCEADD RSMD0603..2
R 1
(-900 -3050);
FORCEPROP 1 LAST LOCATION R63
R 1
J 1
(-937 -3045);
DISPLAY 0.723404 (-937 -3045);
PAINT WHITE (-937 -3045);
FORCEPROP 1 LAST VALUE XX
R 1
J 1
......@@ -214,6 +516,12 @@ J 1
(-840 -3045);
DISPLAY 0.617021 (-840 -3045);
PAINT WHITE (-840 -3045);
FORCEPROP 1 LAST LOCATION R63
R 1
J 1
(-937 -3045);
DISPLAY 0.723404 (-937 -3045);
PAINT WHITE (-937 -3045);
FORCEPROP 1 LAST DIST FLAT
R 1
J 0
......@@ -309,15 +617,51 @@ J 1
DISPLAY 0.617021 (-775 -3045);
PAINT WHITE (-775 -3045);
DISPLAY INVISIBLE (-775 -3045);
FORCEADD P3V3..1
(2900 850);
FORCEPROP 3 LASTPIN (2900 800) SIG_NAME P3V3\g
J 0
(2910 810);
DISPLAY 0.659574 (2910 810);
PAINT MONO (2910 810);
DISPLAY INVISIBLE (2910 810);
FORCEPROP 1 LAST PATH I130
J 0
(2950 850);
DISPLAY 0.872340 (2950 850);
PAINT PINK (2950 850);
DISPLAY INVISIBLE (2950 850);
FORCEPROP 1 LAST HDL_POWER P3V3
J 1
(2900 900);
DISPLAY 0.468085 (2900 900);
PAINT GREEN (2900 900);
FORCEPROP 2 LAST CDS_LIB cnpower
J 0
(2900 850);
DISPLAY INVISIBLE (2900 850);
FORCEPROP 1 LASTPIN (2900 800) VHDL_INIT 1
R 1
J 0
(2950 635);
DISPLAY 0.468085 (2950 635);
PAINT GREEN (2950 635);
DISPLAY INVISIBLE (2950 635);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(2900 850);
DISPLAY 0.468085 (2900 850);
PAINT GREEN (2900 850);
DISPLAY INVISIBLE (2900 850);
FORCEPROP 1 LAST SIZE 1B
J 0
(2875 950);
DISPLAY 0.872340 (2875 950);
PAINT SKYBLUE (2875 950);
DISPLAY INVISIBLE (2875 950);
FORCEADD RSMD0603..2
R 1
(-750 -3050);
FORCEPROP 1 LAST LOCATION R65
R 1
J 1
(-787 -3045);
DISPLAY 0.723404 (-787 -3045);
PAINT WHITE (-787 -3045);
FORCEPROP 1 LAST VALUE XX
R 1
J 1
......@@ -330,6 +674,12 @@ J 1
(-690 -3045);
DISPLAY 0.617021 (-690 -3045);
PAINT WHITE (-690 -3045);
FORCEPROP 1 LAST LOCATION R65
R 1
J 1
(-787 -3045);
DISPLAY 0.723404 (-787 -3045);
PAINT WHITE (-787 -3045);
FORCEPROP 1 LAST DIST FLAT
R 1
J 0
......@@ -428,12 +778,6 @@ DISPLAY INVISIBLE (-625 -3045);
FORCEADD RSMD0603..2
R 1
(-1050 -2600);
FORCEPROP 1 LAST LOCATION R60
R 1
J 1
(-1087 -2595);
DISPLAY 0.723404 (-1087 -2595);
PAINT WHITE (-1087 -2595);
FORCEPROP 1 LAST VALUE 00
R 1
J 1
......@@ -446,6 +790,12 @@ J 1
(-990 -2595);
DISPLAY 0.617021 (-990 -2595);
PAINT WHITE (-990 -2595);
FORCEPROP 1 LAST LOCATION R60
R 1
J 1
(-1087 -2595);
DISPLAY 0.723404 (-1087 -2595);
PAINT WHITE (-1087 -2595);
FORCEPROP 1 LAST DIST FLAT
R 1
J 0
......@@ -544,12 +894,6 @@ DISPLAY INVISIBLE (-925 -2595);
FORCEADD RSMD0603..2
R 1
(-900 -2600);
FORCEPROP 1 LAST LOCATION R62
R 1
J 1
(-937 -2595);
DISPLAY 0.723404 (-937 -2595);
PAINT WHITE (-937 -2595);
FORCEPROP 1 LAST VALUE 00
R 1
J 1
......@@ -562,6 +906,12 @@ J 1
(-840 -2595);
DISPLAY 0.617021 (-840 -2595);
PAINT WHITE (-840 -2595);
FORCEPROP 1 LAST LOCATION R62
R 1
J 1
(-937 -2595);
DISPLAY 0.723404 (-937 -2595);
PAINT WHITE (-937 -2595);
FORCEPROP 1 LAST DIST FLAT
R 1
J 0
......@@ -660,12 +1010,6 @@ DISPLAY INVISIBLE (-775 -2595);
FORCEADD RSMD0603..2
R 1
(-750 -2600);
FORCEPROP 1 LAST LOCATION R64
R 1
J 1
(-787 -2595);
DISPLAY 0.723404 (-787 -2595);
PAINT WHITE (-787 -2595);
FORCEPROP 1 LAST VALUE 00
R 1
J 1
......@@ -678,6 +1022,12 @@ J 1
(-690 -2595);
DISPLAY 0.617021 (-690 -2595);
PAINT WHITE (-690 -2595);
FORCEPROP 1 LAST LOCATION R64
R 1
J 1
(-787 -2595);
DISPLAY 0.723404 (-787 -2595);
PAINT WHITE (-787 -2595);
FORCEPROP 1 LAST DIST FLAT
R 1
J 0
......@@ -1212,146 +1562,6 @@ J 0
DISPLAY 0.404255 (4586 560);
PAINT SKYBLUE (4586 560);
DISPLAY INVISIBLE (4586 560);
FORCEADD TAP..1
(1750 -1450);
FORCEPROP 1 LASTPIN (1700 -1450) BN 3
J 0
(1688 -1442);
DISPLAY 0.680851 (1688 -1442);
PAINT GREEN (1688 -1442);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(2075 -1575);
DISPLAY 0.872340 (2075 -1575);
DISPLAY INVISIBLE (2075 -1575);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(1750 -1400);
DISPLAY 0.872340 (1750 -1400);
PAINT GREEN (1750 -1400);
DISPLAY INVISIBLE (1750 -1400);
FORCEPROP 1 LAST PATH I20
J 0
(1748 -1450);
DISPLAY 0.872340 (1748 -1450);
PAINT GREEN (1748 -1450);
DISPLAY INVISIBLE (1748 -1450);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(1750 -1450);
DISPLAY INVISIBLE (1750 -1450);
FORCEADD TAP..1
(1750 -750);
FORCEPROP 1 LASTPIN (1700 -750) BN 21
J 0
(1688 -742);
DISPLAY 0.680851 (1688 -742);
PAINT GREEN (1688 -742);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(1750 -750);
DISPLAY INVISIBLE (1750 -750);
FORCEPROP 1 LAST PATH I21
J 0
(1748 -750);
DISPLAY 0.872340 (1748 -750);
PAINT GREEN (1748 -750);
DISPLAY INVISIBLE (1748 -750);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(1750 -700);
DISPLAY 0.872340 (1750 -700);
PAINT GREEN (1750 -700);
DISPLAY INVISIBLE (1750 -700);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(2075 -875);
DISPLAY 0.872340 (2075 -875);
DISPLAY INVISIBLE (2075 -875);
FORCEADD TAP..1
(1750 -1825);
FORCEPROP 1 LASTPIN (1700 -1825) BN 8
J 0
(1688 -1817);
DISPLAY 0.680851 (1688 -1817);
PAINT GREEN (1688 -1817);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(1750 -1825);
DISPLAY INVISIBLE (1750 -1825);
FORCEPROP 1 LAST PATH I22
J 0
(1748 -1825);
DISPLAY 0.872340 (1748 -1825);
PAINT GREEN (1748 -1825);
DISPLAY INVISIBLE (1748 -1825);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(1750 -1775);
DISPLAY 0.872340 (1750 -1775);
PAINT GREEN (1750 -1775);
DISPLAY INVISIBLE (1750 -1775);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(2075 -1950);
DISPLAY 0.872340 (2075 -1950);
DISPLAY INVISIBLE (2075 -1950);
FORCEADD TAP..1
(1750 -1575);
FORCEPROP 1 LASTPIN (1700 -1575) BN 14
J 0
(1688 -1567);
DISPLAY 0.680851 (1688 -1567);
PAINT GREEN (1688 -1567);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(2075 -1700);
DISPLAY 0.872340 (2075 -1700);
DISPLAY INVISIBLE (2075 -1700);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(1750 -1525);
DISPLAY 0.872340 (1750 -1525);
PAINT GREEN (1750 -1525);
DISPLAY INVISIBLE (1750 -1525);
FORCEPROP 1 LAST PATH I24
J 0
(1748 -1575);
DISPLAY 0.872340 (1748 -1575);
PAINT GREEN (1748 -1575);
DISPLAY INVISIBLE (1748 -1575);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(1750 -1575);
DISPLAY INVISIBLE (1750 -1575);
FORCEADD TAP..1
(1750 -1700);
FORCEPROP 1 LASTPIN (1700 -1700) BN 18
J 0
(1688 -1692);
DISPLAY 0.680851 (1688 -1692);
PAINT GREEN (1688 -1692);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(1750 -1700);
DISPLAY INVISIBLE (1750 -1700);
FORCEPROP 1 LAST PATH I28
J 0
(1748 -1700);
DISPLAY 0.872340 (1748 -1700);
PAINT GREEN (1748 -1700);
DISPLAY INVISIBLE (1748 -1700);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(1750 -1650);
DISPLAY 0.872340 (1750 -1650);
PAINT GREEN (1750 -1650);
DISPLAY INVISIBLE (1750 -1650);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(2075 -1825);
DISPLAY 0.872340 (2075 -1825);
DISPLAY INVISIBLE (2075 -1825);
FORCEADD GND_SIGNAL..1
(4300 -1600);
FORCEPROP 3 LASTPIN (4350 -1550) SIG_NAME GND_SIGNAL\g
......@@ -1378,62 +1588,6 @@ J 0
(4300 -1600);
DISPLAY INVISIBLE (4300 -1600);
FORCEADD TAP..1
(1750 -1325);
FORCEPROP 1 LASTPIN (1700 -1325) BN 27
J 0
(1688 -1317);
DISPLAY 0.680851 (1688 -1317);
PAINT GREEN (1688 -1317);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(2075 -1450);
DISPLAY 0.872340 (2075 -1450);
DISPLAY INVISIBLE (2075 -1450);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(1750 -1275);
DISPLAY 0.872340 (1750 -1275);
PAINT GREEN (1750 -1275);
DISPLAY INVISIBLE (1750 -1275);
FORCEPROP 1 LAST PATH I31
J 0
(1748 -1325);
DISPLAY 0.872340 (1748 -1325);
PAINT GREEN (1748 -1325);
DISPLAY INVISIBLE (1748 -1325);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(1750 -1325);
DISPLAY INVISIBLE (1750 -1325);
FORCEADD TAP..1
(1750 -500);
FORCEPROP 1 LASTPIN (1700 -500) BN 11
J 0
(1688 -492);
DISPLAY 0.680851 (1688 -492);
PAINT GREEN (1688 -492);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(2075 -625);
DISPLAY 0.872340 (2075 -625);
DISPLAY INVISIBLE (2075 -625);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(1750 -450);
DISPLAY 0.872340 (1750 -450);
PAINT GREEN (1750 -450);
DISPLAY INVISIBLE (1750 -450);
FORCEPROP 1 LAST PATH I35
J 0
(1748 -500);
DISPLAY 0.872340 (1748 -500);
PAINT GREEN (1748 -500);
DISPLAY INVISIBLE (1748 -500);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(1750 -500);
DISPLAY INVISIBLE (1750 -500);
FORCEADD TAP..1
(1750 250);
FORCEPROP 1 LASTPIN (1700 250) BN 25
J 0
......@@ -1588,174 +1742,6 @@ J 0
(1750 500);
DISPLAY INVISIBLE (1750 500);
FORCEADD TAP..1
(1750 -2050);
FORCEPROP 1 LASTPIN (1700 -2050) BN 15
J 0
(1688 -2042);
DISPLAY 0.680851 (1688 -2042);
PAINT GREEN (1688 -2042);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(1750 -2050);
DISPLAY INVISIBLE (1750 -2050);
FORCEPROP 1 LAST PATH I41
J 0
(1748 -2050);
DISPLAY 0.872340 (1748 -2050);
PAINT GREEN (1748 -2050);
DISPLAY INVISIBLE (1748 -2050);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(1750 -2000);
DISPLAY 0.872340 (1750 -2000);
PAINT GREEN (1750 -2000);
DISPLAY INVISIBLE (1750 -2000);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(2075 -2175);
DISPLAY 0.872340 (2075 -2175);
DISPLAY INVISIBLE (2075 -2175);
FORCEADD TAP..1
(1750 -875);
FORCEPROP 1 LASTPIN (1700 -875) BN 20
J 0
(1688 -867);
DISPLAY 0.680851 (1688 -867);
PAINT GREEN (1688 -867);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(2075 -1000);
DISPLAY 0.872340 (2075 -1000);
DISPLAY INVISIBLE (2075 -1000);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(1750 -825);
DISPLAY 0.872340 (1750 -825);
PAINT GREEN (1750 -825);
DISPLAY INVISIBLE (1750 -825);
FORCEPROP 1 LAST PATH I42
J 0
(1748 -875);
DISPLAY 0.872340 (1748 -875);
PAINT GREEN (1748 -875);
DISPLAY INVISIBLE (1748 -875);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(1750 -875);
DISPLAY INVISIBLE (1750 -875);
FORCEADD TAP..1
(1750 -125);
FORCEPROP 1 LASTPIN (1700 -125) BN 16
J 0
(1688 -117);
DISPLAY 0.680851 (1688 -117);
PAINT GREEN (1688 -117);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(2075 -250);
DISPLAY 0.872340 (2075 -250);
DISPLAY INVISIBLE (2075 -250);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(1750 -75);
DISPLAY 0.872340 (1750 -75);
PAINT GREEN (1750 -75);
DISPLAY INVISIBLE (1750 -75);
FORCEPROP 1 LAST PATH I43
J 0
(1748 -125);
DISPLAY 0.872340 (1748 -125);
PAINT GREEN (1748 -125);
DISPLAY INVISIBLE (1748 -125);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(1750 -125);
DISPLAY INVISIBLE (1750 -125);
FORCEADD TAP..1
(1750 -375);
FORCEPROP 1 LASTPIN (1700 -375) BN 7
J 0
(1688 -367);
DISPLAY 0.680851 (1688 -367);
PAINT GREEN (1688 -367);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(2075 -500);
DISPLAY 0.872340 (2075 -500);
DISPLAY INVISIBLE (2075 -500);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(1750 -325);
DISPLAY 0.872340 (1750 -325);
PAINT GREEN (1750 -325);
DISPLAY INVISIBLE (1750 -325);
FORCEPROP 1 LAST PATH I44
J 0
(1748 -375);
DISPLAY 0.872340 (1748 -375);
PAINT GREEN (1748 -375);
DISPLAY INVISIBLE (1748 -375);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(1750 -375);
DISPLAY INVISIBLE (1750 -375);
FORCEADD TAP..1
(1750 -250);
FORCEPROP 1 LASTPIN (1700 -250) BN 12
J 0
(1688 -242);
DISPLAY 0.680851 (1688 -242);
PAINT GREEN (1688 -242);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(2075 -375);
DISPLAY 0.872340 (2075 -375);
DISPLAY INVISIBLE (2075 -375);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(1750 -200);
DISPLAY 0.872340 (1750 -200);
PAINT GREEN (1750 -200);
DISPLAY INVISIBLE (1750 -200);
FORCEPROP 1 LAST PATH I45
J 0
(1748 -250);
DISPLAY 0.872340 (1748 -250);
PAINT GREEN (1748 -250);
DISPLAY INVISIBLE (1748 -250);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(1750 -250);
DISPLAY INVISIBLE (1750 -250);
FORCEADD TAP..1
(1750 -1000);
FORCEPROP 1 LASTPIN (1700 -1000) BN 19
J 0
(1688 -992);
DISPLAY 0.680851 (1688 -992);
PAINT GREEN (1688 -992);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(1750 -1000);
DISPLAY INVISIBLE (1750 -1000);
FORCEPROP 1 LAST PATH I46
J 0
(1748 -1000);
DISPLAY 0.872340 (1748 -1000);
PAINT GREEN (1748 -1000);
DISPLAY INVISIBLE (1748 -1000);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(1750 -950);
DISPLAY 0.872340 (1750 -950);
PAINT GREEN (1750 -950);
DISPLAY INVISIBLE (1750 -950);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(2075 -1125);
DISPLAY 0.872340 (2075 -1125);
DISPLAY INVISIBLE (2075 -1125);
FORCEADD TAP..1
(1750 625);
FORCEPROP 1 LASTPIN (1700 625) BN 28
J 0
......@@ -1784,34 +1770,6 @@ J 0
DISPLAY 0.872340 (2075 500);
DISPLAY INVISIBLE (2075 500);
FORCEADD TAP..1
(1750 0);
FORCEPROP 1 LASTPIN (1700 0) BN 2
J 0
(1688 8);
DISPLAY 0.680851 (1688 8);
PAINT GREEN (1688 8);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(1750 0);
DISPLAY INVISIBLE (1750 0);
FORCEPROP 1 LAST PATH I48
J 0
(1748 0);
DISPLAY 0.872340 (1748 0);
PAINT GREEN (1748 0);
DISPLAY INVISIBLE (1748 0);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(1750 50);
DISPLAY 0.872340 (1750 50);
PAINT GREEN (1750 50);
DISPLAY INVISIBLE (1750 50);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(2075 -125);
DISPLAY 0.872340 (2075 -125);
DISPLAY INVISIBLE (2075 -125);
FORCEADD TAP..1
(1750 750);
FORCEPROP 1 LASTPIN (1700 750) BN 31
J 0
......@@ -1995,34 +1953,6 @@ J 0
DISPLAY 0.872340 (475 625);
DISPLAY INVISIBLE (475 625);
FORCEADD TAP..1
(150 0);
FORCEPROP 1 LASTPIN (100 0) BN 2
J 0
(88 8);
DISPLAY 0.680851 (88 8);
PAINT GREEN (88 8);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(150 0);
DISPLAY INVISIBLE (150 0);
FORCEPROP 1 LAST PATH I56
J 0
(148 0);
DISPLAY 0.872340 (148 0);
PAINT GREEN (148 0);
DISPLAY INVISIBLE (148 0);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(150 50);
DISPLAY 0.872340 (150 50);
PAINT GREEN (150 50);
DISPLAY INVISIBLE (150 50);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(475 -125);
DISPLAY 0.872340 (475 -125);
DISPLAY INVISIBLE (475 -125);
FORCEADD TAP..1
(150 625);
FORCEPROP 1 LASTPIN (100 625) BN 28
J 0
......@@ -2051,174 +1981,6 @@ J 0
DISPLAY 0.872340 (475 500);
DISPLAY INVISIBLE (475 500);
FORCEADD TAP..1
(150 -250);
FORCEPROP 1 LASTPIN (100 -250) BN 12
J 0
(88 -242);
DISPLAY 0.680851 (88 -242);
PAINT GREEN (88 -242);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(150 -250);
DISPLAY INVISIBLE (150 -250);
FORCEPROP 1 LAST PATH I58
J 0
(148 -250);
DISPLAY 0.872340 (148 -250);
PAINT GREEN (148 -250);
DISPLAY INVISIBLE (148 -250);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(150 -200);
DISPLAY 0.872340 (150 -200);
PAINT GREEN (150 -200);
DISPLAY INVISIBLE (150 -200);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(475 -375);
DISPLAY 0.872340 (475 -375);
DISPLAY INVISIBLE (475 -375);
FORCEADD TAP..1
(150 -1000);
FORCEPROP 1 LASTPIN (100 -1000) BN 19
J 0
(88 -992);
DISPLAY 0.680851 (88 -992);
PAINT GREEN (88 -992);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(150 -1000);
DISPLAY INVISIBLE (150 -1000);
FORCEPROP 1 LAST PATH I59
J 0
(148 -1000);
DISPLAY 0.872340 (148 -1000);
PAINT GREEN (148 -1000);
DISPLAY INVISIBLE (148 -1000);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(150 -950);
DISPLAY 0.872340 (150 -950);
PAINT GREEN (150 -950);
DISPLAY INVISIBLE (150 -950);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(475 -1125);
DISPLAY 0.872340 (475 -1125);
DISPLAY INVISIBLE (475 -1125);
FORCEADD TAP..1
(150 -375);
FORCEPROP 1 LASTPIN (100 -375) BN 7
J 0
(88 -367);
DISPLAY 0.680851 (88 -367);
PAINT GREEN (88 -367);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(150 -375);
DISPLAY INVISIBLE (150 -375);
FORCEPROP 1 LAST PATH I60
J 0
(148 -375);
DISPLAY 0.872340 (148 -375);
PAINT GREEN (148 -375);
DISPLAY INVISIBLE (148 -375);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(150 -325);
DISPLAY 0.872340 (150 -325);
PAINT GREEN (150 -325);
DISPLAY INVISIBLE (150 -325);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(475 -500);
DISPLAY 0.872340 (475 -500);
DISPLAY INVISIBLE (475 -500);
FORCEADD TAP..1
(150 -125);
FORCEPROP 1 LASTPIN (100 -125) BN 16
J 0
(88 -117);
DISPLAY 0.680851 (88 -117);
PAINT GREEN (88 -117);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(150 -125);
DISPLAY INVISIBLE (150 -125);
FORCEPROP 1 LAST PATH I61
J 0
(148 -125);
DISPLAY 0.872340 (148 -125);
PAINT GREEN (148 -125);
DISPLAY INVISIBLE (148 -125);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(150 -75);
DISPLAY 0.872340 (150 -75);
PAINT GREEN (150 -75);
DISPLAY INVISIBLE (150 -75);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(475 -250);
DISPLAY 0.872340 (475 -250);
DISPLAY INVISIBLE (475 -250);
FORCEADD TAP..1
(150 -875);
FORCEPROP 1 LASTPIN (100 -875) BN 20
J 0
(88 -867);
DISPLAY 0.680851 (88 -867);
PAINT GREEN (88 -867);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(150 -875);
DISPLAY INVISIBLE (150 -875);
FORCEPROP 1 LAST PATH I62
J 0
(148 -875);
DISPLAY 0.872340 (148 -875);
PAINT GREEN (148 -875);
DISPLAY INVISIBLE (148 -875);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(150 -825);
DISPLAY 0.872340 (150 -825);
PAINT GREEN (150 -825);
DISPLAY INVISIBLE (150 -825);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(475 -1000);
DISPLAY 0.872340 (475 -1000);
DISPLAY INVISIBLE (475 -1000);
FORCEADD TAP..1
(150 -2050);
FORCEPROP 1 LASTPIN (100 -2050) BN 4
J 0
(88 -2042);
DISPLAY 0.680851 (88 -2042);
PAINT GREEN (88 -2042);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(475 -2175);
DISPLAY 0.872340 (475 -2175);
DISPLAY INVISIBLE (475 -2175);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(150 -2000);
DISPLAY 0.872340 (150 -2000);
PAINT GREEN (150 -2000);
DISPLAY INVISIBLE (150 -2000);
FORCEPROP 1 LAST PATH I63
J 0
(148 -2050);
DISPLAY 0.872340 (148 -2050);
PAINT GREEN (148 -2050);
DISPLAY INVISIBLE (148 -2050);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(150 -2050);
DISPLAY INVISIBLE (150 -2050);
FORCEADD TAP..1
(150 375);
FORCEPROP 1 LASTPIN (100 375) BN 24
J 0
......@@ -2333,31 +2095,6 @@ DISPLAY INVISIBLE (475 125);
FORCEADD PLEMO2CI..1
R 2
(2050 50);
FORCEPROP 2 LASTPIN (2200 50) $PN 2
J 0
(2210 60);
DISPLAY 0.808511 (2210 60);
FORCEPROP 2 LASTPIN (2200 150) $PN 1
J 0
(2210 160);
DISPLAY 0.808511 (2210 160);
FORCEPROP 1 LAST PATH I7
J 0
(2100 250);
DISPLAY 1.021277 (2100 250);
FORCEPROP 1 LAST TYPE PLEMO2-00B
J 0
(2100 400);
DISPLAY 1.021277 (2100 400);
FORCEPROP 1 LAST $LOCATION PX1
J 0
(2100 500);
DISPLAY 0.680851 (2100 500);
PAINT MONO (2100 500);
FORCEPROP 0 LAST POWER_GROUP GND=GND_SIGNAL
J 0
(2100 450);
DISPLAY 1.021277 (2100 450);
FORCEPROP 2 LASTPIN (2200 50) SIG_NAME UN$1$PLEMO2CI$I7$B
J 0
(2210 60);
......@@ -2370,172 +2107,49 @@ J 0
DISPLAY 0.659574 (2210 160);
PAINT MONO (2210 160);
DISPLAY INVISIBLE (2210 160);
FORCEPROP 1 LAST TYPE EPG.00.302.NLN
J 2
(2475 350);
DISPLAY 0.723404 (2475 350);
PAINT WHITE (2475 350);
FORCEPROP 2 LAST CDS_LIB cnconnector
J 0
(2050 50);
DISPLAY INVISIBLE (2050 50);
FORCEPROP 0 LAST POWER_GROUP GND=GND_SIGNAL
J 0
(2100 450);
DISPLAY 1.021277 (2100 450);
FORCEPROP 2 LAST CDS_SEC 1
J 0
(2100 550);
DISPLAY 1.021277 (2100 550);
DISPLAY INVISIBLE (2100 550);
FORCEPROP 2 LAST $SEC 1
J 0
(2100 550);
DISPLAY 0.680851 (2100 550);
PAINT MONO (2100 550);
DISPLAY INVISIBLE (2100 550);
FORCEPROP 2 LAST CDS_LOCATION PX1
J 0
(2100 550);
DISPLAY 1.021277 (2100 550);
DISPLAY INVISIBLE (2100 550);
FORCEPROP 1 LAST $LOCATION PX1
J 2
(2025 100);
DISPLAY 0.723404 (2025 100);
PAINT WHITE (2025 100);
FORCEPROP 1 LAST NEEDS_NO_SIZE TRUE
J 2
(2025 75);
DISPLAY 0.872340 (2025 75);
PAINT GREEN (2025 75);
DISPLAY INVISIBLE (2025 75);
FORCEPROP 2 LAST CDS_LIB cnconnector
J 0
(2050 50);
DISPLAY INVISIBLE (2050 50);
FORCEADD TAP..1
(150 -500);
FORCEPROP 1 LASTPIN (100 -500) BN 11
J 0
(88 -492);
DISPLAY 0.680851 (88 -492);
PAINT GREEN (88 -492);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(150 -500);
DISPLAY INVISIBLE (150 -500);
FORCEPROP 1 LAST PATH I70
J 0
(148 -500);
DISPLAY 0.872340 (148 -500);
PAINT GREEN (148 -500);
DISPLAY INVISIBLE (148 -500);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(150 -450);
DISPLAY 0.872340 (150 -450);
PAINT GREEN (150 -450);
DISPLAY INVISIBLE (150 -450);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(475 -625);
DISPLAY 0.872340 (475 -625);
DISPLAY INVISIBLE (475 -625);
FORCEADD TAP..1
(150 -1325);
FORCEPROP 1 LASTPIN (100 -1325) BN 27
J 0
(88 -1317);
DISPLAY 0.680851 (88 -1317);
PAINT GREEN (88 -1317);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(150 -1325);
DISPLAY INVISIBLE (150 -1325);
FORCEPROP 1 LAST PATH I73
J 0
(148 -1325);
DISPLAY 0.872340 (148 -1325);
PAINT GREEN (148 -1325);
DISPLAY INVISIBLE (148 -1325);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(150 -1275);
DISPLAY 0.872340 (150 -1275);
PAINT GREEN (150 -1275);
DISPLAY INVISIBLE (150 -1275);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(475 -1450);
DISPLAY 0.872340 (475 -1450);
DISPLAY INVISIBLE (475 -1450);
FORCEADD TAP..1
(150 -1700);
FORCEPROP 1 LASTPIN (100 -1700) BN 18
J 0
(88 -1692);
DISPLAY 0.680851 (88 -1692);
PAINT GREEN (88 -1692);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(475 -1825);
DISPLAY 0.872340 (475 -1825);
DISPLAY INVISIBLE (475 -1825);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(150 -1650);
DISPLAY 0.872340 (150 -1650);
PAINT GREEN (150 -1650);
DISPLAY INVISIBLE (150 -1650);
FORCEPROP 1 LAST PATH I76
J 0
(148 -1700);
DISPLAY 0.872340 (148 -1700);
PAINT GREEN (148 -1700);
DISPLAY INVISIBLE (148 -1700);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(150 -1700);
DISPLAY INVISIBLE (150 -1700);
FORCEADD TAP..1
(150 -1575);
FORCEPROP 1 LASTPIN (100 -1575) BN 14
J 0
(88 -1567);
DISPLAY 0.680851 (88 -1567);
PAINT GREEN (88 -1567);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(475 -1700);
DISPLAY 0.872340 (475 -1700);
DISPLAY INVISIBLE (475 -1700);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(150 -1525);
DISPLAY 0.872340 (150 -1525);
PAINT GREEN (150 -1525);
DISPLAY INVISIBLE (150 -1525);
FORCEPROP 1 LAST PATH I79
J 0
(148 -1575);
DISPLAY 0.872340 (148 -1575);
PAINT GREEN (148 -1575);
DISPLAY INVISIBLE (148 -1575);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(150 -1575);
DISPLAY INVISIBLE (150 -1575);
FORCEADD 24AA025E48..1
(-200 -2950);
FORCEPROP 1 LAST LOCATION IC9
J 1
(-195 -2600);
DISPLAY 0.723404 (-195 -2600);
PAINT GREEN (-195 -2600);
FORCEPROP 1 LAST PACK_TYPE SOIC
J 1
(-195 -2650);
DISPLAY 0.723404 (-195 -2650);
PAINT GREEN (-195 -2650);
FORCEPROP 1 LAST TYPE 24AA025E48
J 1
(-195 -2705);
DISPLAY 0.851064 (-195 -2705);
PAINT GREEN (-195 -2705);
FORCEPROP 1 LAST PATH I8
J 0
(-50 -2800);
DISPLAY 0.723404 (-50 -2800);
PAINT GREEN (-50 -2800);
DISPLAY INVISIBLE (-50 -2800);
FORCEPROP 2 LAST CDS_LIB cnmemory
J 0
(-200 -2950);
DISPLAY INVISIBLE (-200 -2950);
FORCEPROP 2 LASTPIN (-400 -2900) SIG_NAME UN$1$24AA025E48$I8$A2
FORCEPROP 1 LAST PATH I7
J 1
(2175 200);
DISPLAY 0.723404 (2175 200);
PAINT WHITE (2175 200);
DISPLAY INVISIBLE (2175 200);
FORCEADD 24AA025E48..1
(-200 -2950);
FORCEPROP 2 LASTPIN (-400 -2900) SIG_NAME UN$1$24AA025E48$I8$A2
J 0
(-390 -2890);
DISPLAY 0.659574 (-390 -2890);
......@@ -2553,34 +2167,31 @@ J 0
DISPLAY 0.659574 (-390 -2790);
PAINT MONO (-390 -2790);
DISPLAY INVISIBLE (-390 -2790);
FORCEADD TAP..1
(150 -1825);
FORCEPROP 1 LASTPIN (100 -1825) BN 8
J 0
(88 -1817);
DISPLAY 0.680851 (88 -1817);
PAINT GREEN (88 -1817);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(150 -1825);
DISPLAY INVISIBLE (150 -1825);
FORCEPROP 1 LAST PATH I81
J 0
(148 -1825);
DISPLAY 0.872340 (148 -1825);
PAINT GREEN (148 -1825);
DISPLAY INVISIBLE (148 -1825);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
FORCEPROP 1 LAST PACK_TYPE SOIC
J 1
(-150 -2820);
DISPLAY 0.723404 (-150 -2820);
PAINT GREEN (-150 -2820);
FORCEPROP 1 LAST TYPE 24AA025E48T-I/SN
J 1
(-195 -2740);
DISPLAY 0.723404 (-195 -2740);
PAINT GREEN (-195 -2740);
FORCEPROP 2 LAST CDS_LIB cnmemory
J 0
(150 -1775);
DISPLAY 0.872340 (150 -1775);
PAINT GREEN (150 -1775);
DISPLAY INVISIBLE (150 -1775);
FORCEPROP 1 LAST HDL_TAP TRUE
(-200 -2950);
DISPLAY INVISIBLE (-200 -2950);
FORCEPROP 1 LAST $LOCATION IC?
J 1
(-200 -2695);
DISPLAY 0.723404 (-200 -2695);
PAINT GREEN (-200 -2695);
FORCEPROP 1 LAST PATH I8
J 0
(475 -1950);
DISPLAY 0.872340 (475 -1950);
DISPLAY INVISIBLE (475 -1950);
(-50 -2800);
DISPLAY 0.723404 (-50 -2800);
PAINT GREEN (-50 -2800);
DISPLAY INVISIBLE (-50 -2800);
FORCEADD TAP..1
(150 -2200);
FORCEPROP 1 LASTPIN (100 -2200) BN 0
......@@ -2609,161 +2220,6 @@ J 0
(475 -2325);
DISPLAY 0.872340 (475 -2325);
DISPLAY INVISIBLE (475 -2325);
FORCEADD TAP..1
(150 -750);
FORCEPROP 1 LASTPIN (100 -750) BN 21
J 0
(88 -742);
DISPLAY 0.680851 (88 -742);
PAINT GREEN (88 -742);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(150 -750);
DISPLAY INVISIBLE (150 -750);
FORCEPROP 1 LAST PATH I83
J 0
(148 -750);
DISPLAY 0.872340 (148 -750);
PAINT GREEN (148 -750);
DISPLAY INVISIBLE (148 -750);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(150 -700);
DISPLAY 0.872340 (150 -700);
PAINT GREEN (150 -700);
DISPLAY INVISIBLE (150 -700);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(475 -875);
DISPLAY 0.872340 (475 -875);
DISPLAY INVISIBLE (475 -875);
FORCEADD TAP..1
(150 -1450);
FORCEPROP 1 LASTPIN (100 -1450) BN 3
J 0
(88 -1442);
DISPLAY 0.680851 (88 -1442);
PAINT GREEN (88 -1442);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(150 -1450);
DISPLAY INVISIBLE (150 -1450);
FORCEPROP 1 LAST PATH I84
J 0
(148 -1450);
DISPLAY 0.872340 (148 -1450);
PAINT GREEN (148 -1450);
DISPLAY INVISIBLE (148 -1450);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(475 -1575);
DISPLAY 0.872340 (475 -1575);
DISPLAY INVISIBLE (475 -1575);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(150 -1400);
DISPLAY 0.872340 (150 -1400);
PAINT GREEN (150 -1400);
DISPLAY INVISIBLE (150 -1400);
FORCEADD TAP..1
(150 -1125);
FORCEPROP 1 LASTPIN (100 -1125) BN 22
J 0
(88 -1117);
DISPLAY 0.680851 (88 -1117);
PAINT GREEN (88 -1117);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(150 -1125);
DISPLAY INVISIBLE (150 -1125);
FORCEPROP 1 LAST PATH I85
J 0
(148 -1125);
DISPLAY 0.872340 (148 -1125);
PAINT GREEN (148 -1125);
DISPLAY INVISIBLE (148 -1125);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(475 -1250);
DISPLAY 0.872340 (475 -1250);
DISPLAY INVISIBLE (475 -1250);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(150 -1075);
DISPLAY 0.872340 (150 -1075);
PAINT GREEN (150 -1075);
DISPLAY INVISIBLE (150 -1075);
FORCEADD TAP..1
(1750 -1125);
FORCEPROP 1 LASTPIN (1700 -1125) BN 22
J 0
(1688 -1117);
DISPLAY 0.680851 (1688 -1117);
PAINT GREEN (1688 -1117);
FORCEPROP 1 LAST HDL_TAP TRUE
J 0
(2075 -1250);
DISPLAY 0.872340 (2075 -1250);
DISPLAY INVISIBLE (2075 -1250);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(1750 -1075);
DISPLAY 0.872340 (1750 -1075);
PAINT GREEN (1750 -1075);
DISPLAY INVISIBLE (1750 -1075);
FORCEPROP 1 LAST PATH I86
J 0
(1748 -1125);
DISPLAY 0.872340 (1748 -1125);
PAINT GREEN (1748 -1125);
DISPLAY INVISIBLE (1748 -1125);
FORCEPROP 2 LAST CDS_LIB standard
J 0
(1750 -1125);
DISPLAY INVISIBLE (1750 -1125);
FORCEADD P2V5..1
(2900 850);
FORCEPROP 3 LASTPIN (2900 800) SIG_NAME P2V5\g
J 0
(2910 810);
DISPLAY 0.659574 (2910 810);
PAINT MONO (2910 810);
DISPLAY INVISIBLE (2910 810);
FORCEPROP 2 LAST CDS_LIB cnpower
J 0
(2900 850);
DISPLAY INVISIBLE (2900 850);
FORCEPROP 1 LASTPIN (2900 800) VHDL_INIT 1
R 1
J 0
(2950 635);
DISPLAY 0.468085 (2950 635);
PAINT GREEN (2950 635);
DISPLAY INVISIBLE (2950 635);
FORCEPROP 1 LAST SIZE 1B
J 0
(2875 950);
DISPLAY 0.872340 (2875 950);
PAINT SKYBLUE (2875 950);
DISPLAY INVISIBLE (2875 950);
FORCEPROP 1 LAST HDL_POWER P2V5
J 0
(2900 850);
DISPLAY 0.468085 (2900 850);
PAINT GREEN (2900 850);
DISPLAY INVISIBLE (2900 850);
FORCEPROP 1 LAST BODY_TYPE PLUMBING
J 0
(2900 850);
DISPLAY 0.468085 (2900 850);
PAINT GREEN (2900 850);
DISPLAY INVISIBLE (2900 850);
FORCEPROP 1 LAST PATH I88
J 0
(2950 850);
DISPLAY 0.872340 (2950 850);
PAINT PINK (2950 850);
DISPLAY INVISIBLE (2950 850);
FORCEADD GND_SIGNAL..1
(2250 -150);
FORCEPROP 3 LASTPIN (2300 -100) SIG_NAME GND_SIGNAL\g
......@@ -2834,11 +2290,6 @@ DISPLAY INVISIBLE (-475 -3100);
FORCEADD CAPCERSMDCL2..1
R 1
(3050 500);
FORCEPROP 1 LAST LOCATION C1
R 1
J 0
(3000 475);
DISPLAY 0.723404 (3000 475);
FORCEPROP 1 LAST VALUE 100NF
R 1
J 1
......@@ -2849,6 +2300,11 @@ R 1
J 1
(3200 500);
DISPLAY 0.723404 (3200 500);
FORCEPROP 1 LAST LOCATION C1
R 1
J 0
(3000 475);
DISPLAY 0.723404 (3000 475);
FORCEPROP 1 LAST PATH I90
R 1
J 0
......@@ -2912,11 +2368,6 @@ DISPLAY 0.978723 (3000 450);
DISPLAY INVISIBLE (3000 450);
FORCEADD USBLC6-2..1
(2600 100);
FORCEPROP 1 LAST LOCATION D3
J 1
(2605 318);
DISPLAY 0.723404 (2605 318);
PAINT WHITE (2605 318);
FORCEPROP 1 LAST TYPE USBLC6-2SC6
J 1
(2605 263);
......@@ -2927,6 +2378,11 @@ J 1
(2605 -98);
DISPLAY 0.723404 (2605 -98);
PAINT WHITE (2605 -98);
FORCEPROP 1 LAST LOCATION D3
J 1
(2605 318);
DISPLAY 0.723404 (2605 318);
PAINT WHITE (2605 318);
FORCEPROP 2 LAST CDS_LIB cndiscrete
J 0
(2600 100);
......@@ -3114,16 +2570,11 @@ J 0
DISPLAY INVISIBLE (2600 -3650);
FORCEADD ZENER..1
(3325 525);
FORCEPROP 1 LAST LOCATION Z4
FORCEPROP 1 LAST TYPE BZT52-C3V6
J 2
(3467 487);
DISPLAY 0.723404 (3467 487);
PAINT WHITE (3467 487);
FORCEPROP 1 LAST TYPE BZT52C2V7
J 2
(3690 570);
DISPLAY 0.723404 (3690 570);
PAINT WHITE (3690 570);
(3750 525);
DISPLAY 0.723404 (3750 525);
PAINT WHITE (3750 525);
FORCEPROP 1 LAST PACK_TYPE SOD123-CA
J 0
(3365 520);
......@@ -3134,6 +2585,11 @@ FORCEPROP 2 LAST CDS_LIB cndiscrete
J 0
(3325 525);
DISPLAY INVISIBLE (3325 525);
FORCEPROP 1 LAST $LOCATION ZD?
J 2
(3292 537);
DISPLAY 0.723404 (3292 537);
PAINT WHITE (3292 537);
FORCEPROP 1 LAST PATH I98
J 0
(3350 850);
......@@ -3184,34 +2640,29 @@ J 0
DISPLAY INVISIBLE (4050 750);
FORCEADD A3-2000..1
(1500 350);
FORCEPROP 0 LAST CDS_CON_LAST_MODIFIED Thu Apr 21 14:46:20 2016
FORCEPROP 0 LAST CDS_CON_LAST_MODIFIED Fri May 20 14:40:51 2016
J 0
(3250 -2450);
DISPLAY INVISIBLE (3250 -2450);
FORCEPROP 1 LAST CUSTOM_TXT_CDS <CON_LAST_MODIFIED>
J 0
(3250 -2450);
PAINT GREEN (3250 -2450);
FORCEPROP 1 LAST CUSTOM_TXT_CDS OVERALL PAGE: <CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
J 0
(4875 -3850);
DISPLAY 1.255319 (4875 -3850);
PAINT GREEN (4875 -3850);
FORCEPROP 1 LAST CUSTOM_TXT_CDS MODULE PAGE: <CON_PAGE_NUM> OF <CON_TOTAL_PAGES>
J 0
(4925 -3750);
DISPLAY 1.255319 (4925 -3750);
PAINT GREEN (4925 -3750);
FORCEPROP 1 LAST CUSTOM_TXT_CDS <CON_DESIGN_LIB>
J 0
(3350 -3225);
DISPLAY 1.978723 (3350 -3225);
PAINT GREEN (3350 -3225);
FORCEPROP 1 LAST CUSTOM_TXT_CDS MODULE: <CON_DESIGN_NAME>
J 0
(2900 -3350);
DISPLAY 1.255319 (2900 -3350);
PAINT GREEN (2900 -3350);
FORCEPROP 1 LAST COMMENT_BODY TRUE
J 0
(6300 -5625);
......@@ -3222,499 +2673,385 @@ FORCEPROP 2 LAST CDS_LIB bris_cds_standard
J 0
(1500 350);
DISPLAY INVISIBLE (1500 350);
WIRE 16 -1 (50 -3300)(50 -3350);
WIRE 16 -1 (-100 -3300)(50 -3300);
WIRE 16 -1 (4050 700)(4050 425);
WIRE 16 -1 (2600 -3500)(2600 -3600);
WIRE 16 -1 (1050 -3500)(2600 -3500);
WIRE 16 -1 (2600 -3450)(2600 -3350);
WIRE 16 -1 (1050 -3450)(2600 -3450);
WIRE 16 -1 (1900 -2800)(1900 -2500);
WIRE 16 -1 (1200 -2800)(1900 -2800);
WIRE 16 -1 (1900 -3350)(1900 -3650);
WIRE 16 -1 (1900 -3250)(1900 -3350);
WIRE 16 -1 (1050 -3350)(1900 -3350);
WIRE 16 -1 (3050 375)(3050 350);
WIRE 16 -1 (3325 375)(3050 375);
WIRE 16 -1 (3050 400)(3050 375);
WIRE 16 -1 (-450 -3300)(-450 -3250);
WIRE 16 -1 (-450 -3300)(-750 -3300);
WIRE 16 -1 (-450 -3300)(-300 -3300);
WIRE 16 -1 (2300 100)(2300 -100);
WIRE 16 -1 (2350 100)(2300 100);
WIRE 16 -1 (4450 700)(4450 425);
WIRE 16 -1 (4350 -1550)(4350 -1375);
WIRE 16 -1 (-1300 -2400)(-1300 -2600);
WIRE 16 -1 (-1050 -2400)(-1300 -2400);
WIRE 16 -1 (4350 -1550)(4350 -1375);
WIRE 16 -1 (50 -3300)(50 -3350);
WIRE 16 -1 (-100 -3300)(50 -3300);
WIRE 16 -1 (4250 700)(4250 425);
WIRE 16 -1 (4450 700)(4450 425);
WIRE 16 -1 (2900 650)(2900 800);
WIRE 16 -1 (3050 650)(2900 650);
WIRE 16 -1 (2900 100)(2900 650);
WIRE 16 -1 (2300 100)(2300 -100);
WIRE 16 -1 (2350 100)(2300 100);
WIRE 16 -1 (-450 -3300)(-450 -3250);
WIRE 16 -1 (-450 -3300)(-750 -3300);
WIRE 16 -1 (-450 -3300)(-300 -3300);
WIRE 16 -1 (3050 375)(3050 350);
WIRE 16 -1 (3325 375)(3050 375);
WIRE 16 -1 (3050 400)(3050 375);
WIRE 16 -1 (1900 -3350)(1900 -3650);
WIRE 16 -1 (1900 -3250)(1900 -3350);
WIRE 16 -1 (1050 -3350)(1900 -3350);
WIRE 16 -1 (1900 -2800)(1900 -2500);
WIRE 16 -1 (1200 -2800)(1900 -2800);
WIRE 16 -1 (2600 -3450)(2600 -3350);
WIRE 16 -1 (1050 -3450)(2600 -3450);
WIRE 16 -1 (2600 -3500)(2600 -3600);
WIRE 16 -1 (1050 -3500)(2600 -3500);
WIRE 16 -1 (4050 700)(4050 425);
WIRE 16 -1 (-1050 -2400)(-1050 -2500);
WIRE 16 -1 (-900 -2400)(-1050 -2400);
WIRE 16 -1 (-900 -2400)(-900 -2500);
WIRE 16 -1 (-750 -2400)(-900 -2400);
WIRE 16 -1 (-750 -2500)(-750 -2400);
WIRE 16 -1 (3325 475)(3325 375);
WIRE 16 -1 (2850 100)(2900 100);
WIRE 16 -1 (3050 600)(3050 650);
WIRE 16 -1 (3325 650)(3050 650);
WIRE 16 -1 (3325 575)(3325 650);
WIRE 16 -1 (-300 -3150)(-300 -3300);
WIRE 16 -1 (-750 -3150)(-750 -3300);
WIRE 16 -1 (-400 -3000)(-600 -3000);
FORCEPROP 2 LAST SIG_NAME SCL
J 0
(-610 -2990);
DISPLAY 1.021277 (-610 -2990);
WIRE 16 -1 (0 -3000)(250 -3000);
FORCEPROP 2 LAST SIG_NAME SDA
J 0
(90 -2990);
DISPLAY 1.021277 (90 -2990);
WIRE 16 -1 (-100 -3150)(-100 -3300);
WIRE 16 -1 (-1050 -3150)(-1050 -3300);
WIRE 16 -1 (-900 -3150)(-900 -3300);
WIRE 16 -1 (-900 -3300)(-750 -3300);
WIRE 16 -1 (-1050 -3300)(-900 -3300);
WIRE 16 -1 (-1050 -3150)(-1050 -3300);
WIRE 16 -1 (3325 475)(3325 375);
WIRE 16 -1 (1050 -3250)(1900 -3250);
WIRE 16 -1 (1900 -3150)(1900 -3250);
WIRE 16 -1 (1050 -3150)(1900 -3150);
WIRE 16 -1 (1900 -3050)(1900 -3150);
WIRE 16 -1 (1050 -3050)(1900 -3050);
WIRE 16 -1 (1900 -2950)(1900 -3050);
WIRE 16 -1 (1050 -2950)(1900 -2950);
WIRE 16 -1 (1900 -2850)(1900 -2950);
WIRE 16 -1 (1050 -2850)(1900 -2850);
WIRE 16 -1 (1050 -2800)(1200 -2800);
WIRE 16 -1 (1200 -2750)(1200 -2800);
WIRE 16 -1 (1050 -2750)(1200 -2750);
WIRE 16 -1 (-100 -3150)(-100 -3300);
WIRE 16 -1 (1700 1125)(500 1125);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER_CFD*<0>
WIRE 16 -1 (-750 -3150)(-750 -3300);
WIRE 16 -1 (-900 -3300)(-750 -3300);
WIRE 16 -1 (-300 -3150)(-300 -3300);
WIRE 16 -1 (-1050 -2800)(-1050 -2950);
WIRE 16 -1 (-1050 -2700)(-1050 -2800);
WIRE 16 -1 (-400 -2800)(-1050 -2800);
WIRE 16 -1 (-900 -2850)(-900 -2950);
WIRE 16 -1 (-900 -2700)(-900 -2850);
WIRE 16 -1 (-400 -2850)(-900 -2850);
WIRE 16 -1 (-750 -2900)(-750 -2950);
WIRE 16 -1 (-750 -2700)(-750 -2900);
WIRE 16 -1 (-400 -2900)(-750 -2900);
WIRE 16 -1 (2250 200)(2350 200);
WIRE 16 -1 (2250 150)(2250 200);
WIRE 16 -1 (2200 150)(2250 150);
WIRE 16 -1 (2250 0)(2350 0);
WIRE 16 -1 (2250 50)(2250 0);
WIRE 16 -1 (2200 50)(2250 50);
WIRE 16 -1 (1700 625)(500 625);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER_CFD*<2>
J 0
(540 1135);
DISPLAY 1.021277 (540 1135);
(540 635);
DISPLAY 1.021277 (540 635);
WIRE 16 -1 (2850 200)(2950 200);
WIRE 16 -1 (2950 200)(2950 125);
WIRE 16 -1 (3700 125)(2950 125);
FORCEPROP 2 LAST SIG_NAME FRONT_PANEL_CLK
J 0
(2990 160);
DISPLAY 1.021277 (2990 160);
WIRE 17 -1 (3700 -375)(3700 -350);
WIRE 17 -1 (3700 -350)(2700 -350);
WIRE 17 -1 (2700 -350)(2700 -2200);
WIRE 17 -1 (1800 -2200)(2700 -2200);
FORCEPROP 2 LAST SIG_NAME FMC_LA<33..0>*
J 0
(1865 -2140);
DISPLAY 1.021277 (1865 -2140);
WIRE 17 -1 (1800 -2200)(1800 -650);
WIRE 17 -1 (1800 -450)(1800 -650);
WIRE 17 -1 (1800 -250)(1800 -450);
WIRE 17 -1 (1800 -50)(1800 -250);
WIRE 17 -1 (1800 150)(1800 -50);
WIRE 17 -1 (1800 275)(1800 150);
WIRE 17 -1 (1800 400)(1800 275);
WIRE 17 -1 (1800 525)(1800 400);
WIRE 17 -1 (1800 1150)(1800 1025);
WIRE 17 -1 (1800 650)(1800 525);
WIRE 17 -1 (1800 775)(1800 650);
WIRE 17 -1 (1800 1025)(1800 900);
WIRE 17 -1 (1800 900)(1800 775);
WIRE 16 -1 (1700 125)(-1100 125);
FORCEPROP 2 LAST SIG_NAME CONT_TO_FPGA<0>
J 0
(-1125 135);
DISPLAY 1.021277 (-1125 135);
WIRE 16 -1 (-1100 -75)(1700 -75);
FORCEPROP 2 LAST SIG_NAME SPARE_TO_FPGA<0>
J 0
(-1125 -65);
DISPLAY 1.021277 (-1125 -65);
WIRE 16 -1 (-1100 -275)(1700 -275);
FORCEPROP 2 LAST SIG_NAME TRIG_TO_FPGA<0>
J 0
(-1125 -265);
DISPLAY 1.021277 (-1125 -265);
WIRE 16 -1 (1700 -475)(-1100 -475);
FORCEPROP 2 LAST SIG_NAME BUSY_TO_FPGA<0>
J 0
(-1125 -465);
DISPLAY 1.021277 (-1125 -465);
WIRE 16 -1 (1700 -675)(-1100 -675);
FORCEPROP 2 LAST SIG_NAME CLK_TO_FPGA<0>
J 0
(-1125 -665);
DISPLAY 1.021277 (-1125 -665);
WIRE 16 -1 (1700 250)(500 250);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER*<3>
J 0
(540 260);
DISPLAY 1.021277 (540 260);
WIRE 17 -1 (200 1150)(200 1025);
WIRE 17 -1 (200 1025)(200 900);
WIRE 17 -1 (200 900)(200 775);
WIRE 17 -1 (200 775)(200 650);
WIRE 17 -1 (3700 -475)(3700 -450);
WIRE 17 -1 (200 650)(200 525);
WIRE 17 -1 (200 525)(200 400);
WIRE 17 -1 (3700 -450)(2925 -450);
WIRE 17 -1 (2925 -450)(2925 -2350);
WIRE 17 -1 (200 400)(200 275);
WIRE 17 -1 (200 275)(200 100);
WIRE 17 -1 (200 -2350)(2925 -2350);
FORCEPROP 2 LAST SIG_NAME FMC_LA<33..0>
J 0
(2015 -2340);
DISPLAY 1.021277 (2015 -2340);
WIRE 17 -1 (200 -2350)(200 -2175);
WIRE 17 -1 (200 -2175)(200 -2025);
WIRE 17 -1 (200 -1800)(200 -2025);
WIRE 17 -1 (200 -1675)(200 -1800);
WIRE 17 -1 (200 -1550)(200 -1675);
WIRE 17 -1 (200 -1425)(200 -1550);
WIRE 17 -1 (200 -1300)(200 -1425);
WIRE 17 -1 (200 -1100)(200 -1300);
WIRE 17 -1 (200 -975)(200 -1100);
WIRE 17 -1 (200 -850)(200 -975);
WIRE 17 -1 (200 -725)(200 -850);
WIRE 17 -1 (200 -475)(200 -725);
WIRE 17 -1 (200 -350)(200 -475);
WIRE 17 -1 (200 -225)(200 -350);
WIRE 17 -1 (200 -100)(200 -225);
WIRE 17 -1 (200 25)(200 -100);
WIRE 17 -1 (200 275)(200 25);
WIRE 17 -1 (200 400)(200 275);
WIRE 17 -1 (200 525)(200 400);
WIRE 17 -1 (200 650)(200 525);
WIRE 17 -1 (200 775)(200 650);
WIRE 17 -1 (200 900)(200 775);
WIRE 17 -1 (200 1025)(200 900);
WIRE 17 -1 (200 1150)(200 1025);
WIRE 16 -1 (100 1000)(-1100 1000);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER<0>
WIRE 17 -1 (200 100)(200 -100);
WIRE 17 -1 (200 -100)(200 -300);
WIRE 17 -1 (200 -2175)(200 -850);
WIRE 17 -1 (200 -700)(200 -850);
WIRE 17 -1 (200 -300)(200 -500);
WIRE 17 -1 (200 -500)(200 -700);
WIRE 16 -1 (100 -525)(-1100 -525);
FORCEPROP 2 LAST SIG_NAME BUSY_FROM_FPGA<0>
J 0
(-1125 -515);
DISPLAY 1.021277 (-1125 -515);
WIRE 16 -1 (100 -325)(-1100 -325);
FORCEPROP 2 LAST SIG_NAME TRIG_FROM_FPGA<0>
J 0
(-1125 -315);
DISPLAY 1.021277 (-1125 -315);
WIRE 16 -1 (100 75)(-1100 75);
FORCEPROP 2 LAST SIG_NAME CONT_FROM_FPGA<0>
J 0
(-1125 85);
DISPLAY 1.021277 (-1125 85);
WIRE 16 -1 (100 -125)(-1100 -125);
FORCEPROP 2 LAST SIG_NAME SPARE_FROM_FPGA<0>
J 0
(-1060 1010);
DISPLAY 1.021277 (-1060 1010);
WIRE 16 -1 (100 875)(-1100 875);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER_CFD<1>
(-1125 -115);
DISPLAY 1.021277 (-1125 -115);
WIRE 16 -1 (100 250)(-1100 250);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER<3>
J 0
(-1060 885);
DISPLAY 1.021277 (-1060 885);
(-1060 260);
DISPLAY 1.021277 (-1060 260);
WIRE 16 -1 (100 1125)(-1100 1125);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER_CFD<0>
J 0
(-1060 1135);
DISPLAY 1.021277 (-1060 1135);
WIRE 16 -1 (1700 500)(500 500);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER*<2>
J 0
(540 510);
DISPLAY 1.021277 (540 510);
WIRE 16 -1 (1700 375)(500 375);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER_CFD*<3>
J 0
(540 385);
DISPLAY 1.021277 (540 385);
WIRE 16 -1 (1700 250)(500 250);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER*<3>
J 0
(540 260);
DISPLAY 1.021277 (540 260);
WIRE 16 -1 (1700 0)(500 0);
FORCEPROP 2 LAST SIG_NAME CLK2*
WIRE 16 -1 (1050 -2750)(1200 -2750);
WIRE 16 -1 (1050 -2800)(1200 -2800);
WIRE 16 -1 (1200 -2750)(1200 -2800);
WIRE 16 -1 (1050 -2850)(1900 -2850);
WIRE 16 -1 (1050 -2950)(1900 -2950);
WIRE 16 -1 (1900 -2850)(1900 -2950);
WIRE 16 -1 (1050 -3050)(1900 -3050);
WIRE 16 -1 (1900 -2950)(1900 -3050);
WIRE 16 -1 (1050 -3150)(1900 -3150);
WIRE 16 -1 (1900 -3050)(1900 -3150);
WIRE 16 -1 (1050 -3250)(1900 -3250);
WIRE 16 -1 (1900 -3150)(1900 -3250);
WIRE 16 -1 (-750 -2500)(-750 -2400);
WIRE 16 -1 (-900 -2400)(-900 -2500);
WIRE 16 -1 (-750 -2400)(-900 -2400);
WIRE 16 -1 (-1050 -2400)(-1050 -2500);
WIRE 16 -1 (-900 -2400)(-1050 -2400);
WIRE 16 -1 (5000 -575)(5000 -550);
WIRE 16 -1 (5000 -550)(5650 -550);
FORCEPROP 2 LAST SIG_NAME SDA
J 0
(540 10);
DISPLAY 1.021277 (540 10);
WIRE 16 -1 (100 -2050)(-1100 -2050);
FORCEPROP 2 LAST SIG_NAME HDMI_POWER_ENABLE1
(5490 -540);
DISPLAY 1.021277 (5490 -540);
WIRE 16 -1 (2850 0)(2950 0);
WIRE 16 -1 (2950 0)(2950 50);
WIRE 16 -1 (3700 25)(3700 50);
WIRE 16 -1 (3700 50)(2950 50);
FORCEPROP 2 LAST SIG_NAME FRONT_PANEL_CLK*
J 0
(-1060 -2040);
DISPLAY 1.021277 (-1060 -2040);
WIRE 16 -1 (100 -2200)(-1100 -2200);
FORCEPROP 2 LAST SIG_NAME GPIO_CLK
(2990 10);
DISPLAY 1.021277 (2990 10);
WIRE 16 -1 (5000 -675)(5000 -700);
WIRE 16 -1 (5000 -700)(5650 -700);
FORCEPROP 2 LAST SIG_NAME SCL
J 0
(-1110 -2190);
DISPLAY 1.021277 (-1110 -2190);
WIRE 16 -1 (-750 -2900)(-750 -2950);
WIRE 16 -1 (-400 -2900)(-750 -2900);
WIRE 16 -1 (-750 -2700)(-750 -2900);
WIRE 16 -1 (-900 -2850)(-900 -2950);
WIRE 16 -1 (-400 -2850)(-900 -2850);
WIRE 16 -1 (-900 -2700)(-900 -2850);
WIRE 16 -1 (-1050 -2800)(-1050 -2950);
WIRE 16 -1 (-400 -2800)(-1050 -2800);
WIRE 16 -1 (-1050 -2700)(-1050 -2800);
WIRE 16 -1 (1050 -2900)(2200 -2900);
(5490 -690);
DISPLAY 1.021277 (5490 -690);
WIRE 16 -1 (3700 -75)(2950 -75);
FORCEPROP 2 LAST SIG_NAME CLK_IO_1
J 0
(2040 -2890);
DISPLAY 1.021277 (2040 -2890);
WIRE 16 -1 (1050 -3000)(2200 -3000);
FORCEPROP 2 LAST SIG_NAME GPIO_CLK
J 0
(2140 -2990);
DISPLAY 1.021277 (2140 -2990);
WIRE 16 -1 (1050 -3100)(2200 -3100);
(2990 -65);
DISPLAY 1.021277 (2990 -65);
WIRE 16 -1 (3700 -175)(2975 -175);
FORCEPROP 2 LAST SIG_NAME CLK_IO_2
J 0
(2090 -3090);
DISPLAY 1.021277 (2090 -3090);
WIRE 16 -1 (1050 -3300)(2200 -3300);
FORCEPROP 2 LAST SIG_NAME SDA
(3015 -165);
DISPLAY 1.021277 (3015 -165);
WIRE 16 -1 (3725 -175)(3700 -175);
WIRE 16 -1 (100 500)(-1100 500);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER<2>
J 0
(2140 -3290);
DISPLAY 1.021277 (2140 -3290);
WIRE 16 -1 (1050 -3400)(2200 -3400);
FORCEPROP 2 LAST SIG_NAME SCL
(-1060 510);
DISPLAY 1.021277 (-1060 510);
WIRE 16 -1 (100 625)(-1100 625);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER_CFD<2>
J 0
(2140 -3390);
DISPLAY 1.021277 (2140 -3390);
WIRE 17 -1 (1800 1150)(1800 1025);
WIRE 17 -1 (1800 1025)(1800 900);
WIRE 17 -1 (1800 900)(1800 775);
WIRE 17 -1 (1800 775)(1800 650);
WIRE 17 -1 (1800 650)(1800 525);
WIRE 17 -1 (1800 525)(1800 400);
WIRE 17 -1 (1800 400)(1800 275);
WIRE 17 -1 (1800 275)(1800 25);
WIRE 17 -1 (1800 25)(1800 -100);
WIRE 17 -1 (1800 -100)(1800 -225);
WIRE 17 -1 (1800 -225)(1800 -350);
WIRE 17 -1 (1800 -350)(1800 -475);
WIRE 17 -1 (1800 -475)(1800 -725);
WIRE 17 -1 (1800 -725)(1800 -850);
WIRE 17 -1 (1800 -975)(1800 -850);
WIRE 17 -1 (1800 -975)(1800 -1100);
WIRE 17 -1 (1800 -1100)(1800 -1300);
WIRE 17 -1 (1800 -1300)(1800 -1425);
WIRE 17 -1 (1800 -1425)(1800 -1550);
WIRE 17 -1 (1800 -1550)(1800 -1675);
WIRE 17 -1 (1800 -1675)(1800 -1800);
WIRE 17 -1 (1800 -1800)(1800 -2025);
WIRE 17 -1 (1800 -2200)(1800 -2025);
WIRE 17 -1 (1800 -2200)(2700 -2200);
FORCEPROP 2 LAST SIG_NAME FMC_LA<33..0>*
(-1060 635);
DISPLAY 1.021277 (-1060 635);
WIRE 16 -1 (100 750)(-1100 750);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER<1>
J 0
(1865 -2140);
DISPLAY 1.021277 (1865 -2140);
WIRE 17 -1 (2700 -350)(2700 -2200);
WIRE 17 -1 (3700 -350)(2700 -350);
WIRE 17 -1 (3700 -375)(3700 -350);
WIRE 16 -1 (1700 -500)(500 -500);
FORCEPROP 2 LAST SIG_NAME SPARE2*
J 0
(540 -490);
DISPLAY 1.021277 (540 -490);
WIRE 16 -1 (1700 -375)(500 -375);
FORCEPROP 2 LAST SIG_NAME CONT2*
J 0
(540 -365);
DISPLAY 1.021277 (540 -365);
WIRE 16 -1 (1700 -250)(500 -250);
FORCEPROP 2 LAST SIG_NAME BUSY2*
J 0
(540 -240);
DISPLAY 1.021277 (540 -240);
WIRE 16 -1 (1700 -125)(500 -125);
FORCEPROP 2 LAST SIG_NAME TRIG2*
J 0
(540 -115);
DISPLAY 1.021277 (540 -115);
WIRE 16 -1 (1700 625)(500 625);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER_CFD*<2>
(-1060 760);
DISPLAY 1.021277 (-1060 760);
WIRE 16 -1 (1700 750)(500 750);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER*<1>
J 0
(540 635);
DISPLAY 1.021277 (540 635);
(540 760);
DISPLAY 1.021277 (540 760);
WIRE 16 -1 (1700 875)(500 875);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER_CFD*<1>
J 0
(540 885);
DISPLAY 1.021277 (540 885);
WIRE 16 -1 (1700 1000)(500 1000);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER*<0>
J 0
(540 1010);
DISPLAY 1.021277 (540 1010);
WIRE 16 -1 (1700 875)(500 875);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER_CFD*<1>
WIRE 16 -1 (1050 -3400)(2200 -3400);
FORCEPROP 2 LAST SIG_NAME SCL
J 0
(540 885);
DISPLAY 1.021277 (540 885);
WIRE 16 -1 (1700 750)(500 750);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER*<1>
(2140 -3390);
DISPLAY 1.021277 (2140 -3390);
WIRE 16 -1 (1050 -3300)(2200 -3300);
FORCEPROP 2 LAST SIG_NAME SDA
J 0
(540 760);
DISPLAY 1.021277 (540 760);
WIRE 16 -1 (100 750)(-1100 750);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER<1>
(2140 -3290);
DISPLAY 1.021277 (2140 -3290);
WIRE 16 -1 (1050 -3100)(2200 -3100);
FORCEPROP 2 LAST SIG_NAME CLK_IO_2
J 0
(-1060 760);
DISPLAY 1.021277 (-1060 760);
WIRE 16 -1 (100 625)(-1100 625);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER_CFD<2>
(2090 -3090);
DISPLAY 1.021277 (2090 -3090);
WIRE 16 -1 (1050 -3000)(2200 -3000);
FORCEPROP 2 LAST SIG_NAME GPIO_CLK
J 0
(-1060 635);
DISPLAY 1.021277 (-1060 635);
WIRE 16 -1 (100 500)(-1100 500);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER<2>
(2140 -2990);
DISPLAY 1.021277 (2140 -2990);
WIRE 16 -1 (1050 -2900)(2200 -2900);
FORCEPROP 2 LAST SIG_NAME CLK_IO_1
J 0
(-1060 510);
DISPLAY 1.021277 (-1060 510);
WIRE 16 -1 (1700 -875)(500 -875);
FORCEPROP 2 LAST SIG_NAME TRIG0*
J 0
(540 -865);
DISPLAY 1.021277 (540 -865);
WIRE 16 -1 (1700 -750)(500 -750);
FORCEPROP 2 LAST SIG_NAME DUT_CLK0*
J 0
(490 -740);
DISPLAY 1.021277 (490 -740);
WIRE 16 -1 (100 -500)(-1100 -500);
FORCEPROP 2 LAST SIG_NAME SPARE2
J 0
(-1110 -490);
DISPLAY 1.021277 (-1110 -490);
WIRE 16 -1 (100 -375)(-1100 -375);
FORCEPROP 2 LAST SIG_NAME CONT2
J 0
(-1110 -365);
DISPLAY 1.021277 (-1110 -365);
WIRE 16 -1 (100 250)(-1100 250);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER<3>
(2040 -2890);
DISPLAY 1.021277 (2040 -2890);
WIRE 16 -1 (1700 375)(500 375);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER_CFD*<3>
J 0
(-1060 260);
DISPLAY 1.021277 (-1060 260);
WIRE 16 -1 (100 -250)(-1100 -250);
FORCEPROP 2 LAST SIG_NAME BUSY2
(540 385);
DISPLAY 1.021277 (540 385);
WIRE 16 -1 (1700 500)(500 500);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER*<2>
J 0
(-1110 -240);
DISPLAY 1.021277 (-1110 -240);
WIRE 16 -1 (100 -750)(-1100 -750);
FORCEPROP 2 LAST SIG_NAME DUT_CLK0
(540 510);
DISPLAY 1.021277 (540 510);
WIRE 16 -1 (1700 1125)(500 1125);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER_CFD*<0>
J 0
(-1060 -740);
DISPLAY 1.021277 (-1060 -740);
WIRE 16 -1 (100 -875)(-1100 -875);
FORCEPROP 2 LAST SIG_NAME TRIG0
J 0
(-1060 -865);
DISPLAY 1.021277 (-1060 -865);
WIRE 16 -1 (100 -1000)(-1100 -1000);
FORCEPROP 2 LAST SIG_NAME BUSY0
J 0
(-1060 -990);
DISPLAY 1.021277 (-1060 -990);
WIRE 16 -1 (100 -1125)(-1125 -1125);
FORCEPROP 2 LAST SIG_NAME CONT0
J 0
(-1135 -1115);
DISPLAY 1.021277 (-1135 -1115);
WIRE 16 -1 (100 -1325)(-1100 -1325);
FORCEPROP 2 LAST SIG_NAME CLK1
J 0
(-1110 -1315);
DISPLAY 1.021277 (-1110 -1315);
WIRE 16 -1 (1700 -1575)(500 -1575);
FORCEPROP 2 LAST SIG_NAME BUSY1*
J 0
(490 -1565);
DISPLAY 1.021277 (490 -1565);
WIRE 16 -1 (1700 -1700)(500 -1700);
FORCEPROP 2 LAST SIG_NAME CONT1*
J 0
(490 -1690);
DISPLAY 1.021277 (490 -1690);
WIRE 16 -1 (1700 -1825)(525 -1825);
FORCEPROP 2 LAST SIG_NAME SPARE1*
J 0
(490 -1815);
DISPLAY 1.021277 (490 -1815);
WIRE 16 -1 (1700 -1000)(500 -1000);
FORCEPROP 2 LAST SIG_NAME BUSY0*
J 0
(540 -990);
DISPLAY 1.021277 (540 -990);
WIRE 16 -1 (450 -1125)(1700 -1125);
FORCEPROP 2 LAST SIG_NAME CONT0*
J 0
(440 -1115);
DISPLAY 1.021277 (440 -1115);
WIRE 16 -1 (100 -125)(-1100 -125);
FORCEPROP 2 LAST SIG_NAME TRIG2
(540 1135);
DISPLAY 1.021277 (540 1135);
WIRE 16 -1 (100 -2200)(-1100 -2200);
FORCEPROP 2 LAST SIG_NAME GPIO_CLK
J 0
(-1110 -115);
DISPLAY 1.021277 (-1110 -115);
WIRE 16 -1 (100 0)(-1100 0);
FORCEPROP 2 LAST SIG_NAME CLK2
(-1110 -2190);
DISPLAY 1.021277 (-1110 -2190);
WIRE 16 -1 (100 1000)(-1100 1000);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER<0>
J 0
(-1110 10);
DISPLAY 1.021277 (-1110 10);
WIRE 16 -1 (2850 200)(2950 200);
WIRE 16 -1 (2950 200)(2950 125);
WIRE 16 -1 (3700 125)(2950 125);
FORCEPROP 2 LAST SIG_NAME FRONT_PANEL_CLK
(-1060 1010);
DISPLAY 1.021277 (-1060 1010);
WIRE 16 -1 (100 875)(-1100 875);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER_CFD<1>
J 0
(2990 160);
DISPLAY 1.021277 (2990 160);
WIRE 16 -1 (1700 -1325)(500 -1325);
FORCEPROP 2 LAST SIG_NAME CLK1*
J 0
(490 -1315);
DISPLAY 1.021277 (490 -1315);
WIRE 16 -1 (100 -1825)(-1100 -1825);
FORCEPROP 2 LAST SIG_NAME SPARE1
J 0
(-1110 -1815);
DISPLAY 1.021277 (-1110 -1815);
WIRE 16 -1 (1700 -1450)(500 -1450);
FORCEPROP 2 LAST SIG_NAME TRIG1*
J 0
(490 -1440);
DISPLAY 1.021277 (490 -1440);
WIRE 16 -1 (100 -1575)(-1100 -1575);
FORCEPROP 2 LAST SIG_NAME BUSY1
J 0
(-1110 -1565);
DISPLAY 1.021277 (-1110 -1565);
(-1060 885);
DISPLAY 1.021277 (-1060 885);
WIRE 16 -1 (100 375)(-1100 375);
FORCEPROP 2 LAST SIG_NAME BEAM_TRIGGER_CFD<3>
J 0
(-1060 385);
DISPLAY 1.021277 (-1060 385);
WIRE 16 -1 (100 -1450)(-1100 -1450);
FORCEPROP 2 LAST SIG_NAME TRIG1
J 0
(-1110 -1440);
DISPLAY 1.021277 (-1110 -1440);
WIRE 16 -1 (100 -1700)(-1100 -1700);
FORCEPROP 2 LAST SIG_NAME CONT1
J 0
(-1110 -1690);
DISPLAY 1.021277 (-1110 -1690);
WIRE 16 -1 (1700 -2050)(500 -2050);
FORCEPROP 2 LAST SIG_NAME HDMI_POWER_ENABLE2
J 0
(590 -2040);
DISPLAY 1.021277 (590 -2040);
WIRE 16 -1 (3700 -175)(2975 -175);
FORCEPROP 2 LAST SIG_NAME CLK_IO_2
J 0
(3015 -165);
DISPLAY 1.021277 (3015 -165);
WIRE 16 -1 (3725 -175)(3700 -175);
WIRE 16 -1 (3700 -75)(2950 -75);
FORCEPROP 2 LAST SIG_NAME CLK_IO_1
J 0
(2990 -65);
DISPLAY 1.021277 (2990 -65);
WIRE 16 -1 (2200 150)(2250 150);
WIRE 16 -1 (2250 150)(2250 200);
WIRE 16 -1 (2250 200)(2350 200);
WIRE 16 -1 (5000 -675)(5000 -700);
WIRE 16 -1 (5000 -700)(5650 -700);
FORCEPROP 2 LAST SIG_NAME SCL
J 0
(5490 -690);
DISPLAY 1.021277 (5490 -690);
WIRE 16 -1 (0 -3000)(250 -3000);
FORCEPROP 2 LAST SIG_NAME SDA
J 0
(90 -2990);
DISPLAY 1.021277 (90 -2990);
WIRE 16 -1 (3700 25)(3700 50);
WIRE 16 -1 (3700 50)(2950 50);
FORCEPROP 2 LAST SIG_NAME FRONT_PANEL_CLK*
J 0
(2990 10);
DISPLAY 1.021277 (2990 10);
WIRE 16 -1 (2950 0)(2950 50);
WIRE 16 -1 (2850 0)(2950 0);
WIRE 16 -1 (2200 50)(2250 50);
WIRE 16 -1 (2250 50)(2250 0);
WIRE 16 -1 (2250 0)(2350 0);
WIRE 16 -1 (5000 -575)(5000 -550);
WIRE 16 -1 (5000 -550)(5650 -550);
FORCEPROP 2 LAST SIG_NAME SDA
WIRE 16 -1 (100 -875)(-1100 -875);
FORCEPROP 2 LAST SIG_NAME HDMI_POWER_ENABLE<0>
J 0
(5490 -540);
DISPLAY 1.021277 (5490 -540);
WIRE 16 -1 (-400 -3000)(-600 -3000);
FORCEPROP 2 LAST SIG_NAME SCL
(-1125 -865);
DISPLAY 1.021277 (-1125 -865);
WIRE 16 -1 (100 -725)(-1100 -725);
FORCEPROP 2 LAST SIG_NAME CLK_FROM_FPGA<0>
J 0
(-610 -2990);
DISPLAY 1.021277 (-610 -2990);
DOT 1 (3050 650);
DOT 1 (3050 375);
DOT 1 (1900 -3350);
DOT 1 (1900 -3150);
DOT 1 (-900 -2400);
DOT 1 (-1050 -2400);
DOT 1 (-750 -2900);
DOT 1 (-450 -3300);
DOT 1 (-750 -3300);
DOT 1 (-900 -3300);
DOT 1 (2900 650);
DOT 1 (1200 -2800);
DOT 1 (1900 -2950);
DOT 1 (1900 -3250);
DOT 1 (-900 -2850);
DOT 1 (-1050 -2800);
(-1125 -715);
DISPLAY 1.021277 (-1125 -715);
DOT 1 (1900 -3050);
DOT 1 (-1050 -2800);
DOT 1 (-900 -2850);
DOT 1 (1900 -3250);
DOT 1 (1900 -2950);
DOT 1 (1200 -2800);
DOT 1 (2900 650);
DOT 1 (-900 -3300);
DOT 1 (-750 -3300);
DOT 1 (-450 -3300);
DOT 1 (-750 -2900);
DOT 1 (-1050 -2400);
DOT 1 (-900 -2400);
DOT 1 (1900 -3150);
DOT 1 (1900 -3350);
DOT 1 (3050 375);
DOT 1 (3050 650);
FORCENOTE
LICENSED UNDER THE TAPR OPEN HARDWARE LICENSE (WWW.TAPR.ORG/OHL)
(4100 -3600) 0;
DISPLAY LEFT (4100 -3600);
DISPLAY 0.808511 (4100 -3600);
11
(6200 -2850) 0;
DISPLAY LEFT (6200 -2850);
DISPLAY 1.021277 (6200 -2850);
FORCENOTE
AND I2C EEPROM
(5100 -3450) 0;
DISPLAY LEFT (5100 -3450);
DISPLAY 1.021277 (5100 -3450);
CONTAINS PRE-PROGRAMMED
(-1250 -3600) 0;
DISPLAY LEFT (-1250 -3600);
DISPLAY 1.021277 (-1250 -3600);
FORCENOTE
FMC CONNECTOR
(5100 -3300) 0;
DISPLAY LEFT (5100 -3300);
DISPLAY 2.000000 (5100 -3300);
UNIQUE ID CODE
(-1250 -3700) 0;
DISPLAY LEFT (-1250 -3700);
DISPLAY 1.021277 (-1250 -3700);
FORCENOTE
I2C EEPROM,
(-1250 -3500) 0;
DISPLAY LEFT (-1250 -3500);
DISPLAY 1.021277 (-1250 -3500);
FORCENOTE
UNIQUE ID CODE
(-1250 -3700) 0;
DISPLAY LEFT (-1250 -3700);
DISPLAY 1.021277 (-1250 -3700);
FMC CONNECTOR
(5100 -3300) 0;
DISPLAY LEFT (5100 -3300);
DISPLAY 2.000000 (5100 -3300);
FORCENOTE
CONTAINS PRE-PROGRAMMED
(-1250 -3600) 0;
DISPLAY LEFT (-1250 -3600);
DISPLAY 1.021277 (-1250 -3600);
AND I2C EEPROM
(5100 -3450) 0;
DISPLAY LEFT (5100 -3450);
DISPLAY 1.021277 (5100 -3450);
FORCENOTE
11
(6200 -2850) 0;
DISPLAY LEFT (6200 -2850);
DISPLAY 1.021277 (6200 -2850);
LICENSED UNDER THE TAPR OPEN HARDWARE LICENSE (WWW.TAPR.ORG/OHL)
(4100 -3600) 0;
DISPLAY LEFT (4100 -3600);
DISPLAY 0.808511 (4100 -3600);
QUIT
Cadence/worklib/fmc_tlu_toplevel_c/sch_1/page1.csv
View file @ a648eb8d
FILE_TYPE = CONNECTIVITY;
{Allegro Design Entry HDL 16.6-S055 (v16-6-112EN) 8/10/2015}
{Allegro Design Entry HDL 16.6-S055 (v16-6-112EP) 8/13/2015}
"PAGE_NUMBER" = 1;
0"NC";
1"GND_SIGNAL\g";
2"GND_SIGNAL\g";
3"P3V3\g";
4"P2V5\g";
5"P2V5\g";
6"GND_SIGNAL\g";
7"P3V3\g";
8"GND_SIGNAL\g";
9"GND_SIGNAL\g";
10"P3V3\g";
11"P5V\g";
12"M5V\g";
13"P12V\g";
14"GND_SIGNAL\g";
15"BEAM_TRIGGER_CFD*<0>";
16"FMC_LA<33..0>";
17"BEAM_TRIGGER<0>";
18"BEAM_TRIGGER_CFD<1>";
19"BEAM_TRIGGER_CFD<0>";
20"BEAM_TRIGGER*<2>";
21"BEAM_TRIGGER_CFD*<3>";
22"BEAM_TRIGGER*<3>";
23"CLK2*";
24"HDMI_POWER_ENABLE1";
25"GPIO_CLK";
26"UN$1$24AA025E48$I8$A2";
27"UN$1$24AA025E48$I8$A1";
28"UN$1$24AA025E48$I8$A0";
29"CLK_IO_1";
30"GPIO_CLK";
31"CLK_IO_2";
32"SDA";
33"SCL";
34"FMC_LA<33..0>*";
35"SPARE2*";
36"CONT2*";
37"BUSY2*";
38"TRIG2*";
39"BEAM_TRIGGER_CFD*<2>";
40"BEAM_TRIGGER*<0>";
41"BEAM_TRIGGER_CFD*<1>";
42"BEAM_TRIGGER*<1>";
43"BEAM_TRIGGER<1>";
2"P3V3\g";
3"SCL";
4"SDA";
5"GND_SIGNAL\g";
6"P3V3\g";
7"UN$1$24AA025E48$I8$A0";
8"UN$1$24AA025E48$I8$A1";
9"UN$1$24AA025E48$I8$A2";
10"UN$1$PLEMO2CI$I7$A";
11"UN$1$PLEMO2CI$I7$B";
12"BEAM_TRIGGER_CFD*<2>";
13"FRONT_PANEL_CLK";
14"FMC_LA<33..0>*";
15"CONT_TO_FPGA<0>";
16"SPARE_TO_FPGA<0>";
17"TRIG_TO_FPGA<0>";
18"BUSY_TO_FPGA<0>";
19"CLK_TO_FPGA<0>";
20"BEAM_TRIGGER*<3>";
21"FMC_LA<33..0>";
22"BUSY_FROM_FPGA<0>";
23"TRIG_FROM_FPGA<0>";
24"CONT_FROM_FPGA<0>";
25"SPARE_FROM_FPGA<0>";
26"BEAM_TRIGGER<3>";
27"BEAM_TRIGGER_CFD<0>";
28"P12V\g";
29"M5V\g";
30"P5V\g";
31"P3V3\g";
32"GND_SIGNAL\g";
33"GND_SIGNAL\g";
34"P2V5\g";
35"P3V3\g";
36"GND_SIGNAL\g";
37"GND_SIGNAL\g";
38"SDA";
39"FRONT_PANEL_CLK*";
40"SCL";
41"CLK_IO_1";
42"CLK_IO_2";
43"BEAM_TRIGGER<2>";
44"BEAM_TRIGGER_CFD<2>";
45"BEAM_TRIGGER<2>";
46"TRIG0*";
47"DUT_CLK0*";
48"SPARE2";
49"CONT2";
50"BEAM_TRIGGER<3>";
51"BUSY2";
52"DUT_CLK0";
53"TRIG0";
54"BUSY0";
55"CONT0";
56"CLK1";
57"BUSY1*";
58"CONT1*";
59"SPARE1*";
60"BUSY0*";
61"CONT0*";
62"TRIG2";
63"CLK2";
64"FRONT_PANEL_CLK";
65"CLK1*";
66"SPARE1";
67"TRIG1*";
68"BUSY1";
69"BEAM_TRIGGER_CFD<3>";
70"TRIG1";
71"CONT1";
72"HDMI_POWER_ENABLE2";
73"CLK_IO_2";
74"CLK_IO_1";
75"UN$1$PLEMO2CI$I7$A";
76"SCL";
77"SDA";
78"FRONT_PANEL_CLK*";
79"UN$1$PLEMO2CI$I7$B";
80"SDA";
81"SCL";
45"BEAM_TRIGGER<1>";
46"BEAM_TRIGGER*<1>";
47"BEAM_TRIGGER_CFD*<1>";
48"BEAM_TRIGGER*<0>";
49"SCL";
50"SDA";
51"CLK_IO_2";
52"GPIO_CLK";
53"CLK_IO_1";
54"BEAM_TRIGGER_CFD*<3>";
55"BEAM_TRIGGER*<2>";
56"BEAM_TRIGGER_CFD*<0>";
57"GPIO_CLK";
58"BEAM_TRIGGER<0>";
59"BEAM_TRIGGER_CFD<1>";
60"BEAM_TRIGGER_CFD<3>";
61"HDMI_POWER_ENABLE<0>";
62"CLK_FROM_FPGA<0>";
%"GND_SIGNAL"
"1","(0,-3400)","0","standard","I10";
;
CDS_LIB"standard"
HDL_POWER"GND_SIGNAL"
BODY_TYPE"PLUMBING";
"GND"14;
"GND"5;
%"TAP"
"1","(1750,125)","0","standard","I100";
;
HDL_TAP"TRUE"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"B \NAC \NWC"14;
"S \NAC"
BN"0"15;
%"TAP"
"1","(150,-725)","0","standard","I104";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"21;
"S \NAC"
BN"4"62;
%"TAP"
"1","(150,-525)","0","standard","I108";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"21;
"S \NAC"
BN"3"22;
%"CAPCERSMDCL2"
"1","(-200,-3300)","0","cnpassive","I11";
;
$LOCATION"C70"
CDS_SEC"1"
$SEC"1"
CDS_LOCATION"C70"
VOLTAGE"16V"
VALUE"100NF"
LOCATION"C70"
PACK_TYPE"0603"
CDS_LIB"cnpassive"
SIZE"1";
"B <SIZE-1..0>\NAC"
$PN"2"14;
"A <SIZE-1..0>\NAC"
$PN"1"7;
$PN"1"6;
"B <SIZE-1..0>\NAC"
$PN"2"5;
%"TAP"
"1","(150,-325)","0","standard","I112";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"21;
"S \NAC"
BN"2"23;
%"TAP"
"1","(150,-125)","0","standard","I116";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"21;
"S \NAC"
BN"1"25;
%"RSMD0603"
"2","(-1050,-3050)","1","cnpassive","I12";
;
$LOCATION"R61"
CDS_SEC"1"
$SEC"1"
CDS_LOCATION"R61"
VALUE"XX"
PACK_TYPE"1/10W"
LOCATION"R61"
DIST"FLAT"
MAX_TEMP"RTMAX"
NEGTOL"RTOL%"
......@@ -129,18 +155,72 @@ VOLTAGE"RVMAX"
CDS_LIB"cnpassive"
TOL"1%";
"A <SIZE-1..0>\NAC"
$PN"1"7;
$PN"1"6;
"B <SIZE-1..0>\NAC"
$PN"2"28;
$PN"2"7;
%"TAP"
"1","(150,75)","0","standard","I120";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"21;
"S \NAC"
BN"0"24;
%"TAP"
"1","(150,-875)","0","standard","I125";
;
HDL_TAP"TRUE"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"B \NAC \NWC"21;
"S \NAC"
BN"5"61;
%"TAP"
"1","(1750,-675)","0","standard","I126";
;
CDS_LIB"standard"
HDL_TAP"TRUE"
BODY_TYPE"PLUMBING";
"B \NAC \NWC"14;
"S \NAC"
BN"4"19;
%"TAP"
"1","(1750,-475)","0","standard","I127";
;
CDS_LIB"standard"
HDL_TAP"TRUE"
BODY_TYPE"PLUMBING";
"B \NAC \NWC"14;
"S \NAC"
BN"3"18;
%"TAP"
"1","(1750,-275)","0","standard","I128";
;
CDS_LIB"standard"
HDL_TAP"TRUE"
BODY_TYPE"PLUMBING";
"B \NAC \NWC"14;
"S \NAC"
BN"2"17;
%"TAP"
"1","(1750,-75)","0","standard","I129";
;
CDS_LIB"standard"
HDL_TAP"TRUE"
BODY_TYPE"PLUMBING";
"B \NAC \NWC"14;
"S \NAC"
BN"1"16;
%"RSMD0603"
"2","(-900,-3050)","1","cnpassive","I13";
;
$LOCATION"R63"
CDS_SEC"1"
$SEC"1"
CDS_LOCATION"R63"
VALUE"XX"
PACK_TYPE"1/10W"
LOCATION"R63"
DIST"FLAT"
MAX_TEMP"RTMAX"
NEGTOL"RTOL%"
......@@ -155,18 +235,27 @@ VOLTAGE"RVMAX"
CDS_LIB"cnpassive"
TOL"1%";
"A <SIZE-1..0>\NAC"
$PN"1"7;
$PN"1"6;
"B <SIZE-1..0>\NAC"
$PN"2"27;
$PN"2"8;
%"P3V3"
"1","(2900,850)","0","cnpower","I130";
;
HDL_POWER"P3V3"
CDS_LIB"cnpower"
BODY_TYPE"PLUMBING"
SIZE"1B";
"A<SIZE-1..0>\NAC"
VHDL_INIT"1"2;
%"RSMD0603"
"2","(-750,-3050)","1","cnpassive","I14";
;
$LOCATION"R65"
CDS_SEC"1"
$SEC"1"
CDS_LOCATION"R65"
VALUE"XX"
PACK_TYPE"1/10W"
LOCATION"R65"
DIST"FLAT"
MAX_TEMP"RTMAX"
NEGTOL"RTOL%"
......@@ -181,18 +270,18 @@ VOLTAGE"RVMAX"
CDS_LIB"cnpassive"
TOL"1%";
"A <SIZE-1..0>\NAC"
$PN"1"7;
$PN"1"6;
"B <SIZE-1..0>\NAC"
$PN"2"26;
$PN"2"9;
%"RSMD0603"
"2","(-1050,-2600)","1","cnpassive","I15";
;
$LOCATION"R60"
CDS_SEC"1"
$SEC"1"
CDS_LOCATION"R60"
VALUE"00"
PACK_TYPE""
LOCATION"R60"
DIST"FLAT"
MAX_TEMP"RTMAX"
NEGTOL"RTOL%"
......@@ -207,18 +296,18 @@ VOLTAGE"RVMAX"
CDS_LIB"cnpassive"
TOL"";
"A <SIZE-1..0>\NAC"
$PN"1"28;
$PN"1"7;
"B <SIZE-1..0>\NAC"
$PN"2"1;
$PN"2"37;
%"RSMD0603"
"2","(-900,-2600)","1","cnpassive","I16";
;
$LOCATION"R62"
CDS_SEC"1"
$SEC"1"
CDS_LOCATION"R62"
VALUE"00"
PACK_TYPE""
LOCATION"R62"
DIST"FLAT"
MAX_TEMP"RTMAX"
NEGTOL"RTOL%"
......@@ -233,18 +322,18 @@ VOLTAGE"RVMAX"
CDS_LIB"cnpassive"
TOL"";
"A <SIZE-1..0>\NAC"
$PN"1"27;
$PN"1"8;
"B <SIZE-1..0>\NAC"
$PN"2"1;
$PN"2"37;
%"RSMD0603"
"2","(-750,-2600)","1","cnpassive","I17";
;
$LOCATION"R64"
CDS_SEC"1"
$SEC"1"
CDS_LOCATION"R64"
VALUE"00"
PACK_TYPE""
LOCATION"R64"
DIST"FLAT"
MAX_TEMP"RTMAX"
NEGTOL"RTOL%"
......@@ -259,25 +348,25 @@ VOLTAGE"RVMAX"
CDS_LIB"cnpassive"
TOL"";
"A <SIZE-1..0>\NAC"
$PN"1"26;
$PN"1"9;
"B <SIZE-1..0>\NAC"
$PN"2"1;
$PN"2"37;
%"GND_SIGNAL"
"1","(-1350,-2650)","0","standard","I18";
;
HDL_POWER"GND_SIGNAL"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"GND"1;
"GND"37;
%"TAP"
"1","(1750,1125)","0","standard","I19";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"34;
"B \NAC \NWC"14;
"S \NAC"
BN"32"15;
BN"32"56;
%"PC036A_FMC_LPC_CONNECTOR"
"1","(4350,-350)","0","fmc_tlu_v1_lib","I2";
;
......@@ -289,22 +378,22 @@ USE1"ieee.std_logic_1164.all"
LIBRARY1"ieee";
"FMC_LA<33..0>*"
VHDL_MODE"inout"
VHDL_VECTOR_TYPE"std_logic_vector"34;
VHDL_VECTOR_TYPE"std_logic_vector"14;
"FMC_LA<33..0>"
VHDL_MODE"inout"
VHDL_VECTOR_TYPE"std_logic_vector"16;
VHDL_VECTOR_TYPE"std_logic_vector"21;
"FMC_CLK1_M2C*"
VHDL_MODE"inout"
VHDL_SCALAR_TYPE"std_logic"73;
VHDL_SCALAR_TYPE"std_logic"42;
"FMC_CLK1_M2C"
VHDL_MODE"inout"
VHDL_SCALAR_TYPE"std_logic"74;
VHDL_SCALAR_TYPE"std_logic"41;
"FMC_CLK0_M2C*"
VHDL_MODE"inout"
VHDL_SCALAR_TYPE"std_logic"78;
VHDL_SCALAR_TYPE"std_logic"39;
"FMC_CLK0_M2C"
VHDL_MODE"inout"
VHDL_SCALAR_TYPE"std_logic"64;
VHDL_SCALAR_TYPE"std_logic"13;
"DP0_C2M"
VHDL_MODE"inout"
VHDL_SCALAR_TYPE"std_logic"0;
......@@ -328,7 +417,7 @@ VHDL_MODE"out"
VHDL_SCALAR_TYPE"std_logic"0;
"IIC_SDA_MAIN"
VHDL_MODE"inout"
VHDL_SCALAR_TYPE"std_logic"80;
VHDL_SCALAR_TYPE"std_logic"38;
"DP0_C2M*"
VHDL_MODE"inout"
VHDL_SCALAR_TYPE"std_logic"0;
......@@ -346,19 +435,19 @@ VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"0;
"P12V"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"13;
VHDL_SCALAR_TYPE"std_logic"28;
"P3V3"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"3;
VHDL_SCALAR_TYPE"std_logic"35;
"P2V5"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"4;
VHDL_SCALAR_TYPE"std_logic"34;
"IIC_SCL_MAIN"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"76;
VHDL_SCALAR_TYPE"std_logic"40;
"GND"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"2;
VHDL_SCALAR_TYPE"std_logic"36;
"GBTCLK0_M2C*"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"0;
......@@ -371,103 +460,40 @@ VHDL_SCALAR_TYPE"std_logic"0;
"FPGA_TDO"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"0;
%"TAP"
"1","(1750,-1450)","0","standard","I20";
;
HDL_TAP"TRUE"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"B \NAC \NWC"34;
"S \NAC"
BN"3"67;
%"TAP"
"1","(1750,-750)","0","standard","I21";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"34;
"S \NAC"
BN"21"47;
%"TAP"
"1","(1750,-1825)","0","standard","I22";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"34;
"S \NAC"
BN"8"59;
%"TAP"
"1","(1750,-1575)","0","standard","I24";
;
HDL_TAP"TRUE"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"B \NAC \NWC"34;
"S \NAC"
BN"14"57;
%"TAP"
"1","(1750,-1700)","0","standard","I28";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"34;
"S \NAC"
BN"18"58;
%"GND_SIGNAL"
"1","(4300,-1600)","0","standard","I3";
;
BODY_TYPE"PLUMBING"
HDL_POWER"GND_SIGNAL"
CDS_LIB"standard";
"GND"2;
%"TAP"
"1","(1750,-1325)","0","standard","I31";
;
HDL_TAP"TRUE"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"B \NAC \NWC"34;
"S \NAC"
BN"27"65;
%"TAP"
"1","(1750,-500)","0","standard","I35";
;
HDL_TAP"TRUE"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"B \NAC \NWC"34;
"S \NAC"
BN"11"35;
"GND"36;
%"TAP"
"1","(1750,250)","0","standard","I36";
;
HDL_TAP"TRUE"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"B \NAC \NWC"34;
"B \NAC \NWC"14;
"S \NAC"
BN"25"22;
BN"25"20;
%"TAP"
"1","(1750,875)","0","standard","I38";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"34;
"B \NAC \NWC"14;
"S \NAC"
BN"30"41;
BN"30"47;
%"TAP"
"1","(1750,375)","0","standard","I39";
;
HDL_TAP"TRUE"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"B \NAC \NWC"34;
"B \NAC \NWC"14;
"S \NAC"
BN"24"21;
BN"24"54;
%"P3V3"
"1","(4250,750)","0","cnpower","I4";
;
......@@ -476,97 +502,34 @@ CDS_LIB"cnpower"
BODY_TYPE"PLUMBING"
SIZE"1B";
"A<SIZE-1..0>\NAC"
VHDL_INIT"1"3;
VHDL_INIT"1"35;
%"TAP"
"1","(1750,500)","0","standard","I40";
;
HDL_TAP"TRUE"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"B \NAC \NWC"34;
"B \NAC \NWC"14;
"S \NAC"
BN"29"20;
%"TAP"
"1","(1750,-2050)","0","standard","I41";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"34;
"S \NAC"
BN"15"72;
%"TAP"
"1","(1750,-875)","0","standard","I42";
;
HDL_TAP"TRUE"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"B \NAC \NWC"34;
"S \NAC"
BN"20"46;
%"TAP"
"1","(1750,-125)","0","standard","I43";
;
HDL_TAP"TRUE"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"B \NAC \NWC"34;
"S \NAC"
BN"16"38;
%"TAP"
"1","(1750,-375)","0","standard","I44";
;
HDL_TAP"TRUE"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"B \NAC \NWC"34;
"S \NAC"
BN"7"36;
%"TAP"
"1","(1750,-250)","0","standard","I45";
;
HDL_TAP"TRUE"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"B \NAC \NWC"34;
"S \NAC"
BN"12"37;
%"TAP"
"1","(1750,-1000)","0","standard","I46";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"34;
"S \NAC"
BN"19"60;
BN"29"55;
%"TAP"
"1","(1750,625)","0","standard","I47";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"34;
"B \NAC \NWC"14;
"S \NAC"
BN"28"39;
%"TAP"
"1","(1750,0)","0","standard","I48";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"34;
"S \NAC"
BN"2"23;
BN"28"12;
%"TAP"
"1","(1750,750)","0","standard","I49";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"34;
"B \NAC \NWC"14;
"S \NAC"
BN"31"42;
BN"31"46;
%"P2V5"
"1","(4450,750)","0","cnpower","I5";
;
......@@ -575,298 +538,134 @@ HDL_POWER"P2V5"
SIZE"1B"
CDS_LIB"cnpower";
"A<SIZE-1..0>\NAC"
VHDL_INIT"1"4;
VHDL_INIT"1"34;
%"TAP"
"1","(1750,1000)","0","standard","I51";
;
HDL_TAP"TRUE"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"B \NAC \NWC"34;
"B \NAC \NWC"14;
"S \NAC"
BN"33"40;
BN"33"48;
%"TAP"
"1","(150,1125)","0","standard","I52";
;
HDL_TAP"TRUE"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"B \NAC \NWC"16;
"B \NAC \NWC"21;
"S \NAC"
BN"32"19;
BN"32"27;
%"TAP"
"1","(150,1000)","0","standard","I54";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"16;
"B \NAC \NWC"21;
"S \NAC"
BN"33"17;
BN"33"58;
%"TAP"
"1","(150,750)","0","standard","I55";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"16;
"S \NAC"
BN"31"43;
%"TAP"
"1","(150,0)","0","standard","I56";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"16;
"B \NAC \NWC"21;
"S \NAC"
BN"2"63;
BN"31"45;
%"TAP"
"1","(150,625)","0","standard","I57";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"16;
"B \NAC \NWC"21;
"S \NAC"
BN"28"44;
%"TAP"
"1","(150,-250)","0","standard","I58";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"16;
"S \NAC"
BN"12"51;
%"TAP"
"1","(150,-1000)","0","standard","I59";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"16;
"S \NAC"
BN"19"54;
%"TAP"
"1","(150,-375)","0","standard","I60";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"16;
"S \NAC"
BN"7"49;
%"TAP"
"1","(150,-125)","0","standard","I61";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"16;
"S \NAC"
BN"16"62;
%"TAP"
"1","(150,-875)","0","standard","I62";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"16;
"S \NAC"
BN"20"53;
%"TAP"
"1","(150,-2050)","0","standard","I63";
;
HDL_TAP"TRUE"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"B \NAC \NWC"16;
"S \NAC"
BN"4"24;
%"TAP"
"1","(150,375)","0","standard","I64";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"16;
"B \NAC \NWC"21;
"S \NAC"
BN"24"69;
BN"24"60;
%"TAP"
"1","(150,500)","0","standard","I65";
;
HDL_TAP"TRUE"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"B \NAC \NWC"16;
"B \NAC \NWC"21;
"S \NAC"
BN"29"45;
BN"29"43;
%"TAP"
"1","(150,875)","0","standard","I66";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"16;
"B \NAC \NWC"21;
"S \NAC"
BN"30"18;
BN"30"59;
%"TAP"
"1","(150,250)","0","standard","I68";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"16;
"B \NAC \NWC"21;
"S \NAC"
BN"25"50;
BN"25"26;
%"PLEMO2CI"
"1","(2050,50)","2","cnconnector","I7";
;
ABBREV"PT6911"
TYPE"PLEMO2-00B"
$LOCATION"PX1"
TYPE"EPG.00.302.NLN"
CDS_LIB"cnconnector"
POWER_GROUP"GND=GND_SIGNAL"
ABBREV"PT6911"
CDS_SEC"1"
$SEC"1"
CDS_LOCATION"PX1"
NEEDS_NO_SIZE"TRUE"
CDS_LIB"cnconnector";
"B\nac"
$PN"2"79;
"A\nac"
$PN"1"75;
%"TAP"
"1","(150,-500)","0","standard","I70";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"16;
"S \NAC"
BN"11"48;
%"TAP"
"1","(150,-1325)","0","standard","I73";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"16;
"S \NAC"
BN"27"56;
%"TAP"
"1","(150,-1700)","0","standard","I76";
;
HDL_TAP"TRUE"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"B \NAC \NWC"16;
"S \NAC"
BN"18"71;
%"TAP"
"1","(150,-1575)","0","standard","I79";
;
HDL_TAP"TRUE"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"B \NAC \NWC"16;
"S \NAC"
BN"14"68;
$LOCATION"PX1"
NEEDS_NO_SIZE"TRUE";
"B\nac"11;
"A\nac"10;
%"24AA025E48"
"1","(-200,-2950)","0","cnmemory","I8";
;
PACK_TYPE"SOIC"
TYPE"24AA025E48T-I/SN"
CDS_LIB"cnmemory"
CDS_LMAN_SYM_OUTLINE"-150,75,150,-150"
$LOCATION"IC9"
CDS_SEC"1"
$SEC"1"
CDS_LOCATION"IC9"
PACK_TYPE"SOIC"
TYPE"24AA025E48"
CDS_LIB"cnmemory";
"A2"
$PN"3"26;
"A1"
$PN"2"27;
"A0"
$PN"1"28;
"VCC"
$PN"8"7;
"VSS"
$PN"4"14;
"SDA"
$PN"5"77;
"SCL"
$PN"6"81;
%"TAP"
"1","(150,-1825)","0","standard","I81";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"16;
"S \NAC"
BN"8"66;
$LOCATION"IC?";
"A2"9;
"A1"8;
"A0"7;
"VCC"6;
"VSS"5;
"SDA"4;
"SCL"3;
%"TAP"
"1","(150,-2200)","0","standard","I82";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"16;
"B \NAC \NWC"21;
"S \NAC"
BN"0"25;
%"TAP"
"1","(150,-750)","0","standard","I83";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_TAP"TRUE";
"B \NAC \NWC"16;
"S \NAC"
BN"21"52;
%"TAP"
"1","(150,-1450)","0","standard","I84";
;
CDS_LIB"standard"
HDL_TAP"TRUE"
BODY_TYPE"PLUMBING";
"B \NAC \NWC"16;
"S \NAC"
BN"3"70;
%"TAP"
"1","(150,-1125)","0","standard","I85";
;
CDS_LIB"standard"
HDL_TAP"TRUE"
BODY_TYPE"PLUMBING";
"B \NAC \NWC"16;
"S \NAC"
BN"22"55;
%"TAP"
"1","(1750,-1125)","0","standard","I86";
;
HDL_TAP"TRUE"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"B \NAC \NWC"34;
"S \NAC"
BN"22"61;
%"P2V5"
"1","(2900,850)","0","cnpower","I88";
;
CDS_LIB"cnpower"
SIZE"1B"
HDL_POWER"P2V5"
BODY_TYPE"PLUMBING";
"A<SIZE-1..0>\NAC"
VHDL_INIT"1"5;
BN"0"57;
%"GND_SIGNAL"
"1","(2250,-150)","0","standard","I89";
;
CDS_LIB"standard"
HDL_POWER"GND_SIGNAL"
BODY_TYPE"PLUMBING";
"GND"6;
"GND"33;
%"P3V3"
"1","(-450,-3200)","0","cnpower","I9";
;
......@@ -875,52 +674,52 @@ CDS_LIB"cnpower"
BODY_TYPE"PLUMBING"
SIZE"1B";
"A<SIZE-1..0>\NAC"
VHDL_INIT"1"7;
VHDL_INIT"1"6;
%"CAPCERSMDCL2"
"1","(3050,500)","1","cnpassive","I90";
;
$LOCATION"C1"
CDS_SEC"1"
$SEC"1"
CDS_LOCATION"C1"
VALUE"100NF"
VOLTAGE"16V"
LOCATION"C1"
PACK_TYPE"0603"
CDS_LIB"cnpassive"
SIZE"1";
"B <SIZE-1..0>\NAC"
$PN"2"5;
"A <SIZE-1..0>\NAC"
$PN"1"8;
$PN"1"1;
"B <SIZE-1..0>\NAC"
$PN"2"2;
%"GND_SIGNAL"
"1","(3000,300)","0","standard","I91";
;
CDS_LIB"standard"
HDL_POWER"GND_SIGNAL"
BODY_TYPE"PLUMBING";
"GND"8;
"GND"1;
%"USBLC6-2"
"1","(2600,100)","0","cndiscrete","I92";
;
$LOCATION"D3"
CDS_SEC"1"
$SEC"1"
CDS_LOCATION"D3"
TYPE"USBLC6-2SC6"
PACK_TYPE"SOT23"
LOCATION"D3"
CDS_LIB"cndiscrete";
"I/O1<1>"
$PN"6"64;
$PN"6"13;
"I/O1<0>"
$PN"1"75;
$PN"1"10;
"GND"
$PN"2"6;
$PN"2"33;
"I/O2<0>"
$PN"3"79;
$PN"3"11;
"I/O2<1>"
$PN"4"78;
$PN"4"39;
"VBUS"
$PN"5"5;
$PN"5"2;
%"CON16P"
"1","(900,-2950)","6","cnconnector","I93";
;
......@@ -931,44 +730,44 @@ $LOCATION"PL1"
TYPE"HW8_08G_SM"
CDS_LIB"cnconnector";
"A<0>\NAC"
$PN"1"10;
$PN"1"31;
"A<1>\NAC"
$PN"2"10;
$PN"2"31;
"A<2>\NAC"
$PN"3"9;
$PN"3"32;
"A<3>\NAC"
$PN"4"29;
$PN"4"53;
"A<4>\NAC"
$PN"5"9;
$PN"5"32;
"A<5>\NAC"
$PN"6"30;
$PN"6"52;
"A<6>\NAC"
$PN"7"9;
$PN"7"32;
"A<7>\NAC"
$PN"8"31;
$PN"8"51;
"A<8>\NAC"
$PN"9"9;
$PN"9"32;
"A<9>\NAC"
$PN"10"0;
"A<15>\NAC"
$PN"16"12;
$PN"16"29;
"A<14>\NAC"
$PN"15"11;
$PN"15"30;
"A<13>\NAC"
$PN"14"33;
$PN"14"49;
"A<12>\NAC"
$PN"13"9;
$PN"13"32;
"A<11>\NAC"
$PN"12"32;
$PN"12"50;
"A<10>\NAC"
$PN"11"9;
$PN"11"32;
%"GND_SIGNAL"
"1","(1850,-3700)","0","standard","I94";
;
BODY_TYPE"PLUMBING"
HDL_POWER"GND_SIGNAL"
CDS_LIB"standard";
"GND"9;
"GND"32;
%"P3V3"
"1","(1900,-2450)","0","cnpower","I95";
;
......@@ -977,7 +776,7 @@ CDS_LIB"cnpower"
SIZE"1B"
BODY_TYPE"PLUMBING";
"A<SIZE-1..0>\NAC"
VHDL_INIT"1"10;
VHDL_INIT"1"31;
%"P5V"
"1","(2600,-3300)","0","cnpower","I96";
;
......@@ -986,7 +785,7 @@ SIZE"1B"
BODY_TYPE"PLUMBING"
CDS_LIB"cnpower";
"A<SIZE-1..0>\NAC"
VHDL_INIT"1"11;
VHDL_INIT"1"30;
%"M5V"
"1","(2600,-3650)","6","cnpower","I97";
;
......@@ -995,21 +794,18 @@ BODY_TYPE"plumbing"
SIZE"1B"
CDS_LIB"cnpower";
"A<SIZE-1..0>\NAC"
vhdl_init"0"12;
vhdl_init"0"29;
%"ZENER"
"1","(3325,525)","0","cndiscrete","I98";
;
$LOCATION"Z4"
TYPE"BZT52-C3V6"
PACK_TYPE"SOD123-CA"
CDS_LIB"cndiscrete"
CDS_SEC"1"
$SEC"1"
CDS_LOCATION"Z4"
TYPE"BZT52C2V7"
PACK_TYPE"SOD123-CA"
CDS_LIB"cndiscrete";
"K <SIZE-1..0>\NAC"
$PN"C"5;
"A <SIZE-1..0>\NAC"
$PN"A"8;
$LOCATION"ZD?";
"K <SIZE-1..0>\NAC"2;
"A <SIZE-1..0>\NAC"1;
%"P12V"
"1","(4050,750)","0","cnpower","I99";
;
......@@ -1018,5 +814,5 @@ HDL_POWER"P12V"
BODY_TYPE"PLUMBING"
CDS_LIB"cnpower";
"A<SIZE-1..0>\NAC"
VHDL_INIT"1"13;
VHDL_INIT"1"28;
END.
Cadence/worklib/fmc_tlu_toplevel_c/sch_1/page2.cpc
View file @ a648eb8d
......@@ -2,179 +2,5 @@
bris_cds_standard a3-2000 *
*
#CELL
cnpassive rsmd0603 *
page4_i10
#CELL
cnpassive rsmd0603 *
page4_i11
#ISCELL
standard gnd_signal *
page4_i12
#CELL
cnpassive rsmd0603 *
page4_i18
#CELL
cnpassive capcersmdcl2 *
page4_i19
#CELL
cnconnector con19p *
page4_i2
#ISCELL
standard gnd_signal *
page4_i20
#CELL
cnpassive rsmd0603 *
page4_i21
#CELL
cnpassive capcersmdcl2 *
page4_i22
#ISCELL
standard gnd_signal *
page4_i25
#CELL
cndiscrete trans#20mosfet *
page4_i26
#CELL
cninterface 74lvc1g07 *
page4_i28
#CELL
cnpassive rsmd0603 *
page4_i29
#CELL
cnconnector con19p *
page4_i3
#ISCELL
cnpower p5v *
page4_i30
#CELL
cndiscrete usblc6-2 *
page4_i33
#ISCELL
standard gnd_signal *
page4_i34
#ISCELL
cnpower p2v5 *
page4_i35
#ISCELL
standard gnd_signal *
page4_i37
#CELL
cnpassive rsmd0603 *
page4_i38
#CELL
cnpassive rsmd0603 *
page4_i39
#CELL
cninterface 74lvc1g07 *
page4_i40
#CELL
cnpassive capcersmdcl2 *
page4_i41
#CELL
cnpassive capcersmdcl2 *
page4_i42
#ISCELL
cnpower p5v *
page4_i43
#CELL
cnpassive rsmd0603 *
page4_i44
#CELL
cndiscrete trans#20mosfet *
page4_i45
#ISCELL
cnpower p2v5 *
page4_i48
#CELL
cndiscrete usblc6-2 *
page4_i49
#ISCELL
standard gnd_signal *
page4_i50
#ISCELL
standard gnd_signal *
page4_i51
#ISCELL
cnpower p3v3 *
page4_i54
#ISCELL
cnpower p3v3 *
page4_i55
#CELL
cnpassive capcersmdcl2 *
page4_i56
#ISCELL
standard gnd_signal *
page4_i57
#ISCELL
cnpower p2v5 *
page4_i58
#ISCELL
cnpower p2v5 *
page4_i59
#ISCELL
cnpower frame *
page4_i6
#CELL
cnpassive capcersmdcl2 *
page4_i60
#ISCELL
standard gnd_signal *
page4_i61
#CELL
fmc_tlu_v1_lib fmc_tlu_diode_clamp *
page4_i62
#CELL
fmc_tlu_v1_lib fmc_tlu_diode_clamp *
page4_i63
#CELL
fmc_tlu_v1_lib fmc_tlu_diode_clamp *
page4_i64
#CELL
cnpassive tp *
page4_i65
#CELL
cnpassive tp *
page4_i66
#CELL
cnpassive tp *
page4_i67
#CELL
cnpassive tp *
page4_i68
#CELL
cnpassive tp *
page4_i69
#CELL
cnpassive tp *
page4_i70
#CELL
cnpassive tp *
page4_i71
#CELL
cnpassive tp *
page4_i72
#CELL
cnpassive tp *
page4_i73
#CELL
cnpassive tp *
page4_i74
#CELL
cnpassive tp *
page4_i75
#CELL
cnpassive tp *
page4_i76
#ISCELL
standard gnd_signal *
page4_i77
#CELL
cnconnector con8p *
page4_i78
#CELL
cnpassive capcersmdcl2 *
page4_i8
#CELL
cnpassive capcersmdcl2 *
page4_i9
fmc_tlu_v1_lib fmc_tlu_hdmi_dut_connector *
page4_i1
Cadence/worklib/fmc_tlu_toplevel_c/sch_1/page2.csa
View file @ a648eb8d
This source diff could not be displayed because it is too large. You can view the blob instead.
Cadence/worklib/fmc_tlu_toplevel_c/sch_1/page2.csv
View file @ a648eb8d
......@@ -2,955 +2,97 @@ FILE_TYPE = CONNECTIVITY;
{Allegro Design Entry HDL 16.6-S055 (v16-6-112EP) 8/13/2015}
"PAGE_NUMBER" = 4;
0"NC";
1"P5V\g";
2"GND_SIGNAL\g";
3"P5V\g";
4"GND_SIGNAL\g";
5"P3V3\g";
6"P3V3\g";
7"GND_SIGNAL\g";
8"P2V5\g";
9"P2V5\g";
10"GND_SIGNAL\g";
11"CTRIG2*";
12"CTRIG2";
13"CLK2";
14"BUSY2";
15"GND_SIGNAL\g";
16"DUT_CLK0*";
17"DUT_CLK0";
18"BUSY0*";
19"CONT0*";
20"TRIG0";
21"UN$4$CAPCERSMDCL2$I8$B";
22"UN$4$CAPCERSMDCL2$I9$B";
23"HDMI_POWER_ENABLE1";
24"HDMI_POWER_ENABLE2";
25"UN$4$CAPCERSMDCL2$I41$B";
26"UN$4$CAPCERSMDCL2$I42$B";
27"GND_HDMI2";
28"UN$4$74LVC1G07$I40$Y";
29"UN$4$CAPCERSMDCL2$I19$B";
30"UN$4$CAPCERSMDCL2$I22$B";
31"GND_HDMI1";
32"TRIG1*";
33"TRIG1";
34"TRIG2";
35"TRIG2*";
36"CLK1*";
37"CLK1";
38"BUSY1";
39"BUSY1*";
40"CTRIG1";
41"CONT1";
42"CONT1*";
43"SPARE1";
44"SPARE1*";
45"UN$4$CON19P$I2$A";
46"CTRIG1*";
47"CLK2*";
48"BUSY2*";
49"CONT2";
50"CONT2*";
51"SPARE2";
52"SPARE2*";
53"UN$4$CON19P$I3$A";
54"UN$4$74LVC1G07$I28$Y";
55"TRIG0*";
56"BUSY0";
57"CONT0";
58"GND_SIGNAL\g";
59"FRAME\g";
60"P2V5\g";
61"GND_SIGNAL\g";
62"P2V5\g";
63"GND_SIGNAL\g";
64"GND_SIGNAL\g";
65"GND_SIGNAL\g";
%"RSMD0603"
"2","(1750,350)","0","cnpassive","I10";
;
VALUE"51"
PACK_TYPE"1/10W"
$LOCATION"R11"
DIST"FLAT"
MAX_TEMP"RTMAX"
NEGTOL"RTOL%"
POSTOL"RTOL%"
POWER"RMAX"
SIZE"1B"
SLOPE"RSMAX"
TC1"RTMPL"
TC2"RTMPQ"
TOL_ON_OFF"ON"
VOLTAGE"RVMAX"
CDS_LIB"cnpassive"
TOL"1%"
CDS_LOCATION"R11"
$SEC"1"
CDS_SEC"1";
"A <SIZE-1..0>\NAC"
$PN"1"22;
"B <SIZE-1..0>\NAC"
$PN"2"65;
%"RSMD0603"
"2","(1750,150)","0","cnpassive","I11";
;
PACK_TYPE"1/10W"
VALUE"51"
$LOCATION"R12"
DIST"FLAT"
MAX_TEMP"RTMAX"
NEGTOL"RTOL%"
POSTOL"RTOL%"
POWER"RMAX"
SIZE"1B"
SLOPE"RSMAX"
TC1"RTMPL"
TC2"RTMPQ"
TOL_ON_OFF"ON"
VOLTAGE"RVMAX"
CDS_LIB"cnpassive"
TOL"1%"
CDS_LOCATION"R12"
$SEC"1"
CDS_SEC"1";
"A <SIZE-1..0>\NAC"
$PN"1"21;
"B <SIZE-1..0>\NAC"
$PN"2"65;
%"GND_SIGNAL"
"1","(2000,150)","0","standard","I12";
;
HDL_POWER"GND_SIGNAL"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"GND"65;
%"RSMD0603"
"2","(300,-3400)","0","cnpassive","I18";
;
$LOCATION"R13"
VALUE"51"
PACK_TYPE"1/10W"
CDS_SEC"1"
$SEC"1"
CDS_LOCATION"R13"
DIST"FLAT"
MAX_TEMP"RTMAX"
NEGTOL"RTOL%"
POSTOL"RTOL%"
POWER"RMAX"
SIZE"1B"
SLOPE"RSMAX"
TC1"RTMPL"
TC2"RTMPQ"
TOL_ON_OFF"ON"
VOLTAGE"RVMAX"
CDS_LIB"cnpassive"
TOL"1%";
"A <SIZE-1..0>\NAC"
$PN"1"29;
"B <SIZE-1..0>\NAC"
$PN"2"64;
%"CAPCERSMDCL2"
"1","(0,-3400)","0","cnpassive","I19";
;
$LOCATION"C10"
VALUE"100NF"
VOLTAGE"16V"
CDS_SEC"1"
$SEC"1"
CDS_LOCATION"C10"
SIZE"1"
CDS_LIB"cnpassive"
PACK_TYPE"0603";
"B <SIZE-1..0>\NAC"
$PN"2"29;
"A <SIZE-1..0>\NAC"
$PN"1"59;
%"CON19P"
"1","(-250,250)","0","cnconnector","I2";
;
POWER_GROUP"GND=GND_HDMI1"
$LOCATION"J1"
TYPE"MHDMI-19-02-H-TH-L-TR"
CDS_LOCATION"J1"
CDS_SEC"1"
CDS_LMAN_SYM_OUTLINE"0,25,150,-475"
CDS_LIB"cnconnector";
"A<17>"
$PN"18"0;
"A<15>"
$PN"16"46;
"A<13>"
$PN"14"45;
"A<11>"
$PN"12"44;
"A<9>"
$PN"10"43;
"A<7>"
$PN"8"63;
"A<5>"
$PN"6"42;
"A<3>"
$PN"4"41;
"A<1>"
$PN"2"63;
"A<18>"
$PN"19"0;
"A<16>"
$PN"17"63;
"A<14>"
$PN"15"40;
"A<12>"
$PN"13"0;
"A<10>"
$PN"11"63;
"A<8>"
$PN"9"39;
"A<6>"
$PN"7"38;
"A<4>"
$PN"5"63;
"A<2>"
$PN"3"37;
"A<0>"
$PN"1"36;
%"GND_SIGNAL"
"1","(550,-3600)","0","standard","I20";
;
BODY_TYPE"PLUMBING"
HDL_POWER"GND_SIGNAL"
CDS_LIB"standard";
"GND"64;
%"RSMD0603"
"2","(300,-3600)","0","cnpassive","I21";
;
$LOCATION"R14"
VALUE"51"
PACK_TYPE"1/10W"
CDS_SEC"1"
$SEC"1"
CDS_LOCATION"R14"
DIST"FLAT"
MAX_TEMP"RTMAX"
NEGTOL"RTOL%"
POSTOL"RTOL%"
POWER"RMAX"
SIZE"1B"
SLOPE"RSMAX"
TC1"RTMPL"
TC2"RTMPQ"
TOL_ON_OFF"ON"
VOLTAGE"RVMAX"
CDS_LIB"cnpassive"
TOL"1%";
"A <SIZE-1..0>\NAC"
$PN"1"30;
"B <SIZE-1..0>\NAC"
$PN"2"64;
%"CAPCERSMDCL2"
"1","(0,-3600)","0","cnpassive","I22";
;
$LOCATION"C11"
VALUE"100NF"
VOLTAGE"16V"
CDS_SEC"1"
$SEC"1"
CDS_LOCATION"C11"
SIZE"1"
CDS_LIB"cnpassive"
PACK_TYPE"0603";
"B <SIZE-1..0>\NAC"
$PN"2"30;
"A <SIZE-1..0>\NAC"
$PN"1"59;
%"GND_SIGNAL"
"1","(-1000,-300)","0","standard","I25";
;
HDL_POWER"GND_SIGNAL"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"GND"63;
%"TRANS MOSFET"
"1","(400,800)","2","cndiscrete","I26";
;
$LOCATION"T1"
TYPE"SOT23"
VALUE"FDV301N"
CDS_LIB"cndiscrete"
PACK_TYPE"GSD";
"D\NAC"5;
"S\NAC"45;
"G\NAC"54;
%"74LVC1G07"
"1","(1450,750)","2","cninterface","I28";
;
PACK_TYPE"SC70"
TYPE"SN74LVC1G07DCK"
$LOCATION"IC4"
POWER_GROUP"VCC=P2V5;GND=GND_SIGNAL"
CDS_LIB"cninterface";
"Y"54;
"A"23;
%"RSMD0603"
"2","(800,900)","1","cnpassive","I29";
;
VALUE"1K"
PACK_TYPE"1/10W"
$LOCATION"R15"
CDS_LIB"cnpassive"
VOLTAGE"RVMAX"
TOL_ON_OFF"ON"
TC2"RTMPQ"
TC1"RTMPL"
SLOPE"RSMAX"
SIZE"1B"
POWER"RMAX"
POSTOL"RTOL%"
NEGTOL"RTOL%"
MAX_TEMP"RTMAX"
DIST"FLAT"
TOL"1%";
"A <SIZE-1..0>\NAC"54;
"B <SIZE-1..0>\NAC"1;
%"CON19P"
"1","(3300,250)","0","cnconnector","I3";
;
POWER_GROUP"GND=GND_HDMI2"
$LOCATION"J2"
TYPE"MHDMI-19-02-H-TH-L-TR"
CDS_LOCATION"J2"
CDS_SEC"1"
CDS_LMAN_SYM_OUTLINE"0,25,150,-475"
CDS_LIB"cnconnector";
"A<17>"
$PN"18"0;
"A<15>"
$PN"16"11;
"A<13>"
$PN"14"53;
"A<11>"
$PN"12"52;
"A<9>"
$PN"10"51;
"A<7>"
$PN"8"15;
"A<5>"
$PN"6"50;
"A<3>"
$PN"4"49;
"A<1>"
$PN"2"15;
"A<18>"
$PN"19"0;
"A<16>"
$PN"17"15;
"A<14>"
$PN"15"12;
"A<12>"
$PN"13"0;
"A<10>"
$PN"11"15;
"A<8>"
$PN"9"48;
"A<6>"
$PN"7"14;
"A<4>"
$PN"5"15;
"A<2>"
$PN"3"13;
"A<0>"
$PN"1"47;
%"P5V"
"1","(800,1150)","0","cnpower","I30";
;
HDL_POWER"P5V"
SIZE"1B"
BODY_TYPE"PLUMBING"
CDS_LIB"cnpower";
"A<SIZE-1..0>\NAC"
VHDL_INIT"1"1;
%"USBLC6-2"
"1","(1100,-1800)","0","cndiscrete","I33";
;
PACK_TYPE"SOT23"
TYPE"USBLC6-2SC6"
$LOCATION"D3"
CDS_LIB"cndiscrete";
"I/O1<1>"32;
"I/O1<0>"46;
"GND"2;
"I/O2<0>"40;
"I/O2<1>"33;
"VBUS"62;
%"GND_SIGNAL"
"1","(750,-2050)","0","standard","I34";
;
BODY_TYPE"PLUMBING"
HDL_POWER"GND_SIGNAL"
CDS_LIB"standard";
"GND"2;
%"P2V5"
"1","(1500,-1550)","0","cnpower","I35";
;
CDS_LIB"cnpower"
SIZE"1B"
HDL_POWER"P2V5"
BODY_TYPE"PLUMBING";
"A<SIZE-1..0>\NAC"
VHDL_INIT"1"62;
%"GND_SIGNAL"
"1","(5550,150)","0","standard","I37";
;
CDS_LIB"standard"
HDL_POWER"GND_SIGNAL"
BODY_TYPE"PLUMBING";
"GND"61;
%"RSMD0603"
"2","(5300,350)","0","cnpassive","I38";
;
PACK_TYPE"1/10W"
VALUE"51"
$LOCATION"R9"
CDS_SEC"1"
$SEC"1"
TOL"1%"
CDS_LIB"cnpassive"
VOLTAGE"RVMAX"
TOL_ON_OFF"ON"
TC2"RTMPQ"
TC1"RTMPL"
SLOPE"RSMAX"
SIZE"1B"
POWER"RMAX"
POSTOL"RTOL%"
NEGTOL"RTOL%"
MAX_TEMP"RTMAX"
DIST"FLAT"
CDS_LOCATION"R9";
"A <SIZE-1..0>\NAC"
$PN"1"25;
"B <SIZE-1..0>\NAC"
$PN"2"61;
%"RSMD0603"
"2","(5300,150)","0","cnpassive","I39";
;
VALUE"51"
$LOCATION"R10"
PACK_TYPE"1/10W"
CDS_SEC"1"
$SEC"1"
TOL"1%"
CDS_LIB"cnpassive"
VOLTAGE"RVMAX"
TOL_ON_OFF"ON"
TC2"RTMPQ"
TC1"RTMPL"
SLOPE"RSMAX"
SIZE"1B"
POWER"RMAX"
POSTOL"RTOL%"
NEGTOL"RTOL%"
MAX_TEMP"RTMAX"
DIST"FLAT"
CDS_LOCATION"R10";
"A <SIZE-1..0>\NAC"
$PN"1"26;
"B <SIZE-1..0>\NAC"
$PN"2"61;
%"74LVC1G07"
"1","(5000,750)","2","cninterface","I40";
;
POWER_GROUP"VCC=P2V5;GND=GND_SIGNAL"
TYPE"SN74LVC1G07DCK"
PACK_TYPE"SC70"
$LOCATION"IC6"
CDS_LIB"cninterface";
"Y"28;
"A"24;
%"CAPCERSMDCL2"
"1","(5000,350)","0","cnpassive","I41";
;
VOLTAGE"16V"
VALUE"100NF"
$LOCATION"C7"
CDS_SEC"1"
$SEC"1"
PACK_TYPE"0603"
CDS_LIB"cnpassive"
SIZE"1"
CDS_LOCATION"C7";
"B <SIZE-1..0>\NAC"
$PN"2"25;
"A <SIZE-1..0>\NAC"
$PN"1"27;
%"CAPCERSMDCL2"
"1","(5000,150)","0","cnpassive","I42";
;
VOLTAGE"16V"
VALUE"100NF"
$LOCATION"C12"
CDS_SEC"1"
$SEC"1"
PACK_TYPE"0603"
CDS_LIB"cnpassive"
SIZE"1"
CDS_LOCATION"C12";
"B <SIZE-1..0>\NAC"
$PN"2"26;
"A <SIZE-1..0>\NAC"
$PN"1"27;
%"P5V"
"1","(4350,1150)","0","cnpower","I43";
;
HDL_POWER"P5V"
SIZE"1B"
BODY_TYPE"PLUMBING"
CDS_LIB"cnpower";
"A<SIZE-1..0>\NAC"
VHDL_INIT"1"3;
%"RSMD0603"
"2","(4350,900)","1","cnpassive","I44";
;
PACK_TYPE"1/10W"
VALUE"1K"
$LOCATION"R16"
TOL"1%"
DIST"FLAT"
MAX_TEMP"RTMAX"
NEGTOL"RTOL%"
POSTOL"RTOL%"
POWER"RMAX"
SIZE"1B"
SLOPE"RSMAX"
TC1"RTMPL"
TC2"RTMPQ"
TOL_ON_OFF"ON"
VOLTAGE"RVMAX"
CDS_LIB"cnpassive";
"A <SIZE-1..0>\NAC"28;
"B <SIZE-1..0>\NAC"3;
%"TRANS MOSFET"
"1","(3950,800)","2","cndiscrete","I45";
;
TYPE"SOT23"
VALUE"FDV301N"
$LOCATION"T2"
PACK_TYPE"GSD"
CDS_LIB"cndiscrete";
"D\NAC"6;
"S\NAC"53;
"G\NAC"28;
%"P2V5"
"1","(5050,-1550)","0","cnpower","I48";
;
CDS_LIB"cnpower"
SIZE"1B"
HDL_POWER"P2V5"
BODY_TYPE"PLUMBING";
"A<SIZE-1..0>\NAC"
VHDL_INIT"1"60;
%"USBLC6-2"
"1","(4650,-1800)","0","cndiscrete","I49";
;
PACK_TYPE"SOT23"
TYPE"USBLC6-2SC6"
$LOCATION"D2"
CDS_LIB"cndiscrete";
"I/O1<1>"35;
"I/O1<0>"11;
"GND"4;
"I/O2<0>"12;
"I/O2<1>"34;
"VBUS"60;
%"GND_SIGNAL"
"1","(4300,-2050)","0","standard","I50";
;
CDS_LIB"standard"
HDL_POWER"GND_SIGNAL"
BODY_TYPE"PLUMBING";
"GND"4;
%"GND_SIGNAL"
"1","(2600,-300)","0","standard","I51";
;
HDL_POWER"GND_SIGNAL"
BODY_TYPE"PLUMBING"
CDS_LIB"standard";
"GND"15;
%"P3V3"
"1","(350,1100)","0","cnpower","I54";
;
HDL_POWER"P3V3"
CDS_LIB"cnpower"
BODY_TYPE"PLUMBING"
SIZE"1B";
"A<SIZE-1..0>\NAC"
VHDL_INIT"1"5;
%"P3V3"
"1","(3900,1100)","0","cnpower","I55";
;
HDL_POWER"P3V3"
CDS_LIB"cnpower"
BODY_TYPE"PLUMBING"
SIZE"1B";
"A<SIZE-1..0>\NAC"
VHDL_INIT"1"6;
%"CAPCERSMDCL2"
"1","(1900,1050)","0","cnpassive","I56";
;
VALUE"100NF"
VOLTAGE"16V"
$LOCATION"C1"
CDS_SEC"1"
$SEC"1"
PACK_TYPE"0603"
CDS_LIB"cnpassive"
SIZE"1"
CDS_LOCATION"C1";
"B <SIZE-1..0>\NAC"
$PN"2"7;
"A <SIZE-1..0>\NAC"
$PN"1"8;
%"GND_SIGNAL"
"1","(1950,950)","0","standard","I57";
;
BODY_TYPE"PLUMBING"
HDL_POWER"GND_SIGNAL"
CDS_LIB"standard";
"GND"7;
%"P2V5"
"1","(1800,1150)","0","cnpower","I58";
;
SIZE"1B"
HDL_POWER"P2V5"
BODY_TYPE"PLUMBING"
CDS_LIB"cnpower";
"A<SIZE-1..0>\NAC"
VHDL_INIT"1"8;
%"P2V5"
"1","(5300,1150)","0","cnpower","I59";
;
CDS_LIB"cnpower"
BODY_TYPE"PLUMBING"
HDL_POWER"P2V5"
SIZE"1B";
"A<SIZE-1..0>\NAC"
VHDL_INIT"1"9;
%"FRAME"
"1","(-400,-3550)","0","cnpower","I6";
;
HDL_POWER"FRAME"
SIZE"1B"
BODY_TYPE"PLUMBING"
CDS_LIB"cnpower";
"A<SIZE-1..0>\NAC"
VHDL_INIT"0"59;
%"CAPCERSMDCL2"
"1","(5400,1050)","0","cnpassive","I60";
;
VOLTAGE"16V"
VALUE"100NF"
$LOCATION"C13"
SIZE"1"
CDS_LIB"cnpassive"
PACK_TYPE"0603"
$SEC"1"
CDS_SEC"1"
CDS_LOCATION"C13";
"B <SIZE-1..0>\NAC"
$PN"2"10;
"A <SIZE-1..0>\NAC"
$PN"1"9;
%"GND_SIGNAL"
"1","(5450,950)","0","standard","I61";
;
CDS_LIB"standard"
HDL_POWER"GND_SIGNAL"
BODY_TYPE"PLUMBING";
"GND"10;
%"FMC_TLU_DIODE_CLAMP"
"1","(1550,-850)","0","fmc_tlu_v1_lib","I62";
1"ENABLE_CONT_FROM_FPGA<0>";
2"CONT_TO_FPGA<0>";
3"CONT_FROM_FPGA<0>";
4"ENABLE_SPARE_FROM_FPGA<0>";
5"SPARE_FROM_FPGA<0>";
6"HDMI_CLK*<0>";
7"HDMI_CLK<0>";
8"HDMI_POWER_ENABLE<0>";
9"ENABLE_CLK_TO_DUT<0>";
10"CLK_TO_DUT*<0>";
11"CLK_TO_DUT<0>";
12"SPARE_TO_FPGA<0>";
13"CLK_TO_FPGA<0>";
14"BUSY_TO_FPGA<0>";
15"TRIG_FROM_FPGA<0>";
16"ENABLE_TRIG_FROM_FPGA<0>";
17"ENABLE_CLK_FROM_FPGA<0>";
18"ENABLE_BUSY_FROM_FPGA<0>";
19"CLK_FROM_FPGA<0>";
20"BUSY_FROM_FPGA<0>";
21"TRIG_TO_FPGA<0>";
%"FMC_TLU_HDMI_DUT_CONNECTOR"
"1","(775,250)","0","fmc_tlu_v1_lib","I1";
;
CDS_LIB"fmc_tlu_v1_lib"
BLOCK"TRUE"
USE2"work.all"
CDS_LMAN_SYM_OUTLINE"-775,775,750,-725"
LIBRARY1"ieee"
USE1"ieee.std_logic_1164.all"
LIBRARY1"ieee";
"SIG1"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"44;
"SIG2"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"37;
"SIG4"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"39;
"SIG5"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"38;
"SIG6"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"41;
"SIG7"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"42;
"SIG3"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"36;
"SIG0"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"43;
%"FMC_TLU_DIODE_CLAMP"
"1","(2050,-2850)","0","fmc_tlu_v1_lib","I63";
;
CDS_LIB"fmc_tlu_v1_lib"
BLOCK"TRUE"
USE2"work.all"
USE1"ieee.std_logic_1164.all"
LIBRARY1"ieee";
"SIG1"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"55;
"SIG2"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"56;
"SIG4"
BLOCK"TRUE";
"SPARE_TO_FPGA"
VHDL_MODE"out"
VHDL_SCALAR_TYPE"std_logic"12;
"HDMI_CLK* \B"
VHDL_MODE"out"
VHDL_SCALAR_TYPE"std_logic"6;
"HDMI_CLK"
VHDL_MODE"out"
VHDL_SCALAR_TYPE"std_logic"7;
"CLK_TO_FPGA"
VHDL_MODE"out"
VHDL_SCALAR_TYPE"std_logic"13;
"BUSY_TO_FPGA"
VHDL_MODE"out"
VHDL_SCALAR_TYPE"std_logic"14;
"TRIG_FROM_FPGA"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"19;
"SIG5"
VHDL_SCALAR_TYPE"std_logic"15;
"SPARE_FROM_FPGA"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"18;
"SIG6"
VHDL_SCALAR_TYPE"std_logic"5;
"HDMI_POWER_ENABLE"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"17;
"SIG7"
VHDL_SCALAR_TYPE"std_logic"8;
"ENABLE_TRIG_FROM_FPGA"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"16;
"SIG3"
"ENABLE_SPARE_FROM_FPGA"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"57;
"SIG0"
VHDL_SCALAR_TYPE"std_logic"4;
"ENABLE_CONT_FROM_FPGA"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"20;
%"FMC_TLU_DIODE_CLAMP"
"1","(5000,-800)","0","fmc_tlu_v1_lib","I64";
;
CDS_LIB"fmc_tlu_v1_lib"
BLOCK"TRUE"
USE2"work.all"
USE1"ieee.std_logic_1164.all"
LIBRARY1"ieee";
"SIG1"
VHDL_SCALAR_TYPE"std_logic"1;
"ENABLE_CLK_TO_DUT"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"52;
"SIG2"
VHDL_SCALAR_TYPE"std_logic"9;
"ENABLE_CLK_FROM_FPGA"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"13;
"SIG4"
VHDL_SCALAR_TYPE"std_logic"17;
"ENABLE_BUSY_FROM_FPGA"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"48;
"SIG5"
VHDL_SCALAR_TYPE"std_logic"18;
"CONT_FROM_FPGA"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"14;
"SIG6"
VHDL_SCALAR_TYPE"std_logic"3;
"CLK_TO_DUT* \B"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"49;
"SIG7"
VHDL_SCALAR_TYPE"std_logic"10;
"CLK_TO_DUT"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"50;
"SIG3"
VHDL_SCALAR_TYPE"std_logic"11;
"CLK_FROM_FPGA"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"47;
"SIG0"
VHDL_SCALAR_TYPE"std_logic"19;
"BUSY_FROM_FPGA"
VHDL_MODE"in"
VHDL_SCALAR_TYPE"std_logic"51;
%"TP"
"1","(700,-150)","0","cnpassive","I65";
;
$LOCATION"TP11"
PART_NAME"TP"
PACK_TYPE"HOLE"
VALUE"0.8MM"
CDS_LIB"cnpassive"
SIZE"1B";
"A <SIZE-1..0>\NAC"
$PN"1"43;
%"TP"
"1","(700,-250)","0","cnpassive","I66";
;
$LOCATION"TP12"
PART_NAME"TP"
PACK_TYPE"HOLE"
VALUE"0.8MM"
CDS_LIB"cnpassive"
SIZE"1B";
"A <SIZE-1..0>\NAC"
$PN"1"44;
%"TP"
"1","(-750,-1050)","1","cnpassive","I67";
;
$LOCATION"TP4"
PART_NAME"TP"
PACK_TYPE"HOLE"
VALUE"0.8MM"
CDS_LIB"cnpassive"
SIZE"1B";
"A <SIZE-1..0>\NAC"
$PN"1"58;
%"TP"
"1","(350,-150)","0","cnpassive","I68";
;
$LOCATION"TP9"
PART_NAME"TP"
PACK_TYPE"HOLE"
VALUE"0.8MM"
CDS_LIB"cnpassive"
SIZE"1B";
"A <SIZE-1..0>\NAC"
$PN"1"41;
%"TP"
"1","(350,-250)","0","cnpassive","I69";
;
$LOCATION"TP10"
PART_NAME"TP"
PACK_TYPE"HOLE"
VALUE"0.8MM"
CDS_LIB"cnpassive"
SIZE"1B";
"A <SIZE-1..0>\NAC"
$PN"1"42;
%"TP"
"1","(-900,-1050)","1","cnpassive","I70";
;
$LOCATION"TP3"
PART_NAME"TP"
PACK_TYPE"HOLE"
VALUE"0.8MM"
CDS_LIB"cnpassive"
SIZE"1B";
"A <SIZE-1..0>\NAC"
$PN"1"58;
%"TP"
"1","(-250,-1250)","0","cnpassive","I71";
;
$LOCATION"TP7"
PART_NAME"TP"
PACK_TYPE"HOLE"
VALUE"0.8MM"
CDS_LIB"cnpassive"
SIZE"1B";
"A <SIZE-1..0>\NAC"
$PN"1"40;
%"TP"
"1","(-100,-1250)","2","cnpassive","I72";
;
$LOCATION"TP8"
PART_NAME"TP"
PACK_TYPE"HOLE"
VALUE"0.8MM"
CDS_LIB"cnpassive"
SIZE"1B";
"A <SIZE-1..0>\NAC"
$PN"1"46;
%"TP"
"1","(-600,-400)","2","cnpassive","I73";
;
$LOCATION"TP5"
PART_NAME"TP"
SIZE"1B"
CDS_LIB"cnpassive"
VALUE"0.8MM"
PACK_TYPE"HOLE";
"A <SIZE-1..0>\NAC"
$PN"1"38;
%"TP"
"1","(-600,-500)","2","cnpassive","I74";
;
$LOCATION"TP6"
PART_NAME"TP"
SIZE"1B"
CDS_LIB"cnpassive"
VALUE"0.8MM"
PACK_TYPE"HOLE";
"A <SIZE-1..0>\NAC"
$PN"1"39;
%"TP"
"1","(-950,-600)","2","cnpassive","I75";
;
$LOCATION"TP1"
PART_NAME"TP"
PACK_TYPE"HOLE"
VALUE"0.8MM"
CDS_LIB"cnpassive"
SIZE"1B";
"A <SIZE-1..0>\NAC"
$PN"1"37;
%"TP"
"1","(-950,-700)","2","cnpassive","I76";
;
$LOCATION"TP2"
PART_NAME"TP"
PACK_TYPE"HOLE"
VALUE"0.8MM"
CDS_LIB"cnpassive"
SIZE"1B";
"A <SIZE-1..0>\NAC"
$PN"1"36;
%"GND_SIGNAL"
"1","(-900,-1250)","0","standard","I77";
;
CDS_LIB"standard"
BODY_TYPE"PLUMBING"
HDL_POWER"GND_SIGNAL";
"GND"58;
%"CON8P"
"1","(150,-2800)","0","cnconnector","I78";
;
$LOCATION"J3"
TYPE"44661-1011"
POWER_GROUP"GND=FRAME"
CDS_SEC"1"
CDS_LOCATION"J3"
CDS_LIB"cnconnector";
"A<6>\NAC"55;
"A<5>\NAC"56;
"A<4>\NAC"57;
"A<3>\NAC"19;
"A<2>\NAC"18;
"A<1>\NAC"17;
"A<0>\NAC"16;
"A<7>\NAC"20;
%"CAPCERSMDCL2"
"1","(1450,150)","0","cnpassive","I8";
;
VOLTAGE"16V"
VALUE"100NF"
$LOCATION"C9"
SIZE"1"
CDS_LIB"cnpassive"
PACK_TYPE"0603"
CDS_LOCATION"C9"
$SEC"1"
CDS_SEC"1";
"B <SIZE-1..0>\NAC"
$PN"2"21;
"A <SIZE-1..0>\NAC"
$PN"1"31;
%"CAPCERSMDCL2"
"1","(1450,350)","0","cnpassive","I9";
;
VALUE"100NF"
$LOCATION"C8"
VOLTAGE"16V"
SIZE"1"
CDS_LIB"cnpassive"
PACK_TYPE"0603"
CDS_LOCATION"C8"
$SEC"1"
CDS_SEC"1";
"B <SIZE-1..0>\NAC"
$PN"2"22;
"A <SIZE-1..0>\NAC"
$PN"1"31;
VHDL_SCALAR_TYPE"std_logic"20;
"CONT_TO_FPGA"
VHDL_MODE"out"
VHDL_SCALAR_TYPE"std_logic"2;
"TRIG_TO_FPGA"
VHDL_MODE"out"
VHDL_SCALAR_TYPE"std_logic"21;
END.
Cadence/worklib/fmc_tlu_toplevel_c/sch_1/pc.db
View file @ a648eb8d
-- pcdb file, Rev:1.0 written by Allegro Design Entry HDL 16.6-S055 (v16-6-112EN) 8/10/2015 on Thu Apr 21 14:46:21 2016
-- pcdb file, Rev:1.0 written by Allegro Design Entry HDL 16.6-S055 (v16-6-112EP) 8/13/2015 on Fri May 20 14:40:51 2016
#ISCELL
bris_cds_standard a3-2000 *
*
#ISCELL
standard gnd_signal *
page1_i10
#ISCELL
standard tap *
page1_i100
#ISCELL
standard tap *
page1_i104
#ISCELL
standard tap *
page1_i108
#CELL
cnpassive capcersmdcl2 *
page1_i11
#ISCELL
standard tap *
page1_i112
#ISCELL
standard tap *
page1_i116
#CELL
cnpassive rsmd0603 *
page1_i12
#ISCELL
standard tap *
page1_i120
#ISCELL
standard tap *
page1_i125
#ISCELL
standard tap *
page1_i126
#ISCELL
standard tap *
page1_i127
#ISCELL
standard tap *
page1_i128
#ISCELL
standard tap *
page1_i129
#CELL
cnpassive rsmd0603 *
page1_i13
#ISCELL
cnpower p3v3 *
page1_i130
#CELL
cnpassive rsmd0603 *
page1_i14
......@@ -35,30 +71,9 @@
#CELL
fmc_tlu_v1_lib pc036a_fmc_lpc_connector *
page1_i2
#ISCELL
standard tap *
page1_i20
#ISCELL
standard tap *
page1_i21
#ISCELL
standard tap *
page1_i22
#ISCELL
standard tap *
page1_i24
#ISCELL
standard tap *
page1_i28
#ISCELL
standard gnd_signal *
page1_i3
#ISCELL
standard tap *
page1_i31
#ISCELL
standard tap *
page1_i35
#ISCELL
standard tap *
page1_i36
......@@ -74,30 +89,9 @@
#ISCELL
standard tap *
page1_i40
#ISCELL
standard tap *
page1_i41
#ISCELL
standard tap *
page1_i42
#ISCELL
standard tap *
page1_i43
#ISCELL
standard tap *
page1_i44
#ISCELL
standard tap *
page1_i45
#ISCELL
standard tap *
page1_i46
#ISCELL
standard tap *
page1_i47
#ISCELL
standard tap *
page1_i48
#ISCELL
standard tap *
page1_i49
......@@ -116,30 +110,9 @@
#ISCELL
standard tap *
page1_i55
#ISCELL
standard tap *
page1_i56
#ISCELL
standard tap *
page1_i57
#ISCELL
standard tap *
page1_i58
#ISCELL
standard tap *
page1_i59
#ISCELL
standard tap *
page1_i60
#ISCELL
standard tap *
page1_i61
#ISCELL
standard tap *
page1_i62
#ISCELL
standard tap *
page1_i63
#ISCELL
standard tap *
page1_i64
......@@ -155,42 +128,12 @@
#CELL
cnconnector plemo2ci *
page1_i7
#ISCELL
standard tap *
page1_i70
#ISCELL
standard tap *
page1_i73
#ISCELL
standard tap *
page1_i76
#ISCELL
standard tap *
page1_i79
#CELL
cnmemory 24aa025e48 *
page1_i8
#ISCELL
standard tap *
page1_i81
#ISCELL
standard tap *
page1_i82
#ISCELL
standard tap *
page1_i83
#ISCELL
standard tap *
page1_i84
#ISCELL
standard tap *
page1_i85
#ISCELL
standard tap *
page1_i86
#ISCELL
cnpower p2v5 *
page1_i88
#ISCELL
standard gnd_signal *
page1_i89
......@@ -231,182 +174,8 @@
bris_cds_standard a3-2000 *
*
#CELL
cnpassive rsmd0603 *
page4_i10
#CELL
cnpassive rsmd0603 *
page4_i11
#ISCELL
standard gnd_signal *
page4_i12
#CELL
cnpassive rsmd0603 *
page4_i18
#CELL
cnpassive capcersmdcl2 *
page4_i19
#CELL
cnconnector con19p *
page4_i2
#ISCELL
standard gnd_signal *
page4_i20
#CELL
cnpassive rsmd0603 *
page4_i21
#CELL
cnpassive capcersmdcl2 *
page4_i22
#ISCELL
standard gnd_signal *
page4_i25
#CELL
cndiscrete trans#20mosfet *
page4_i26
#CELL
cninterface 74lvc1g07 *
page4_i28
#CELL
cnpassive rsmd0603 *
page4_i29
#CELL
cnconnector con19p *
page4_i3
#ISCELL
cnpower p5v *
page4_i30
#CELL
cndiscrete usblc6-2 *
page4_i33
#ISCELL
standard gnd_signal *
page4_i34
#ISCELL
cnpower p2v5 *
page4_i35
#ISCELL
standard gnd_signal *
page4_i37
#CELL
cnpassive rsmd0603 *
page4_i38
#CELL
cnpassive rsmd0603 *
page4_i39
#CELL
cninterface 74lvc1g07 *
page4_i40
#CELL
cnpassive capcersmdcl2 *
page4_i41
#CELL
cnpassive capcersmdcl2 *
page4_i42
#ISCELL
cnpower p5v *
page4_i43
#CELL
cnpassive rsmd0603 *
page4_i44
#CELL
cndiscrete trans#20mosfet *
page4_i45
#ISCELL
cnpower p2v5 *
page4_i48
#CELL
cndiscrete usblc6-2 *
page4_i49
#ISCELL
standard gnd_signal *
page4_i50
#ISCELL
standard gnd_signal *
page4_i51
#ISCELL
cnpower p3v3 *
page4_i54
#ISCELL
cnpower p3v3 *
page4_i55
#CELL
cnpassive capcersmdcl2 *
page4_i56
#ISCELL
standard gnd_signal *
page4_i57
#ISCELL
cnpower p2v5 *
page4_i58
#ISCELL
cnpower p2v5 *
page4_i59
#ISCELL
cnpower frame *
page4_i6
#CELL
cnpassive capcersmdcl2 *
page4_i60
#ISCELL
standard gnd_signal *
page4_i61
#CELL
fmc_tlu_v1_lib fmc_tlu_diode_clamp *
page4_i62
#CELL
fmc_tlu_v1_lib fmc_tlu_diode_clamp *
page4_i63
#CELL
fmc_tlu_v1_lib fmc_tlu_diode_clamp *
page4_i64
#CELL
cnpassive tp *
page4_i65
#CELL
cnpassive tp *
page4_i66
#CELL
cnpassive tp *
page4_i67
#CELL
cnpassive tp *
page4_i68
#CELL
cnpassive tp *
page4_i69
#CELL
cnpassive tp *
page4_i70
#CELL
cnpassive tp *
page4_i71
#CELL
cnpassive tp *
page4_i72
#CELL
cnpassive tp *
page4_i73
#CELL
cnpassive tp *
page4_i74
#CELL
cnpassive tp *
page4_i75
#CELL
cnpassive tp *
page4_i76
#ISCELL
standard gnd_signal *
page4_i77
#CELL
cnconnector con8p *
page4_i78
#CELL
cnpassive capcersmdcl2 *
page4_i8
#CELL
cnpassive capcersmdcl2 *
page4_i9
fmc_tlu_v1_lib fmc_tlu_hdmi_dut_connector *
page4_i1
#ISCELL
bris_cds_standard a3-2000-ohl *
*
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment