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AIDA-2020 TLU - Hardware
Commit b6a613b5 authored by David Cussans's avatar David Cussans
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Checking in files before converting repository to Git

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Showing with 366853 additions and 24688 deletions
Cadence/adw/shoppingCart.xml
View file @ b6a613b5
This diff is collapsed.
Cadence/fmc_tlu_leds_pmt_pwr.cpm
View file @ b6a613b5
{ Machine generated file created by SPI }
{ Last modified was 14:17:26 Wednesday, December 06, 2017 }
{ Last modified was 14:34:56 Wednesday, February 07, 2018 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
......@@ -28,7 +28,6 @@ DOC_GRID_TOGGLE 'ON'
DOC_GRID_SIZE '0.0500'
CHECK_VOLTAGE_ON_HDL 'OFF'
PLOT_FIT_TO_PAGE 'ON'
DONT_SHOW_CM_DLG 'ON'
PRESELECT_FLAG 'ON'
WINDOWSMODE_FLAG 'ON'
SEARCH_HISTORY 'C4' 'c12' 'r2' 'C9' 'C1'
......@@ -60,7 +59,7 @@ create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'fmc_tlu_leds_pmt_pwr_09.brd'
last_board_file 'fmc_tlu_leds_pmt_pwr_26.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'YES'
......
Cadence/fmc_tlu_v1e.cpm
View file @ b6a613b5
{ Machine generated file created by SPI }
{ Last modified was 13:53:54 Wednesday, January 10, 2018 }
{ Last modified was 12:14:53 Friday, February 02, 2018 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
......@@ -38,13 +38,13 @@ CHECK_VOLTAGE_ON_HDL 'OFF'
PLOT_FIT_TO_PAGE 'ON'
PRESELECT_FLAG 'ON'
WINDOWSMODE_FLAG 'ON'
SEARCH_HISTORY 'CN1*' 'CN2*' 'CLK_IO_2' 'CLK_FROM_FPGA*' 'DATA_FROM_CDR*'
PAPER_SIZE '8'
PAPER_ORIENTATION '2'
PAPER_SOURCE '15'
WPLOTTER_NAME 'PDF Writer - bioPDF'
PLOTTER_FACILITY 'DEVICE'
PLOT_EDGE_TO_EDGE 'ON'
SEARCH_HISTORY 'I2C_RESET*' 'cn1_1' 'r1_6' 'd1_6' 'J1_9'
END_CONCEPTHDL
START_PKGRXL
......@@ -66,7 +66,7 @@ create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'fmc_tlu_v1e_150.brd'
last_board_file 'fmc_tlu_v1e_151.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'YES'
......@@ -74,12 +74,12 @@ show_report 'NO'
END_DESIGNSYNC
START_BOMHDL
last_output_file './worklib/fmc_tlu_toplevel_e/bom/tlu_v1e_bom_line.rpt'
last_template_file 'P:/cad/tools/cadence_templates/spreadsheet-format_1per_line.bom'
last_output_file './worklib/fmc_tlu_toplevel_e/bom/tlu_v1e_151_multi_bom.txt'
last_template_file 'P:/cad/tools/cadence_templates/spreadsheet-format.bom'
last_standard_option '1'
last_what_to_output '0'
last_variant_file ''
last_ss_delimiter 'Comma ,'
last_ss_delimiter 'Tab '
use_filters '0'
last_callout_file ''
last_variant ''
......
Cadence/pc042a_lib/nbsg53a_mod/metadata/pinlist.txt 0 → 100755
View file @ b6a613b5
(Pinlist
)
\ No newline at end of file
Cadence/pc042a_lib/nbsg53a_mod/metadata/revision.dat 0 → 100755
View file @ b6a613b5
(Cell nbsg53a_mod
(RevisionInfoBlock
(Baselined 0)
(Revision 0.0.1)
(ModificationStatus NULL)
(Status Created)
(ErrorStatus 0)
(CreateInfo
(Time 04/12/17,15:01:01)
(User phpgb)
(Path uob_hep_pc036a_lib.nbsg53a_mod)
)
)
(Views
(Checksum 0000000019900301)
)
(VersionInfoBlock
(ToolName PDV)
(Version 16.6-S051 (v16-6-112ED))
(License Allegro_performance)
)
(Checksum 000000001a170318)
)
Cadence/worklib/fmc_tlu_clock_gen/entity/pc.db 0 → 100755
View file @ b6a613b5
-- pcdb file, Rev:1.0 written by VAN 08.01-p01 on Mar 29, 2017 13:31:44
Cadence/worklib/fmc_tlu_clock_gen/metadata/pdv_validation.txt 0 → 100755
View file @ b6a613b5
SPLBPD-170,Cell 'fmc_tlu_clock_gen':Pin(s) CLK_FROM_FPGA*,CLK_TO_FFD_* is (are) not present in any package or symbol. You can choose Pins - Add from the Package Pin page and delete these pins. If the HAS_FIXED_SIZE value has been reduced, reload the part.,Warning
Cadence/worklib/fmc_tlu_clock_gen/metadata/pinlist.txt 0 → 100755
View file @ b6a613b5
(Pinlist
(Pin
(Name CLK_TO_FPGA*)
(MSB )
(LSB )
(Type UNSPEC)
(Location Right)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape )
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name CLK_TO_FFD*)
(MSB )
(LSB )
(Type UNSPEC)
(Location Right)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape )
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name CLK*)
(MSB 3)
(LSB 0)
(Type UNSPEC)
(Location Right)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape )
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name CLK_IO_1*)
(MSB )
(LSB )
(Type UNSPEC)
(Location Right)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape )
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name CLK_FROM_CDR*)
(MSB )
(LSB )
(Type UNSPEC)
(Location Left)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape )
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name CLK_FROM_CDR_P)
(MSB )
(LSB )
(Type UNSPEC)
(Location Left)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape )
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name ENABLE_CLK_TO_DUT)
(MSB 3)
(LSB 0)
(Type UNSPEC)
(Location Left)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape )
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name ENABLE_CLK_TO_LEMO)
(MSB )
(LSB )
(Type UNSPEC)
(Location Left)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape )
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name RST*)
(MSB )
(LSB )
(Type UNSPEC)
(Location Left)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape )
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name DUT_CLK_TO_FPGA)
(MSB 3)
(LSB 0)
(Type UNSPEC)
(Location Right)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape )
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name CLK_TO_FFD_P)
(MSB )
(LSB )
(Type UNSPEC)
(Location Left)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape )
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name CLK_IO_2)
(MSB )
(LSB )
(Type UNSPEC)
(Location Right)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape )
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name ENABLE_DUT_CLK_FROM_FPGA)
(MSB 3)
(LSB 0)
(Type UNSPEC)
(Location Left)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape )
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name DUT_CLK_FROM_FPGA)
(MSB 3)
(LSB 0)
(Type UNSPEC)
(Location Left)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape )
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name SCL)
(MSB )
(LSB )
(Type UNSPEC)
(Location Left)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape )
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name SDA)
(MSB )
(LSB )
(Type UNSPEC)
(Location Left)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape )
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name LOL*)
(MSB )
(LSB )
(Type UNSPEC)
(Location Right)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape )
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name CLK_P)
(MSB 3)
(LSB 0)
(Type UNSPEC)
(Location Right)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape )
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name CLK_TO_FPGA_P)
(MSB )
(LSB )
(Type UNSPEC)
(Location Right)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape )
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name CLK_IO_1_P)
(MSB )
(LSB )
(Type UNSPEC)
(Location Right)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape )
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name INTR*)
(MSB )
(LSB )
(Type UNSPEC)
(Location Right)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape )
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name CLK_FROM_FPGA*)
(MSB )
(LSB )
(Type UNSPEC)
(Location Left)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape )
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
(Pin
(Name CLK_TO_FFD_*)
(MSB )
(LSB )
(Type UNSPEC)
(Location Left)
(InputLoadLow )
(InputLoadHigh )
(OutputLoadLow )
(OutputLoadHigh )
(CheckLoad Off)
(CheckIO Off)
(CheckDir 0)
(CheckAssert 0)
(CheckOutput 0)
(UnknownLoading 0)
(PinShape )
(DIFF_PAIR_PINS_POS )
(DIFF_PAIR_PINS_NEG )
)
)
\ No newline at end of file
Cadence/worklib/fmc_tlu_clock_gen/metadata/revision.dat 0 → 100755
View file @ b6a613b5
This diff is collapsed.
Cadence/worklib/fmc_tlu_clock_gen/sch_1/fmc_tlu_clock_gen.dcf,1
View file @ b6a613b5
......@@ -7,7 +7,7 @@
( 16.6 )
)
( revisionNumber
( logicalViewRevNum 111 )
( logicalViewRevNum 112 )
( physicalViewRevNum 4 )
( otherViewRevNum 0 )
)
......@@ -2238,6 +2238,9 @@
)
( objectStatus "UNNAMED_3_RSMD0603_I64_B" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_capcersmdcl2_i133_b"
( objectStatus "unnamed_3_capcersmdcl2_i133_b" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i62_b"
( attribute "CDS_PHYS_NET_NAME" "UNNAMED_3_RSMD0603_I62_B"
( Origin gPackager )
......@@ -2598,6 +2601,9 @@
( signal "@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_osc6pendiffout_i37_endis"
( objectStatus "unnamed_3_osc6pendiffout_i37_endis" )
)
( signal "@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_capcersmdcl2_i134_b"
( objectStatus "unnamed_3_capcersmdcl2_i134_b" )
)
( gate "@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):page3_i15"
( attribute "CDS_LIB" "cninterface"
( Origin gPackager )
......@@ -9768,7 +9774,7 @@
( Units "uVoltage" "V" 1.000000)
( Origin gFrontEnd )
)
( attribute "XY" "(3575,3350)"
( attribute "XY" "(4125,3350)"
( Origin gFrontEnd )
)
( attribute "CHIPS_PART_NAME" "RSMD0603"
......@@ -9780,15 +9786,6 @@
( attribute "CDS_PHYS_PART_NAME" "RSMD0603_1/10W-100,1%"
( Origin gPackager )
)
( attribute "CDS_LOCATION" "R26"
( Origin gPackager )
)
( attribute "CDS_SEC" "1"
( Origin gPackager )
)
( attribute "SEC" "1"
( Origin gPackager )
)
( objectStatus "R26" )
( pin "a(0)"
( attribute "PN" "1"
......@@ -10664,6 +10661,100 @@
( pin "outp"
)
)
( gate "@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):page3_i133"
( attribute "CDS_LIB" "cnpassive"
( Origin gPackager )
)
( attribute "PACK_TYPE" "0603"
( Origin gFrontEnd )
)
( attribute "PHYS_PAGE" "1"
( Origin gFrontEnd )
)
( attribute "ROT" "0"
( Origin gFrontEnd )
)
( attribute "SIZE" "1"
( Origin gFrontEnd )
)
( attribute "VALUE" "100NF"
( Origin gFrontEnd )
)
( attribute "VER" "1"
( Origin gFrontEnd )
)
( attribute "VOLTAGE" "16V"
( Units "uVoltage" "V" 1.000000)
( Origin gFrontEnd )
)
( attribute "XY" "(3975,3500)"
( Origin gFrontEnd )
)
( attribute "CHIPS_PART_NAME" "CAPCERSMDCL2"
( Origin gPackager )
)
( attribute "CDS_PART_NAME" "CAPCERSMDCL2_0603-100NF,16V"
( Origin gPackager )
)
( objectStatus "PAGE3_I133" )
( pin "a(0)"
( attribute "PN" "#"
( Origin gPackager )
)
)
( pin "b(0)"
( attribute "PN" "#"
( Origin gPackager )
)
)
)
( gate "@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):page3_i134"
( attribute "CDS_LIB" "cnpassive"
( Origin gPackager )
)
( attribute "PACK_TYPE" "0603"
( Origin gFrontEnd )
)
( attribute "PHYS_PAGE" "1"
( Origin gFrontEnd )
)
( attribute "ROT" "0"
( Origin gFrontEnd )
)
( attribute "SIZE" "1"
( Origin gFrontEnd )
)
( attribute "VALUE" "100NF"
( Origin gFrontEnd )
)
( attribute "VER" "1"
( Origin gFrontEnd )
)
( attribute "VOLTAGE" "16V"
( Units "uVoltage" "V" 1.000000)
( Origin gFrontEnd )
)
( attribute "XY" "(3975,3225)"
( Origin gFrontEnd )
)
( attribute "CHIPS_PART_NAME" "CAPCERSMDCL2"
( Origin gPackager )
)
( attribute "CDS_PART_NAME" "CAPCERSMDCL2_0603-100NF,16V"
( Origin gPackager )
)
( objectStatus "PAGE3_I134" )
( pin "a(0)"
( attribute "PN" "#"
( Origin gPackager )
)
)
( pin "b(0)"
( attribute "PN" "#"
( Origin gPackager )
)
)
)
( pin "@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):page3_i123(0):a(0)"
( objectStatus "RN3.1" )
)
......
Cadence/worklib/fmc_tlu_leds_pmt_pwr/packaged/pstback.dat
View file @ b6a613b5
{ Packager-XL run on 15-Nov-2017 AT 11:15:55 }
{ Packager-XL run on 07-Feb-2018 AT 14:34:47 }
FILE_TYPE = BACK_ANNOTATION;
DRAWING = "@fmc_tlu_v1_lib.fmc_tlu_leds_pmt_pwr(sch_1):page1";
BODY = "CAPCERSMDCL2","I50": LOCATION = "C7" #&CDS_LOCATION = "C7" &SEC = "1" #&CDS_SEC = "1";
......@@ -381,6 +381,9 @@ BODY = "LED_TRICOLOR_4P_1A3C","I198": LOCATION = "LD13" #&CDS_LOCATION = "LD13"
BODY = "RSMD0603","I201": LOCATION = "R51" #&CDS_LOCATION = "R51" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "RSMD0603","I204": LOCATION = "R50" #&CDS_LOCATION = "R50" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
DRAWING = "@fmc_tlu_v1_lib.fmc_tlu_leds_pmt_pwr(sch_1):page3";
BODY = "CON16P","I146": LOCATION = "J2" #&CDS_LOCATION = "J2" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
......
Cadence/worklib/fmc_tlu_leds_pmt_pwr/packaged/pstchip.dat
View file @ b6a613b5
FILE_TYPE = LIBRARY_PARTS;
{ Packager-XL run on 15-Nov-2017 AT 11:15:55 }
{ Packager-XL run on 07-Feb-2018 AT 14:34:47 }
primitive 'AD5665RBRUZ-1-GND=GND_SIGNAL,VA';
pin
'LDAC*':
......@@ -1164,6 +1164,47 @@ primitive 'RSMD0603_1/10W-4.7K,1%';
PARENT_PPT_PART='RSMD0603_1/10W-4.7K,1%';
end_body;
end_primitive;
primitive 'RSMD0603_1/10W-5.6K,1%';
pin
'A'<0>:
PIN_NUMBER='(1)';
PIN_GROUP='1';
INPUT_LOAD='(*,*)';
OUTPUT_LOAD='(*,*)';
BIDIRECTIONAL='TRUE';
PINUSE='BI';
'B'<0>:
PIN_NUMBER='(2)';
PIN_GROUP='1';
INPUT_LOAD='(*,*)';
OUTPUT_LOAD='(*,*)';
BIDIRECTIONAL='TRUE';
PINUSE='BI';
end_pin;
body
PART_NAME='RSMD0603';
BODY_NAME='RSMD0603';
CLASS='DISCRETE';
PINCOUNT='2';
SIZE='1';
PHYS_DES_PREFIX='R';
DESCRIPTION='SMD Resistor';
CASE='0603';
SMD='YES';
STATUS='Preferred';
PART_NUMBER='R0603_5K6_1%_0.1W_100PPM';
VALUE='5.6k';
TOL='1%';
PWR='0.1W';
JEDEC_TYPE='C0603';
MANUFACTURER='GENERIC';
SCEM='http://edhcat.cern.ch/edhcat/Browser?command=searchItems&scem=11.24.~
03.356.1';
PARENT_PART_TYPE='RSMD0603_1/10W';
PARENT_PPT='RSMD0603';
PARENT_PPT_PART='RSMD0603_1/10W-5.6K,1%';
end_body;
end_primitive;
primitive 'SK_RA_MOLEX_105313_1202-RA';
pin
'A'<1>:
......
Cadence/worklib/fmc_tlu_leds_pmt_pwr/packaged/pstpin.dat
View file @ b6a613b5
FILE_TYPE=PINLIST;
{ Packager-XL run on 15-Nov-2017 AT 11:15:55 }
TIME=' COMPILATION ON 15-Nov-2017 AT 11:15:55';
{ Packager-XL run on 07-Feb-2018 AT 14:34:47 }
TIME=' COMPILATION ON 07-Feb-2018 AT 14:34:47';
primitive 'AD5665RBRUZ-1-GND=GND_SIGNAL,VA';body 'AD5665R';
'LDAC*':'(1)';IN;
'ADDR1':'(2)';IN;
......@@ -148,6 +148,10 @@ primitive 'RSMD0603_1/10W-4.7K,1%';body 'RSMD0603';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'RSMD0603_1/10W-5.6K,1%';body 'RSMD0603';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'SK_RA_MOLEX_105313_1202-RA';body 'SK_RA_MOLEX_105313_1202';
'A'<1>:'(2)';
'A'<0>:'(1)';
......
Cadence/worklib/fmc_tlu_leds_pmt_pwr/packaged/pstrprt.dat
View file @ b6a613b5
......@@ -20,14 +20,15 @@ LM1117-DTX-3.3 LM1117DTX-3.3 1
LP5951_SOT23-5-1.3V,TEXAS INSTA LP5951MF-1.3 1
PCA9539PW-VDD=P3V3,VSS=GND_SIGA PCA9539PW 2
PLEMO4CI-EPL.0S.304.HLN-GND=GNA EPL.0S.304.HLN 4
RSMD0603_-00, R0603_00_JUMPER 7
RSMD0603_-00, R0603_00_JUMPER 8
RSMD0603_1/10W-1.6K,1% R0603_1K6_1%_0.1W_100PPM 4
RSMD0603_1/10W-180,1% R0603_180R_1%_0.1W_100PPM 10
RSMD0603_1/10W-1K,1% R0603_1K_1%_0.1W_100PPM 5
RSMD0603_1/10W-1K,1% R0603_1K_1%_0.1W_100PPM 1
RSMD0603_1/10W-270,1% R0603_270R_1%_0.1W_100PPM 25
RSMD0603_1/10W-4.7K,1% R0603_4K7_1%_0.1W_100PPM 2
RSMD0603_1/10W-5.6K,1% R0603_5K6_1%_0.1W_100PPM 4
SK_RA_MOLEX_105313_1202-RA 105313-1202 1
TP_HOLE-0.8MM TP_HOLE_0.8mm 8
ZENER_SOD123-CA-BZT52-C13 BZT52-C13 1
Total 105
Total 106
Cadence/worklib/fmc_tlu_leds_pmt_pwr/packaged/pstxnet.dat
View file @ b6a613b5
FILE_TYPE = EXPANDEDNETLIST;
{ Packager-XL run on 15-Nov-2017 AT 11:15:55 CONSTRAINTS_VIEW_GENERATED}
{ Packager-XL run on 07-Feb-2018 AT 14:34:47 CONSTRAINTS_VIEW_GENERATED}
NET_NAME
'CDR_LOL'
'@FMC_TLU_V1_LIB.FMC_TLU_LEDS_PMT_PWR(SCH_1):CDR_LOL':
......@@ -169,6 +169,9 @@ NODE_NAME IC2 3
NODE_NAME IC3 3
'@FMC_TLU_V1_LIB.FMC_TLU_LEDS_PMT_PWR(SCH_1):PAGE2_I6@CNINTERFACE.PCA9539(CHIPS)':
'RESET*': CDS_PINID='\reset*\';
NODE_NAME R50 1
'@FMC_TLU_V1_LIB.FMC_TLU_LEDS_PMT_PWR(SCH_1):PAGE2_I204@CNPASSIVE.RSMD0603(CHIPS)':
'A'<0>: CDS_PINID='A(0)';
NET_NAME
'LED<0>'
'@FMC_TLU_V1_LIB.FMC_TLU_LEDS_PMT_PWR(SCH_1):LED'<0>:
......@@ -619,6 +622,9 @@ NODE_NAME REG1 2
NODE_NAME C4 1
'@FMC_TLU_V1_LIB.FMC_TLU_LEDS_PMT_PWR(SCH_1):PAGE1_I131@CNPASSIVE.ELCAPTAN(CHIPS)':
'A'<0>: CDS_PINID='A(0)';
NODE_NAME R50 2
'@FMC_TLU_V1_LIB.FMC_TLU_LEDS_PMT_PWR(SCH_1):PAGE2_I204@CNPASSIVE.RSMD0603(CHIPS)':
'B'<0>: CDS_PINID='B(0)';
NET_NAME
'P3V3D'
'@FMC_TLU_V1_LIB.FMC_TLU_LEDS_PMT_PWR(SCH_1):P3V3D':
......
Cadence/worklib/fmc_tlu_leds_pmt_pwr/packaged/pxl.chg
View file @ b6a613b5
{ Packager-XL run on 15-Nov-2017 AT 11:15:55.00 }
{ Packager-XL run on 07-Feb-2018 AT 14:34:48.00 }
BINDING CHANGES LIST
DELETED BINDINGS:
@FMC_TLU_V1_LIB.FMC_TLU_LEDS_PMT_PWR(SCH_1):PAGE2_I98@CNPASSIVE.RSMD0603(CHIPS) (0) WAS ASSIGNED TO R33 SECTION WITH PIN 1
CHANGED BINDINGS:
@FMC_TLU_V1_LIB.FMC_TLU_LEDS_PMT_PWR(SCH_1):PAGE2_I98@CNPASSIVE.RSMD0603(CHIPS) RSMD0603_1/10W-180,1% (0) IS ASSIGNED TO R33 SECTION 1
END BINDING CHANGES LIST
......@@ -17,11 +15,9 @@ LOGICAL CHANGES LIST
LOGICAL PARTS DELETED FROM DESIGN:
@FMC_TLU_V1_LIB.FMC_TLU_LEDS_PMT_PWR(SCH_1):PAGE2_I98@CNPASSIVE.RSMD0603(CHIPS) (0) R33 SECTION WITH PIN 1
LOGICAL PARTS ADDED TO DESIGN:
@FMC_TLU_V1_LIB.FMC_TLU_LEDS_PMT_PWR(SCH_1):PAGE2_I98@CNPASSIVE.RSMD0603(CHIPS) RSMD0603_1/10W-180,1% (0)
END LOGICAL CHANGES LIST
......@@ -30,11 +26,9 @@ PHYSICAL CHANGES LIST
PHYSICAL PARTS ADDED TO DESIGN:
R33 RSMD0603_1/10W-180,1%
PHYSICAL PARTS DELETED FROM DESIGN:
R33 RSMD0603_1/10W-270,1%
END PHYSICAL CHANGES LIST
......
Cadence/worklib/fmc_tlu_leds_pmt_pwr/physical/master.tag
View file @ b6a613b5
fmc_tlu_leds_pmt_pwr_24.brd
fmc_tlu_leds_pmt_pwr_26.brd
Cadence/worklib/fmc_tlu_leds_pmt_pwr/sch_1/page2.cpc
View file @ b6a613b5
......@@ -244,6 +244,12 @@
#ISCELL
cnpower m5v *
page2_i203
#CELL
cnpassive rsmd0603 *
page2_i204
#ISCELL
cnpower p3v3 *
page2_i205
#CELL
cnpassive rsmd0603 *
page2_i3
......
Cadence/worklib/fmc_tlu_toplevel_e/packaged/pstback.dat
View file @ b6a613b5
{ Packager-XL run on 31-May-2017 AT 17:03:12 }
{ Packager-XL run on 30-Jan-2018 AT 16:40:22 }
FILE_TYPE = BACK_ANNOTATION;
DRAWING = "@fmc_tlu_v1_lib.fmc_tlu_toplevel_e(sch_1):page1";
BODY = "24AA025E48","I8": LOCATION = "IC5" #&CDS_LOCATION = "IC5" &SEC = "1" #&CDS_SEC = "1";
......
Cadence/worklib/fmc_tlu_toplevel_e/physical/tlu_v1e_150.tgz 0 → 100755
View file @ b6a613b5
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fmc_tlu_leds_database.odb 0 → 100644
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