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AIDA-2020 TLU - Hardware
Commit c3dd4c22 authored by David Cussans's avatar David Cussans
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Manual merge of scripted firmware build files from dgc_scripted_build_ipbus2 back into trunk. 

Also, a few PCB files updated when I tested cleaned up trunk 
by exporting schematic to pcb.
parent 1ffed034
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Cadence/fmc_tlu_v1a.cpm
View file @ c3dd4c22
{ Machine generated file created by SPI }
{ Last modified was 13:02:03 Thursday, October 10, 2013 }
{ Last modified was 18:42:38 Tuesday, February 11, 2014 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
......@@ -50,7 +50,7 @@ create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'fmc_tlu_v1a_63.brd'
last_board_file 'fmc_tlu_v1a_66_gloss4a.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'NO'
......
Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstback.dat
View file @ c3dd4c22
{ Packager-XL run on 02-Oct-2013 AT 09:57:38 }
{ Packager-XL run on 11-Feb-2014 AT 18:41:05 }
FILE_TYPE = BACK_ANNOTATION;
DRAWING = "@fmc_tlu_v1_lib.fmc_tlu_toplevel_b(sch_1):page1";
BODY = "PLEMO2CI","I7": LOCATION = "PX1" #&CDS_LOCATION = "PX1" &SEC = "1" #&CDS_SEC = "1";
......
Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstpin.dat
View file @ c3dd4c22
FILE_TYPE=PINLIST;
{ Packager-XL run on 02-Oct-2013 AT 09:57:38 }
TIME=' COMPILATION ON 02-Oct-2013 AT 09:57:38';
{ Packager-XL run on 11-Feb-2014 AT 18:41:05 }
TIME=' COMPILATION ON 11-Feb-2014 AT 18:41:05';
primitive '24AA025E48'; body '24AA025E48';
'VCC':'(8)';
'VSS':'(4)';
......
Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstxnet.dat
View file @ c3dd4c22
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Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstxref.dat
View file @ c3dd4c22
This source diff could not be displayed because it is too large. You can view the blob instead.
Cadence/worklib/fmc_tlu_toplevel_b/packaged/pxl.chg
View file @ c3dd4c22
This source diff could not be displayed because it is too large. You can view the blob instead.
Cadence/worklib/fmc_tlu_toplevel_b/packaged/pxl.log
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Cadence/worklib/fmc_tlu_toplevel_b/physical/master.tag
View file @ c3dd4c22
fmc_tlu_v1a_66_gloss4.brd
fmc_tlu_v1a_66_gloss4a.brd
Cadence/worklib/fmc_tlu_toplevel_b/physical/netrev.lst
View file @ c3dd4c22
......@@ -2,9 +2,9 @@
( )
( Allegro Netrev Import Logic )
( )
( Drawing : fmc_tlu_v1_44.brd )
( Software Version : 16.5P002 )
( Date/Time : Thu Dec 06 10:13:00 2012 )
( Drawing : fmc_tlu_v1a_66_gloss4.brd )
( Software Version : 16.6S014 )
( Date/Time : Tue Feb 11 18:41:14 2014 )
( )
(---------------------------------------------------------------------)
......@@ -16,21 +16,21 @@ RIPUP_DELETE_FIRST_SEGMENT FALSE;
RIPUP_RETAIN_BONDWIRE FALSE;
RIPUP_SYMBOLS ALWAYS;
Missing symbol has error FALSE;
SCHEMATIC_DIRECTORY 'X:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_toplevel\packaged';
SCHEMATIC_DIRECTORY '/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged';
BOARD_DIRECTORY '';
OLD_BOARD_NAME 'X:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel/physical/fmc_tlu_v1_44.brd';
NEW_BOARD_NAME 'fmc_tlu_v1_45.brd';
OLD_BOARD_NAME '/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/physical/fmc_tlu_v1a_66_gloss4.brd';
NEW_BOARD_NAME 'fmc_tlu_v1a_66_gloss4a.brd';
CmdLine: netrev -proj X:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\fmc_tlu_v1.cpm -5 -y 1 -O X:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_toplevel\physical\fmc_tlu_v1_44.brd X:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_toplevel\physical\fmc_tlu_v1_45.brd -$
CmdLine: netrev -proj /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/fmc_tlu_v1a.cpm -y 1 -O /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/physical/fmc_tlu_v1a_66_gloss4.brd /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/physical/fmc_tlu_v1a_66_gloss4a.brd -$
------ Preparing to read pst files ------
Starting to read X:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel/packaged/pstchip.dat
Finished reading X:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel/packaged/pstchip.dat (00:00:00.56)
Starting to read X:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel/packaged/pstxprt.dat
Finished reading X:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel/packaged/pstxprt.dat (00:00:00.09)
Starting to read X:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel/packaged/pstxnet.dat
Finished reading X:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel/packaged/pstxnet.dat (00:00:00.06)
Starting to read /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstchip.dat
Finished reading /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstchip.dat (00:00:00.21)
Starting to read /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstxprt.dat
Finished reading /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstxprt.dat (00:00:00.01)
Starting to read /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstxnet.dat
Finished reading /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstxnet.dat (00:00:00.00)
------ Oversights/Warnings/Errors ------
......@@ -39,54 +39,59 @@ Starting to read X:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc
===========================================================
Start Constraint Diff3 Import
Constraint File: X:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel/packaged/pstcmdb.dat
Allegro Baseline: C:/Temp/#Taaaaae02620.tmp
Start time: Thu Dec 06 10:13:00 2012
Constraint File: /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstcmdb.dat
Allegro Baseline: /tmp/#Taaaaad01896.tmp
Schematic Baseline: /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstcmbc.dat
Start time: Tue Feb 11 18:41:15 2014
===========================================================
===========================================================
Finished Constraint Update Time: Thu Dec 06 10:13:01 2012
Finished Constraint Update Time: Tue Feb 11 18:41:16 2014
===========================================================
------ Library Paths ------
MODULEPATH = .
C:/Cadence/SPB_16.5/share/local/pcb/modules
/cadence/psd15.1/share/local/pcb/modules
../../../modules
../../fmc_tlu_cfd/physical
../../../pc042a_lib/pc042b_vsupply5v/physical
../../fmc_tlu_vsupply5v/physical
PSMPATH = .
/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/symbols
/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/formats
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/connector
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/soic
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/discrete
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/dip
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/so
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/bga
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/qfp
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/passif
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/cap
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/led
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/rel
/projects/HEP_Instrumentation/cad/ral_cdslib/lib_psd15.x/symbols
PADPATH = .
symbols
..
../symbols
C:/Cadence/SPB_16.5/share/local/pcb/symbols
C:/Cadence/SPB_16.5/share/pcb/pcb_lib/symbols
C:/Cadence/SPB_16.5/share/pcb/allegrolib/symbols
x:\cad\cern_cdslib\lib_psd16.x\allegro_libs\pe16\symbols/discrete
g:\cad\bris_cdslib\lib_psd14.x/symbols
x:\cad\cern_cdslib\lib_psd16.x\allegro_libs\pe16\symbols/bga
x:\cad\cern_cdslib\lib_psd16.x\allegro_libs\pe16\symbols/led
x:\cad\cern_cdslib\lib_psd16.x\allegro_libs\pe16\symbols/so
x:\cad\cern_cdslib\lib_psd16.x\allegro_libs\pe16\symbols/soic
x:\cad\cern_cdslib\lib_psd16.x\allegro_libs\pe16\symbols/cap
x:\cad\cern_cdslib\lib_psd16.x\allegro_libs\pe16\symbols/rel
x:\cad\cern_cdslib\lib_psd16.x\allegro_libs\pe16\symbols/dip
x:\cad\cern_cdslib\lib_psd16.x\allegro_libs\pe16\symbols/connector
PADPATH = x:\cad\ral_cdslib\lib_psd15.x/pads
.
symbols
..
../symbols
x:\cad\cern_cdslib/lib_psd16.x/allegro_libs/pe16/padstacks/padstack_smd
g:\cad\bris_cdslib\lib_psd14.x/pads
x:\cad\cern_cdslib/lib_psd16.x/allegro_libs/pe16/padstacks/padstack3
x:\cad\cern_cdslib/lib_psd16.x/allegro_libs/pe16/padstacks/padstackm
x:\cad\cern_cdslib/lib_psd16.x/allegro_libs/pe16/padstacks/padstack_smd
/software/CAD/Cadence/SPB16.60.000/share/local/pcb/padstacks
/software/CAD/Cadence/SPB16.60.000/share/pcb/pcb_lib/symbols
/software/CAD/Cadence/SPB16.60.000/share/pcb/allegrolib/symbols
/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/pads
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/padstacks/padstack_smd
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/padstacks/padstack3
/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/padstacks/padstackm
/projects/HEP_Instrumentation/cad/ral_cdslib/lib_psd15.x/pads
------ Summary Statistics ------
netrev run on Dec 6 10:12:59 2012
DESIGN NAME : 'FMC_TLU_TOPLEVEL'
PACKAGING ON 06-Dec-2012 AT 10:12:42
netrev run on Feb 11 18:41:14 2014
DESIGN NAME : 'FMC_TLU_TOPLEVEL_B'
PACKAGING ON 11-Feb-2014 AT 18:41:05
COMPILE 'logic'
CHECK_PIN_NAMES OFF
......@@ -118,6 +123,6 @@ netrev run on Dec 6 10:12:59 2012
No oversight detected
No warning detected
cpu time 0:05:45
elapsed time 0:00:03
cpu time 0:00:01
elapsed time 0:00:02
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