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AIDA-2020 TLU - Hardware
Commit ccaca958 authored by David Cussans's avatar David Cussans
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Comitting files before copying tlu-c/d to tlu-e

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Cadence/worklib/fmc_tlu_clock_gen/packaged/cmbcview.dat 0 → 100644
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Cadence/worklib/fmc_tlu_clock_gen/packaged/cmdbview.dat 0 → 100644
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Cadence/worklib/fmc_tlu_clock_gen/packaged/compview.dat 0 → 100644
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A!REFDES!COMP_REUSE_ID!COMP_SIGNAL_MODEL!COMP_NO_XNET_CONNECTION!COMP_PARENT_PPT!COMP_SYMBOL_EDITED!COMP_PARENT_PPT_PART!COMP_EMBEDDED_PLACEMENT!
J!P:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_clock_gen/physical/fmc_tlu_clk_gen_02p_v21_allrouted.brd!Wed Jul 27 10:44:06 2016!-35.0000!-75.0000!180.0000!225.0000!0.0001!millimeters!FMC_TLU_CLOCK_GEN!64.921260 mil!6!UP TO DATE!
S!IC1!73!!!DS92001!!DS92001TLD!!
S!IC2!62!!!DS92001!!DS92001TLD!!
S!IC3!72!!!DS92001!!DS92001TLD!!
S!IC4!61!!!DS92001!!DS92001TLD!!
S!IC5!60!!!DS92001!!DS92001TLD!!
S!IC7!28!!!DS92001!!DS92001TLD!!
S!C31!89!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-10NF,16V_GEN!!
S!C32!88!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-10NF,16V_GEN!!
S!C33!87!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-10NF,16V_GEN!!
S!C34!86!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-10NF,16V_GEN!!
S!C35!85!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-10NF,16V_GEN!!
S!C36!84!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-10NF,16V_GEN!!
S!LK1!34!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK2!33!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK3!13!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK4!6!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!QZ1!42!!!OSC_6P_ENDIS_OUTP_OUTN!!BF-100.000MBE-T!!
S!C37!82!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C11!49!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C12!48!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C14!45!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C15!43!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C17!36!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C19!32!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C22!26!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C23!25!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C25!20!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C27!93!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C28!92!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C29!91!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C30!90!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C1!81!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C2!79!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C3!76!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C4!75!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C5!71!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C6!94!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C10!50!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C18!35!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C20!31!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C8!55!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-10UF,6.3V!!
S!C9!54!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-10UF,6.3V!!
S!C16!40!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-10UF,6.3V!!
S!C24!21!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-10UF,6.3V!!
S!C26!19!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-10UF,6.3V!!
S!C13!47!!!CAPCERSMDCL2!!CAPCERSMDCL2_0805-22UF,6.3V!!
S!C21!27!!!CAPCERSMDCL2!!CAPCERSMDCL2_0805-22UF,6.3V!!
S!C7!57!!!CAPCERSMDCL2!!CAPCERSMDCL2_1210-10UF,10V_GEN!!
S!CN1!69!!!CAPN4I!!CAPN4I-1UF,16V,X5R,GNM21!!
S!CN2!23!!!CAPN4I!!CAPN4I-1UF,16V,X5R,GNM21!!
S!L1!78!!!COMMON_MODE_LINE_FILTER!!COMMON_MODE_LINE_FILTER_4312-744231091,90OHM!!
S!L2!77!!!COMMON_MODE_LINE_FILTER!!COMMON_MODE_LINE_FILTER_4312-744231091,90OHM!!
S!L3!65!!!COMMON_MODE_LINE_FILTER!!COMMON_MODE_LINE_FILTER_4312-744231091,90OHM!!
S!L4!64!!!COMMON_MODE_LINE_FILTER!!COMMON_MODE_LINE_FILTER_4312-744231091,90OHM!!
S!L8!38!!!COMMON_MODE_LINE_FILTER!!COMMON_MODE_LINE_FILTER_4312-744231091,90OHM!!
S!J1!30!!!CON3P!!CON3P-SIL254D!!
S!L5!53!!!FERRITE!!FERRITE_C0805-LI0805H121R-10,LI0805H121R-10!!
S!L6!52!!!FERRITE!!FERRITE_C0805-LI0805H121R-10,LI0805H121R-10!!
S!L7!51!!!FERRITE!!FERRITE_C0805-LI0805H121R-10,LI0805H121R-10!!
S!U1!41!!!LP38692SD!!LP38692SD_WSON-1.8V,TEXAS INSTRUMENTS!!
S!LM1!56!!!PLEMO2CI!!PLEMO2CI-EPG.00.302.NLN!!
S!RN1!74!!!RES_ARRAY_X4!!RES_ARRAY_X4_1206_TC164-47,1%!!
S!RN2!63!!!RES_ARRAY_X4!!RES_ARRAY_X4_1206_TC164-47,1%!!
S!RN3!29!!!RES_ARRAY_X4!!RES_ARRAY_X4_1206_TC164-47,1%!!
S!R26!83!!!RSMD0603!!RSMD0603_1/10W-100,1%!!
S!R1!68!!!RSMD0603!!RSMD0603_1/10W-100,1%!!
S!R2!67!!!RSMD0603!!RSMD0603_1/10W-100,1%!!
S!R3!59!!!RSMD0603!!RSMD0603_1/10W-100,1%!!
S!R4!58!!!RSMD0603!!RSMD0603_1/10W-100,1%!!
S!R9!24!!!RSMD0603!!RSMD0603_1/10W-100,1%!!
S!R10!22!!!RSMD0603!!RSMD0603_1/10W-100,1%!!
S!R12!17!!!RSMD0603!!RSMD0603_1/10W-100,1%!!
S!R19!9!!!RSMD0603!!RSMD0603_1/10W-100,1%!!
S!R24!2!!!RSMD0603!!RSMD0603_1/10W-100,1%!!
S!R25!1!!!RSMD0603!!RSMD0603_1/10W-100,1%!!
S!R5!46!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R11!18!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R13!16!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R14!15!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R15!14!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R16!12!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R17!11!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R18!10!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R20!8!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R21!7!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R22!5!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R23!4!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R6!44!!!RSMD0603!!RSMD0603_1/10W-4.7K,1%!!
S!R7!39!!!RSMD0603!!RSMD0603_1/10W-XX,1%!!
S!R8!37!!!RSMD0603!!RSMD0603_1/10W-XX,1%!!
S!IC8!3!!!SI5345!!SI5345A-B-GM!!
S!IC6!66!!!SN65MLVD040!!SN65MLVD040RGZ!!
S!D3!80!!!USBLC6-2!!USBLC6-2SC6!!
Cadence/worklib/fmc_tlu_clock_gen/packaged/erc.rpt 0 → 100644
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Cadence/worklib/fmc_tlu_clock_gen/packaged/funcview.dat 0 → 100644
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Cadence/worklib/fmc_tlu_clock_gen/packaged/netview.dat 0 → 100644
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A!NET_NAME!NET_LOGICAL_PATH!NET_VOLTAGE!
J!P:/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_clock_gen/physical/fmc_tlu_clk_gen_02p_v21_allrouted.brd!Wed Jul 27 10:44:07 2016 CONSTRAINTS_VIEW_GENERATED!-35.0000!
S!ENABLE_DUT_CLK_FROM_FPGA<1>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):enable_dut_clk_from_fpga(1)!!
S!XA!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):xa!!
S!XB!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):xb!!
S!VDDO_CLK40!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):vddo_clk40!!
S!UNNAMED_3_RSMD0603_I87_B!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i87_b!!
S!UNNAMED_3_RSMD0603_I87_A!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i87_a!!
S!UNNAMED_3_RSMD0603_I86_B!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i86_b!!
S!UNNAMED_3_RSMD0603_I86_A!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i86_a!!
S!UNNAMED_3_RSMD0603_I69_B!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i69_b!!
S!UNNAMED_3_RSMD0603_I68_B!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i68_b!!
S!UNNAMED_3_RSMD0603_I65_B!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i65_b!!
S!UNNAMED_3_RSMD0603_I64_B!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i64_b!!
S!UNNAMED_3_RSMD0603_I62_B!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i62_b!!
S!UNNAMED_3_RSMD0603_I60_B!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i60_b!!
S!UNNAMED_3_RSMD0603_I58_B!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i58_b!!
S!UNNAMED_3_RSMD0603_I57_B!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i57_b!!
S!UNNAMED_3_PLEMO2CI_I7_B!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_plemo2ci_i7_b!!
S!UNNAMED_3_PLEMO2CI_I7_A!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_plemo2ci_i7_a!!
S!UNNAMED_3_OSC6PENDISOUTPOUTN_I3!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_osc6pendisoutpoutn_i37_endis!!
S!UNNAMED_3_LP38692SD_I85_EN!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_lp38692sd_i85_en!!
S!UNNAMED_3_CAPN4I_I11_A!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_capn4i_i11_a!!
S!UNNAMED_3_CAPCERSMDCL2_I45_B!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_capcersmdcl2_i45_b!!
S!UNNAMED_3_CAPCERSMDCL2_I44_B!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_capcersmdcl2_i44_b!!
S!UNNAMED_3_1-HOLE_I95_A!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):\unnamed_3_1-hole_i95_a\!!
S!UNNAMED_3_1-HOLE_I94_A!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):\unnamed_3_1-hole_i94_a\!!
S!UNNAMED_1_COMMONMODELINEFILTE_7!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_1_commonmodelinefilter_i228_2!!
S!UNNAMED_1_COMMONMODELINEFILTE_6!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_1_commonmodelinefilter_i228_1!!
S!UNNAMED_1_COMMONMODELINEFILTE_5!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_1_commonmodelinefilter_i210_2!!
S!UNNAMED_1_COMMONMODELINEFILTE_4!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_1_commonmodelinefilter_i210_1!!
S!UNNAMED_1_COMMONMODELINEFILTE_3!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_1_commonmodelinefilter_i194_2!!
S!UNNAMED_1_COMMONMODELINEFILTE_2!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_1_commonmodelinefilter_i194_1!!
S!UNNAMED_1_COMMONMODELINEFILTE_1!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_1_commonmodelinefilter_i80_2!!
S!UNNAMED_1_COMMONMODELINEFILTER_!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_1_commonmodelinefilter_i80_1!!
S!UNNAMED_1_CAPN4I_I83_A!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_1_capn4i_i83_a!!
S!UNNAMED_1_CAPN4I_I224_A!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_1_capn4i_i224_a!!
S!UNNAMED_1_CAPN4I_I205_A!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_1_capn4i_i205_a!!
S!UNNAMED_1_CAPN4I_I190_A!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):unnamed_1_capn4i_i190_a!!
S!SDA!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):sda!!
S!SCL!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):scl!!
S!RST*!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):\rst*\!!
S!LOL*!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):\lol*\!!
S!LEMO_CLK_P!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):lemo_clk_p!!
S!LEMO_CLK_N!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):lemo_clk_n!!
S!INTR*!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):\intr*\!!
S!ENABLE_DUT_CLK_FROM_FPGA<3>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):enable_dut_clk_from_fpga(3)!!
S!ENABLE_DUT_CLK_FROM_FPGA<2>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):enable_dut_clk_from_fpga(2)!!
S!ENABLE_CLK_TO_DUT<2>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):enable_clk_to_dut(2)!!
S!ENABLE_DUT_CLK_FROM_FPGA<0>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):enable_dut_clk_from_fpga(0)!!
S!ENABLE_CLK_TO_LEMO!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):enable_clk_to_lemo!!
S!ENABLE_CLK_TO_DUT<1>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):enable_clk_to_dut(1)!!
S!ENABLE_CLK_TO_DUT<3>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):enable_clk_to_dut(3)!!
S!ENABLE_CLK_TO_DUT<0>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):enable_clk_to_dut(0)!!
S!DUT_CLK_TO_FPGA<3>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):dut_clk_to_fpga(3)!!
S!DUT_CLK_TO_FPGA<2>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):dut_clk_to_fpga(2)!!
S!DUT_CLK_TO_FPGA<1>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):dut_clk_to_fpga(1)!!
S!DUT_CLK_TO_FPGA<0>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):dut_clk_to_fpga(0)!!
S!DUT_CLK_FROM_FPGA<3>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):dut_clk_from_fpga(3)!!
S!DUT_CLK_FROM_FPGA<2>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):dut_clk_from_fpga(2)!!
S!DUT_CLK_FROM_FPGA<1>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):dut_clk_from_fpga(1)!!
S!DUT_CLK_FROM_FPGA<0>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):dut_clk_from_fpga(0)!!
S!CLK_TO_LEMO_P!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_to_lemo_p!!
S!CLK_TO_LEMO_N!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_to_lemo_n!!
S!CLK_TO_FPGA_P!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_to_fpga_p!!
S!CLK_TO_FPGA_N!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_to_fpga_n!!
S!CLK_TO_DUT_P<3>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_to_dut_p(3)!!
S!CLK_TO_DUT_P<2>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_to_dut_p(2)!!
S!CLK_TO_DUT_P<1>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_to_dut_p(1)!!
S!CLK_TO_DUT_P<0>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_to_dut_p(0)!!
S!CLK_TO_DUT_N<3>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_to_dut_n(3)!!
S!CLK_TO_DUT_N<2>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_to_dut_n(2)!!
S!CLK_TO_DUT_N<1>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_to_dut_n(1)!!
S!CLK_TO_DUT_N<0>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_to_dut_n(0)!!
S!CLK_N<3>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_n(3)!!
S!CLK_N<2>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_n(2)!!
S!CLK_N<1>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_n(1)!!
S!CLK_N<0>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_n(0)!!
S!CLK_P<3>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_p(3)!!
S!CLK_P<2>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_p(2)!!
S!CLK_P<1>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_p(1)!!
S!CLK_P<0>!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_p(0)!!
S!CLK_IO_2!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_io_2!!
S!CLK_IO_1_P!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_io_1_p!!
S!CLK_IO_1_N!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_io_1_n!!
S!CLK_FROM_LEMO_P!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_from_lemo_p!!
S!CLK_FROM_LEMO_N!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_from_lemo_n!!
S!CLK_FROM_HDMI_P!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_from_hdmi_p!!
S!CLK_FROM_HDMI_N!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_from_hdmi_n!!
S!CLK_FROM_FPGA_P!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_from_fpga_p!!
S!CLK_FROM_FPGA_N!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):clk_from_fpga_n!!
S!VDD_OSC!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):vdd_osc!!
S!VDDA_CLK40!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):vdda_clk40!!
S!VDD_CLK40!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):vdd_clk40!!
S!P3V3!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):p3v3!!
S!GND_SIGNAL!@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):gnd_signal!!
Cadence/worklib/fmc_tlu_clock_gen/packaged/pinview.dat 0 → 100644
View file @ ccaca958
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Cadence/worklib/fmc_tlu_clock_gen/packaged/pstcmbc.dat 0 → 100644
View file @ ccaca958
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Cadence/worklib/fmc_tlu_toplevel_c/bom/fmc_tlu_v1d.csv 0 → 100644
View file @ ccaca958
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