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AIDA-2020 TLU - Hardware
Commit daabf61c authored by David Cussans's avatar David Cussans
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Checking in edited schematic for clock generator

parent 679c6aed
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Showing with 10417 additions and 6292 deletions
Cadence/adw/shoppingCart.xml
View file @ daabf61c
......@@ -133,4 +133,9 @@
<property name="TOL" value="1%"/>
<property name="VALUE" value="82"/>
</component>
<component cell="capcersmdcl2" library="cnpassive" partname="CAPCERSMDCL2" partno="CC0402_10NF_16V_10%_X7R" quantity="1" >
<property name="PACK_TYPE" value="0402"/>
<property name="VALUE" value="10nF"/>
<property name="VOLTAGE" value="16V_GEN"/>
</component>
</sc:shoppingCart>
Cadence/fmc_tlu_clock_gen.cpm
View file @ daabf61c
{ Machine generated file created by SPI }
{ Last modified was 15:19:04 Wednesday, June 08, 2016 }
{ Last modified was 14:11:52 Tuesday, June 21, 2016 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
......@@ -35,7 +35,6 @@ PLOT_EDGE_TO_EDGE 'ON'
END_CONCEPTHDL
START_PKGRXL
repackage 'ON'
regenerate_physical_net_name 'OFF'
electrical_constraints 'ON'
overwrite_constraints 'OFF'
......@@ -52,7 +51,7 @@ create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'fmc_tlu_clk_gen_01.brd'
last_board_file 'fmc_tlu_clk_gen_02.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'NO'
......
Cadence/fmc_tlu_threshold_discriminator_dual.cpm
View file @ daabf61c
{ Machine generated file created by SPI }
{ Last modified was 14:40:25 Wednesday, June 08, 2016 }
{ Last modified was 11:31:33 Thursday, June 09, 2016 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
......@@ -44,7 +44,7 @@ create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'fmc_tlu_threshold_discriminator_dual_01.brd'
last_board_file 'fmc_tlu_threshold_discriminator_dual_02.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'NO'
......
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstback.dat
View file @ daabf61c
{ Packager-XL run on 08-Jun-2016 AT 15:18:50 }
{ Packager-XL run on 21-Jun-2016 AT 14:11:12 }
FILE_TYPE = BACK_ANNOTATION;
DRAWING = "@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):page1";
BODY = "SN65MLVD040","I79": LOCATION = "IC3" #&CDS_LOCATION = "IC3" &SEC = "1" #&CDS_SEC = "1";
......@@ -30,9 +30,6 @@ BODY = "RSMD0603","I106": LOCATION = "R1" #&CDS_LOCATION = "R1" &SEC = "1" #&CDS
BODY = "CAPCERSMDCL2","I160": LOCATION = "C2" #&CDS_LOCATION = "C2" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "CAPCERSMDCL2","I161": LOCATION = "C6" #&CDS_LOCATION = "C6" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "CAPCERSMDCL2","I162": LOCATION = "C5" #&CDS_LOCATION = "C5" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
......@@ -150,6 +147,36 @@ BODY = "DS92001","I234": LOCATION = "IC5" #&CDS_LOCATION = "IC5" &SEC = "1" #&CD
"IN-": PN = "2" !CDS_PN = "2";
"OUT+": PN = "6" !CDS_PN = "6";
"OUT-": PN = "7" !CDS_PN = "7";
BODY = "CAPCERSMDCL2","I237": LOCATION = "C6" #&CDS_LOCATION = "C6" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "CAPCERSMDCL2","I238": LOCATION = "C30" #&CDS_LOCATION = "C30" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "CAPCERSMDCL2","I239": LOCATION = "C29" #&CDS_LOCATION = "C29" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "CAPCERSMDCL2","I240": LOCATION = "C28" #&CDS_LOCATION = "C28" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "CAPCERSMDCL2","I241": LOCATION = "C27" #&CDS_LOCATION = "C27" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "CAPCERSMDCL2","I244": LOCATION = "C35" #&CDS_LOCATION = "C35" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "CAPCERSMDCL2","I245": LOCATION = "C34" #&CDS_LOCATION = "C34" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "CAPCERSMDCL2","I246": LOCATION = "C33" #&CDS_LOCATION = "C33" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "CAPCERSMDCL2","I247": LOCATION = "C32" #&CDS_LOCATION = "C32" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "CAPCERSMDCL2","I248": LOCATION = "C31" #&CDS_LOCATION = "C31" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
DRAWING = "@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):page3";
BODY = "SI5345","I1": LOCATION = "IC8" #&CDS_LOCATION = "IC8" &SEC = "1" #&CDS_SEC = "1";
"A0/CS": PN = "19" !CDS_PN = "19";
......@@ -401,4 +428,13 @@ BODY = "RSMD0603","I108": LOCATION = "R7" #&CDS_LOCATION = "R7" &SEC = "1" #&CDS
BODY = "RSMD0603","I109": LOCATION = "R8" #&CDS_LOCATION = "R8" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "RSMD0603","I116": LOCATION = "R26" #&CDS_LOCATION = "R26" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "CAPCERSMDCL2","I117": LOCATION = "C37" #&CDS_LOCATION = "C37" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "CAPCERSMDCL2","I118": LOCATION = "C36" #&CDS_LOCATION = "C36" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
END.
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstback.dat,1
View file @ daabf61c
{ Packager-XL run on 03-Jun-2016 AT 10:45:06 }
{ Packager-XL run on 08-Jun-2016 AT 14:50:07 }
FILE_TYPE = BACK_ANNOTATION;
DRAWING = "@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):page1";
BODY = "SN65MLVD040","I79": LOCATION = "IC3" #&CDS_LOCATION = "IC3" &SEC = "1" #&CDS_SEC = "1";
......@@ -225,7 +225,7 @@ BODY = "USBLC6-2","I6": #LOCATION = "D3" !CDS_LOCATION = "D3" &SEC = "1" #&CDS_S
BODY = "PLEMO2CI","I7": LOCATION = "LM1" #&CDS_LOCATION = "LM1" &SEC = "1" #&CDS_SEC = "1";
"A": PN = "1" !CDS_PN = "1";
"B": PN = "2" !CDS_PN = "2";
BODY = "RSMD0603","I10": LOCATION = "R7" #&CDS_LOCATION = "R7" &SEC = "1" #&CDS_SEC = "1";
BODY = "RSMD0603","I10": LOCATION = "R10" #&CDS_LOCATION = "R10" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "CAPN4I","I11": LOCATION = "CN2" #&CDS_LOCATION = "CN2" &SEC = "1" #&CDS_SEC = "1";
......@@ -266,7 +266,7 @@ BODY = "FERRITE","I22": LOCATION = "L7" #&CDS_LOCATION = "L7" &SEC = "1" #&CDS_S
BODY = "CAPCERSMDCL2","I23": LOCATION = "C9" #&CDS_LOCATION = "C9" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "CAPCERSMDCL2","I24": LOCATION = "C23" #&CDS_LOCATION = "C23" &SEC = "1" #&CDS_SEC = "1";
BODY = "CAPCERSMDCL2","I24": LOCATION = "C24" #&CDS_LOCATION = "C24" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "CAPCERSMDCL2","I25": LOCATION = "C22" #&CDS_LOCATION = "C22" &SEC = "1" #&CDS_SEC = "1";
......@@ -278,16 +278,10 @@ BODY = "CAPCERSMDCL2","I26": LOCATION = "C19" #&CDS_LOCATION = "C19" &SEC = "1"
BODY = "CAPCERSMDCL2","I27": LOCATION = "C17" #&CDS_LOCATION = "C17" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "RSMD0603","I28": LOCATION = "R9" #&CDS_LOCATION = "R9" &SEC = "1" #&CDS_SEC = "1";
BODY = "RSMD0603","I28": LOCATION = "R12" #&CDS_LOCATION = "R12" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "RSMD0603","I30": LOCATION = "R11" #&CDS_LOCATION = "R11" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "RSMD0603","I31": LOCATION = "R13" #&CDS_LOCATION = "R13" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "RSMD0603","I36": LOCATION = "R6" #&CDS_LOCATION = "R6" &SEC = "1" #&CDS_SEC = "1";
BODY = "RSMD0603","I36": LOCATION = "R5" #&CDS_LOCATION = "R5" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "OSC_6P_ENDIS_OUTP_OUTN","I37": LOCATION = "QZ1" #&CDS_LOCATION = "QZ1" &SEC = "1" #&CDS_SEC = "1";
......@@ -313,16 +307,16 @@ BODY = "CON3P","I47": LOCATION = "J1" #&CDS_LOCATION = "J1" &SEC = "1" #&CDS_SEC
"A<0>": PN = "1" !CDS_PN = "1";
"A<1>": PN = "2" !CDS_PN = "2";
"A<2>": PN = "3" !CDS_PN = "3";
BODY = "RSMD0603","I48": LOCATION = "R8" #&CDS_LOCATION = "R8" &SEC = "1" #&CDS_SEC = "1";
BODY = "RSMD0603","I48": LOCATION = "R9" #&CDS_LOCATION = "R9" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "RSMD0603","I54": LOCATION = "R14" #&CDS_LOCATION = "R14" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "RSMD0603","I55": LOCATION = "R12" #&CDS_LOCATION = "R12" &SEC = "1" #&CDS_SEC = "1";
BODY = "RSMD0603","I55": LOCATION = "R13" #&CDS_LOCATION = "R13" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "RSMD0603","I56": LOCATION = "R10" #&CDS_LOCATION = "R10" &SEC = "1" #&CDS_SEC = "1";
BODY = "RSMD0603","I56": LOCATION = "R11" #&CDS_LOCATION = "R11" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "RSMD0603","I57": LOCATION = "R22" #&CDS_LOCATION = "R22" &SEC = "1" #&CDS_SEC = "1";
......@@ -356,7 +350,7 @@ BODY = "CAPCERSMDCL2","I74": LOCATION = "C21" #&CDS_LOCATION = "C21" &SEC = "1"
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "1-HOLE","I76": LOCATION = "LK1" #&CDS_LOCATION = "LK1" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
BODY = "RSMD0603","I79": LOCATION = "R5" #&CDS_LOCATION = "R5" &SEC = "1" #&CDS_SEC = "1";
BODY = "RSMD0603","I79": LOCATION = "R6" #&CDS_LOCATION = "R6" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "CAPCERSMDCL2","I80": LOCATION = "C13" #&CDS_LOCATION = "C13" &SEC = "1" #&CDS_SEC = "1";
......@@ -392,4 +386,19 @@ BODY = "1-HOLE","I94": LOCATION = "LK4" #&CDS_LOCATION = "LK4" &SEC = "1" #&CDS_
"A<0>": PN = "1" !CDS_PN = "1";
BODY = "1-HOLE","I95": LOCATION = "LK3" #&CDS_LOCATION = "LK3" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
BODY = "CAPCERSMDCL2","I96": LOCATION = "C26" #&CDS_LOCATION = "C26" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "CAPCERSMDCL2","I97": LOCATION = "C25" #&CDS_LOCATION = "C25" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "CAPCERSMDCL2","I98": LOCATION = "C23" #&CDS_LOCATION = "C23" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "RSMD0603","I108": LOCATION = "R7" #&CDS_LOCATION = "R7" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "RSMD0603","I109": LOCATION = "R8" #&CDS_LOCATION = "R8" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
END.
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstback.dat,2
View file @ daabf61c
{ Packager-XL run on 03-Jun-2016 AT 13:35:26 }
{ Packager-XL run on 08-Jun-2016 AT 15:18:50 }
FILE_TYPE = BACK_ANNOTATION;
DRAWING = "@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):page1";
BODY = "SN65MLVD040","I79": LOCATION = "IC3" #&CDS_LOCATION = "IC3" &SEC = "1" #&CDS_SEC = "1";
......@@ -395,20 +395,6 @@ BODY = "CAPCERSMDCL2","I97": LOCATION = "C25" #&CDS_LOCATION = "C25" &SEC = "1"
BODY = "CAPCERSMDCL2","I98": LOCATION = "C23" #&CDS_LOCATION = "C23" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "CAPN4I","I100": LOCATION = "CN2" #&CDS_LOCATION = "CN2" &SEC = "2" #&CDS_SEC = "2";
"A<0>": PN = "3" !CDS_PN = "3";
"B<0>": PN = "4" !CDS_PN = "4";
BODY = "RES_ARRAY_X4","I101": LOCATION = "RN3" #&CDS_LOCATION = "RN3" &SEC = "4" #&CDS_SEC = "4";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "8" !CDS_PN = "8";
BODY = "RES_ARRAY_X4","I102": LOCATION = "RN3" #&CDS_LOCATION = "RN3" &SEC = "3" #&CDS_SEC = "3";
"A<0>": PN = "2" !CDS_PN = "2";
"B<0>": PN = "7" !CDS_PN = "7";
BODY = "COMMON_MODE_LINE_FILTER","I103": LOCATION = "L9" #&CDS_LOCATION = "L9" &SEC = "1" #&CDS_SEC = "1";
"1<0>": PN = "3" !CDS_PN = "3";
"1DOT<0>": PN = "4" !CDS_PN = "4";
"2<0>": PN = "2" !CDS_PN = "2";
"2DOT<0>": PN = "1" !CDS_PN = "1";
BODY = "RSMD0603","I108": LOCATION = "R7" #&CDS_LOCATION = "R7" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
......
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstback.dat,3
View file @ daabf61c
{ Packager-XL run on 08-Jun-2016 AT 14:50:07 }
{ Packager-XL run on 21-Jun-2016 AT 13:51:31 }
FILE_TYPE = BACK_ANNOTATION;
DRAWING = "@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):page1";
BODY = "SN65MLVD040","I79": LOCATION = "IC3" #&CDS_LOCATION = "IC3" &SEC = "1" #&CDS_SEC = "1";
......
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstchip.dat
View file @ daabf61c
FILE_TYPE = LIBRARY_PARTS;
{ Packager-XL run on 08-Jun-2016 AT 15:18:50 }
{ Packager-XL run on 21-Jun-2016 AT 14:11:12 }
primitive '1-HOLE_0-8-BASE';
pin
'A'<0>:
......@@ -103,6 +103,49 @@ primitive 'CAPCERSMDCL2_0402-100NF,16V_GEN';
PARENT_PPT_PART='CAPCERSMDCL2_0402-100NF,16V_GEN';
end_body;
end_primitive;
primitive 'CAPCERSMDCL2_0402-10NF,16V_GEN';
pin
'A'<0>:
PIN_NUMBER='(1)';
PIN_GROUP='1';
INPUT_LOAD='(*,*)';
OUTPUT_LOAD='(*,*)';
BIDIRECTIONAL='TRUE';
PINUSE='BI';
'B'<0>:
PIN_NUMBER='(2)';
PIN_GROUP='1';
INPUT_LOAD='(*,*)';
OUTPUT_LOAD='(*,*)';
BIDIRECTIONAL='TRUE';
PINUSE='BI';
end_pin;
body
PART_NAME='CAPCERSMDCL2';
BODY_NAME='CAPCERSMDCL2';
UNKNOWN_LOADING='TRUE';
NO_LOAD_CHECK='TRUE';
ALLOW_CONNECT='TRUE';
PINCOUNT='2';
SIZE='1';
PHYS_DES_PREFIX='C';
CLASS='DISCRETE';
STATUS='Preferred';
PART_NUMBER='CC0402_10NF_16V_10%_X7R';
MANUFACTURER='GENERIC';
DESCRIPTION='SMD X7R Ceramic Capacitor';
DATASHEET_URL='';
SMD='YES';
CASE='0402';
JEDEC_TYPE='C0402';
VALUE='10nF';
VOLT='16V';
TOL='10%';
PARENT_PART_TYPE='CAPCERSMDCL2_0402';
PARENT_PPT='CAPCERSMDCL2';
PARENT_PPT_PART='CAPCERSMDCL2_0402-10NF,16V_GEN';
end_body;
end_primitive;
primitive 'CAPCERSMDCL2_0603-100NF,16V';
pin
'A'<0>:
......
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstchip.dat,1
View file @ daabf61c
FILE_TYPE = LIBRARY_PARTS;
{ Packager-XL run on 03-Jun-2016 AT 10:45:06 }
{ Packager-XL run on 08-Jun-2016 AT 14:50:07 }
primitive '1-HOLE_0-8-BASE';
pin
'A'<0>:
......@@ -760,6 +760,46 @@ primitive 'RSMD0603_1/10W-4.7K,1%';
PARENT_PPT_PART='RSMD0603_1/10W-4.7K,1%';
end_body;
end_primitive;
primitive 'RSMD0603_1/10W-XX,1%';
pin
'A'<0>:
PIN_NUMBER='(1)';
PIN_GROUP='1';
INPUT_LOAD='(*,*)';
OUTPUT_LOAD='(*,*)';
BIDIRECTIONAL='TRUE';
PINUSE='BI';
'B'<0>:
PIN_NUMBER='(2)';
PIN_GROUP='1';
INPUT_LOAD='(*,*)';
OUTPUT_LOAD='(*,*)';
BIDIRECTIONAL='TRUE';
PINUSE='BI';
end_pin;
body
PART_NAME='RSMD0603';
BODY_NAME='RSMD0603';
CLASS='DISCRETE';
PINCOUNT='2';
SIZE='1';
PHYS_DES_PREFIX='R';
DESCRIPTION='SMD Resistor';
CASE='0603';
SMD='YES';
STATUS='Not Preferred';
PART_NUMBER='R0603_XX_1%_0.1W_100PPM';
VALUE='XX';
TOL='1%';
PWR='0.1W';
JEDEC_TYPE='C0603';
MANUFACTURER='GENERIC';
MOUNTED='NO';
PARENT_PART_TYPE='RSMD0603_1/10W';
PARENT_PPT='RSMD0603';
PARENT_PPT_PART='RSMD0603_1/10W-XX,1%';
end_body;
end_primitive;
primitive 'SI5345A-B-GM-GND=GND_SIGNAL,VDA';
pin
'A0/CS':
......
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstchip.dat,2
View file @ daabf61c
FILE_TYPE = LIBRARY_PARTS;
{ Packager-XL run on 03-Jun-2016 AT 13:35:26 }
{ Packager-XL run on 08-Jun-2016 AT 15:18:50 }
primitive '1-HOLE_0-8-BASE';
pin
'A'<0>:
......
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstchip.dat,3
View file @ daabf61c
FILE_TYPE = LIBRARY_PARTS;
{ Packager-XL run on 08-Jun-2016 AT 14:50:07 }
{ Packager-XL run on 21-Jun-2016 AT 13:51:31 }
primitive '1-HOLE_0-8-BASE';
pin
'A'<0>:
......
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstcmdb.dat
View file @ daabf61c
; Packager-XL run on 08-Jun-2016 AT 15:18:50 CONSTRAINTS_VIEW_GENERATED
; Packager-XL run on 21-Jun-2016 AT 14:11:12 CONSTRAINTS_VIEW_GENERATED
( ConstraintFile "fmc_tlu_clock_gen"
( constraintHeader
( objectKey
......@@ -8,7 +8,7 @@
( 16.6 )
)
( revisionNumber
( logicalViewRevNum 54 )
( logicalViewRevNum 58 )
( physicalViewRevNum 0 )
( otherViewRevNum 0 )
)
......@@ -1562,7 +1562,7 @@
)
)
( gate "C6"
( objectStatus "@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):page1_i161" )
( objectStatus "@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):page1_i237" )
( pin "C6.1"
( objectStatus "a(0)" )
)
......@@ -2056,6 +2056,114 @@
( objectStatus "b(0)" )
)
)
( gate "R26"
( objectStatus "@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):page3_i116" )
( pin "R26.1"
( objectStatus "a(0)" )
)
( pin "R26.2"
( objectStatus "b(0)" )
)
)
( gate "C37"
( objectStatus "@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):page3_i117" )
( pin "C37.1"
( objectStatus "a(0)" )
)
( pin "C37.2"
( objectStatus "b(0)" )
)
)
( gate "C36"
( objectStatus "@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):page3_i118" )
( pin "C36.1"
( objectStatus "a(0)" )
)
( pin "C36.2"
( objectStatus "b(0)" )
)
)
( gate "C30"
( objectStatus "@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):page1_i238" )
( pin "C30.1"
( objectStatus "a(0)" )
)
( pin "C30.2"
( objectStatus "b(0)" )
)
)
( gate "C29"
( objectStatus "@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):page1_i239" )
( pin "C29.1"
( objectStatus "a(0)" )
)
( pin "C29.2"
( objectStatus "b(0)" )
)
)
( gate "C28"
( objectStatus "@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):page1_i240" )
( pin "C28.1"
( objectStatus "a(0)" )
)
( pin "C28.2"
( objectStatus "b(0)" )
)
)
( gate "C27"
( objectStatus "@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):page1_i241" )
( pin "C27.1"
( objectStatus "a(0)" )
)
( pin "C27.2"
( objectStatus "b(0)" )
)
)
( gate "C35"
( objectStatus "@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):page1_i244" )
( pin "C35.1"
( objectStatus "a(0)" )
)
( pin "C35.2"
( objectStatus "b(0)" )
)
)
( gate "C34"
( objectStatus "@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):page1_i245" )
( pin "C34.1"
( objectStatus "a(0)" )
)
( pin "C34.2"
( objectStatus "b(0)" )
)
)
( gate "C33"
( objectStatus "@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):page1_i246" )
( pin "C33.1"
( objectStatus "a(0)" )
)
( pin "C33.2"
( objectStatus "b(0)" )
)
)
( gate "C32"
( objectStatus "@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):page1_i247" )
( pin "C32.1"
( objectStatus "a(0)" )
)
( pin "C32.2"
( objectStatus "b(0)" )
)
)
( gate "C31"
( objectStatus "@fmc_tlu_v1_lib.fmc_tlu_clock_gen(sch_1):page1_i248" )
( pin "C31.1"
( objectStatus "a(0)" )
)
( pin "C31.2"
( objectStatus "b(0)" )
)
)
( bus "CLK_N"
( memberType ( signal ) )
( member ( signalRef "CLK_N<0>") )
......
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstpin.dat
View file @ daabf61c
FILE_TYPE=PINLIST;
{ Packager-XL run on 08-Jun-2016 AT 15:18:50 }
TIME=' COMPILATION ON 08-Jun-2016 AT 15:18:50';
{ Packager-XL run on 21-Jun-2016 AT 14:11:12 }
TIME=' COMPILATION ON 21-Jun-2016 AT 14:11:12';
primitive '1-HOLE_0-8-BASE';body '1-HOLE';
'A'<0>:'(1)';IN;
end_primitive;
......@@ -13,6 +13,10 @@ primitive 'CAPCERSMDCL2_0402-100NF,16V_GEN';body 'CAPCERSMDCL2';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'CAPCERSMDCL2_0402-10NF,16V_GEN';body 'CAPCERSMDCL2';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'CAPCERSMDCL2_0603-100NF,16V';body 'CAPCERSMDCL2';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
......
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstpin.dat,1
View file @ daabf61c
FILE_TYPE=PINLIST;
{ Packager-XL run on 03-Jun-2016 AT 10:45:06 }
TIME=' COMPILATION ON 03-Jun-2016 AT 10:45:06';
{ Packager-XL run on 08-Jun-2016 AT 14:50:07 }
TIME=' COMPILATION ON 08-Jun-2016 AT 14:50:07';
primitive '1-HOLE_0-8-BASE';body '1-HOLE';
'A'<0>:'(1)';IN;
end_primitive;
......@@ -91,6 +91,10 @@ primitive 'RSMD0603_1/10W-4.7K,1%';body 'RSMD0603';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'RSMD0603_1/10W-XX,1%';body 'RSMD0603';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'SI5345A-B-GM-GND=GND_SIGNAL,VDA';body 'SI5345';
'A0/CS':'(19)';IN;
'A1/SDO':'(17)';BIDI;
......
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstpin.dat,2
View file @ daabf61c
FILE_TYPE=PINLIST;
{ Packager-XL run on 03-Jun-2016 AT 13:35:26 }
TIME=' COMPILATION ON 03-Jun-2016 AT 13:35:26';
{ Packager-XL run on 08-Jun-2016 AT 15:18:50 }
TIME=' COMPILATION ON 08-Jun-2016 AT 15:18:50';
primitive '1-HOLE_0-8-BASE';body '1-HOLE';
'A'<0>:'(1)';IN;
end_primitive;
......
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstpin.dat,3
View file @ daabf61c
FILE_TYPE=PINLIST;
{ Packager-XL run on 08-Jun-2016 AT 14:50:07 }
TIME=' COMPILATION ON 08-Jun-2016 AT 14:50:07';
{ Packager-XL run on 21-Jun-2016 AT 13:51:31 }
TIME=' COMPILATION ON 21-Jun-2016 AT 13:51:31';
primitive '1-HOLE_0-8-BASE';body '1-HOLE';
'A'<0>:'(1)';IN;
end_primitive;
......
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstrprt.dat
View file @ daabf61c
......@@ -9,8 +9,9 @@ RES_ARRAY_X4_1206_TC164-47,1%
1-HOLE_0-8-BASE 4
BF-100.000MBE-T-GND=GND_SIGNALA BF-100.000MBE-T 1
CAPCERSMDCL2_0402-100NF,16V_GEN CC0402_100NF_16V_10%_X7R 9
CAPCERSMDCL2_0603-100NF,16V CC0603_100NF_16V_10%_X7R 9
CAPCERSMDCL2_0402-100NF,16V_GEN CC0402_100NF_16V_10%_X7R 10
CAPCERSMDCL2_0402-10NF,16V_GEN CC0402_10NF_16V_10%_X7R 6
CAPCERSMDCL2_0603-100NF,16V CC0603_100NF_16V_10%_X7R 13
CAPCERSMDCL2_0603-10UF,6.3V CC0603_10UF_6V3_20%_X5R 5
CAPCERSMDCL2_0805-22UF,6.3V CC0805_22UF_6V3_15%_X7R 2
CAPCERSMDCL2_1210-10UF,10V_GEN CC1210_10UF_25V_10%_X5R 1
......@@ -23,7 +24,7 @@ FERRITE_C0805-LI0805H121R-10,LA LI0805H121R-10 3
LP38692SD_WSON-1.8V,TEXAS INSTA LP38692SD-1.8 1
PLEMO2CI-EPG.00.302.NLN-GND=GNA EPG.00.302.NLN 1
RES_ARRAY_X4_1206_TC164-47,1% TC164-FR-##47RL 3
RSMD0603_1/10W-100,1% R0603_100R_1%_0.1W_100PPM 10
RSMD0603_1/10W-100,1% R0603_100R_1%_0.1W_100PPM 11
RSMD0603_1/10W-1K,1% R0603_1K_1%_0.1W_100PPM 12
RSMD0603_1/10W-4.7K,1% R0603_4K7_1%_0.1W_100PPM 1
RSMD0603_1/10W-XX,1% R0603_XX_1%_0.1W_100PPM 2
......@@ -31,4 +32,4 @@ SI5345A-B-GM-GND=GND_SIGNAL,VDA Si5345A-B-GM 1
SN65MLVD040RGZ-GND=GND_SIGNAL,A SN65MLVD040RGZ 1
USBLC6-2SC6 USBLC6-2SC6 1
Total 81
Total 93
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstrprt.dat,1
View file @ daabf61c
......@@ -9,9 +9,9 @@ RES_ARRAY_X4_1206_TC164-47,1%
1-HOLE_0-8-BASE 4
BF-100.000MBE-T-GND=GND_SIGNALA BF-100.000MBE-T 1
CAPCERSMDCL2_0402-100NF,16V_GEN CC0402_100NF_16V_10%_X7R 7
CAPCERSMDCL2_0402-100NF,16V_GEN CC0402_100NF_16V_10%_X7R 9
CAPCERSMDCL2_0603-100NF,16V CC0603_100NF_16V_10%_X7R 9
CAPCERSMDCL2_0603-10UF,6.3V CC0603_10UF_6V3_20%_X5R 4
CAPCERSMDCL2_0603-10UF,6.3V CC0603_10UF_6V3_20%_X5R 5
CAPCERSMDCL2_0805-22UF,6.3V CC0805_22UF_6V3_15%_X7R 2
CAPCERSMDCL2_1210-10UF,10V_GEN CC1210_10UF_25V_10%_X5R 1
CAPN4I-1UF,16V,X5R,GNM21 GNM214B11C105MA01D 2
......@@ -23,11 +23,12 @@ FERRITE_C0805-LI0805H121R-10,LA LI0805H121R-10 3
LP38692SD_WSON-1.8V,TEXAS INSTA LP38692SD-1.8 1
PLEMO2CI-EPG.00.302.NLN-GND=GNA EPG.00.302.NLN 1
RES_ARRAY_X4_1206_TC164-47,1% TC164-FR-##47RL 3
RSMD0603_1/10W-100,1% R0603_100R_1%_0.1W_100PPM 12
RSMD0603_1/10W-100,1% R0603_100R_1%_0.1W_100PPM 10
RSMD0603_1/10W-1K,1% R0603_1K_1%_0.1W_100PPM 12
RSMD0603_1/10W-4.7K,1% R0603_4K7_1%_0.1W_100PPM 1
RSMD0603_1/10W-XX,1% R0603_XX_1%_0.1W_100PPM 2
SI5345A-B-GM-GND=GND_SIGNAL,VDA Si5345A-B-GM 1
SN65MLVD040RGZ-GND=GND_SIGNAL,A SN65MLVD040RGZ 1
USBLC6-2SC6 USBLC6-2SC6 1
Total 78
Total 81
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstrprt.dat,2
View file @ daabf61c
- SPARES LIST -
CAPN4I-1UF,16V,X5R,GNM21
CN2 3, 4
CN2 2, 3, 4
RES_ARRAY_X4_1206_TC164-47,1%
RN3 3, 4
- PART SUMMARY -
......@@ -13,7 +15,7 @@ CAPCERSMDCL2_0603-10UF,6.3V CC0603_10UF_6V3_20%_X5R 5
CAPCERSMDCL2_0805-22UF,6.3V CC0805_22UF_6V3_15%_X7R 2
CAPCERSMDCL2_1210-10UF,10V_GEN CC1210_10UF_25V_10%_X5R 1
CAPN4I-1UF,16V,X5R,GNM21 GNM214B11C105MA01D 2
COMMON_MODE_LINE_FILTER_4312-7A 744231091 6
COMMON_MODE_LINE_FILTER_4312-7A 744231091 5
CON3P-SIL254D MTLW-103-07-L-S-250 1
DS92001TLD-GND=GND_SIGNAL,VCC=A DS92001TLD 1
DS92001TLD-GND=GND_SIGNAL,VCC=B DS92001TLD 5
......@@ -29,4 +31,4 @@ SI5345A-B-GM-GND=GND_SIGNAL,VDA Si5345A-B-GM 1
SN65MLVD040RGZ-GND=GND_SIGNAL,A SN65MLVD040RGZ 1
USBLC6-2SC6 USBLC6-2SC6 1
Total 82
Total 81
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstxnet.dat
View file @ daabf61c
FILE_TYPE = EXPANDEDNETLIST;
{ Packager-XL run on 08-Jun-2016 AT 15:18:50 CONSTRAINTS_VIEW_GENERATED}
{ Packager-XL run on 21-Jun-2016 AT 14:11:12 CONSTRAINTS_VIEW_GENERATED}
NET_NAME
'CLK_FROM_FPGA_N'
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):CLK_FROM_FPGA_N':
......@@ -30,6 +30,9 @@ NODE_NAME IC6 7
NODE_NAME IC8 15
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I1@CNINTERFACE.SI5345(CHIPS)':
'IN2*': CDS_PINID='\in2*\';
NODE_NAME R26 2
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I116@CNPASSIVE.RSMD0603(CHIPS)':
'B'<0>: CDS_PINID='B(0)';
NET_NAME
'CLK_FROM_HDMI_P'
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):CLK_FROM_HDMI_P':
......@@ -40,6 +43,9 @@ NODE_NAME IC6 6
NODE_NAME IC8 14
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I1@CNINTERFACE.SI5345(CHIPS)':
'IN2': CDS_PINID='IN2';
NODE_NAME R26 1
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I116@CNPASSIVE.RSMD0603(CHIPS)':
'A'<0>: CDS_PINID='A(0)';
NET_NAME
'CLK_FROM_LEMO_N'
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):CLK_FROM_LEMO_N':
......@@ -429,9 +435,6 @@ NODE_NAME CN1 2
NODE_NAME C2 1
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I160@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'A'<0>: CDS_PINID='A(0)';
NODE_NAME C6 1
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I161@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'A'<0>: CDS_PINID='A(0)';
NODE_NAME C5 1
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I162@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'A'<0>: CDS_PINID='A(0)';
......@@ -570,6 +573,42 @@ NODE_NAME R7 1
NODE_NAME R8 1
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I109@CNPASSIVE.RSMD0603(CHIPS)':
'A'<0>: CDS_PINID='A(0)';
NODE_NAME C37 1
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I117@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'A'<0>: CDS_PINID='A(0)';
NODE_NAME C36 1
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I118@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'A'<0>: CDS_PINID='A(0)';
NODE_NAME C6 1
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I237@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'A'<0>: CDS_PINID='A(0)';
NODE_NAME C30 1
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I238@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'A'<0>: CDS_PINID='A(0)';
NODE_NAME C29 1
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I239@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'A'<0>: CDS_PINID='A(0)';
NODE_NAME C28 1
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I240@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'A'<0>: CDS_PINID='A(0)';
NODE_NAME C27 1
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I241@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'A'<0>: CDS_PINID='A(0)';
NODE_NAME C35 1
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I244@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'A'<0>: CDS_PINID='A(0)';
NODE_NAME C34 1
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I245@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'A'<0>: CDS_PINID='A(0)';
NODE_NAME C33 1
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I246@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'A'<0>: CDS_PINID='A(0)';
NODE_NAME C32 1
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I247@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'A'<0>: CDS_PINID='A(0)';
NODE_NAME C31 1
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I248@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'A'<0>: CDS_PINID='A(0)';
NET_NAME
'INTR*'
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):INTR*':
......@@ -649,9 +688,6 @@ NODE_NAME IC3 30
NODE_NAME C2 2
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I160@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'B'<0>: CDS_PINID='B(0)';
NODE_NAME C6 2
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I161@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'B'<0>: CDS_PINID='B(0)';
NODE_NAME C5 2
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I162@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'B'<0>: CDS_PINID='B(0)';
......@@ -688,6 +724,42 @@ NODE_NAME L6 1
NODE_NAME C8 2
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I91@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'B'<0>: CDS_PINID='B(0)';
NODE_NAME C37 2
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I117@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'B'<0>: CDS_PINID='B(0)';
NODE_NAME C36 2
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I118@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'B'<0>: CDS_PINID='B(0)';
NODE_NAME C6 2
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I237@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'B'<0>: CDS_PINID='B(0)';
NODE_NAME C30 2
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I238@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'B'<0>: CDS_PINID='B(0)';
NODE_NAME C29 2
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I239@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'B'<0>: CDS_PINID='B(0)';
NODE_NAME C28 2
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I240@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'B'<0>: CDS_PINID='B(0)';
NODE_NAME C27 2
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I241@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'B'<0>: CDS_PINID='B(0)';
NODE_NAME C35 2
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I244@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'B'<0>: CDS_PINID='B(0)';
NODE_NAME C34 2
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I245@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'B'<0>: CDS_PINID='B(0)';
NODE_NAME C33 2
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I246@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'B'<0>: CDS_PINID='B(0)';
NODE_NAME C32 2
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I247@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'B'<0>: CDS_PINID='B(0)';
NODE_NAME C31 2
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1_I248@CNPASSIVE.CAPCERSMDCL2(CHIPS)':
'B'<0>: CDS_PINID='B(0)';
NET_NAME
'RST*'
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):RST*':
......
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstxnet.dat,3
View file @ daabf61c
FILE_TYPE = EXPANDEDNETLIST;
{ Packager-XL run on 08-Jun-2016 AT 14:50:07 CONSTRAINTS_VIEW_GENERATED}
{ Packager-XL run on 21-Jun-2016 AT 13:51:31 CONSTRAINTS_VIEW_GENERATED}
NET_NAME
'CLK_FROM_FPGA_N'
'@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):CLK_FROM_FPGA_N':
......
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstxprt.dat,3
View file @ daabf61c
FILE_TYPE=EXPANDEDPARTLIST;
{ Packager-XL run on 08-Jun-2016 AT 14:50:07 }
{ Packager-XL run on 21-Jun-2016 AT 13:51:31 }
DIRECTIVES
PST_VERSION='PST_HDL_CENTRIC_VERSION_0';
ROOT_DRAWING='FMC_TLU_CLOCK_GEN';
POST_TIME='08-Jun-2016 AT 14:50:07';
POST_TIME='21-Jun-2016 AT 13:51:31';
SOURCE_TOOL='PACKAGER_XL';
END_DIRECTIVES;
......
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstxref.dat,3
View file @ daabf61c
LOGICAL PART CROSS REFERENCE - 08-Jun-2016 AT 14:50:07
LOGICAL PART CROSS REFERENCE - 21-Jun-2016 AT 13:51:31
DRAWING: @FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE1
......@@ -499,7 +499,7 @@ RSMD0603_1/10W-XX,1% I109 R8
2 UNNAMED_3_CAPCERSMDCL2_I44_B B<0> @FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):UNNAMED_3_CAPCERSMDCL2_I44_B
END LOGICAL PART CROSS REFERENCE
GLOBAL SIGNAL CROSS REFERENCE - 08-Jun-2016 AT 14:50:07
GLOBAL SIGNAL CROSS REFERENCE - 21-Jun-2016 AT 13:51:31
CLK_FROM_FPGA_N @FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):CLK_FROM_FPGA_N
IC8 62 IN3/FB_IN* SI5345A-B-GM-GND=GND_SIGNAL,VDA I1 @FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3
R12 1 A<0> RSMD0603_1/10W-100,1% I28 @FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3
......@@ -996,7 +996,7 @@ XB @FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):XB
R9 1 A<0> RSMD0603_1/10W-100,1% I48 @FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3
END GLOBAL SIGNAL CROSS REFERENCE
GLOBAL PART CROSS REFERENCE - 08-Jun-2016 AT 14:50:07
GLOBAL PART CROSS REFERENCE - 21-Jun-2016 AT 13:51:31
C1 CAPCERSMDCL2_0603-100NF,16V
1 GND_SIGNAL @FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):GND_SIGNAL I4 @FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3
......
Cadence/worklib/fmc_tlu_clock_gen/packaged/pxl.chg,2
View file @ daabf61c
{ Packager-XL run on 03-Jun-2016 AT 13:35:26.00 }
{ Packager-XL run on 08-Jun-2016 AT 15:18:51.00 }
BINDING CHANGES LIST
......@@ -99,10 +99,6 @@ CHANGED BINDINGS:
@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I96@CNPASSIVE.CAPCERSMDCL2(CHIPS) CAPCERSMDCL2_0603-10UF,6.3V (0) IS ASSIGNED TO C26 SECTION 1
@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I97@CNPASSIVE.CAPCERSMDCL2(CHIPS) CAPCERSMDCL2_0402-100NF,16V_GEN (0) IS ASSIGNED TO C25 SECTION 1
@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I98@CNPASSIVE.CAPCERSMDCL2(CHIPS) CAPCERSMDCL2_0402-100NF,16V_GEN (0) IS ASSIGNED TO C23 SECTION 1
@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I100@CNPASSIVE.CAPN4I(CHIPS) CAPN4I-1UF,16V,X5R,GNM21 (0) IS ASSIGNED TO CN2 SECTION 2
@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I101@CNPASSIVE.RES_ARRAY_X4(CHIPS) RES_ARRAY_X4_1206_TC164-47,1% (0) IS ASSIGNED TO RN3 SECTION 4
@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I102@CNPASSIVE.RES_ARRAY_X4(CHIPS) RES_ARRAY_X4_1206_TC164-47,1% (0) IS ASSIGNED TO RN3 SECTION 3
@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I103@CNDISCRETE.COMMON_MODE_LINE_FILTER(CHIPS) COMMON_MODE_LINE_FILTER_4312-7A (0) IS ASSIGNED TO L9 SECTION 1
@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I108@CNPASSIVE.RSMD0603(CHIPS) RSMD0603_1/10W-XX,1% (0) IS ASSIGNED TO R7 SECTION 1
@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I109@CNPASSIVE.RSMD0603(CHIPS) RSMD0603_1/10W-XX,1% (0) IS ASSIGNED TO R8 SECTION 1
......@@ -208,10 +204,6 @@ LOGICAL PARTS ADDED TO DESIGN:
@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I96@CNPASSIVE.CAPCERSMDCL2(CHIPS) CAPCERSMDCL2_0603-10UF,6.3V (0)
@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I97@CNPASSIVE.CAPCERSMDCL2(CHIPS) CAPCERSMDCL2_0402-100NF,16V_GEN (0)
@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I98@CNPASSIVE.CAPCERSMDCL2(CHIPS) CAPCERSMDCL2_0402-100NF,16V_GEN (0)
@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I100@CNPASSIVE.CAPN4I(CHIPS) CAPN4I-1UF,16V,X5R,GNM21 (0)
@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I101@CNPASSIVE.RES_ARRAY_X4(CHIPS) RES_ARRAY_X4_1206_TC164-47,1% (0)
@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I102@CNPASSIVE.RES_ARRAY_X4(CHIPS) RES_ARRAY_X4_1206_TC164-47,1% (0)
@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I103@CNDISCRETE.COMMON_MODE_LINE_FILTER(CHIPS) COMMON_MODE_LINE_FILTER_4312-7A (0)
@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I108@CNPASSIVE.RSMD0603(CHIPS) RSMD0603_1/10W-XX,1% (0)
@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):PAGE3_I109@CNPASSIVE.RSMD0603(CHIPS) RSMD0603_1/10W-XX,1% (0)
......@@ -244,7 +236,6 @@ C26 CAPCERSMDCL2_0603-10UF,6.3V
C25 CAPCERSMDCL2_0402-100NF,16V_GEN
C24 CAPCERSMDCL2_0603-10UF,6.3V
R10 RSMD0603_1/10W-100,1%
L9 COMMON_MODE_LINE_FILTER_4312-7A
CN2 CAPN4I-1UF,16V,X5R,GNM21
R9 RSMD0603_1/10W-100,1%
C23 CAPCERSMDCL2_0402-100NF,16V_GEN
......@@ -318,18 +309,6 @@ LOGICAL NET DELETIONS:
LOGICAL NET ADDITIONS:
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):CLK_FROM_FPGA(0)' 'CLK_FROM_FPGA<0>' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):CLK_FROM_FPGA(1)' 'CLK_FROM_FPGA<1>' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):CLK_FROM_FPGA(2)' 'CLK_FROM_FPGA<2>' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):CLK_FROM_FPGA(3)' 'CLK_FROM_FPGA<3>' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):CLK_TO_FPGA(0)' 'CLK_TO_FPGA<0>' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):CLK_TO_FPGA(1)' 'CLK_TO_FPGA<1>' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):CLK_TO_FPGA(2)' 'CLK_TO_FPGA<2>' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):CLK_TO_FPGA(3)' 'CLK_TO_FPGA<3>' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):ENABLE_CLK_FROM_FPGA(0)' 'ENABLE_CLK_FROM_FPGA<0>' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):ENABLE_CLK_FROM_FPGA(1)' 'ENABLE_CLK_FROM_FPGA<1>' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):ENABLE_CLK_FROM_FPGA(2)' 'ENABLE_CLK_FROM_FPGA<2>' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):ENABLE_CLK_FROM_FPGA(3)' 'ENABLE_CLK_FROM_FPGA<3>' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):ENABLE_CLK_TO_DUT(0)' 'ENABLE_CLK_TO_DUT<0>' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):ENABLE_CLK_TO_DUT(1)' 'ENABLE_CLK_TO_DUT<1>' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):ENABLE_CLK_TO_DUT(2)' 'ENABLE_CLK_TO_DUT<2>' {ADDED}
......@@ -387,10 +366,20 @@ NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):CLK_IO_1_N' 'CLK_IO_1_N' {ADD
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):CLK_IO_1_P' 'CLK_IO_1_P' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):CLK_IO_2' 'CLK_IO_2' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):VDD_CLK40' 'VDD_CLK40' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):HDMI_CLK_N' 'HDMI_CLK_N' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):HDMI_CLK_P' 'HDMI_CLK_P' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):LEMO_CLK_N' 'LEMO_CLK_N' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):LEMO_CLK_P' 'LEMO_CLK_P' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):DUT_CLK_FROM_FPGA(0)' 'DUT_CLK_FROM_FPGA<0>' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):DUT_CLK_FROM_FPGA(1)' 'DUT_CLK_FROM_FPGA<1>' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):DUT_CLK_FROM_FPGA(2)' 'DUT_CLK_FROM_FPGA<2>' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):DUT_CLK_FROM_FPGA(3)' 'DUT_CLK_FROM_FPGA<3>' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):DUT_CLK_TO_FPGA(0)' 'DUT_CLK_TO_FPGA<0>' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):DUT_CLK_TO_FPGA(1)' 'DUT_CLK_TO_FPGA<1>' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):DUT_CLK_TO_FPGA(2)' 'DUT_CLK_TO_FPGA<2>' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):DUT_CLK_TO_FPGA(3)' 'DUT_CLK_TO_FPGA<3>' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):ENABLE_DUT_CLK_FROM_FPGA(0)' 'ENABLE_DUT_CLK_FROM_FPGA<0>' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):ENABLE_DUT_CLK_FROM_FPGA(1)' 'ENABLE_DUT_CLK_FROM_FPGA<1>' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):ENABLE_DUT_CLK_FROM_FPGA(2)' 'ENABLE_DUT_CLK_FROM_FPGA<2>' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):ENABLE_DUT_CLK_FROM_FPGA(3)' 'ENABLE_DUT_CLK_FROM_FPGA<3>' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):P3V3' 'P3V3' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):GND_SIGNAL' 'GND_SIGNAL' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):UNNAMED_3_CAPN4I_I11_A' 'UNNAMED_3_CAPN4I_I11_A' {ADDED}
......@@ -414,6 +403,5 @@ NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):UNNAMED_3_RSMD0603_I87_A' 'UN
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):UNNAMED_3_RSMD0603_I87_B' 'UNNAMED_3_RSMD0603_I87_B' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):UNNAMED_3_1-HOLE_I94_A' 'UNNAMED_3_1-HOLE_I94_A' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):UNNAMED_3_1-HOLE_I95_A' 'UNNAMED_3_1-HOLE_I95_A' {ADDED}
NET_NAME '@FMC_TLU_V1_LIB.FMC_TLU_CLOCK_GEN(SCH_1):UNNAMED_3_CAPN4I_I100_A' 'UNNAMED_3_CAPN4I_I100_A' {ADDED}
END NET CHANGES LIST
Cadence/worklib/fmc_tlu_clock_gen/packaged/pxl.state,3
View file @ daabf61c
FILE_TYPE = PXL_HDL_CENTRIC_STATE_FILE;
VERSION = PXL_HDL_CENTRIC_VERSION_1;
TIME = '08-Jun-2016 AT 14:50:07.00';
TIME = '21-Jun-2016 AT 13:51:32.00';
{--------------------------------------------------------------------------}
......
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