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AIDA FMC Mini-TLU
Firmware for FMC-based mini-TLU (Trigger/Timing/Tagging Logic Unit) for AIDA
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Processes | |
ipbus_write | ( ipbus_clk_i ) |
p_reset | ( s_clk160_internal ) |
generate_4x_strobe | ( s_clk160 , s_clk40_out ) |
Signals | |
s_clk40 | std_logic |
s_clk40_internal | std_logic |
s_clk160 | std_logic |
s_clk160_internal | std_logic |
s_clk640 | std_logic |
s_clk640_internal | std_logic |
s_clk40_out | std_logic |
s_clk40_copy | std_logic |
s_extclk_is_input | std_logic := ' 1 ' |
s_extclk_is_input_buf | std_logic |
s_clk_is_xtal | std_logic := ' 1 ' |
s_locked_pll | std_logic |
s_locked_bufpll | std_logic |
s_extclk | std_logic |
s_clk | std_logic |
s_clk_d1 | std_logic |
s_strobe_4x_p1 | std_logic |
s_strobe_4x_logic | std_logic |
s_clkfbout_buf | std_logic |
s_clkfbout | std_logic |
s_strobe_generator | std_logic_vector ( 3 downto 0 ) := " 1000 " |
s_logic_clk_generator | std_logic_vector ( 3 downto 0 ) := " 1100 " |
Stores state of 40MHz "clock". | |
s_strobe_fb | std_logic := ' 0 ' |
s_logic_reset_ipb | std_logic := ' 0 ' |
s_logic_reset | std_logic := ' 0 ' |
s_logic_reset_d1 | std_logic := ' 0 ' |
s_logic_reset_d2 | std_logic := ' 0 ' |
s_logic_reset_d3 | std_logic := ' 0 ' |
s_ipbus_ack | std_logic := ' 0 ' |
Instantiations | |
clock_mux | bufgmux |
For now just connect input of PLL to clock from Xtal... | |
ext_clk_io | ibufgds |
Buffer external clock. | |
pll_base_inst | pll_base |
Clocking primitive. | |
bufpll_inst | bufpll |
clkf_buf | bufio2fb |
clk160_o_buf | bufg |
clk40_o_buf | bufg |
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Instantiation |
Clocking primitive.
Instantiation of the PLL primitive