|
rtl | architecture |
| goes low during calibration sequence. More...
|
|
|
serdes_reset_i | in |
| Starts recalibration sequence and resets the ISERDES.
|
data_i | in |
fastClk_i | in |
| 4x fabric clock. e.g. 640MHz
|
fabricClk_i | in |
| clock for output to FPGA. e.g. 160MHz
|
strobe_i | in |
| Strobes once every 4 cycles of fastClk.
|
data_o | out ( 7 downto 0 ) |
| --! Deserialized data. Interleaved between prompt and delayed serdes.
|
serdes_ready_o | out |
data_o(0) is the oldest data
The documentation for this class was generated from the following file: