#
# UCF for version 1a of updated mini-TLU
#

NET "sysclk_p_i" TNM_NET = "tnm_sysclk";
NET "sysclk_p_i" LOC = K15;
NET "sysclk_p_i" IOSTANDARD = LVDS_25;
NET "sysclk_p_i" DIFF_TERM = "TRUE";
NET "sysclk_n_i" LOC = K16;
NET "sysclk_n_i" IOSTANDARD = LVDS_25;
NET "sysclk_n_i" DIFF_TERM = "TRUE";

TIMESPEC TS_sysclk = PERIOD "tnm_sysclk" 200 MHz;

# remove for now
#NET Reset_i LOC=P4; ## Global Reset

#NET ipb_clk TNM_NET = tnm_ipb_clk;
#NET clk125  TNM_NET = tnm_clk125;
#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;

# NET clocks/rst* TIG;
NET "I6/s_clk_is_xtal" TIG;

NET "leds_o[0]" LOC = E13;
NET "leds_o[0]" IOSTANDARD = LVCMOS25;
NET "leds_o[1]" LOC = C14;
NET "leds_o[1]" IOSTANDARD = LVCMOS25;
NET "leds_o[2]" LOC = C4;
NET "leds_o[2]" IOSTANDARD = LVCMOS25;
NET "leds_o[3]" LOC = A4;
NET "leds_o[3]" IOSTANDARD = LVCMOS25;

NET "dip_switch_i[0]" LOC = D14;
NET "dip_switch_i[1]" LOC = E12;
NET "dip_switch_i[2]" LOC = F12;
NET "dip_switch_i[3]" LOC = V13;

# Ethernet PHY

TIMEGRP TG_gmii_tx =   PADS("gmii_tx*");
TIMEGRP "TG_gmii_tx" OFFSET = OUT  AFTER "sysclk_p_i" REFERENCE_PIN "gmii_gtx_clk_o" RISING;

NET "gmii_gtx_clk_o" LOC = A9;
NET "gmii_gtx_clk_o" IOSTANDARD = LVCMOS25;
NET "gmii_gtx_clk_o" SLEW = FAST;
NET "gmii_txd_o[0]" LOC = F8;
NET "gmii_txd_o[0]" IOSTANDARD = LVCMOS25;
NET "gmii_txd_o[1]" LOC = G8;
NET "gmii_txd_o[1]" IOSTANDARD = LVCMOS25;
NET "gmii_txd_o[2]" LOC = A6;
NET "gmii_txd_o[2]" IOSTANDARD = LVCMOS25;
NET "gmii_txd_o[3]" LOC = B6;
NET "gmii_txd_o[3]" IOSTANDARD = LVCMOS25;
NET "gmii_txd_o[4]" LOC = E6;
NET "gmii_txd_o[4]" IOSTANDARD = LVCMOS25;
NET "gmii_txd_o[5]" LOC = F7;
NET "gmii_txd_o[5]" IOSTANDARD = LVCMOS25;
NET "gmii_txd_o[6]" LOC = A5;
NET "gmii_txd_o[6]" IOSTANDARD = LVCMOS25;
NET "gmii_txd_o[7]" LOC = C5;
NET "gmii_txd_o[7]" IOSTANDARD = LVCMOS25;
NET "gmii_tx_en_o" LOC = B8;
NET "gmii_tx_en_o" IOSTANDARD = LVCMOS25;
NET "gmii_tx_er_o" LOC = A8;
NET "gmii_tx_er_o" IOSTANDARD = LVCMOS25;

NET "gmii_rx_clk_i" TNM_NET = "gmii_rx_clk_i";
NET "gmii_rx_clk_i" LOC = L16;
NET "gmii_rx_clk_i" IOSTANDARD = LVCMOS25;
TIMESPEC TS_GMII_RX_CLK_I = PERIOD "gmii_rx_clk_i" 125 MHz;
OFFSET = IN 2 ns VALID 3 ns BEFORE "gmii_rx_clk_i";
NET "gmii_rxd_i[0]" LOC = M14;
NET "gmii_rxd_i[0]" IOSTANDARD = LVCMOS25;
NET "gmii_rxd_i[1]" LOC = U18;
NET "gmii_rxd_i[1]" IOSTANDARD = LVCMOS25;
NET "gmii_rxd_i[2]" LOC = U17;
NET "gmii_rxd_i[2]" IOSTANDARD = LVCMOS25;
NET "gmii_rxd_i[3]" LOC = T18;
NET "gmii_rxd_i[3]" IOSTANDARD = LVCMOS25;
NET "gmii_rxd_i[4]" LOC = T17;
NET "gmii_rxd_i[4]" IOSTANDARD = LVCMOS25;
NET "gmii_rxd_i[5]" LOC = N16;
NET "gmii_rxd_i[5]" IOSTANDARD = LVCMOS25;
NET "gmii_rxd_i[6]" LOC = N15;
NET "gmii_rxd_i[6]" IOSTANDARD = LVCMOS25;
NET "gmii_rxd_i[7]" LOC = P18;
NET "gmii_rxd_i[7]" IOSTANDARD = LVCMOS25;
NET "gmii_rx_dv_i" LOC = N18;
NET "gmii_rx_dv_i" IOSTANDARD = LVCMOS25;
NET "gmii_rx_er_i" LOC = P17;
NET "gmii_rx_er_i" IOSTANDARD = LVCMOS25;

NET "phy_rstb_o" LOC = L13;
NET "phy_rstb_o" IOSTANDARD = LVCMOS25;

# Main I2C bus
##  C30 on FMC
NET "i2c_scl_b" LOC = P11;
##  C31 on FMC
NET "i2c_sda_b" LOC = N10;

#
# I/O to devices under test

#NET "BUSY_N_I<0>"  LOC = "P7"; ##  "FMC_LA19_N"  ,  H23  on FMC
#NET "BUSY_N_I<1>"  LOC = "A2"; ##  "FMC_LA14_N"  ,  C19  on FMC
#NET "BUSY_N_I<2>"  LOC = "C6"; ##  "FMC_LA12_N"  ,  G16  on FMC
##  "FMC_LA19_P"  ,  H22  on FMC
#NET "busy_p_i[0]" LOC = N6;
##  "FMC_LA14_P"  ,  C18  on FMC
#NET "busy_p_i[1]" LOC = B2;
##  "FMC_LA12_P"  ,  G15  on FMC
#NET "busy_p_i[2]" LOC = D6;

#NET "TRIGGERS_N_O<0>"  LOC = "P8"; ##  "FMC_LA20_N"  ,  G22  on FMC
#NET "TRIGGERS_N_O<1>"  LOC = "A13"; ##  "FMC_LA03_N"  ,  G10  on FMC
#NET "TRIGGERS_N_O<2>"  LOC = "A7"; ##  "FMC_LA16_N"  ,  G19  on FMC
##  "FMC_LA20_P"  ,  G21  on FMC
#NET "triggers_p_o[0]" LOC = N7;
##  "FMC_LA03_P"  ,  G9  on FMC
#NET "triggers_p_o[1]" LOC = C13;
##  "FMC_LA16_P"  ,  G18  on FMC
#NET "triggers_p_o[2]" LOC = C7;

# Remove shutters ( also known as SPARE ) for now
#NET "SPARE_N_O<1>"  LOC = "E11"; ##  "FMC_LA08_N"  ,  G13  on FMC
#NET "SPARE_N_O<2>"  LOC = "A12"; ##  "FMC_LA11_N"  ,  H17  on FMC
#NET "SPARE_P_O<1>"  LOC = "F11"; ##  "FMC_LA08_P"  ,  G12  on FMC
#NET "SPARE_P_O<2>"  LOC = "B12"; ##  "FMC_LA11_P"  ,  H16  on FMC

# Labelled DUT_CLK on schematic for RJ45, CLK on HDMI
#NET "DUT_CLK_N_I<0>"  LOC = "V4"; ##  "FMC_LA21_N"  ,  H26  on FMC
#NET "DUT_CLK_N_I<1>"  LOC = "T11"; ##  "FMC_LA27_N"  ,  C27  on FMC
#NET "DUT_CLK_N_I<2>"  LOC = "A15"; ##  "FMC_LA02_N"  ,  H8  on FMC
##  "FMC_LA27_P"  ,  C26  on FMC
##  "FMC_LA02_P"  ,  H7  on FMC
##  "FMC_LA21_P"  ,  H25  on FMC

# Labelled CONT on schematic.
#NET "RESET_OR_CLK_N_O<0>"  LOC = "T7"; ##  "FMC_LA22_N"  ,  G25  on FMC
#NET "RESET_OR_CLK_N_O<1>"  LOC = "T10"; ##  "FMC_LA18_CC_N"  ,  C23  on FMC
#NET "RESET_OR_CLK_N_O<2>"  LOC = "E8"; ##  "FMC_LA07_N"  ,  H14  on FMC
##  "FMC_LA22_P"  ,  G24  on FMC
#NET "reset_or_clk_p_o[0]" LOC = R7;
##  "FMC_LA18_CC_P"  ,  C22  on FMC
#NET "reset_or_clk_p_o[1]" LOC = R10;
##  "FMC_LA07_P"  ,  H13  on FMC
#NET "reset_or_clk_p_o[2]" LOC = E7;

# Trigger Inputs

# Constant-fraction-discrimiator comparator outputs
##  "FMC_LA32_N"  ,  H38  on FMC
NET "cfd_discr_n_i[0]" LOC = V15;
##  "FMC_LA30_N"  ,  H35  on FMC
NET "cfd_discr_n_i[1]" LOC = V12;
##  "FMC_LA28_N"  ,  H32  on FMC
NET "cfd_discr_n_i[2]" LOC = V11;
##  "FMC_LA24_N"  ,  H29  on FMC
NET "cfd_discr_n_i[3]" LOC = V8;
##  "FMC_LA32_P"  ,  H37  on FMC
NET "cfd_discr_p_i[0]" LOC = U15;
##  "FMC_LA30_P"  ,  H34  on FMC
NET "cfd_discr_p_i[1]" LOC = T12;
##  "FMC_LA28_P"  ,  H31  on FMC
NET "cfd_discr_p_i[2]" LOC = U11;
##  "FMC_LA24_P"  ,  H28  on FMC
NET "cfd_discr_p_i[3]" LOC = U8;

# Threshold comparator outputs
##  "FMC_LA33_N"  ,  G37  on FMC
NET "threshold_discr_n_i[0]" LOC = N9;
##  "FMC_LA31_N"  ,  G34  on FMC
NET "threshold_discr_n_i[1]" LOC = V6;
##  "FMC_LA29_N"  ,  G31  on FMC
NET "threshold_discr_n_i[2]" LOC = N8;
##  "FMC_LA25_N"  ,  G28  on FMC
NET "threshold_discr_n_i[3]" LOC = N11;
##  "FMC_LA33_P"  ,  G36  on FMC
NET "threshold_discr_p_i[0]" LOC = M10;
##  "FMC_LA31_P"  ,  G33  on FMC
NET "threshold_discr_p_i[1]" LOC = T6;
##  "FMC_LA29_P"  ,  G30  on FMC
NET "threshold_discr_p_i[2]" LOC = M8;
##  "FMC_LA25_P"  ,  G27  on FMC
NET "threshold_discr_p_i[3]" LOC = M11;

############
# External clock pins
## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"	
NET "extclk_p_b" LOC = C10;
## "FMC_CLK0_M2C_N" , H5 on FMC ,  "FRONT_PANEL_CLK_N"
NET "extclk_n_b" LOC = A10;


#NET "HDMI_POWER_ENABLE1"  LOC = "B16"; ##  "FMC_LA04_P"  ,  H10  on FMC
#NET "HDMI_POWER_ENABLE2"  LOC = "F9"; ##  "FMC_LA15_N"  ,  H20  on FMC

# GPIO pins for debugging.
## 1 on J13 (thru series R100 200 ohm)
#NET "gpio_hdr[0]" LOC = N17;
## 3 on J13 (thru series R102 200 ohm)
#NET "gpio_hdr[1]" LOC = M18;
## 5 on J13 (thru series R101 200 ohm)
#NET "gpio_hdr[2]" LOC = A3;
## 7 on J13 (thru series R103 200 ohm)
#NET "gpio_hdr[3]" LOC = L15;
## 2 on J13 (thru series R99 200 ohm)
#NET "gpio_hdr[4]" LOC = F15;
## 4 on J13 (thru series R98 200 ohm)
#NET "gpio_hdr[5]" LOC = B4;
## 6 on J13 (thru series R97 200 ohm)
#NET "gpio_hdr[6]" LOC = F13;
## 8 on J13 (thru series R96 20
#NET "gpio_hdr[7]" LOC = P12;


#NET "busy_p_i[2]" PULLDOWN;
#NET "busy_p_i[1]" PULLDOWN;
#NET "busy_p_i[0]" PULLDOWN;

# PlanAhead Generated miscellaneous constraints 

NET "I4/ipbus/udp_if/clock_crossing_if/enable_buf[1]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/rarp_buf[1]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/we_buf[1]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/rst_ipb_buf[1]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/rst_ipb_buf[0]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/we_buf[0]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/pkt_done_read_buf[2]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/pkt_done_read_buf[1]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/pkt_done_write_buf[2]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/pkt_done_write_buf[1]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/rarp_buf[0]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/enable_buf[0]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/req_send_buf[2]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/req_send_buf[1]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/req_send_buf[0]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/busy_up_buf[2]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/busy_up_buf[1]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/busy_down_buf[2]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/busy_down_buf[1]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/pkt_done_write_buf[0]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/pkt_done_read_buf[0]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/busy_up_buf[0]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/busy_down_buf[0]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/rx_read_buf_buf[1]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/rx_read_buf_buf[0]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/tx_write_buf_buf[1]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/tx_write_buf_buf[0]" KEEP = "TRUE";

# PlanAhead Generated physical constraints 

NET "output_0_p[0]" LOC = N7;
NET "output_0_p[1]" LOC = C13;
NET "output_0_p[2]" LOC = C7;
NET "output_0_n[0]" LOC = P8;
NET "output_0_n[1]" LOC = A13;
NET "output_0_n[2]" LOC = A7;
NET "output_1_p[0]" LOC = R11;
NET "output_1_p[1]" LOC = C15;
NET "output_1_p[2]" LOC = T4;
NET "output_1_n[0]" LOC = T11;
NET "output_1_n[1]" LOC = A15;
NET "output_1_n[2]" LOC = V4;
NET "output_2_p[0]" LOC = R7;
NET "output_2_p[1]" LOC = R10;
NET "output_2_p[2]" LOC = E7;
NET "output_2_n[0]" LOC = T7;
NET "output_2_n[1]" LOC = T10;
NET "output_2_n[2]" LOC = E8;
NET "output_3_p[0]" LOC = N6;
NET "output_3_p[1]" LOC = B2;
NET "output_3_p[2]" LOC = D6;
NET "output_3_n[0]" LOC = P7;
NET "output_3_n[1]" LOC = A2;
NET "output_3_n[2]" LOC = C6;
