pax_global_header 0000666 0000000 0000000 00000000064 12415504633 0014515 g ustar 00root root 0000000 0000000 52 comment=12238f2d6a24476e38039e702c1e1f844aa0f95d
fmc-mtlu-copy_ADosil_branch_r156/ 0000775 0000000 0000000 00000000000 12415504633 0017102 5 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/ 0000775 0000000 0000000 00000000000 12415504633 0020716 5 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/Introduction.markdown 0000664 0000000 0000000 00000003274 12415504633 0025151 0 ustar 00root root 0000000 0000000 Introduction to AIDA FMC Mini-TLU {#mainpage}
=================================
The TLU provides different parts of a Particle Physics Beam-Test
system with the information they need to synchronize data taken with
different detectors. The detectors are also refered to as Devices
Under Test (DUT).
Functions of TLU
----------------
- Trigger.
The TLU can combine signals from detectors in the beam-line ( often
scintillation detectors ) to produce a trigger that is sent to the
different DUT. Each DUT can indicate to the TLU that it is busy and
unable to take any further data.
- Particle Timestamping
The arrival time of every pulse from the beam-detectors is recorded.
- Clock and Synchronization Signals.
The TLU produces clock and synchronization signals that allow the
internal counters of different DUT to be sychronized.
N.B. Not all the functions of the TLU may be used in a given beam-test
system. For example, it is common to only use the Trigger/Busy
function of the TLU.
Firmare Structure
-----------------
The firmware is almost exclusively written in VHDL. The top level
entitity is [top_extphy](top_extphy_struct)
The HDL-Designer package by Mentor graphics has been used to develop
some of the code, mainly the top-level structure. However, is is not
necessary to use HDL-Designer to build the firmware. In fact the VHDL
files produced by HDL-Designer can also be edited "by hand" without
using the tool.
A block diagram, generated by HDL-Designer, is [here](http://www.ohwr.org/attachments/2710/hdl_designer_test_print_2.pdf)
Building Firmware
-----------------
Instructions on building the firmware are found
[here](http://www.ohwr.org/projects/fmc-mtlu/wiki/FirmwareBuild).
fmc-mtlu-copy_ADosil_branch_r156/firmware/config/ 0000775 0000000 0000000 00000000000 12415504633 0022163 5 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/config/ise14/ 0000775 0000000 0000000 00000000000 12415504633 0023110 5 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/config/ise14/sp601/ 0000775 0000000 0000000 00000000000 12415504633 0023761 5 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/config/ise14/sp601/build_bitstream.tcl 0000664 0000000 0000000 00000001154 12415504633 0027637 0 ustar 00root root 0000000 0000000 project open fmc-mtlu
puts "Regenerating cores"
cd $::env(FW_WORKSPACE)/workspace/ipcore_dir
catch {exec coregen -r -b tri_mode_eth_mac_v5_4.xco -p coregen.cgp}
catch {exec coregen -r -b mac_fifo_axi4.xco -p coregen.cgp}
catch {exec coregen -r -b tlu_event_fifo.xco -p coregen.cgp}
catch {exec coregen -r -b FIFO.xco -p coregen.cgp}
# catch {exec coregen -r -b CounterUp.xco -p coregen.cgp}
catch {exec coregen -r -b internalTriggerGenerator.xco -p coregen.cgp}
process run "Synthesize"
process run "Translate"
process run "Map"
process run "Place & Route"
process run "Generate Programming File"
project close
fmc-mtlu-copy_ADosil_branch_r156/firmware/config/ise14/sp601/coregen.cgp 0000664 0000000 0000000 00000000342 12415504633 0026075 0 ustar 00root root 0000000 0000000 SET busformat = BusFormatAngleBracketNotRipped
SET designentry = VHDL
SET device = xc6slx16
SET devicefamily = spartan6
SET flowvendor = Other
SET package = csg324
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
fmc-mtlu-copy_ADosil_branch_r156/firmware/config/ise14/sp601/file_list 0000664 0000000 0000000 00000000251 12415504633 0025654 0 ustar 00root root 0000000 0000000 hdl ipbus/firmware/example_designs/hdl/clocks_s6_extphy.vhd
include ipbus/firmware/ethernet/cfg/file_list_s6_extphy
include ipbus/firmware/ipbus_core/cfg/file_list
fmc-mtlu-copy_ADosil_branch_r156/firmware/config/ise14/sp601/setup_project.tcl 0000664 0000000 0000000 00000015566 12415504633 0027370 0 ustar 00root root 0000000 0000000 project new fmc-mtlu
project set family spartan6
project set device xc6slx16
project set package csg324
project set speed -3
project set "Enable Multi-Threading" "2" -process "Map"
project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" -process "Map"
project set "Enable Multi-Threading" "2" -process "Place & Route"
project set "Enable BitStream Compression" TRUE -process "Generate Programming File"
project set "Preferred Language" "VHDL"
# source $::env(REPOS_FW_DIR)/firmware/example_designs/scripts/addfiles.tcl
# Just list files by hand for now. Can't get addfiles.tcl to work.
#xfile add ipbus/firmware/example_designs/hdl/clocks_s6_extphy.vhd
# IPBus Ethernet for gig_eth_pcs_pma_v11_5
xfile add ipbus/firmware/ethernet/hdl/eth_s6_gmii.vhd
xfile add ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
puts "Adding and Regenerating Ethernet cores"
# Add cores for Ethernet
exec cp ipbus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4.xco ipcore_dir
exec cp ipbus/firmware/ethernet/coregen/mac_fifo_axi4.xco ipcore_dir
xfile add ipcore_dir/tri_mode_eth_mac_v5_4.xco
xfile add ipcore_dir/mac_fifo_axi4.xco
# Don't regenerate cores for now...
#cd ipcore_dir
#catch {exec coregen -r -b tri_mode_eth_mac_v5_4.xco -p coregen.cgp}
#catch {exec coregen -r -b mac_fifo_axi4.xco -p coregen.cgp}
#cd ..
puts "Adding IPBus files"
# Xilinx ISE setup fragment for ipbus core
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_package.vhd
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_trans_decl.vhd
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_ctrl.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_if_flat.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_buffer_selector.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_arp.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_payload.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_ping.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_resend.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_status.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_byte_sum.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_clock_crossing_if.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_do_rx_reset.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_dualportram.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_dualportram_rx.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_dualportram_tx.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_ipaddr_block.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_packet_parser.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rarp_block.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rxram_mux.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rxram_shim.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rxtransactor_if_simple.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_status_buffer.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_tx_mux.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_txtransactor_if_simple.vhd
xfile add ipbus/firmware/ipbus_core/hdl/trans_arb.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor_if.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor_sm.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor_cfg.vhd
xfile add ipbus/firmware/ipbus_core/hdl/stretcher.vhd
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_fabric.vhd
xfile add ipbus/firmware/example_designs/hdl/clock_div.vhd
xfile add ipbus/firmware/slaves/hdl/ipbus_reg_types.vhd
xfile add ipbus/firmware/slaves/hdl/ipbus_reg_v.vhd
#xfile add ipbus/firmware/slaves/hdl/syncreg_r.vhd
#xfile add ipbus/firmware/slaves/hdl/syncreg_w.vhd
#xfile add ipbus/firmware/slaves/hdl/ipbus_syncreg_v.vhd
xfile add ipbus/firmware/slaves/hdl/ipbus_ctrlreg_v.vhd
# Add Opencores files for i2c interface
xfile add external/opencores_i2c/i2c_master_bit_ctrl.vhd
xfile add external/opencores_i2c/i2c_master_byte_ctrl.vhd
xfile add external/opencores_i2c/i2c_master_registers.vhd
xfile add external/opencores_i2c/i2c_master_top.vhd
# Add TLU cores....
# Add cores for Ethernet
puts "Adding and Regenerating TLU cores"
exec cp fmc-mtlu/firmware/ise/ipcore_dir/tlu_event_fifo.xco ipcore_dir
exec cp fmc-mtlu/firmware/ise/ipcore_dir/FIFO.xco ipcore_dir
exec cp fmc-mtlu/firmware/ise/ipcore_dir/CounterUp.xco ipcore_dir
exec cp fmc-mtlu/firmware/ise/ipcore_dir/internalTriggerGenerator.xco ipcore_dir
xfile add ipcore_dir/tlu_event_fifo.xco
xfile add ipcore_dir/FIFO.xco
# xfile add ipcore_dir/CounterUp.xco
xfile add ipcore_dir/internalTriggerGenerator.xco
# Don't regenerate cores for now...
#cd ipcore_dir
#catch {exec coregen -r -b tlu_event_fifo.xco -p coregen.cgp}
#catch {exec coregen -r -b FIFO.xco -p coregen.cgp}
#catch {exec coregen -r -b CounterUp.xco -p coregen.cgp}
#catch {exec coregen -r -b internalTriggerGenerator.xco -p coregen.cgp}
#cd ..
puts "Adding TLU Files "
# Add FMC-MTLU files. First the hand-written VHDL
xfile add fmc-mtlu/firmware/hdl/common/dualSERDES_1to4_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/i2c_master_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/ipbus_addr_decode.vhd
xfile add fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/ipbus_ver.vhd
xfile add fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd
#xfile add fmc-mtlu/firmware/hdl/common/pulseClockDomainCrossing_rtl.vhd
#xfile add fmc-mtlu/firmware/hdl/common/Reg_2clks.vhd
xfile add fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd
# xfile add fmc-mtlu/firmware/hdl/common/serdes_1_to_n_SDR.vhd
xfile add fmc-mtlu/firmware/hdl/common/serdesCalibrateFSM_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd
xfile add fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
xfile add fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/handshakes_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/TPx3Logic_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/GPP_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/counterDown.vhd
# Then add the HDL-Designer generated files..
xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg_body.vhd
xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd
# Add user constraints file
# UCF for TLU with FMC connector wrong way round.
#xfile add fmc-mtlu/firmware/ucf/sp601_FMC_mTLU.ucf
# bug-fixed TLU:
xfile add fmc-mtlu/firmware/ucf/sp601_FMC_mTLU_v1a.ucf
project close
puts "Successfully finished building project file"
fmc-mtlu-copy_ADosil_branch_r156/firmware/config/ise14/sp605/ 0000775 0000000 0000000 00000000000 12415504633 0023765 5 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/config/ise14/sp605/build_bitstream.tcl 0000664 0000000 0000000 00000001154 12415504633 0027643 0 ustar 00root root 0000000 0000000 project open fmc-mtlu
puts "Regenerating cores"
cd $::env(FW_WORKSPACE)/workspace/ipcore_dir
catch {exec coregen -r -b tri_mode_eth_mac_v5_4.xco -p coregen.cgp}
catch {exec coregen -r -b mac_fifo_axi4.xco -p coregen.cgp}
catch {exec coregen -r -b tlu_event_fifo.xco -p coregen.cgp}
catch {exec coregen -r -b FIFO.xco -p coregen.cgp}
# catch {exec coregen -r -b CounterUp.xco -p coregen.cgp}
catch {exec coregen -r -b internalTriggerGenerator.xco -p coregen.cgp}
process run "Synthesize"
process run "Translate"
process run "Map"
process run "Place & Route"
process run "Generate Programming File"
project close
fmc-mtlu-copy_ADosil_branch_r156/firmware/config/ise14/sp605/coregen.cgp 0000664 0000000 0000000 00000000343 12415504633 0026102 0 ustar 00root root 0000000 0000000 SET busformat = BusFormatAngleBracketNotRipped
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Other
SET package = fgg484
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
fmc-mtlu-copy_ADosil_branch_r156/firmware/config/ise14/sp605/file_list 0000664 0000000 0000000 00000000251 12415504633 0025660 0 ustar 00root root 0000000 0000000 hdl ipbus/firmware/example_designs/hdl/clocks_s6_extphy.vhd
include ipbus/firmware/ethernet/cfg/file_list_s6_extphy
include ipbus/firmware/ipbus_core/cfg/file_list
fmc-mtlu-copy_ADosil_branch_r156/firmware/config/ise14/sp605/setup_project.tcl 0000664 0000000 0000000 00000015270 12415504633 0027364 0 ustar 00root root 0000000 0000000 project new fmc-mtlu
project set family spartan6
project set device xc6slx45t
project set package fgg484
project set speed -3
project set "Enable Multi-Threading" "2" -process "Map"
project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" -process "Map"
project set "Enable Multi-Threading" "2" -process "Place & Route"
project set "Enable BitStream Compression" TRUE -process "Generate Programming File"
project set "Preferred Language" "VHDL"
# source $::env(REPOS_FW_DIR)/firmware/example_designs/scripts/addfiles.tcl
# Just list files by hand for now. Can't get addfiles.tcl to work.
#xfile add ipbus/firmware/example_designs/hdl/clocks_s6_extphy.vhd
# IPBus Ethernet for gig_eth_pcs_pma_v11_5
xfile add ipbus/firmware/ethernet/hdl/eth_s6_gmii.vhd
xfile add ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
puts "Adding and Regenerating Ethernet cores"
# Add cores for Ethernet
exec cp ipbus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4.xco ipcore_dir
exec cp ipbus/firmware/ethernet/coregen/mac_fifo_axi4.xco ipcore_dir
xfile add ipcore_dir/tri_mode_eth_mac_v5_4.xco
xfile add ipcore_dir/mac_fifo_axi4.xco
# Don't regenerate cores for now...
#cd ipcore_dir
#catch {exec coregen -r -b tri_mode_eth_mac_v5_4.xco -p coregen.cgp}
#catch {exec coregen -r -b mac_fifo_axi4.xco -p coregen.cgp}
#cd ..
puts "Adding IPBus files"
# Xilinx ISE setup fragment for ipbus core
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_package.vhd
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_trans_decl.vhd
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_ctrl.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_if_flat.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_buffer_selector.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_arp.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_payload.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_ping.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_resend.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_status.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_byte_sum.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_clock_crossing_if.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_do_rx_reset.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_dualportram.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_dualportram_rx.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_dualportram_tx.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_ipaddr_block.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_packet_parser.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rarp_block.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rxram_mux.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rxram_shim.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rxtransactor_if_simple.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_status_buffer.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_tx_mux.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_txtransactor_if_simple.vhd
xfile add ipbus/firmware/ipbus_core/hdl/trans_arb.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor_if.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor_sm.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor_cfg.vhd
xfile add ipbus/firmware/ipbus_core/hdl/stretcher.vhd
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_fabric.vhd
xfile add ipbus/firmware/example_designs/hdl/clock_div.vhd
xfile add ipbus/firmware/slaves/hdl/ipbus_reg_types.vhd
#xfile add ipbus/firmware/slaves/hdl/syncreg_r.vhd
#xfile add ipbus/firmware/slaves/hdl/syncreg_w.vhd
#xfile add ipbus/firmware/slaves/hdl/ipbus_syncreg_v.vhd
xfile add ipbus/firmware/slaves/hdl/ipbus_ctrlreg_v.vhd
# Add Opencores files for i2c interface
xfile add external/opencores_i2c/i2c_master_bit_ctrl.vhd
xfile add external/opencores_i2c/i2c_master_byte_ctrl.vhd
xfile add external/opencores_i2c/i2c_master_registers.vhd
xfile add external/opencores_i2c/i2c_master_top.vhd
# Add TLU cores....
# Add cores for Ethernet
puts "Adding and Regenerating TLU cores"
exec cp fmc-mtlu/firmware/ise/ipcore_dir/tlu_event_fifo.xco ipcore_dir
exec cp fmc-mtlu/firmware/ise/ipcore_dir/FIFO.xco ipcore_dir
exec cp fmc-mtlu/firmware/ise/ipcore_dir/CounterUp.xco ipcore_dir
exec cp fmc-mtlu/firmware/ise/ipcore_dir/internalTriggerGenerator.xco ipcore_dir
xfile add ipcore_dir/tlu_event_fifo.xco
xfile add ipcore_dir/FIFO.xco
#xfile add ipcore_dir/CounterUp.xco
xfile add ipcore_dir/internalTriggerGenerator.xco
# Don't regenerate cores for now...
#cd ipcore_dir
#catch {exec coregen -r -b tlu_event_fifo.xco -p coregen.cgp}
#catch {exec coregen -r -b FIFO.xco -p coregen.cgp}
#catch {exec coregen -r -b CounterUp.xco -p coregen.cgp}
#catch {exec coregen -r -b internalTriggerGenerator.xco -p coregen.cgp}
#cd ..
puts "Adding TLU Files "
# Add FMC-MTLU files. First the hand-written VHDL
xfile add fmc-mtlu/firmware/hdl/common/dualSERDES_1to4_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/i2c_master_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/ipbus_addr_decode.vhd
xfile add fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/ipbus_ver.vhd
xfile add fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd
#xfile add fmc-mtlu/firmware/hdl/common/pulseClockDomainCrossing_rtl.vhd
#xfile add fmc-mtlu/firmware/hdl/common/Reg_2clks.vhd
xfile add fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/IODELAYCal_FSM_rtl.vhd
#xfile add fmc-mtlu/firmware/hdl/common/serdes_1_to_n_SDR.vhd
#xfile add fmc-mtlu/firmware/hdl/common/sync_reg.vhd
xfile add fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd
xfile add fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
xfile add fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/handshakes_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/TPx3Logic_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/GPP_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/counterDown.vhd
# Then add the HDL-Designer generated files..
xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg_body.vhd
xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd
# Add user constraints file
xfile add fmc-mtlu/firmware/ucf/sp605_FMC_mTLU_v1a.ucf
project close
puts "Successfully finished building project file"
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/ 0000775 0000000 0000000 00000000000 12415504633 0021465 5 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/common/ 0000775 0000000 0000000 00000000000 12415504633 0022755 5 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/common/DUTInterfaces_rtl.vhd 0000664 0000000 0000000 00000026176 12415504633 0027015 0 ustar 00root root 0000000 0000000 --=============================================================================
--! @file DUTInterfaces_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.DUTInterfaces.rtl
--
--! @brief \n
--! \n
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 15:09:50 11/09/12
--
--! @version v0.1
--
--! @details
--! Address map:\n
--! 5-bit decoded
--! 0x00000000 - DUT interface mode, two bits per DUT. Up to 12 inputs XXXXXXXXBBAA99887766554433221100\n
--! - mode: 0 = EUDET mode , 1 = synchronous ( LHC / Timepix ) , 2,3=reserved
--!
--
--!
--! Dependencies:\n
--!
--! References:\n
--!
--! Modified by:\n
--! Author:
-------------------------------------------------------------------------------
--! \n\nLast changes:\n
-------------------------------------------------------------------------------
--! @todo Indicate if the DUT works under AIDA/EUDET style\n
--! \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
use work.ipbus_reg_types.all;
library unisim;
use unisim.VComponents.all;
ENTITY DUTInterfaces IS
GENERIC(
g_NUM_DUTS : positive := 3;
g_IPBUS_WIDTH : positive := 32
);
PORT(
busy_from_dut_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
busy_from_dut_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
clk_4x_logic_i : IN std_logic;
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus; -- Signals from IPBus core to slave
ipbus_reset_i : IN std_logic;
strobe_4x_logic_i : IN std_logic; -- ! goes high every 4th clock cycle
--trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);
trigger_i : IN std_logic; -- goes high when trigger logic issues a trigger
clk_to_dut_i : IN std_logic ; -- ! clock to DUT
reset_or_clk_to_dut_i : IN std_logic;
AIDAhandshake_i : IN std_logic; -- AIDA/EUDET handshake
ipbus_o : OUT ipb_rbus; -- signals from slave to IPBus core
clk_to_dut_n_o : INOUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
clk_to_dut_p_o : INOUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
reset_or_clk_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
reset_or_clk_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
trigger_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
trigger_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
veto_o : OUT std_logic -- goes high when one or more DUT are busy
);
-- Declarations
END ENTITY DUTInterfaces ;
--
ARCHITECTURE rtl OF DUTInterfaces IS
signal s_intermediate_busy_or : std_logic_vector(g_NUM_DUTS downto 0); -- OR tree
signal s_veto : std_logic;
signal s_strobe_4x_logic_d1 : std_logic;
signal s_clk_to_DUT , s_busy_from_dut , s_reset_or_clk_to_dut , s_trigger_to_dut : std_logic_vector(g_NUM_DUTS-1 downto 0);
signal s_DUT_mask : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0'); --! Mask for the DUTs not used
signal s_clk_is_input, s_clk_is_input_b : std_logic := '0'; --! Indicates the direction of the clock in the RJ45 DUT
signal s_clk_to_tlu : std_logic := '0';
constant c_N_CTRL : positive := 1;
constant c_N_STAT : positive := 1;
signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
signal s_control_from_ipbus,s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
BEGIN
-- Dummy code.
s_intermediate_busy_or(0) <= '0';
--s_busy_from_dut(g_NUM_DUTS-1 downto 0) <= (others=>'0');
-----------------------------------------------------------------------------
-- IPBus interface
-----------------------------------------------------------------------------
ipbus_registers: entity work.ipbus_ctrlreg_v
generic map(
N_CTRL => c_N_CTRL,
N_STAT => c_N_STAT
)
port map(
clk => ipbus_clk_i,
reset=> '0',--ipbus_reset_i ,
ipbus_in=> ipbus_i,
ipbus_out=> ipbus_o,
d=> s_sync_status_to_ipbus,
q=> s_control_from_ipbus,
stb=> open
);
-- Synchronize registers from logic clock to ipbus.
sync_status: entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => c_N_STAT )
port map (
clk_input_i => clk_4x_logic_i,
data_i => s_status_to_ipbus,
data_o => s_sync_status_to_ipbus,
clk_output_i => ipbus_clk_i);
-- Synchronize registers from logic clock to ipbus.
sync_ctrl: entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => c_N_CTRL )
port map (
clk_input_i => ipbus_clk_i,
data_i => s_control_from_ipbus,
data_o => s_sync_control_from_ipbus,
clk_output_i => clk_4x_logic_i);
-- Map the control registers
s_DUT_mask <= s_sync_control_from_ipbus(0)(g_NUM_DUTS-1 downto 0);
-- Map the status registers
s_status_to_ipbus(0) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-g_NUM_DUTS)) & s_DUT_mask;
-- These instances need to be out of the loop because the RJ45 permits a bidirectional clock
clk_to_DUT_OBUFDS_inst_0 : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => clk_to_dut_p_o(0), -- Diff_p output (connect directly to top-level port)
OB => clk_to_dut_n_o(0), -- Diff_n output (connect directly to top-level port)
I => s_clk_to_dut(0) -- Buffer output
);
clk_to_DUT_OBUFDS_inst_1 : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => clk_to_dut_p_o(1), -- Diff_p output (connect directly to top-level port)
OB => clk_to_dut_n_o(1), -- Diff_n output (connect directly to top-level port)
I => s_clk_to_dut(1) -- Buffer output
);
clk_to_DUT_OBUFDS_inst_2 : IOBUFDS
generic map (
IOSTANDARD => "BLVDS_25")
port map (
O => s_clk_to_tlu, -- Buffer output
IO => clk_to_dut_p_o(2), -- Diff_p inout (connect directly to top-level port)
IOB => clk_to_dut_n_o(2), -- Diff_n inout (connect directly to top-level port)
I => s_clk_to_dut(2), -- Buffer input
T => s_clk_is_input_b -- 3-state enable input, high=input, low=output
);
s_clk_is_input <= not AIDAhandshake_i;
--When an ODDR2 primitive is used in conjunction with a 3-state output, the T control pin must
--also use an ODDR2 primitive configured in the same mode as the ODDR2 primitive used for data
--output.
ddr_for_clk_to_DUT_tristate : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => s_clk_is_input_b, -- 1-bit output data
C0 => clk_to_dut_i, -- 1-bit clock input
C1 => not clk_to_dut_i, --not s_clk160_internal, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => s_clk_is_input, -- 1-bit data input (associated with C0)
D1 => s_clk_is_input, -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
duts: for dut in 1 to g_NUM_DUTS generate
busy_IBUFDS_inst : IBUFDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "LVDS_25")
port map (
O => s_busy_from_dut(dut-1), -- Buffer output
I => busy_from_dut_p_i(dut-1), -- Diff_p buffer input (connect directly to top-level port)
IB => busy_from_dut_n_i(dut-1) -- Diff_n buffer input (connect directly to top-level port)
);
trig_OBUFDS_inst : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => trigger_to_dut_p_o(dut-1), -- Diff_p output (connect directly to top-level port)
OB => trigger_to_dut_n_o(dut-1), -- Diff_n output (connect directly to top-level port)
I => s_trigger_to_dut(dut-1) and s_DUT_mask(dut-1) -- Buffer input
);
clk_rst_OBUFDS_inst : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => reset_or_clk_to_dut_p_o(dut-1), -- Diff_p output (connect directly to top-level port)
OB => reset_or_clk_to_dut_n_o(dut-1), -- Diff_n output (connect directly to top-level port)
I => reset_or_clk_to_dut_i --s_reset_or_clk_to_dut(dut-1) and s_DUT_mask(dut-1) -- Buffer input
);
s_intermediate_busy_or(dut) <= s_intermediate_busy_or(dut-1) or
(s_busy_from_dut(dut-1) and
s_DUT_mask(dut-1));
ddr_for_clk_output : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => s_clk_to_dut(dut-1), -- 1-bit output data
C0 => clk_to_dut_i, -- 1-bit clock input
C1 => not clk_to_dut_i, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => '1', -- 1-bit data input (associated with C0)
D1 => '0', -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
end generate duts;
s_veto <= s_intermediate_busy_or(g_NUM_DUTS);
-- purpose: register for internal signals and output signals
-- type : combinational
-- inputs : clk_4x_logic_i , strobe_4x_logic_i , s_veto
-- outputs: veto_o
register_signals: process (clk_4x_logic_i)-- , strobe_4x_logic_i , s_veto)
begin -- process register_signals
if rising_edge(clk_4x_logic_i) then
veto_o <= s_veto;
s_strobe_4x_logic_d1 <= strobe_4x_logic_i;
--s_reset_or_clk_to_dut <= ( others => (s_strobe_4x_logic_d1 or strobe_4x_logic_i));
s_trigger_to_dut <= ( others => trigger_i );
--shutter_to_dut <= ( others => shutter_i );
end if;
end process register_signals;
END ARCHITECTURE rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/common/GPL_doxygen_header.vhdl 0000664 0000000 0000000 00000005105 12415504633 0027324 0 ustar 00root root 0000000 0000000 --! @file dtype_fds.vhdl
--
-------------------------------------------------------------------------------
-- --
-- (c) University of Bristol, High Energy Physics Group --
-- --
-------------------------------------------------------------------------------
--
--
-- This file is part of IPBus.
--
-- IPBus is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- IPBus is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with IPBus. If not, see .
--
-- IPBus is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- IPBus is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with IPBus. If not, see .
--
--
--! Standard library
library IEEE;
-- Standard logic defintions.
use IEEE.STD_LOGIC_1164.all;
--
-- unit name: dtype_fds
--
--! @brief Aims to be the same as the Xilinx "FDS" primitive - D-Type flip-flop
--
--
--! @author David.Cussans@bristol.ac.uk
--
--! @date 7/May/2011
--
--! @version 0.1
--
--! @details -- Modified from D-type example in VHDL book.
--! See Xilinx spartan6_scm.pdf
--! Output goes high when input goes high ( asyncnronous to system clock).
--
--! Dependencies:\n
--!
--! References:\n
--! \n
--!
--!
--! Modified by:\n
--! Author:
-------------------------------------------------------------------------------
--! \n\nLast changes:\n
--! \n
--!
-------------------------------------------------------------------------------
--! @todo \n
--! \n
--
-------------------------------------------------------------------------------
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/common/GPP_rtl.vhd 0000664 0000000 0000000 00000027107 12415504633 0024776 0 ustar 00root root 0000000 0000000 --=============================================================================
--! @file GPP_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Santiago de Compostela, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
--
--
--! @brief GPP - General purpose pulser. Generates a sycronous custom pulse \n
--! IPBus address map:\n
--
--! @author Alvaro Dosil , alvaro.dosil@usc.es
--
--! @date 15:42:31 01/15/2013
--
--! @version v0.1
--
--! @details
--!
--!
--! Dependencies:\n
--!
--! References:\n
--!
--! Modified by:
--! Author:
-------------------------------------------------------------------------------
--! \n\nLast changes:\n
-------------------------------------------------------------------------------
--! @todo \n
--! \n
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity GPP is
GENERIC(
g_IPBUS_WIDTH : positive := 32
);
PORT( clk_i : IN std_logic; --! Rising edge active
Enable_i : IN std_logic; --
Reset_i : IN std_logic; --
RstPulsCnt_i : IN std_logic; -- Reset pulse counter
Trigger_i : IN std_logic; -- Trigger input signal
NMaxPulses_i : IN std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- Max number of pulses
SuDTime_i : IN std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- Startup dead time
PulsLen_i : IN std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- Pulse length
IpDTime_i : IN std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- Interpulse dead time
RearmTime_i : IN std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- Time before rearm after reach the max number of pulses
Force_PullDown_i : IN std_logic; -- Force pull down
WU_i : IN std_logic; -- Output trigger signal with update
PulseDelay_i : IN std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- Pulse delay
event_number_o : OUT std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- Event number
MaxPulses_o : OUT std_logic; -- Maximun number of pulses reached
Pulse_o : OUT std_logic; --! pulse output
Pulse_d_o : OUT std_logic --! pulse output delayed
);
end GPP;
architecture rtl of GPP is
--! FSM state values
type state_values is (st0, st1, st2, st3, st4, st5, st6);
signal pres_state, next_state: state_values;
signal s_PulsCnt_en : std_logic := '0'; --! Pulse counter enable
signal s_RstPulsCnt : std_logic := '0'; --! Reset pulse counter
signal s_RstPulsCnt_int : std_logic := '0'; --! Reset pulse counter internal signal
signal s_PulsLen : std_logic_vector(g_IPBUS_WIDTH-1 downto 0); --! Pulse Length
signal s_PulsCnt : unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); --! Pulse counter value
signal s_MaxPulses : std_logic := '0'; --! Max number of pulses reached
signal s_Pulse : std_logic := '0'; --! Active pulse signal
signal s_Pulse_d : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others=>'0'); --! Active pulse signal delayed
signal s_load_SuDTime : std_logic := '1'; --! Counter load signal
signal s_SuDTime : std_logic_vector(g_IPBUS_WIDTH-1 downto 0); --! Startup dead time counter
signal EOSDT : std_logic := '0'; --! End of startup dead time signal
signal s_load_PulsLen : std_logic := '1'; --! Counter load
signal EOP : std_logic := '0'; --! End of pulse length signal
signal s_load_IpDTime : std_logic := '1'; --! Counter load signal
signal s_IpDTime : std_logic_vector(g_IPBUS_WIDTH-1 downto 0); --! Interpulse dead time counter
signal EOIDT : std_logic := '0'; --! End of interpulse dead time signal
signal s_load_RearmTime : std_logic := '1'; --! Rearm counter load signal
signal s_RearmLen : std_logic_vector(g_IPBUS_WIDTH-1 downto 0); --! Startup dead time counter
signal EOREARM : std_logic := '0'; --! End of startup dead time signal
begin
-----------------------------------------------------------------------------
-- Counters
-----------------------------------------------------------------------------
--! Startup dead time counter
c_startup_dtime : entity work.CounterDown
generic map(
MAX_WIDTH => g_IPBUS_WIDTH
)
port map(
Clk => clk_i,
Reset => '0',
Load => s_load_SuDTime,
InitVal => std_logic_vector(unsigned(s_SuDTime)-1),
Count => open,
Q => EOSDT
);
s_SuDTime <= x"00000001" when SuDTime_i = x"00000000" -- At least one clock cycle pulse is generated
else SuDTime_i;
--! Pulse time counter
c_pulse_time : entity work.CounterDown
generic map(
MAX_WIDTH => g_IPBUS_WIDTH
)
port map(
Clk => clk_i,
Reset => '0',
Load => s_load_PulsLen,
InitVal => std_logic_vector(unsigned(s_PulsLen)-1),
Count => open,
Q => EOP
);
s_PulsLen <= x"00000001" when PulsLen_i = x"00000000" -- At least one clock cycle pulse is generated
else PulsLen_i;
--! Interpulse dead time counter
c_interpulse_dtime : entity work.CounterDown
generic map(
MAX_WIDTH => g_IPBUS_WIDTH
)
port map(
Clk => clk_i,
Reset => '0',
Load => s_load_IpDTime,
InitVal => std_logic_vector(unsigned(s_IpDTime)-1),
Count => open,
Q => EOIDT
);
s_IpDTime <= x"00000001" when IpDTime_i = x"00000000" -- At least one clock cycle pulse is generated
else IpDTime_i;
--! Rearm time after the max pulses reached
c_rearm_dtime : entity work.CounterDown
generic map(
MAX_WIDTH => g_IPBUS_WIDTH
)
port map(
Clk => clk_i,
Reset => '0',
Load => s_load_RearmTime,
InitVal => std_logic_vector(unsigned(s_RearmLen)-1),
Count => open,
Q => EOREARM
);
s_RearmLen <= x"00000001" when RearmTime_i = x"00000000" -- At least one clock cycle pulse is generated
else RearmTime_i;
--! FSM register
statereg: process(clk_i, Enable_i, Reset_i)
begin
if Enable_i = '0' then
pres_state <= st0; -- Move to st0 - INITIAL STATE
elsif Reset_i = '1' then
pres_state <= st0; -- Move to st0 - INITIAL STATE
elsif rising_edge(clk_i) then
pres_state <= next_state; -- Move to next state
end if;
end process statereg;
--! FSM combinational block
fsm: process(pres_state, Enable_i, Reset_i, Trigger_i, s_MaxPulses, EOP, EOSDT, EOIDT, Force_PullDown_i)
begin
next_state <= pres_state;
-- Default values
s_Pulse <= '0';
s_load_SuDTime <= '1';
s_load_PulsLen <= '1';
s_load_IpDTime <= '1';
s_load_RearmTime <= '1';
s_RstPulsCnt_int <= '0';
case pres_state is
-- st0 - INITIAL STATE
when st0=>
if (Enable_i = '1') and (Reset_i = '0') then
next_state <= st1; -- Next state is "st1 - IDLE"
end if;
-- st1 - IDLE STATE
when st1=>
if s_MaxPulses = '1' then
next_state <= st5; -- Next state is "st5 - NMAX PULSES REACHED"
else
if Trigger_i = '1' and Force_PullDown_i = '0' then
if (to_integer(unsigned(SuDTime_i)) = 0) then
next_state <= st3; -- Next state is "st3 - PULSE"
else
next_state <= st2; -- Next state is "st2 - STARTUP DEAD-TIME"
end if;
end if;
end if;
-- st2 - STARTUP DEAD-TIME
when st2=>
s_load_SuDTime <= '0';
if EOSDT = '1' then
next_state <= st3; -- Next state is "st3 - PULSE"
end if;
-- st3 - PULSE
when st3=>
s_Pulse <= '1';
s_load_PulsLen <= '0';
if (EOP = '1') or (Force_PullDown_i = '1')then
if (to_integer(unsigned(IpDTime_i)) = 0) then
next_state <= st1; -- Next state is "st1 - IDLE"
else
next_state <= st4; -- Next state is "st4 - INTERPULSE DEAD-TIME"
end if;
end if;
if Trigger_i = '1' then
if (WU_i = '1') then
next_state <= st6; -- Next state is "st6 - RELOAD PULSE TIMER"
end if;
end if;
-- st4 - INTERPULSE DEAD-TIME
when st4=>
s_load_IpDTime <= '0';
if EOIDT = '1' then
next_state <= st1; -- Next state is "st1 - IDLE"
end if;
-- st5 - NMAX PULSES REACHED
when st5=>
s_load_RearmTime <= '0';
if EOREARM = '1' then
next_state <= st1; -- Next state is "st1 - IDLE"
s_RstPulsCnt_int <= '1';
end if;
-- st6 - RELOAD PULSE TIMER
when st6=>
s_Pulse <= '1';
next_state <= st3; -- Next state is "st3 - PULSE"
-- when others=>
-- next_state<=st0; -- Next state is "st0 - INITIAL STATE"
end case;
end process fsm;
-- Pulse reg
p_reg_pulse : process ( clk_i , Reset_i )
begin
if Reset_i = '1' then
s_Pulse_d <= (others => '0');
elsif rising_edge(clk_i) then
for i in 0 to g_IPBUS_WIDTH-2 loop
s_Pulse_d(i+1) <= s_Pulse_d(i);
end loop;
s_Pulse_d(0) <= s_Pulse;
end if;
end process p_reg_pulse;
event_number_o <= std_logic_vector(s_PulsCnt);
MaxPulses_o <= s_MaxPulses;
Pulse_o <= s_Pulse;
Pulse_d_o <= s_Pulse when PulseDelay_i = x"00000000" else
s_Pulse_d(to_integer(unsigned(PulseDelay_i)-1));
-----------------------------------------------------------------------------
-- Count runs and synchronization
-----------------------------------------------------------------------------
p_PulsCounter : process (clk_i )
begin -- process p_run_counter
if rising_edge(clk_i) then
if s_RstPulsCnt = '1' then
s_PulsCnt <= (others => '0');
elsif s_PulsCnt_en = '1' then
s_PulsCnt <= s_PulsCnt + 1;
end if;
end if;
end process p_PulsCounter;
s_RstPulsCnt <= Reset_i or RstPulsCnt_i or s_RstPulsCnt_int;
s_PulsCnt_en <= '1' when (s_Pulse = '1') and (s_Pulse_d(0) = '0') and (s_MaxPulses = '0')
else '0';
s_MaxPulses <= '1' when (s_PulsCnt = unsigned(NMaxPulses_i)) and (NMaxPulses_i /= x"00000000")
else '0';
END ARCHITECTURE rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/common/IODELAYCal_FSM_rtl.vhd 0000664 0000000 0000000 00000005446 12415504633 0026565 0 ustar 00root root 0000000 0000000 --=============================================================================
--! @file IODELAYCal_FSM_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- UoB , USC
-- --
------------------------------------------------------------------------------- --
--
--! @brief Finite-state machine to control calibration and reset signals to
--! Iserdes, IDelay
--! based on code by Alvaro Dosil\n
--
--! @author Alvaro Dosil
--
--! @date 22/Feb/2014
--
--! @version v0.1
--
--! @details
--
-------------------------------------------------------------------------------
--! \n\nLast changes:\n
-------------------------------------------------------------------------------
--! @todo Implement a periodic calibration sequence\n
--! \n
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity IODELAYCal_FSM is
port (
clk_i : in std_logic; --! Global clock
startcal_i : in std_logic; --! Start calibration
busy_i : in std_logic; --! Status of the IDELAY component
calibrate_o : out std_logic; --! Calibration signals to IODELAY
reset_o : out std_logic --! Reset to IODELAY component
);
end entity IODELAYCal_FSM;
architecture rtl of IODELAYCal_FSM is
--! Calibration FSM state values
type state_values is (st0, st1, st2, st3);
signal pres_state, next_state: state_values := st0;
signal s_cal_FSM : std_logic := '0'; -- IODELAY reset
signal s_rst_FSM : std_logic := '0'; -- IODELAY reset
begin -- rtl
--! Calibration FSM register
statereg: process(clk_i)
begin
if rising_edge(clk_i) then
pres_state <= next_state; -- Move to next state
end if;
end process statereg;
--! Calibration FSM combinational block
fsm: process(pres_state, startcal_i, busy_i)
begin
next_state <= pres_state;
-- Default values
s_Rst_FSM <= '0';
s_cal_FSM <= '0';
case pres_state is
-- st0 - IDLE
when st0=>
if ( startcal_i = '1') then
next_state <= st1; -- Next state is "st1 - SEND CALIBRATION SIGNAL"
end if;
-- st1 - SEND CALIBRATION SIGNAL
when st1=>
s_cal_FSM <= '1';
next_state <= st2; -- Next state is "st2 - WAIT BUSY = '0'"
-- st2 - WAIT BUSY = '0'
when st2=>
if busy_i = '0' then
next_state <= st3; -- Next state is "st3 - RESET STATE"
end if;
-- st3 - RESET STATE
when st3=>
s_Rst_FSM <= '1';
next_state <= st0; -- Next state is "st0 - IDLE"
end case;
end process fsm;
calibrate_o <= s_cal_FSM;
reset_o <= s_Rst_FSM;
end rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/common/IPBusInterface_rtl.vhd 0000664 0000000 0000000 00000015347 12415504633 0027156 0 ustar 00root root 0000000 0000000 --=============================================================================
--! @file IPBusInterface_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.IPBusInterface.rtl
--
--! @brief \n
--! \n
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 16:06:57 11/09/12
--
--! @version v0.1
--
--! @details
--!
--!
--! Dependencies:\n
--!
--! References:\n
--!
--! Modified by:\n
--! Author:
-------------------------------------------------------------------------------
--! \n\nLast changes:\n
-------------------------------------------------------------------------------
--! @todo \n
--! \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
use work.emac_hostbus_decl.all;
ENTITY IPBusInterface IS
GENERIC(
NUM_EXT_SLAVES : positive := 5
);
PORT(
gmii_rx_clk_i : IN std_logic;
gmii_rx_dv_i : IN std_logic;
gmii_rx_er_i : IN std_logic;
gmii_rxd_i : IN std_logic_vector (7 DOWNTO 0);
ipbr_i : IN ipb_rbus_array (NUM_EXT_SLAVES-1 DOWNTO 0); -- ! IPBus read signals
sysclk_n_i : IN std_logic;
sysclk_p_i : IN std_logic; -- ! 200 MHz xtal clock
clocks_locked_o : OUT std_logic;
gmii_gtx_clk_o : OUT std_logic;
gmii_tx_en_o : OUT std_logic;
gmii_tx_er_o : OUT std_logic;
gmii_txd_o : OUT std_logic_vector (7 DOWNTO 0);
ipb_clk_o : OUT std_logic; -- ! IPBus clock to slaves
ipb_rst_o : OUT std_logic; -- ! IPBus reset to slaves
ipbw_o : OUT ipb_wbus_array (NUM_EXT_SLAVES-1 DOWNTO 0); -- ! IBus write signals
onehz_o : OUT std_logic;
phy_rstb_o : OUT std_logic;
dip_switch_i : IN std_logic_vector (3 DOWNTO 0);
clk_logic_xtal_o : OUT std_logic
);
-- Declarations
END ENTITY IPBusInterface ;
--
ARCHITECTURE rtl OF IPBusInterface IS
--! Number of slaves inside the IPBusInterface block.
constant c_NUM_INTERNAL_SLAVES : positive := 1;
signal clk125, locked, rst_125, rst_ipb: STD_LOGIC;
signal mac_txd, mac_rxd : STD_LOGIC_VECTOR(7 downto 0);
signal mac_txdvld, mac_txack, mac_rxclko, mac_rxdvld, mac_rxgoodframe, mac_rxbadframe : STD_LOGIC;
signal ipb_master_out : ipb_wbus;
signal ipb_master_in : ipb_rbus;
signal mac_addr: std_logic_vector(47 downto 0);
signal mac_tx_data, mac_rx_data: std_logic_vector(7 downto 0);
signal mac_tx_valid, mac_tx_last, mac_tx_error, mac_tx_ready, mac_rx_valid, mac_rx_last, mac_rx_error: std_logic;
signal ip_addr: std_logic_vector(31 downto 0);
signal s_ipb_clk : std_logic;
signal s_ipbw_internal: ipb_wbus_array (NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1 DOWNTO 0);
signal s_ipbr_internal: ipb_rbus_array (NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1 DOWNTO 0);
signal s_sysclk : std_logic;
signal pkt_rx, pkt_tx, pkt_rx_led, pkt_tx_led, sys_rst: std_logic;
BEGIN
-- DCM clock generation for internal bus, ethernet
clocks: entity work.clocks_s6_extphy port map(
sysclk_p => sysclk_p_i,
sysclk_n => sysclk_n_i,
clk_logic_xtal_o => clk_logic_xtal_o,
clko_125 => clk125,
clko_ipb => s_ipb_clk,
locked => clocks_locked_o,
rsto_125 => rst_125,
rsto_ipb => rst_ipb,
onehz => onehz_o
);
-- Connect IPBus clock and reset to output ports.
ipb_clk_o <= s_ipb_clk;
ipb_rst_o <= rst_ipb;
-- leds <= ('0', '0', locked, onehz);
-- Ethernet MAC core and PHY interface
-- In this version, consists of hard MAC core and GMII interface to external PHY
-- Can be replaced by any other MAC / PHY combination
eth: entity work.eth_s6_gmii port map(
clk125 => clk125,
rst => rst_125,
gmii_gtx_clk => gmii_gtx_clk_o,
gmii_tx_en => gmii_tx_en_o,
gmii_tx_er => gmii_tx_er_o,
gmii_txd => gmii_txd_o,
gmii_rx_clk => gmii_rx_clk_i,
gmii_rx_dv => gmii_rx_dv_i,
gmii_rx_er => gmii_rx_er_i,
gmii_rxd => gmii_rxd_i,
tx_data => mac_tx_data,
tx_valid => mac_tx_valid,
tx_last => mac_tx_last,
tx_error => mac_tx_error,
tx_ready => mac_tx_ready,
rx_data => mac_rx_data,
rx_valid => mac_rx_valid,
rx_last => mac_rx_last,
rx_error => mac_rx_error
);
phy_rstb_o <= '1';
-- ipbus control logic
ipbus: entity work.ipbus_ctrl
generic map (
BUFWIDTH => 2)
port map(
mac_clk => clk125,
rst_macclk => rst_125,
ipb_clk => s_ipb_clk,
rst_ipb => rst_ipb,
mac_rx_data => mac_rx_data,
mac_rx_valid => mac_rx_valid,
mac_rx_last => mac_rx_last,
mac_rx_error => mac_rx_error,
mac_tx_data => mac_tx_data,
mac_tx_valid => mac_tx_valid,
mac_tx_last => mac_tx_last,
mac_tx_error => mac_tx_error,
mac_tx_ready => mac_tx_ready,
ipb_out => ipb_master_out,
ipb_in => ipb_master_in,
mac_addr => mac_addr,
ip_addr => ip_addr,
pkt_rx => pkt_rx,
pkt_tx => pkt_tx,
pkt_rx_led => pkt_rx_led,
pkt_tx_led => pkt_tx_led
);
mac_addr <= X"020ddba115" & dip_switch_i & X"0"; -- Careful here, arbitrary addresses do not always work
ip_addr <= X"c0a8c8" & dip_switch_i & X"0"; -- 192.168.200.X
fabric: entity work.ipbus_fabric
generic map(NSLV => NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES)
port map(
ipb_in => ipb_master_out,
ipb_out => ipb_master_in,
ipb_to_slaves => s_ipbw_internal,
ipb_from_slaves => s_ipbr_internal
);
ipbw_o <= s_ipbw_internal(NUM_EXT_SLAVES-1 downto 0);
s_ipbr_internal(NUM_EXT_SLAVES-1 downto 0) <= ipbr_i;
-- Slave: firmware ID
firmware_id: entity work.ipbus_ver
port map(
ipbus_in => s_ipbw_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1),
ipbus_out => s_ipbr_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1)
);
END ARCHITECTURE rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/common/Reg_2clks.vhd 0000664 0000000 0000000 00000002720 12415504633 0025274 0 ustar 00root root 0000000 0000000 ----------------------------------------------------------------------------------
-- Company: Universidade de Santiago de Compostela
-- Engineer: Alvaro Dosil
--
-- Create Date: 31/07/2012
-- Module Name: Reg_2clks - Behavioral
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
-------------------------------------------------------
--! @file
--! @brief Synchronization module 1b
--! @author Alvaro Dosil
-------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Reg_2clks is
port(
clk_i : in std_logic; --! Synchronous clock
async_i : in std_logic; --! Asynchronous input data
sync_o : out std_logic --! Synchronous output data
);
end Reg_2clks;
--! @brief
--! @details Synchronize 1 bit of data
architecture Behavioral of Reg_2clks is
signal sreg : std_logic_vector(1 downto 0);
attribute TIG : string;
attribute IOB : string;
attribute ASYNC_REG : string;
attribute SHIFT_EXTRACT : string;
attribute HBLKNM : string;
attribute TIG of async_i : signal is "TRUE";
attribute IOB of async_i : signal is "FALSE";
attribute ASYNC_REG of sreg : signal is "TRUE";
attribute SHIFT_EXTRACT of sreg : signal is "NO";
attribute HBLKNM of sreg : signal is "sync_reg";
begin
process (clk_i)
begin
if rising_edge(clk_i) then
sync_o <= sreg(1);
sreg <= sreg(0) & async_i;
end if;
end process;
end Behavioral;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/common/TPx3Logic_rtl.vhd 0000664 0000000 0000000 00000012417 12415504633 0026122 0 ustar 00root root 0000000 0000000 --=============================================================================
--! @file TPx3Logic_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Santiago de Compostela, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.TPx3Logic.rtl
--
--! @brief Produces shutters \n
--! IPBus address map:\n
--
--! @author Alvaro Dosil , alvaro.dosil@usc.es
--
--! @date 16:06:19 11/06/14
--
--! @version v0.1
--
--! @details
--!
--!
--! Dependencies:\n
--!
--! References:\n
--!
--! Modified by: Alvaro Dosil , alvaro.dosil@usc.es \n
--! Author:
-------------------------------------------------------------------------------
--! \n\nLast changes:\n
--! Move all IPBus stuff into ipbus_syncreg_v , which also handles clock domain
--! crossing. 20/Feb/2014 , David Cussans
-------------------------------------------------------------------------------
--! @todo \n
--! \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
use work.ipbus_reg_types.all;
ENTITY TPx3Logic IS
GENERIC(
g_IPBUS_WIDTH : positive := 32
);
PORT(
clk_i : IN std_logic; -- ! Rising edge active
Start_T0sync_i : IN std_logic;
T0syncLen_i : IN std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0);
logic_reset_i : IN std_logic; -- active high. Synchronous with clk_4x_logic
Busy_i : IN std_logic;
Veto_i : IN std_logic;
Shutter_o : OUT std_logic;
T0sync_o : OUT std_logic
);
-- Declarations
END ENTITY TPx3Logic ;
--
ARCHITECTURE rtl OF TPx3Logic IS
type state_values is (st0, st1);
signal pres_state, next_state: state_values;
signal s_Enable : std_logic := '0';
signal s_Shutter, s_Shutter_d1f, s_Shutter_d1, s_T0sync, s_T0sync_d1f : std_logic := '0';
signal s_Start_T0sync, s_Start_T0sync_d1, s_Start_T0sync_d2, s_Start_T0sync_d3 : std_logic;
signal Rst_T0sync, T0syncT : std_logic; --Load signal and flag for the T0sync
signal s_RunNumber : unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); -- ! counters for runs
BEGIN
-----------------------------------------------------------------------------
-- Counters
-----------------------------------------------------------------------------
--T0sync counter
c_T0sync: entity work.CounterDown
generic map(
MAX_WIDTH => g_IPBUS_WIDTH
)
port map(
Clk => clk_i,
Reset => '0',
Load => Rst_T0sync,
InitVal => std_logic_vector(unsigned(T0syncLen_i)-1),
Count => open,
Q => T0syncT
);
-----------------------------------------------------------------------------
-- FSM register
-----------------------------------------------------------------------------
statereg: process(clk_i)
begin
if rising_edge(clk_i) then
pres_state <= next_state; --Move to the next state
end if;
end process statereg;
-----------------------------------------------------------------------------
-- FSM combinational block
-----------------------------------------------------------------------------
fsm: process(pres_state, s_Start_T0sync, T0syncT)
begin
next_state<=pres_state;
s_T0sync <='0';
Rst_T0sync <= '1';
case pres_state is
when st0=>
if s_Start_T0sync = '1' then
next_state <= st1; --Next state is "Whait for end of T0sync signal"
end if;
when st1 =>
Rst_T0sync <='0';
s_T0sync <='1';
if T0syncT = '1' then
next_state<=st0; --Next state is "Whait for end of T0-sync counter"
end if;
when others=>
next_state<=st0; --Next state is "Whait for T0sync start"
end case;
end process fsm;
-----------------------------------------------------------------------------
-- Busy signals
-----------------------------------------------------------------------------
s_Enable <= not Veto_i;
s_Shutter <= not Busy_i and not Veto_i;
--Shutter_o <= s_Shutter;
--T0sync_o <= s_T0sync;
-----------------------------------------------------------------------------
-- Count runs and synchronization
-----------------------------------------------------------------------------
p_run_counter: process (clk_i )
begin -- process p_run_counter
if rising_edge(clk_i) then
s_Start_T0sync_d1 <= Start_T0sync_i;
s_Start_T0sync_d2 <= s_Start_T0sync_d1;
s_Start_T0sync_d3 <= s_Start_T0sync_d2;
s_Start_T0sync <= s_Start_T0sync_d2 and ( not s_Start_T0sync_d3);
s_Shutter_d1 <= s_Shutter;
if logic_reset_i = '1' then
s_RunNumber <= (others => '0');
elsif s_Shutter='1' and s_Shutter_d1='0' then
s_RunNumber <= s_RunNumber + 1;
end if;
end if;
-- Signals synchronous with falling edge clock
if falling_edge(clk_i) then
s_Shutter_d1f <= s_Shutter;
Shutter_o <= s_Shutter_d1f;
s_T0sync_d1f <= s_T0sync;
T0sync_o <= s_T0sync_d1f;
end if;
end process p_run_counter;
END ARCHITECTURE rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/common/arrivalTimeLUT_rtl.vhd 0000664 0000000 0000000 00000031203 12415504633 0027204 0 ustar 00root root 0000000 0000000 --=============================================================================
--! @file arrivalTimeLUT_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture work.ArivalTimeLUT.rtl
--
--! @brief Uses a look-up-table to convert the eight bits from the two 1:4 deserializers\n
--! into a 5-bit time ( 3 bits from the position in 8-bit deserialized data \n
--! plus two bits from position w.r.t. the strobe_4x_logic_i signal ( one pulse
--! every 4 cycles of clk_4x_logic_i
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 12:46:34 11/21/12
--
--! @version v0.1
--
--! @details
--! Rising and falling edge times encoded as a LUT. Contents:
--! MRFrrrfff
--! M = multiple edges present ( more then one rising or falling edge)
--! R = at least one rising edge present
--! F = at least one falling edge present.
--!
--! Dependencies:\n
--!
--! References:\n
--!
--! Modified by:\n
--! Author:
-------------------------------------------------------------------------------
--! \n\nLast changes:\n
-------------------------------------------------------------------------------
--! @todo \n
--! \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY arrivalTimeLUT IS
GENERIC(
g_NUM_FINE_BITS : positive := 3;
g_NUM_COARSE_BITS : positive := 2
);
PORT(
clk_4x_logic_i : IN std_logic; --! Rising edge active
strobe_4x_logic_i : IN std_logic; --! Pulses high once every 4 cycles of clk_4x_logic
deserialized_data_i : IN std_logic_vector (8 DOWNTO 0); -- Output from the two 4-bit deserializers, concatenated with most recent bit of previous clock cycle. Clocked by clk_4x_logic_i . bit-8 is the most recent data
first_rising_edge_time_o : OUT std_logic_vector (g_NUM_FINE_BITS+g_NUM_COARSE_BITS-1 DOWNTO 0); -- Position of rising edge w.r.t. 40MHz strobe. Clocked by clk_4x_logic_i
last_falling_edge_time_o : OUT std_logic_vector (g_NUM_FINE_BITS+g_NUM_COARSE_BITS-1 DOWNTO 0); -- Position of rising edge w.r.t. 40MHz strobe. Clocked by clk_4x_logic_i
rising_edge_o : OUT std_logic; -- goes high if there is a rising edge in the data. Clocked by clk_4x_logic_i
falling_edge_o : OUT std_logic; -- goes high if there is a falling edge in the data.Clocked by clk_4x_logic_i
multiple_edges_o : OUT std_logic -- there is more than one rising or falling edge transition.
);
-- Declarations
END ENTITY arrivalTimeLUT ;
--
ARCHITECTURE rtl OF arrivalTimeLUT IS
constant c_FALLING_EDGE_BIT : positive := 2*g_NUM_FINE_BITS; --! Bit position of bit set when falling edge detected
constant c_RISING_EDGE_BIT : positive := 2*g_NUM_FINE_BITS+1; --! Bit position of bit set when rising edge detected
constant c_MULTI_EDGE_BIT : positive := 2*g_NUM_FINE_BITS+2; --! Bit position of bit set when rising edge detected
signal s_coarse_bits : std_logic_vector(g_NUM_COARSE_BITS-1 downto 0) := "00"; --! phase w.r.t. strobe
signal s_LUT_entry : std_logic_vector(g_NUM_FINE_BITS*2 +3-1 downto 0); -- stores intermediate LUT value.
type t_LUT is array (natural range <>) of std_logic_vector(g_NUM_FINE_BITS*2 + 3 -1 downto 0);
--! Lookup table for arrival time and rising/falling edge detection (3bits
--! for position in 8-bit deserialized data plus two bits for rising/falling
constant c_LUT : t_LUT(0 to 511) := (
"000000000", "001000000", "011000001", "001000001", "011001010", "011001010", "011000010", "001000010",
"011010011", "011010011", "111000011", "011010011", "011001011", "011001011", "011000011", "001000011",
"011011100", "011011100", "111000100", "011011100", "111001100", "111001100", "111000100", "011011100",
"011010100", "011010100", "111000100", "011010100", "011001100", "011001100", "011000100", "001000100",
"011100101", "011100101", "111000101", "011100101", "111001101", "111001101", "111000101", "011100101",
"111010101", "111010101", "111000101", "111010101", "111001101", "111001101", "111000101", "011100101",
"011011101", "011011101", "111000101", "011011101", "111001101", "111001101", "111000101", "011011101",
"011010101", "011010101", "111000101", "011010101", "011001101", "011001101", "011000101", "001000101",
"011101110", "011101110", "111000110", "011101110", "111001110", "111001110", "111000110", "011101110",
"111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "011101110",
"111011110", "111011110", "111000110", "111011110", "111001110", "111001110", "111000110", "111011110",
"111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "011101110",
"011100110", "011100110", "111000110", "011100110", "111001110", "111001110", "111000110", "011100110",
"111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "011100110",
"011011110", "011011110", "111000110", "011011110", "111001110", "111001110", "111000110", "011011110",
"011010110", "011010110", "111000110", "011010110", "011001110", "011001110", "011000110", "001000110",
"011110111", "011110111", "111000111", "011110111", "111001111", "111001111", "111000111", "011110111",
"111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011110111",
"111011111", "111011111", "111000111", "111011111", "111001111", "111001111", "111000111", "111011111",
"111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011110111",
"111100111", "111100111", "111000111", "111100111", "111001111", "111001111", "111000111", "111100111",
"111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "111100111",
"111011111", "111011111", "111000111", "111011111", "111001111", "111001111", "111000111", "111011111",
"111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011110111",
"011101111", "011101111", "111000111", "011101111", "111001111", "111001111", "111000111", "011101111",
"111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011101111",
"111011111", "111011111", "111000111", "111011111", "111001111", "111001111", "111000111", "111011111",
"111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011101111",
"011100111", "011100111", "111000111", "011100111", "111001111", "111001111", "111000111", "011100111",
"111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011100111",
"011011111", "011011111", "111000111", "011011111", "111001111", "111001111", "111000111", "011011111",
"011010111", "011010111", "111000111", "011010111", "011001111", "011001111", "011000111", "001000111",
"010111000", "011111000", "111000001", "011111001", "111001010", "111001010", "111000010", "011111010",
"111010011", "111010011", "111000011", "111010011", "111001011", "111001011", "111000011", "011111011",
"111011100", "111011100", "111000100", "111011100", "111001100", "111001100", "111000100", "111011100",
"111010100", "111010100", "111000100", "111010100", "111001100", "111001100", "111000100", "011111100",
"111100101", "111100101", "111000101", "111100101", "111001101", "111001101", "111000101", "111100101",
"111010101", "111010101", "111000101", "111010101", "111001101", "111001101", "111000101", "111100101",
"111011101", "111011101", "111000101", "111011101", "111001101", "111001101", "111000101", "111011101",
"111010101", "111010101", "111000101", "111010101", "111001101", "111001101", "111000101", "011111101",
"111101110", "111101110", "111000110", "111101110", "111001110", "111001110", "111000110", "111101110",
"111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "111101110",
"111011110", "111011110", "111000110", "111011110", "111001110", "111001110", "111000110", "111011110",
"111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "111101110",
"111100110", "111100110", "111000110", "111100110", "111001110", "111001110", "111000110", "111100110",
"111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "111100110",
"111011110", "111011110", "111000110", "111011110", "111001110", "111001110", "111000110", "111011110",
"111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "011111110",
"010110000", "011110000", "111000001", "011110001", "111001010", "111001010", "111000010", "011110010",
"111010011", "111010011", "111000011", "111010011", "111001011", "111001011", "111000011", "011110011",
"111011100", "111011100", "111000100", "111011100", "111001100", "111001100", "111000100", "111011100",
"111010100", "111010100", "111000100", "111010100", "111001100", "111001100", "111000100", "011110100",
"111100101", "111100101", "111000101", "111100101", "111001101", "111001101", "111000101", "111100101",
"111010101", "111010101", "111000101", "111010101", "111001101", "111001101", "111000101", "111100101",
"111011101", "111011101", "111000101", "111011101", "111001101", "111001101", "111000101", "111011101",
"111010101", "111010101", "111000101", "111010101", "111001101", "111001101", "111000101", "011110101",
"010101000", "011101000", "111000001", "011101001", "111001010", "111001010", "111000010", "011101010",
"111010011", "111010011", "111000011", "111010011", "111001011", "111001011", "111000011", "011101011",
"111011100", "111011100", "111000100", "111011100", "111001100", "111001100", "111000100", "111011100",
"111010100", "111010100", "111000100", "111010100", "111001100", "111001100", "111000100", "011101100",
"010100000", "011100000", "111000001", "011100001", "111001010", "111001010", "111000010", "011100010",
"111010011", "111010011", "111000011", "111010011", "111001011", "111001011", "111000011", "011100011",
"010011000", "011011000", "111000001", "011011001", "111001010", "111001010", "111000010", "011011010",
"010010000", "011010000", "111000001", "011010001", "010001000", "011001000", "010000000", "000000000"
);
BEGIN
-- purpose: uses the deserialized data as a index into
-- a lookup table holding the position of the first rising edge (if any)
-- and if there is a rising or falling edge
-- type : combinational
-- inputs : clk_4x_logic_i
-- outputs: arrival_time_o , rising_edge_o , falling_edge_o
examine_lut: process (clk_4x_logic_i) -- , deserialized_data_i)
-- variable v_LUT_entry : std_logic_vector(g_NUM_FINE_BITS+2-1 downto 0); --! Entry in LUT pointed to by deserialized data
begin -- process examine_lut
-- v_LUT_entry := c_LUT(to_integer(unsigned(deserialized_data_i)));
if rising_edge(clk_4x_logic_i) then
s_LUT_entry <= c_LUT(to_integer(unsigned(deserialized_data_i)));
first_rising_edge_time_o <= s_coarse_bits & s_LUT_ENTRY(g_NUM_FINE_BITS*2-1 downto g_NUM_FINE_BITS);
last_falling_edge_time_o <= s_coarse_bits & s_LUT_ENTRY(g_NUM_FINE_BITS-1 downto 0);
rising_edge_o <= s_LUT_ENTRY(c_RISING_EDGE_BIT);
falling_edge_o <= s_LUT_ENTRY(c_FALLING_EDGE_BIT);
multiple_edges_o <= s_LUT_ENTRY(c_MULTI_EDGE_BIT);
end if;
end process examine_lut;
--! Coarse time stamp. Phase w.r.t. strobe
-- c_coarse_ts : entity work.CounterUp
-- PORT MAP (
-- clk => clk_4x_logic_i,
-- ce => '1',
-- sinit => strobe_4x_logic_i, --'0',
-- q(31 downto 2) => open,
-- q(1 downto 0) => s_coarse_bits
-- );
--
c_coarse_ts : entity work.CounterWithReset
GENERIC MAP (
g_COUNTER_WIDTH => 2 )
PORT MAP (
clock_i => clk_4x_logic_i,
enable_i => '1',
reset_i => strobe_4x_logic_i, -- Synchronous reset, so the counter will present result_o="11" when reset_i='1'
result_o => s_coarse_bits
);
END ARCHITECTURE rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/common/clocks_s6_extphy.vhd 0000664 0000000 0000000 00000006451 12415504633 0026755 0 ustar 00root root 0000000 0000000 -- clocks_s6_extphy
--
-- Generates a 125MHz ethernet clock and 31MHz ipbus clock from the 200MHz reference
-- Includes reset logic for ipbus
--
-- Dave Newbold, April 2011
--
-- $Id$
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.VComponents.all;
entity clocks_s6_extphy is port(
sysclk_p, sysclk_n: in std_logic;
-- dummy_sysclk : in std_logic;
clk_logic_xtal_o : out std_logic;
clko_125: out std_logic;
clko_ipb: out std_logic;
locked: out std_logic;
rsto_125: out std_logic;
rsto_ipb: out std_logic;
onehz: out std_logic
);
end clocks_s6_extphy;
architecture rtl of clocks_s6_extphy is
signal clk_ipb_i, clk_ipb_b, clk_125_i, clk_125_b, sysclk : std_logic;
-- signal sysclk_in : std_logic;
signal d25, d25_d, dcm_locked: std_logic;
signal rst: std_logic := '1';
signal s_xtal_dcm_locked: std_logic;
signal s_clk_logic_xtal : std_logic;
-- signal clk_400: std_logic;
-- component clock_divider_s6 port(
-- clk: in std_logic;
-- d25: out std_logic;
-- d28: out std_logic
-- );
-- end component;
begin
ibufgds0: IBUFGDS port map(
i => sysclk_p,
ib => sysclk_n,
o => sysclk
);
-- -- Add global clock buffer in sysclk path.
-- bufg_sysclk : BUFG port map (
-- i => sysclk_in,
-- o => sysclk);
bufg_125: BUFG port map(
i => clk_125_i,
o => clk_125_b
);
clko_125 <= clk_125_b;
bufg_ipb: BUFG port map(
i => clk_ipb_i,
o => clk_ipb_b
);
bufg_clk_logic_xtal: BUFG port map(
i => s_clk_logic_xtal,
o => clk_logic_xtal_o
);
clko_ipb <= clk_ipb_b;
dcm0: DCM_CLKGEN
generic map(
CLKIN_PERIOD => 5.0,
CLKFX_MULTIPLY => 5,
CLKFX_DIVIDE => 8,
CLKFXDV_DIVIDE => 4
)
port map(
clkin => sysclk,
clkfx => clk_125_i,
clkfxdv => clk_ipb_i,
locked => dcm_locked,
rst => '0'
);
clkdiv: entity work.clock_divider_s6 port map(
-- clkdiv: entity work.clock_div port map(
clk => sysclk,
-- D17 => open,
d25 => d25,
d28 => onehz
);
process(sysclk)
begin
if rising_edge(sysclk) then
d25_d <= d25;
if d25='1' and d25_d='0' then
rst <= not dcm_locked;
end if;
end if;
end process;
locked <= dcm_locked;
process(clk_ipb_b)
begin
if rising_edge(clk_ipb_b) then
rsto_ipb <= rst;
end if;
end process;
process(clk_125_b)
begin
if rising_edge(clk_125_b) then
rsto_125 <= rst;
end if;
end process;
sys40_gen : BUFIO2
generic map (
DIVIDE => 5, -- DIVCLK divider (1-8)
DIVIDE_BYPASS => FALSE) -- Bypass the divider circuitry (TRUE/FALSE)
port map (
I => SysClk, -- 1-bit input: Clock input (connect to IBUFG)
DIVCLK => s_clk_logic_xtal, -- 1-bit output: Divided clock output
IOCLK => open, -- 1-bit output: I/O output clock
SERDESSTROBE => open); -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
-- Generate 40MHz clock from 200MHz crystal
-- dcmXTAL: DCM_CLKGEN
-- generic map(
-- CLKIN_PERIOD => 5.0,
-- CLKFX_MULTIPLY => 2,
-- CLKFX_DIVIDE => 10,
-- CLKFXDV_DIVIDE => 2
-- )
-- port map(
-- clkin => sysclk,
-- clkfx => s_clk_logic_xtal,
-- clkfxdv => open,
-- locked => s_xtal_dcm_locked,
-- rst => '0'
-- );
--
end rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/common/counterDown.vhd 0000664 0000000 0000000 00000001745 12415504633 0025776 0 ustar 00root root 0000000 0000000 --Counter down
--Outputs: Q<='1' while counting
-- Q<='0' if not counting
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY CounterDown IS
GENERIC(
MAX_WIDTH: positive := 32
);
PORT(
Clk : in std_logic;
Reset : in std_logic;
Load : in std_logic;
InitVal : in std_logic_vector(MAX_WIDTH-1 downto 0);
Count : out Std_logic_vector(MAX_WIDTH-1 downto 0);
Q : out std_logic
);
END ENTITY CounterDown;
architecture rtl of CounterDown is
signal cnt : std_logic_vector(MAX_WIDTH-1 downto 0);
signal Qtmp : std_logic;
begin
Counter: process (Clk, Reset)
begin
if (Reset='1') then
cnt <= (others =>'0');
elsif rising_edge(Clk) then
if (Load='1') then
cnt <= InitVal;
else
if Qtmp='0' then
cnt <= std_logic_vector(unsigned(cnt) - 1);
end if;
end if;
end if;
end process;
Qtmp <= '1' when cnt=(cnt'range=>'0') else
'0';
Count <= cnt;
Q <= Qtmp;
end rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/common/counterWithReset_rtl.vhd 0000664 0000000 0000000 00000006501 12415504633 0027661 0 ustar 00root root 0000000 0000000 --=============================================================================
--! @file counterWithReset_rtl.vhd
--=============================================================================
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- unit name: counterWithReset (counterWithReset / rtl)
--
--! @brief Simple counter with synchronous reset
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date Feb\2012
--
--! @version v0.1
--
--! @details
--!
--! Dependencies:\n
--! None
--!
--! References:\n
--! referenced by ipBusMarocTriggerGenerator \n
--!
--! Modified by:\n
--! Author:
-------------------------------------------------------------------------------
--! \n\nLast changes:\n
--! 5/Mar/12 DGC Changed to use numeric_std\n
--! 26/Feb/14 DGC Added registers to output to aid timing closure.
--!
-------------------------------------------------------------------------------
--! @todo \n
--! \n
---------------------------------------------------------------------------------
--============================================================================
--! Entity declaration for counterWithReset
--============================================================================
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
ENTITY counterWithReset IS
GENERIC (g_COUNTER_WIDTH : integer := 32; --! Number of bits
g_OUTPUT_REGISTERS : integer := 4 --! Number of output registers. Minumum =1. Aids timing closure.
);
PORT
(
clock_i: IN STD_LOGIC; --! rising edge active clock
reset_i: IN STD_LOGIC; --! Active high. syncronous with rising clk
enable_i: IN STD_LOGIC; --! counts when enable=1
result_o: OUT STD_LOGIC_VECTOR ( g_COUNTER_WIDTH-1 downto 0) --! Unsigned integer output
);
END counterWithReset;
ARCHITECTURE rtl OF counterWithReset IS
type t_register_array is array(natural range <>) of UNSIGNED ( g_COUNTER_WIDTH-1 downto 0) ; -- --! Array of arrays for output register...
signal s_output_registers : t_register_array(g_OUTPUT_REGISTERS downto 0) := ( others => ( others => '0')); -- --! Output registers.
BEGIN
--! Process to count up from zero when enable_i is high.
p_counter: PROCESS (clock_i)
BEGIN
IF rising_edge(clock_i) THEN
IF (reset_i = '1') THEN
s_output_registers(0) <= (others => '0');
ELSIF (enable_i='1') THEN
s_output_registers(0) <= s_output_registers(0) + 1;
END IF;
END IF;
END PROCESS p_counter;
--! Generate some output registers. Number controlled by g_OUTPUT_REGISTERS
generate_registers: for v_register in 1 to g_OUTPUT_REGISTERS generate
--! An individual register
p_outputRegister: process (clock_i)
begin -- process p_outputRegister
if rising_edge(clock_i) then
s_output_registers( v_register) <=
s_output_registers( v_register-1);
end if;
end process p_outputRegister;
end generate generate_registers; -- v_register
--! Copy the (registered) result to the output
result_o <= STD_LOGIC_VECTOR(s_output_registers(g_OUTPUT_REGISTERS));
END rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/common/dualSERDES_1to4_rtl.vhd 0000664 0000000 0000000 00000024445 12415504633 0027054 0 ustar 00root root 0000000 0000000 --=============================================================================
--! @file dualSERDES_1to4_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture work.dualSERDES_1to4.rtl
--
--! @brief Two 1:4 Deserializers. One has input delayed w.r.t. other\n
--! based on TDC by Alvaro Dosil\n
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 12:06:53 11/16/12
--
--! @version v0.1
--
--! @details
--! data_o(7) is the most recently arrived data , data_o(0) is the oldest data.
--!
--! Dependencies:\n
--!
--! References:\n
--!
--! Modified by: Alvaro Dosil , alvaro.dosil@usc.es \n
--! Author:
-------------------------------------------------------------------------------
--! \n\nLast changes:\n
--! Separated FSM for calibration control into a separate entity. DGC, 22/Feb/14
-------------------------------------------------------------------------------
--! @todo Implement a periodic calibration sequence\n
--! \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library unisim ;
use unisim.vcomponents.all;
ENTITY dualSERDES_1to4 IS
PORT(
reset_i : IN std_logic; --! Resets IODELAY
--calibrate_i : IN std_logic; --! Starts IODELAY calibration.
data_i : IN std_logic; --! from input buffer.
fastClk_i : IN std_logic; --! 4x fabric clock. e.g. 640MHz
fabricClk_i : IN std_logic; --! clock for output to FPGA. e.g. 160MHz
strobe_i : IN std_logic; --! Strobes once every 4 cycles of fastClk
data_o : OUT std_logic_vector (7 DOWNTO 0); --! Deserialized data. Interleaved between prompt and delayed serdes.
--! data_o(0) is the oldest data
status_o : OUT std_logic_vector(1 downto 0) --! outputs from IODELAY "busy" 0=prompt,1=delayed
);
-- Declarations
END ENTITY dualSERDES_1to4 ;
--
ARCHITECTURE rtl OF dualSERDES_1to4 IS
constant c_S : positive := 4; -- ! SERDES division ratio
signal s_Data_i_d_p : std_logic;
signal s_Data_i_d_d : std_logic;
signal s_busy_idelay_p : std_logic; -- Busy from iodelay.
signal s_busy_idelay_d : std_logic; -- Busy from iodelay.
signal s_busy : std_logic; -- Busy from the two iodelays.
signal s_data_o : std_logic_vector(7 downto 0); --! Deserialized data
signal s_cal : std_logic := '0'; --! Calibration signal
signal s_rst_cal : std_logic := '0'; --! reset after calibration process
BEGIN
-- IODELAYs calibration FSM
IODELAYCal: entity work.IODELAYCal_FSM
port map (
clk_i => fabricClk_i,
startcal_i => reset_i,
busy_i => s_busy,
calibrate_o => s_cal,
reset_o => s_rst_cal);
IODELAY2_Prompt : IODELAY2
generic map (
COUNTER_WRAPAROUND => "STAY_AT_LIMIT" , -- "STAY_AT_LIMIT" or "WRAPAROUND"
DATA_RATE => "SDR", -- "SDR" or "DDR"
DELAY_SRC => "IDATAIN", -- "IO", "ODATAIN" or "IDATAIN"
SERDES_MODE => "NONE", -- , MASTER, SLAVE
IDELAY_TYPE => "VARIABLE_FROM_ZERO",
IDELAY_VALUE => 0 -- Amount of taps for fixed input delay (0-255)
--SIM_TAPDELAY_VALUE=> 10 -- Per tap delay used for simulation in ps
)
port map (
BUSY => s_busy_idelay_p, -- 1-bit output: Busy output after CAL
DATAOUT => s_Data_i_d_p, -- 1-bit output: Delayed data output to ISERDES/input register
DATAOUT2 => open, -- 1-bit output: Delayed data output to general FPGA fabric
DOUT => open, -- 1-bit output: Delayed data output
TOUT => open, -- 1-bit output: Delayed 3-state output
CAL => s_cal, -- 1-bit input: Initiate calibration input
CE => '0', -- 1-bit input: Enable INC input
CLK => fabricClk_i, -- 1-bit input: Clock input
IDATAIN => data_i, -- 1-bit input: Data input (connect to top-level port or I/O buffer)
INC => '0', -- 1-bit input: Increment / decrement input
IOCLK0 => fastClk_i, -- 1-bit input: Input from the I/O clock network
IOCLK1 => '0', -- 1-bit input: Input from the I/O clock network
ODATAIN => '0', -- 1-bit input: Output data input from output register or OSERDES2.
RST => s_rst_cal, -- 1-bit input: reset_i to 1/2 of total delay period
T => '1' -- 1-bit input: 3-state input signal
);
status_o(1) <= s_busy_idelay_p;
IODELAY2_Delayed : IODELAY2
generic map (
COUNTER_WRAPAROUND => "STAY_AT_LIMIT", -- "STAY_AT_LIMIT" or "WRAPAROUND"
DATA_RATE => "SDR", -- "SDR" or "DDR"
DELAY_SRC => "IDATAIN", -- "IO", "ODATAIN" or "IDATAIN"
SERDES_MODE => "NONE", -- , MASTER, SLAVE
IDELAY_TYPE => "VARIABLE_FROM_HALF_MAX",
IDELAY_VALUE => 0, -- Amount of taps for fixed input delay (0-255)
IDELAY2_VALUE => 0 -- Delay value when IDELAY_MODE="PCI" (0-255)
--SIM_TAPDELAY_VALUE => 10 -- Per tap delay used for simulation in ps
)
port map (
BUSY => s_busy_idelay_d, -- 1-bit output: Busy output after CAL
DATAOUT => s_Data_i_d_d, -- 1-bit output: Delayed data output to ISERDES/input register
DATAOUT2 => open, -- 1-bit output: Delayed data output to general FPGA fabric
DOUT => open, -- 1-bit output: Delayed data output
TOUT => open, -- 1-bit output: Delayed 3-state output
CAL => s_cal, -- 1-bit input: Initiate calibration input
CE => '0', -- 1-bit input: Enable INC input
CLK => fabricClk_i, -- 1-bit input: Clock input
IDATAIN => data_i, -- 1-bit input: Data input (connect to top-level port or I/O buffer)
INC => '0', -- 1-bit input: Increment / decrement input
IOCLK0 => fastClk_i, -- 1-bit input: Input from the I/O clock network
IOCLK1 => '0', -- 1-bit input: Input from the I/O clock network
ODATAIN => '0', -- 1-bit input: Output data input from output register or OSERDES2.
RST => s_rst_cal, -- 1-bit input: reset_i to zero
T => '1' -- 1-bit input: 3-state input signal
);
status_o(0) <= s_busy_idelay_d;
s_busy <= s_busy_idelay_p or s_busy_idelay_d;
ISERDES2_Prompt : ISERDES2
generic map (
BITSLIP_ENABLE => FALSE, -- Enable Bitslip Functionality (TRUE/FALSE)
DATA_RATE => "SDR", -- Data-rate ("SDR" or "DDR")
DATA_WIDTH => 4, -- Parallel data width selection (2-8)
INTERFACE_TYPE => "RETIMED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED"
SERDES_MODE => "NONE" -- "NONE", "MASTER" or "SLAVE"
)
port map (
-- Q1 - Q4: 1-bit (each) output Registered outputs to FPGA logic
Q1 => s_Data_o(1), -- Oldest data
Q2 => s_Data_o(3),
Q3 => s_Data_o(5),
Q4 => s_Data_o(7), -- most recent data
--SHIFTOUT => SHIFTOUTsig, -- 1-bit output Cascade output signal for master/slave I/O
VALID => open, -- 1-bit output Output status of the phase detector
BITSLIP => '0', -- 1-bit input Bitslip enable input
CE0 => '1', -- 1-bit input Clock enable input
CLK0 => fastClk_i, -- 1-bit input I/O clock network input
CLK1 => '0', -- 1-bit input Secondary I/O clock network input
CLKDIV => fabricClk_i, -- 1-bit input FPGA logic domain clock input
D => s_Data_i_d_p, -- 1-bit input Input data
IOCE => strobe_i, -- 1-bit input Data strobe_i input
RST => reset_i, -- 1-bit input Asynchronous reset_i input
SHIFTIN => '0' -- 1-bit input Cascade input signal for master/slave I/O
);
ISERDES2_Delayed : ISERDES2
generic map (
BITSLIP_ENABLE => FALSE, -- Enable Bitslip Functionality (TRUE/FALSE)
DATA_RATE => "SDR", -- Data-rate ("SDR" or "DDR")
DATA_WIDTH => 4, -- Parallel data width selection (2-8)
INTERFACE_TYPE => "RETIMED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED"
SERDES_MODE => "NONE" -- "NONE", "MASTER" or "SLAVE"
)
port map (
-- Q1 - Q4: 1-bit (each) output Registered outputs to FPGA logic
Q1 => s_Data_o(0), -- oldest data
Q2 => s_Data_o(2),
Q3 => s_Data_o(4),
Q4 => s_Data_o(6), -- most recent data
--SHIFTOUT => SHIFTOUTsig, -- 1-bit output Cascade output signal for master/slave I/O
VALID => open, -- 1-bit output Output status of the phase detector
BITSLIP => '0', -- 1-bit input Bitslip enable input
CE0 => '1', -- 1-bit input Clock enable input
CLK0 => fastClk_i, -- 1-bit input I/O clock network input
CLK1 => '0', -- 1-bit input Secondary I/O clock network input
CLKDIV => fabricClk_i, -- 1-bit input FPGA logic domain clock input
D => s_Data_i_d_d, -- 1-bit input Input data
IOCE => strobe_i, -- 1-bit input Data strobe_i input
RST => reset_i, -- 1-bit input Asynchronous reset_i input
SHIFTIN => '0' -- 1-bit input Cascade input signal for master/slave I/O
);
reg_out : process(fabricClk_i)
begin
if rising_edge(fabricClk_i) then
Data_o <= s_Data_o;
end if;
end process;
END ARCHITECTURE rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/common/eventBuffer_rtl.vhd 0000664 0000000 0000000 00000016453 12415504633 0026625 0 ustar 00root root 0000000 0000000 --=============================================================================
--! @file eventBuffer_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.eventBuffer.rtl
--
--! @brief Stores input words (64bits) for readout over IPBus. \n
--! Uses a FIFO ( 64bits at input, 32 bits at output )\n
--! Address map:\n
--! 0x0000 - FIFO data\n
--! 0x0001 - FIFO fill level\n
--! 0x0010 - FIFO status/control:\n
--! Writing Bit-0 resets pointers.\n
--! Reading bit-1 returns "prog_full" flag
--
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 15:24:50 11/13/12
--
--! @version v0.1
--
--! @details
--!
--!
--! Dependencies:\n
--!
--! References:\n
--!
--! Modified by: Alvaro Dosil , alvaro.dosil@usc.es \n
--! Author:
-------------------------------------------------------------------------------
--! \n\nLast changes:\n
-------------------------------------------------------------------------------
--! @todo \n
--! \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
ENTITY eventBuffer IS
GENERIC(
g_EVENT_DATA_WIDTH : positive := 64;
g_IPBUS_WIDTH : positive := 32;
g_WRITE_COUNTER_WIDTH : positive := 15;
g_READ_COUNTER_WIDTH : positive := 16
);
PORT(
clk_4x_logic_i : IN std_logic;
data_strobe_i : IN std_logic; -- Indicates data to transfer
event_data_i : IN std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus;
ipbus_reset_i : IN std_logic;
strobe_4x_logic_i : IN std_logic;
--trigger_count_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not used yet.
rst_fifo_o : OUT std_logic; --! rst signal to first level fifos
buffer_full_o : OUT std_logic; --! Goes high when event buffer almost full
ipbus_o : OUT ipb_rbus;
logic_reset_i : IN std_logic -- reset buffers when high. Synch withclk_4x_logic
);
-- Declarations
END ENTITY eventBuffer ;
--
ARCHITECTURE rtl OF eventBuffer IS
-- write addr count width = 13 , read addr count = 14.
--! Counters for input and ouput to/from FIFO
signal s_wr_data_count , s_wr_data_count_reg : std_logic_vector(g_WRITE_COUNTER_WIDTH-1 downto 0) := (others =>'0');
signal s_rd_data_count : std_logic_vector(g_READ_COUNTER_WIDTH-1 downto 0) := (others =>'0');
--signal s_fifo_fill_level : unsigned(g_READ_COUNTER_WIDTH-1 downto 0) := (others =>'0'); -- read-counter - 2*write_count
signal s_fifo_fill_level : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others =>'0'); -- read-counter - 2*write_count
signal s_write_strobe : std_logic := '0';
signal s_rst_fifo, s_rst_fifo_ipb : std_logic := '0'; -- ! Take high to reset FIFO pointers.
signal s_fifo_prog_full : std_logic := '0'; -- ! Controlled by programmable-full flag of FIFO core
signal s_fifo_rd_en : std_logic := '0'; -- ! Take high to clock data out of FIFO
signal s_fifo_dout : std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- ! Output from FIFO ( fall-through mode)
signal s_fifo_valid : std_logic := '1'; -- ! High when data in FIFO
signal s_fifo_full, s_fifo_almost_full, s_fifo_empty, s_fifo_almost_empty : std_logic := '0'; -- ! full and empty FIFO flags
signal s_fifo_status_ipb , s_fifo_fill_level_d1 : std_logic_vector(ipbus_o.ipb_rdata'range) := (others => '0'); -- data registered onto IPBus clock
BEGIN
-----------------------------------------------------------------------------
-- IPBus IO
-----------------------------------------------------------------------------
--! Generate FIFO read enable
s_fifo_rd_en <= '1' when ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '0' and ipbus_i.ipb_addr(1 downto 0) = "00" else '0';
s_fifo_valid <= '1';
--! Generate IPBus ACK
ipbus_o.ipb_ack <= (ipbus_i.ipb_strobe and not s_fifo_rd_en) or (s_fifo_valid and s_fifo_rd_en);
ipbus_o.ipb_err <= '0';
--! Multiplex output data.
with ipbus_i.ipb_addr(1 downto 0) select ipbus_o.ipb_rdata <=
s_fifo_dout when "00",
s_fifo_fill_level when "01",
s_fifo_status_ipb when "10",
(others => '1') when others;
ipbus_write: process (ipbus_clk_i)
begin -- process ipbus_write
if rising_edge(ipbus_clk_i) then
s_rst_fifo_ipb <= '0';
if ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_addr(1 downto 0) = "10" and ipbus_i.ipb_write = '1' then
s_rst_fifo_ipb <= '1';
end if;
-- Register data onto IPBus clock domain to ease timing closure.
s_fifo_status_ipb <= X"000000" & "000" & s_fifo_prog_full & s_fifo_full & s_fifo_almost_full & s_fifo_almost_empty & s_fifo_empty;
--s_fifo_fill_level_d1 <= X"0000" & "00" & std_logic_vector(s_fifo_fill_level);
s_fifo_fill_level <= X"0000" & s_rd_data_count;
end if;
end process ipbus_write;
rst_fifo_o <= s_rst_fifo_ipb;
s_rst_fifo <= s_rst_fifo_ipb or logic_reset_i;
-----------------------------------------------------------------------------
-- FIFO and fill-level calculation
-----------------------------------------------------------------------------
-- Instantiate a buffer to store the data. 64-bit on input, 32-bit on output.
event_fifo : entity work.tlu_event_fifo
PORT MAP (
rst => s_rst_fifo,
wr_clk => clk_4x_logic_i,
rd_clk => ipbus_clk_i,
din => event_data_i,
wr_en => data_strobe_i,
rd_en => s_fifo_rd_en,
dout => s_fifo_dout,
full => s_fifo_full,
almost_full => s_fifo_almost_full,
empty => s_fifo_empty,
almost_empty => s_fifo_almost_empty,
rd_data_count => s_rd_data_count,
wr_data_count => s_wr_data_count,
prog_full => s_fifo_prog_full
);
buffer_full_o <= s_fifo_prog_full;
-- Transfer write-data-count to read clock domain
register_counter_inst : entity work.registerCounter
generic map (
g_DATA_WIDTH => g_WRITE_COUNTER_WIDTH)
port map (
clk_input_i => clk_4x_logic_i,
data_i => s_wr_data_count,
data_o => s_wr_data_count_reg,
clk_output_i => ipbus_clk_i
);
----! Calculate the number of words in the FIFO .
---- (only valid if no buffer overflow.)
---- Each input word (64 bits) is the same as two output words (32 bits) so
---- multiply s_wr_data_count by 2 before subraction
--! wr_data_count and rd_data_count provide exactly the same information but in different clock domains
--s_fifo_fill_level <= (unsigned(std_logic_vector(s_wr_data_count_reg) & "0") - unsigned(s_rd_data_count));
--s_fifo_fill_level <= unsigned(s_rd_data_count);
END ARCHITECTURE rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/common/eventFormatter_rtl.vhd 0000664 0000000 0000000 00000051756 12415504633 0027364 0 ustar 00root root 0000000 0000000 --=============================================================================
--! @file eventFormatter_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.eventFormatter.rtl
--
--! @brief Takes the data delivered on each trigger and turns it into a 64-bit
--! word\n
--! \n
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 15:10:35 11/09/12
--
--! @version v0.1
--
--! @details
--!
--!
--! Dependencies:\n
--!
--! References:\n
--!
--! Modified by: Alvaro Dosil , alvaro.dosil@usc.es \n
--! Author:
-------------------------------------------------------------------------------
--! \n\nLast changes:\n
--! 27/Feb/14 DGC Change "If" when setting s_word2 to a case ... generate. Questasim
--! doesn't like having an if that can take an array out of bounds.
-------------------------------------------------------------------------------
--! @todo Add more input data: \n
--! a) shutter signals. One per DUT. ?? \n
--! b) input levels ( for recording edge data ). Record rising and falling edges\n
--! c) veto levels. One per DUT. Record rising and falling edges.\n
--! \n
--! Add backpressure output if short FIFOs fill up? But many inputs won't
--! respond - e.g. scintillator inputs. This data will be lost....
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.fmcTLU.all;
USE work.ipbus.all;
ENTITY eventFormatter IS
GENERIC(
g_EVENT_DATA_WIDTH : positive := 64;
g_IPBUS_WIDTH : positive := 32;
g_COUNTER_TRIG_WIDTH : positive := 32;
g_COUNTER_WIDTH : positive := 12;
g_EVTTYPE_WIDTH : positive := 4; -- Width of the event type word
--g_NUM_INPUT_TYPES : positive := 4; -- Number of different input types (trigger, shutter, edge...)
g_NUM_EDGE_INPUTS : positive := 4; -- Number of edge inputs
g_NUM_TRIG_INPUTS : positive := 5 -- Number of trigger inputs
);
PORT(
clk_4x_logic_i : IN std_logic; -- ! Rising edge active
ipbus_clk_i : IN std_logic;
logic_strobe_i : IN std_logic; -- ! Pulses high once every 4 cycles of clk_4x_logic
logic_reset_i : IN std_logic; -- goes high to reset counters. Synchronous with clk_4x_logic
rst_fifo_i : IN std_logic; --! Reset fifos
buffer_full_i : IN std_logic; -- Buffer full signal from main buffer
trigger_i : IN std_logic; --! goes high to load trigger data. One cycle of clk_4x_logic
trigger_times_i : IN t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- Array of trigger times ( w.r.t. logic_strobe)
trigger_inputs_fired_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- high for each input that "fired"
trigger_cnt_i : IN std_logic_vector (g_COUNTER_TRIG_WIDTH-1 DOWNTO 0);
shutter_i : IN std_logic;
shutter_cnt_i : IN std_logic_vector(g_COUNTER_WIDTH-1 DOWNTO 0);
spill_i : IN std_logic;
spill_cnt_i : IN std_logic_vector(g_COUNTER_WIDTH-1 DOWNTO 0);
edge_rise_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when rising edge
edge_fall_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when falling edge
edge_rise_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
edge_fall_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
ipbus_i : IN ipb_wbus;
ipbus_o : OUT ipb_rbus;
data_strobe_o : OUT std_logic; -- goes high when data ready to load into event buffer
event_data_o : OUT std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
event_number_i : in std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);
trigger_count_o : OUT std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0)
);
-- Declarations
END ENTITY eventFormatter ;
--
ARCHITECTURE rtl OF eventFormatter IS
-- add to ports
-- trigger_i : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when trigger active
-- signal inputs_triggered_i : std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when trigger active
-- signal logic_reset_i : std_logic := '0'; -- put into ports...
constant c_NUM_INPUT_TYPES : positive := 3+g_NUM_EDGE_INPUTS; -- Number of different input types (trigger, shutter, edge(0), edge(1)...)
type t_fifo_io is array(natural range <>) of std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0);
type t_evttype is array(natural range <>) of std_logic_vector(g_EVTTYPE_WIDTH-1 downto 0);
type t_var is array(natural range <>) of std_logic_vector(g_COUNTER_WIDTH-1 downto 0);
-- Input types:
-- 0 - Trigger
-- 1 - Shutter
-- 2 - Edge signal
-- 3 - Spill
--! delayed strobes
signal s_event_strobe , s_event_strobe_d1 ,s_event_strobe_d2 ,s_event_strobe_d3 , s_event_strobe_d3_opt : std_logic := '0';
signal shutter_i_d1, shutter_i_d2, edge_i_d1, edge_i_d2, spill_i_d1, spill_i_d2 : std_logic := '0';
signal s_evttype : t_evttype(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>(others=>'0')); -- Event type
-- 0000 trigger internal
-- 0001 trigger external
-- 0010 shutter falling
-- 0011 shutter rising
-- 0100 edge falling
-- 0101 edge rising
-- 0111 spill on
-- 0110 spill off
signal s_var : t_var(3+g_NUM_EDGE_INPUTS-1 downto 0) :=(others=>(others=>'0')); -- 12b different in every input
signal s_FIFO_wr : std_logic_vector(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- FIFO write signal
signal s_FIFO_rd : std_logic_vector(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- FIFO read signals
signal s_FIFO_rd_d1 : std_logic_vector(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- FIFO read signals delayed
signal s_FIFO_rd_d2 : std_logic_vector(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- FIFO read signals delayed
signal s_FIFO_rd_mask : unsigned(3+g_NUM_EDGE_INPUTS-1 downto 0) := (0 =>'1',others=>'0'); --(3+g_NUM_EDGE_INPUTS-1 =>'1',others=>'0'); -- FIFO read mask
signal s_FIFO_empty : std_logic_vector(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- FIFO empty signals
signal s_FIFO_full : std_logic_vector(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- FIFO full signals
signal s_FIFO_i : t_fifo_io(3+g_NUM_EDGE_INPUTS-1 downto 0) :=(others=>(others=>'0')); -- FIFO input data
signal s_FIFO_o : t_fifo_io(3+g_NUM_EDGE_INPUTS-1 downto 0) :=(others=>(others=>'0')); -- FIFO output data
signal s_data_o : std_logic_vector(g_EVENT_DATA_WIDTH-1 DOWNTO 0); -- Multiplexed data from FIFOs
--signal s_data_o_mask : unsigned(3+g_NUM_EDGE_INPUTS-1 downto 0) := (g_NUM_TRIG_INPUTS+g_NUM_EDGE_INPUTS-1 =>'1',others=>'0'); -- Output data mask
--constant c_COARSE_TIMESTAMP_WIDTH : positive := 48; -- ! Number of bits in 40MHz timestamp
constant c_COARSE_TIMESTAMP_L_WIDTH : positive := 16; -- ! Number of bits in 40MHz timestamp lower bits
constant c_COARSE_TIMESTAMP_H_WIDTH : positive := 32; -- ! Number of bits in 40MHz timestamp higher bits
signal s_coarse_timestamp_l, s_coarse_timestamp_l_d1, s_coarse_timestamp_l_d2, s_coarse_timestamp_l_d3 : unsigned(c_COARSE_TIMESTAMP_L_WIDTH-1 downto 0) := (others => '0'); -- 40MHz timestamp.
signal s_coarse_timestamp_h, s_coarse_timestamp_h_d1, s_coarse_timestamp_h_d2, s_coarse_timestamp_h_d3 : unsigned(c_COARSE_TIMESTAMP_H_WIDTH-1 downto 0) := (others => '0'); -- 40MHz timestamp.
signal s_timestamp_h_en : std_logic:='0';
-- signal s_event_number : unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); -- increment after each post-veto trigger.
signal s_word0 , s_word1, s_word2 : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0'); -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
signal s_word0_d1 , s_word1_d1, s_word2_d1 : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0'); -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
signal s_word0_d2 , s_word1_d2, s_word2_d2 : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0'); -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
signal s_word0_d3 , s_word1_d3, s_word2_d3 : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0'); -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
signal trigger_inputs_fired_d1 : std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0) := (others => '0');
signal trigger_times_d1 : t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0) := (others => (others=>'0'));
signal s_ipbus_ack : std_logic := '0'; -- used to produce a delayed IPBus ack signal
signal s_enable_record, s_enable_record_ipb : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (2 downto 0 => '1', others=>'0'); -- Enable data record
signal s_enable_trigger : std_logic := '1'; -- Enable trigger record
signal s_enable_shutter : std_logic := '1'; -- Enable shutter record
signal s_enable_spill : std_logic := '1'; -- Enable spill record
signal s_enable_edges : std_logic_vector(g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- Enable edges record
BEGIN
-----------------------------------------------------------------------------
-- IPBus write
-----------------------------------------------------------------------------
ipbus_write: process (ipbus_clk_i)
begin -- process ipb_clk_i
if rising_edge(ipbus_clk_i) then
if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1') then
case ipbus_i.ipb_addr(2 downto 0) is
when "000" => s_enable_record_ipb <= ipbus_i.ipb_wdata ; -- Enable data record
when others => null;
end case;
end if;
s_ipbus_ack <= ipbus_i.ipb_strobe and not s_ipbus_ack;
end if;
end process ipbus_write;
ipbus_o.ipb_ack <= s_ipbus_ack;
ipbus_o.ipb_err <= '0';
-----------------------------------------------------------------------------
-- IPBUS read
-----------------------------------------------------------------------------
with ipbus_i.ipb_addr(2 downto 0) select
ipbus_o.ipb_rdata <=
s_enable_record_ipb when "000",
(others => '1') when others;
-- Change clock domain
p_signals_clk_domain: process (clk_4x_logic_i )
begin -- process p_internal_triggers
if rising_edge(clk_4x_logic_i) then
s_enable_record <= s_enable_record_ipb;
s_enable_trigger <= s_enable_record(0);
s_enable_shutter <= s_enable_record(1);
s_enable_spill <= s_enable_record(2);
s_enable_edges <= s_enable_record(g_NUM_EDGE_INPUTS-1+3 downto 3);
end if;
end process p_signals_clk_domain;
-- purpose: generate delayed strobes and write enable flags to the FIFOs
-- type : combinational
-- inputs : clk_4x_logic_i , s_FIFO_rd
-- outputs: s_event_strobe_d1 , s_event_strobe_d2 , s_event_strobe_d3 , s_FIFO_rd_d , s_**_evttype
p_ff_rst: process (clk_4x_logic_i)
begin -- process p_generate_strobes
if rst_fifo_i = '1' then
s_event_strobe_d1 <= '0';
s_event_strobe_d2 <= '0';
s_event_strobe_d3 <= '0';
shutter_i_d1 <= '0';
shutter_i_d2 <= '0';
spill_i_d1 <= '0';
spill_i_d2 <= '0';
s_FIFO_rd_d1 <= (others=>'0');
s_FIFO_rd_d2 <= (others=>'0');
elsif rising_edge(clk_4x_logic_i) then
s_event_strobe_d1 <= trigger_i and s_enable_trigger and not s_FIFO_full(0);
s_event_strobe_d2 <= s_event_strobe_d1;
s_event_strobe_d3 <= s_event_strobe_d2;
shutter_i_d1 <= shutter_i and s_enable_shutter and not s_FIFO_full(1);
shutter_i_d2 <= shutter_i_d1;
spill_i_d1 <= spill_i and s_enable_spill and not s_FIFO_full(3+g_NUM_EDGE_INPUTS-1);
spill_i_d2 <= spill_i_d1;
s_FIFO_rd_d1 <= s_FIFO_rd;
s_FIFO_rd_d2 <= s_FIFO_rd_d1;
end if;
end process p_ff_rst;
p_ff: process (clk_4x_logic_i)
begin -- process p_generate_strobes
if rising_edge(clk_4x_logic_i) then
for i in 0 to g_NUM_TRIG_INPUTS-1 loop
trigger_inputs_fired_d1(g_NUM_TRIG_INPUTS-1-i) <= trigger_inputs_fired_i(i);
end loop;
trigger_times_d1 <= trigger_times_i;
s_word0_d1 <= s_word0;
s_word1_d1 <= s_word1;
s_word1_d2 <= s_word1_d1;
s_word2_d1 <= s_word2;
s_word2_d2 <= s_word2_d1;
s_word2_d3 <= s_word2_d2;
s_coarse_timestamp_l_d1 <= s_coarse_timestamp_l;
s_coarse_timestamp_l_d2 <= s_coarse_timestamp_l_d1;
s_coarse_timestamp_l_d3 <= s_coarse_timestamp_l_d2;
s_coarse_timestamp_h_d1 <= s_coarse_timestamp_h;
s_coarse_timestamp_h_d2 <= s_coarse_timestamp_h_d1;
s_coarse_timestamp_h_d3 <= s_coarse_timestamp_h_d2;
end if;
end process;
-- If there are more than 4 trigger inputs we need to fill a second word.
-- .. do this by having an optional strobe.
-- If 4 or fewer trigger inputs, just leave s_event_strobe_d3_opt at zero..
gen_strobe_d3: if (g_NUM_TRIG_INPUTS > 4) generate
s_event_strobe_d3_opt <= s_event_strobe_d3;
end generate;
-------------------------------------------------------------------------------
-- Trigger event formater
-------------------------------------------------------------------------------
s_evttype(0) <= "0000" when unsigned(trigger_inputs_fired_d1) = 0 and trigger_i = '1' else
"0001";
s_var(0) <= trigger_inputs_fired_d1 & std_logic_vector(to_unsigned(0,s_var(0)'length-g_NUM_TRIG_INPUTS));
--s_word0 <= s_evttype(0) & s_var(0) & std_logic_vector(s_coarse_timestamp_d2);
s_word0 <= s_evttype(0) & s_var(0) & std_logic_vector(s_coarse_timestamp_h_d2) & std_logic_vector(s_coarse_timestamp_l_d2);
s_word1 <= "000" & trigger_times_d1(0) & "000" & trigger_times_d1(1) &
"000" & trigger_times_d1(2) & "000" & trigger_times_d1(3) &
trigger_cnt_i;
-- Different number of trigger inputs require packing into s_word2 in
-- different ways.
-- Do this in a generate since g_NUM_TRIG_INPUTS is static and
-- Questasim doesn't like refering to indices outside declared range.
s_word2 <= (others=>'0'); -- Set all bits to zero
-- then override with the following assignments....
gen_word2: for v_trigInput in 4 to g_NUM_TRIG_INPUTS-1 generate
s_word2( (((11-v_trigInput)*8)+c_NUM_TIME_BITS-1) downto ((11-v_trigInput)*8) ) <= trigger_times_i(v_trigInput);
end generate;
--! Could also output data on trigger_i , but let's use the delayed signals. \n
--! The counters are one cycle delayed from the signal generation
p_fifo_i : process (clk_4x_logic_i)
begin
if rising_edge(clk_4x_logic_i) then
s_FIFO_wr(0) <= s_event_strobe_d1 or s_event_strobe_d2 or s_event_strobe_d3_opt;
if s_event_strobe_d1 = '1' then
s_FIFO_i(0) <= s_word0_d1;
elsif s_event_strobe_d2 = '1' then
s_FIFO_i(0) <= s_word1_d2;
elsif s_event_strobe_d3_opt = '1' then
s_FIFO_i(0) <= s_word2_d3;
else
s_FIFO_i(0) <= (others=>'0');
end if;
end if;
end process;
s_evttype(1) <= "0011" when shutter_i_d1 = '1' and shutter_i_d2 = '0' else
"0010" when shutter_i_d1 = '0' and shutter_i_d2 = '1' else
(others=>'0');
s_var(1) <= shutter_cnt_i;
edge_formatting : for i in 0 to (g_NUM_EDGE_INPUTS-1) generate
s_evttype(i+2) <= "0101" when edge_rise_i(i) = '1' else
"0100" when edge_fall_i(i) = '1' else
(others=>'0');
s_var(i+2) <= std_logic_vector(to_unsigned(i,4)) & "000" & edge_rise_time_i(i) when edge_rise_i(i) = '1' else
std_logic_vector(to_unsigned(i,4)) & "000" & edge_fall_time_i(i) when edge_fall_i(i) = '1' else
(others=>'0');
end generate;
s_evttype(3+g_NUM_EDGE_INPUTS-1) <= "0111" when spill_i_d1 = '1' and spill_i_d2 = '0' else
"0110" when spill_i_d1 = '0' and spill_i_d2 = '1' else
(others=>'0');
s_var(3+g_NUM_EDGE_INPUTS-1) <= spill_cnt_i;
p_fifo_wr : process (clk_4x_logic_i)
begin
if rising_edge(clk_4x_logic_i) then
s_FIFO_wr(1) <= shutter_i_d1 xor shutter_i_d2;
s_FIFO_wr(3+g_NUM_EDGE_INPUTS-1) <= spill_i_d1 xor spill_i_d2;
end if;
end process;
gen_fifo_wr_edge : for i in 0 to (g_NUM_EDGE_INPUTS-1) generate
p_fifo_wr : process (clk_4x_logic_i)
begin
if rising_edge(clk_4x_logic_i) then
s_FIFO_wr(i+2) <= (edge_rise_i(i) or edge_fall_i(i)) and s_enable_edges(i) and not s_FIFO_full(i+2);
end if;
end process;
end generate;
gen_FIFO_i : for i in 1 to 3+g_NUM_EDGE_INPUTS-1 generate
p_fifo_i_n : process (clk_4x_logic_i)
begin
if rising_edge(clk_4x_logic_i) then
s_FIFO_i(i) <= s_evttype(i) & s_var(i) & std_logic_vector(s_coarse_timestamp_h_d2) & std_logic_vector(s_coarse_timestamp_l_d2);
end if;
end process;
end generate gen_FIFO_i;
-------------------------------------------------------------------------------
-- first level of FIFOs
-------------------------------------------------------------------------------
gen_FIFOs : for i in 0 to 3+g_NUM_EDGE_INPUTS-1 generate
begin
FIFO_i : entity work.FIFO
PORT MAP (
clk => clk_4x_logic_i,
rst => rst_fifo_i, --logic_reset_i,
din => s_FIFO_i(i),
wr_en => s_FIFO_wr(i),
rd_en => s_FIFO_rd(i),
dout => s_FIFO_o(i),
full => open,
prog_full => s_FIFO_full(i),
empty => s_FIFO_empty(i)
);
end generate gen_FIFOs;
-------------------------------------------------------------------------------
-- Reading FIFOs and multiplexing them to the output
-------------------------------------------------------------------------------
-- NOTE: Rewrite this
-- Mux to send the read signal to only one FIFO. Priority order: trigger, shutter, edge, spill
-- every trigger word will be read before jump to other data
p_FIFO_rd: process (rst_fifo_i, s_FIFO_empty,s_FIFO_rd_mask, buffer_full_i)
begin -- process p_generate_strobes
s_FIFO_rd <= (others=>'0');
if buffer_full_i = '0' and rst_fifo_i = '0' then
l_FIFO_rd: for i in 0 to 3+g_NUM_EDGE_INPUTS-1 loop
if s_FIFO_empty(i) = '0' then
s_FIFO_rd <= std_logic_vector(s_FIFO_rd_mask sll i);
exit l_FIFO_rd;
end if;
end loop;
end if;
end process;
p_data_o : process (clk_4x_logic_i)
begin
if rising_edge(clk_4x_logic_i) then
if s_FIFO_rd_d1 = "0000001" then
s_data_o <= s_FIFO_o(0);
elsif s_FIFO_rd_d1 = "0000010" then
s_data_o <= s_FIFO_o(1);
elsif s_FIFO_rd_d1 = "0000100" then
s_data_o <= s_FIFO_o(2);
elsif s_FIFO_rd_d1 = "0001000" then
s_data_o <= s_FIFO_o(3);
elsif s_FIFO_rd_d1 = "0010000" then
s_data_o <= s_FIFO_o(4);
elsif s_FIFO_rd_d1 = "0100000" then
s_data_o <= s_FIFO_o(5);
elsif s_FIFO_rd_d1 = "1000000" then
s_data_o <= s_FIFO_o(6);
else
s_data_o <= (others=>'0');
end if;
end if;
end process;
-- Send out the data and the strobe signal
event_data_o <= s_data_o;
data_strobe_o <= '0' when s_FIFO_rd_d2 = std_logic_vector(to_unsigned(0,s_FIFO_rd_d2'length)) else
'1';
-- purpose: Keep track of 40MHz timestamp
-- type : sequential
-- inputs : clk_4x_logic_i
-- outputs:
p_timestamp_l: process (clk_4x_logic_i, logic_reset_i)
begin -- process p_timestamp
if rising_edge(clk_4x_logic_i) then -- rising clock edge
if logic_reset_i = '1' then
s_coarse_timestamp_l <= ( others => '0');
elsif ( logic_strobe_i = '1' ) then
s_coarse_timestamp_l <= s_coarse_timestamp_l + 1;
end if;
end if;
end process p_timestamp_l;
s_timestamp_h_en <= '1' when s_coarse_timestamp_l = x"ffff" else
'0';
p_timestamp_h: process (clk_4x_logic_i, logic_reset_i)
begin -- process p_timestamp
if rising_edge(clk_4x_logic_i) then -- rising clock edge
if logic_reset_i = '1' then
s_coarse_timestamp_h <= ( others => '0');
elsif ( logic_strobe_i = '1' ) and (s_timestamp_h_en='1') then
s_coarse_timestamp_h <= s_coarse_timestamp_h + 1;
end if;
end if;
end process p_timestamp_h;
-- Generate data in format decided at DESY. Put out two strobes for the
-- two 64 bit words.
-- get trigger inputs to also generate a global time-stamp ??
-- add trigger_inputs_active_i array (to indicate which triggers fired)
END ARCHITECTURE rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/common/handshakes_rtl.vhd 0000664 0000000 0000000 00000020143 12415504633 0026452 0 ustar 00root root 0000000 0000000 --=============================================================================
--! @file handshakes_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Santiago de Compostela, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.handshakes.rtl
--
--! @brief Handshakes between TLU and DUTs. \n
--
--
--! @author Alvaro Dosil , alvaro.dosil@usc.es
--
--! @date 12:08:30 25/06/14
--
--! @version v0.1
--
--! @details
--!
--!
--! Dependencies:\n
--!
--! References:\n
--!
--! Modified by: \n
--! Author:
-------------------------------------------------------------------------------
--! \n\nLast changes:\n
-------------------------------------------------------------------------------
--! @todo \n
--! \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
use work.ipbus_reg_types.all;
ENTITY handshakes IS
GENERIC(
g_IPBUS_WIDTH : positive := 32
);
PORT(
clk_i : IN std_logic;
Trigger_i : IN std_logic;
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus;
ipbus_reset_i : IN std_logic;
ipbus_o : OUT ipb_rbus;
logic_reset_i : IN std_logic;
Busy_i : IN std_logic;
AIDAhandshake_o : OUT std_logic; -- running an AIDA handshake or the old EUDET handshake
Trigger_o : OUT std_logic;
rst_or_clk_o : OUT std_logic -- CONT in schematics
);
-- Declarations
END ENTITY handshakes ;
--
ARCHITECTURE rtl OF handshakes IS
signal s_handshakeEnabled : std_logic_vector(g_IPBUS_WIDTH-1 downto 0);
signal s_Shutter, s_T0sync : std_logic;
signal s_Trigger, s_TrigAux : std_logic := '0';
signal s_Busy, s_Busy_d1, s_Busy_d2, s_Busy_d3 : std_logic;
signal TPx3_T0syncLen : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := x"00000004"; --! T0-sync length
signal TPx3_Start_T0sync : std_logic; --! Flag to start the T0-sync signal
signal s_Veto : std_logic := '0';
signal s_WU : std_logic := '0';
signal s_NMaxPulses : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := (others=>'0');
signal s_SuDTime : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := (others=>'0');
signal s_PulseLen : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := x"00000001";
signal s_IpDTime : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := x"00000001";
signal s_RearmTime : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := x"10000000";
signal s_PulseDelay : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := (others=>'0');
signal s_MaxPulses : std_logic;
signal s_pulse : std_logic;
constant c_N_CTRL : positive := 13;
constant c_N_STAT : positive := 13;
signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
signal s_control_from_ipbus,s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
BEGIN
-----------------------------------------------------------------------------
-- IPBus interface
-----------------------------------------------------------------------------
ipbus_registers: entity work.ipbus_ctrlreg_v
generic map(
N_CTRL => c_N_CTRL,
N_STAT => c_N_STAT
)
port map(
clk => ipbus_clk_i,
reset=> '0',--ipbus_reset_i ,
ipbus_in=> ipbus_i,
ipbus_out=> ipbus_o,
d=> s_sync_status_to_ipbus,
q=> s_control_from_ipbus,
stb=> open
);
-- Synchronize registers from logic clock to ipbus.
sync_status: entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => c_N_STAT )
port map (
clk_input_i => clk_i,
data_i => s_status_to_ipbus,
data_o => s_sync_status_to_ipbus,
clk_output_i => ipbus_clk_i);
-- Synchronize registers from logic clock to ipbus.
sync_ctrl: entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => c_N_CTRL )
port map (
clk_input_i => ipbus_clk_i,
data_i => s_control_from_ipbus,
data_o => s_sync_control_from_ipbus,
clk_output_i => clk_i);
-----------------------------------------------------------------------------
-- Logic not ready to use
-----------------------------------------------------------------------------
--Map the control registers
s_handshakeEnabled <= s_sync_control_from_ipbus(0);
s_status_to_ipbus(0) <= s_handshakeEnabled;
-- No handshake registers
s_NMaxPulses <= s_sync_control_from_ipbus(5);
s_SuDTime <= s_sync_control_from_ipbus(6);
s_PulseLen <= s_sync_control_from_ipbus(7);
s_IpDTime <= s_sync_control_from_ipbus(8);
s_RearmTime <= s_sync_control_from_ipbus(9);
s_PulseDelay <= s_sync_control_from_ipbus(10);
s_Veto <= s_sync_control_from_ipbus(11)(0);
s_WU <= s_sync_control_from_ipbus(11)(1);
s_status_to_ipbus(5) <= s_NMaxPulses;
s_status_to_ipbus(6) <= s_SuDTime;
s_status_to_ipbus(7) <= s_PulseLen;
s_status_to_ipbus(8) <= s_IpDTime;
s_status_to_ipbus(9) <= s_RearmTime;
s_status_to_ipbus(10) <= s_PulseDelay;
s_status_to_ipbus(11) <= x"0000000"& "00" & s_WU & s_Veto;
s_status_to_ipbus(12) <= x"0000000"& "000" & s_MaxPulses;
-- TPx3 registers
TPx3_Start_T0sync <= s_sync_control_from_ipbus(1)(0);
TPx3_T0syncLen <= x"00000001" when s_sync_control_from_ipbus(2) EUDET handshake.
-- All handshakes with s_handshakeEnabled(3)='0' are AIDA handshakes
-- No Handshake (GPP)
No_handshake: entity work.GPP
GENERIC MAP(
g_IPBUS_WIDTH => g_IPBUS_WIDTH)
PORT MAP(
clk_i => clk_i,
Enable_i => not (s_Busy or s_Veto),
Reset_i => logic_reset_i,
RstPulsCnt_i => '0',
Trigger_i => s_Trigger,
NMaxPulses_i => s_NMaxPulses,
SuDTime_i => s_SuDTime,
PulsLen_i => s_PulseLen,
IpDTime_i => s_IpDTime,
RearmTime_i => s_RearmTime,
Force_PullDown_i => s_Busy or s_Veto,
WU_i => s_WU,
PulseDelay_i => s_PulseDelay,
event_number_o => open,
MaxPulses_o => s_MaxPulses,
Pulse_o => s_pulse,
Pulse_d_o => open);
-- TPx3 Handshake
TPx3_logic: entity work.TPx3Logic
PORT MAP(
clk_i => clk_i,
Start_T0sync_i => TPx3_Start_T0sync,
T0syncLen_i => TPx3_T0syncLen,
logic_reset_i => logic_reset_i,
Busy_i => s_Busy,
Veto_i => s_Veto,
Shutter_o => s_Shutter,
T0sync_o => s_T0sync
);
END ARCHITECTURE rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/common/i2c_master_rtl.vhd 0000664 0000000 0000000 00000005715 12415504633 0026401 0 ustar 00root root 0000000 0000000 --=============================================================================
--! @file i2c_master_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture work.i2c_master.rtl
--
--! @brief Wraps the Wishbone I2C master in a wrapper where the IPBus signals\n
--! are bundled together in a record\n
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 17:22:12 11/30/12
--
--! @version v0.1
--
--! @details
--!
--!
--! Dependencies:\n
--!
--! References:\n
--!
--! Modified by:\n
--! Author:
-------------------------------------------------------------------------------
--! \n\nLast changes:\n
-------------------------------------------------------------------------------
--! @todo \n
--! \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
ENTITY i2c_master IS
PORT(
i2c_scl_i : IN std_logic;
i2c_sda_i : IN std_logic;
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus; -- Signals from IPBus core to slave
ipbus_reset_i : IN std_logic;
i2c_scl_enb_o : OUT std_logic;
i2c_sda_enb_o : OUT std_logic;
ipbus_o : OUT ipb_rbus -- signals from slave to IPBus core
);
-- Declarations
END ENTITY i2c_master ;
--
ARCHITECTURE rtl OF i2c_master IS
--signal s_i2c_scl, s_i2c_scl_o, s_i2c_scl_enb, s_i2c_sda, s_i2c_sda_enb : std_logic ;
BEGIN
--i2c_scl_b <= s_i2c_scl when (s_i2c_scl_enb = '0') else 'Z';
--i2c_sda_b <= s_i2c_sda when (s_i2c_sda_enb = '0') else 'Z';
i2c_interface: entity work.i2c_master_top port map(
wb_clk_i => ipbus_clk_i,
wb_rst_i => ipbus_reset_i,
arst_i => '1',
wb_adr_i => ipbus_i.ipb_addr(2 downto 0),
wb_dat_i => ipbus_i.ipb_wdata(7 downto 0),
wb_dat_o => ipbus_o.ipb_rdata(7 downto 0),
wb_we_i => ipbus_i.ipb_write,
wb_stb_i => ipbus_i.ipb_strobe,
wb_cyc_i => '1',
wb_ack_o => ipbus_o.ipb_ack,
wb_inta_o => open,
scl_pad_i => i2c_scl_i,
scl_pad_o => open,
scl_padoen_o => i2c_scl_enb_o,
sda_pad_i => i2c_sda_i,
sda_pad_o => open,
sda_padoen_o => i2c_sda_enb_o
);
ipbus_o.ipb_rdata(31 downto 8) <= ( others => '0');
ipbus_o.ipb_err <= '0'; -- never return an error.
END ARCHITECTURE rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/common/ipbus_addr_decode.vhd 0000664 0000000 0000000 00000004346 12415504633 0027106 0 ustar 00root root 0000000 0000000 -- Address decode logic for ipbus fabric
--
-- This file has been AUTOGENERATED from the address table - do not hand edit
--
-- We assume the synthesis tool is clever enough to recognise exclusive conditions
-- in the if statement.
--
-- Dave Newbold, February 2011
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use work.ipbus.all;
package ipbus_addr_decode is
function ipbus_addr_sel(signal addr : in std_logic_vector(31 downto 0)) return integer;
end ipbus_addr_decode;
package body ipbus_addr_decode is
function ipbus_addr_sel(signal addr : in std_logic_vector(31 downto 0)) return integer is
variable sel : integer;
begin
if std_match(addr, "-----------------------0001-----") then
sel := 0; -- DUTInterfaces / base 00000020 / mask 0000001f
elsif std_match(addr, "-----------------------0010-----") then
sel := 1; -- triggerInputs / base 00000040 / mask 0000001f
elsif std_match(addr, "-----------------------0011-----") then
sel := 2; -- triggerLogic / base 00000060 / mask 0000001f
elsif std_match(addr, "-----------------------0100-----") then
sel := 3; -- eventBuffer / base 00000080 / mask 0000001f
elsif std_match(addr, "-----------------------0101-----") then
sel := 4; -- logic_clocks / base 000000a0 / mask 0000001f
elsif std_match(addr, "-----------------------0110-----") then
sel := 5; -- i2c_master / base 000000c0 / mask 00000007
elsif std_match(addr, "-----------------------0111-----") then
sel := 6; -- Trigger_Generator / base 000000e0 / mask 0000001f
elsif std_match(addr, "-----------------------1000-----") then
sel := 7; -- Shutter_Generator / base 00000100 / mask 0000001f
elsif std_match(addr, "-----------------------1001-----") then
sel := 8; -- Spill_Generator / base 00000120 / mask 0000001f
elsif std_match(addr, "-----------------------1010-----") then
sel := 9; -- Event_Formatter / base 00000140 / mask 0000001f
elsif std_match(addr, "-----------------------1011-----") then
sel := 10; -- Handshakes / base 00000160 / mask 0000001f
elsif std_match(addr, "-----------------------0000-----") then
sel := 11; -- version / base 00000000 / mask 00000000
else
sel := 99;
end if;
return sel;
end ipbus_addr_sel;
end ipbus_addr_decode;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/common/ipbus_ver.vhd 0000664 0000000 0000000 00000002073 12415504633 0025460 0 ustar 00root root 0000000 0000000 -- Version register, returns a fixed value
--
-- To be replaced by a more coherent versioning mechanism later
--
-- Dave Newbold, August 2011
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ipbus.all;
entity ipbus_ver is
port(
ipbus_in: in ipb_wbus;
ipbus_out: out ipb_rbus
);
end ipbus_ver;
architecture rtl of ipbus_ver is
begin
ipbus_out.ipb_rdata <= X"a5ea" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out.ipb_ack <= ipbus_in.ipb_strobe;
ipbus_out.ipb_err <= '0';
end rtl;
-- Build log
--
-- build 0x1000 : 22/08/11 : Starting build ID
-- build 0x1001 : 29/08/11 : Version for SPI testing
-- build 0x1002 : 27/09/11 : Bug fixes, new transactor code; v1.3 candidate
-- build 0x1003 : buggy
-- build 0x1004 : 18/10/11 : New mini-t top level, bug fixes, 1.3 codebase
-- build 0x1005 : 20/10/11 : ipbus address config testing in mini-t
-- build 0x1006 : 26/10/11 : trying with jumbo frames
-- build 0x1007 : 27/10/11 : new slaves / address map + rhino frames
-- build 0x1008 : 31/10/11 : rhino frames + multibus demo
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/common/logic_clocks_rtl.vhd 0000664 0000000 0000000 00000035233 12415504633 0027002 0 ustar 00root root 0000000 0000000 --=============================================================================
--! @file logic_clocks_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.logic_clocks.rtl
--
--! @brief Generates 160MHz , 640MHz clocks from an incoming 40MHz clock. \n
--! Can switch between clock generated from on-board Xtal ( clk_logic_xtal ) and external clock\n
--! Can also output clock to external clock pins.
--!
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 14:20:26 11/14/12
--
--! @version v0.1
--
--! @details
--! Address map:
--! 0x00000000 - control/status register:
--! bit-0 - PLL locked ( 1 = locked )
--! bit-1 - buff-PLL locked ( 1 = locked )
--! bit-2 - use xtal for logic ( 1 = xtal , 0= external)
--! bit-3 - clock connector is an input ( 1=input , 0 = output)
--! 0x00000001 - reset logic. Write to bit-zero to send reset.
--!
--!
--! Dependencies:\n
--!
--! References:\n
--!
--! Modified by:\n
--! Author:
-------------------------------------------------------------------------------
--! \n\nLast changes:\n
-------------------------------------------------------------------------------
--! @todo \n
--! \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
-- Based on output of Xilinx Coregen and Alvro Dosil TLU code.
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___640.000______0.000______50.0______175.916____213.982
-- CLK_OUT2___160.000______0.000______50.0______223.480____213.982
-- CLK_OUT3____40.000______0.000______50.0______306.416____213.982
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________40.000____________0.010
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
library unisim;
use unisim.vcomponents.all;
ENTITY logic_clocks IS
PORT(
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus;
ipbus_reset_i : IN std_logic;
Reset_i : IN std_logic;
clk_logic_xtal_i : IN std_logic; -- ! 40MHz clock from onboard xtal
clk_16x_logic_o : OUT std_logic; -- 640MHz clock
clk_4x_logic_o : OUT std_logic; -- 160MHz clock
ipbus_o : OUT ipb_rbus;
strobe_16x_logic_o : OUT std_logic; -- strobes once every 4 cycles of clk_16x
strobe_4x_logic_o : OUT std_logic; -- one pulse every 4 cycles of clk_4x
extclk_p_b : INOUT std_logic; -- either external clock in, or a clock being driven out
extclk_n_b : INOUT std_logic;
DUT_clk_o : OUT std_logic;
logic_clocks_locked_o : OUT std_logic;
logic_reset_o : OUT std_logic -- Goes high to reset counters etc. Sync with clk_4x_logic
);
-- Declarations
END ENTITY logic_clocks ;
--
ARCHITECTURE rtl OF logic_clocks IS
signal s_clk40 , s_clk40_internal : std_logic;
signal s_clk160 ,s_clk160_internal : std_logic;
signal s_clk640 , s_clk640_internal : std_logic;
signal s_clk40_out : std_logic; -- Clock generated by DDR register to feed out of chip.
-- signal s_clk40_copy : std_logic; -- Clock generated by DDR register to feed out of chip.
-- Eventually connect up clock control & status lines to IPBus
--signal s_extclk_is_input : std_logic := '0';
-- signal s_extclk_is_input_buf : std_logic := '1';
signal s_clk_is_xtal, s_clk_is_ext_buf : std_logic := '1';
-- signal s_logic_clk_rst : std_logic := '0';
signal s_locked_pll, s_locked_bufpll : std_logic;
signal s_clk : std_logic;
signal s_DUT_Clk, s_DUT_Clk_o, s_DUT_ClkG : std_logic;
signal s_extclk, s_extclkG : std_logic;
-- signal s_clk_d1 , s_strobe_4x_p1 , s_strobe_4x_logic : std_logic;
signal s_clkfbout_buf , s_clkfbout : std_logic;
signal s_strobe_generator : std_logic_vector(3 downto 0) := "1000"; -- ! Store state of ring buffer to generate strobe
signal s_logic_clk_generator : std_logic_vector(3 downto 0) := "1100"; --! Stores state of 40MHz "clock"
signal s_strobe_fb : std_logic := '0';
signal s_logic_reset_ipb, s_logic_reset_ipb_d1 : std_logic := '0';
-- ! Reset signal in IPBus clock domain
signal s_logic_reset , s_logic_reset_d1 , s_logic_reset_d2 , s_logic_reset_d3 : std_logic := '0';
-- ! reset signal clocked onto logic-clock domain.
signal s_ipbus_ack : std_logic := '0';
signal s_reset_pll : std_logic := '0';
--signal s_Reset : std_logic := '0';
-- ! Global Reset signal
signal s_extclk_internal : std_logic := '0';
signal s_clock_status_ipb : std_logic_vector( ipbus_o.ipb_rdata'range ); --! Hold status of clocks
BEGIN
-----------------------------------------------------------------------------
-- IPBus write
-----------------------------------------------------------------------------
ipbus_write: process (ipbus_clk_i)
begin -- process ipb_clk_i
if rising_edge(ipbus_clk_i) then
s_logic_reset_ipb <= '0';
if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1') then
case ipbus_i.ipb_addr(1 downto 0) is
when "00" =>
s_clk_is_xtal <= ipbus_i.ipb_wdata(2) ; -- select clock source
when "01" =>
s_logic_reset_ipb <= ipbus_i.ipb_wdata(0) ; -- write to reset
when others => null;
end case;
end if;
-- register reset signal to aid timing.
s_logic_reset_ipb_d1 <= s_logic_reset_ipb;
s_ipbus_ack <= ipbus_i.ipb_strobe and not s_ipbus_ack;
-- register the clock status signals onto IPBus domain.
--s_clock_status_ipb <= x"0000000" & s_extclk_is_input & s_clk_is_xtal & s_locked_bufpll & s_locked_pll;
s_clock_status_ipb <= x"0000000" & '0' & s_clk_is_xtal & s_locked_bufpll & s_locked_pll;
end if;
end process ipbus_write;
ipbus_o.ipb_ack <= s_ipbus_ack;
ipbus_o.ipb_err <= '0';
-----------------------------------------------------------------------------
-- IPBUS read
-----------------------------------------------------------------------------
with ipbus_i.ipb_addr(1 downto 0) select
ipbus_o.ipb_rdata <=
s_clock_status_ipb when "00",
(others => '1') when others;
-----------------------------------------------------------------------------
-- Generate reset signal on logic-clock domain
-- This relies on the IPBus clock being much slower than the 4x logic clock.
-----------------------------------------------------------------------------
p_reset: process (s_clk160_internal)
begin -- process p_reset
if rising_edge(s_clk160_internal) then
s_logic_reset_d1 <= s_logic_reset_ipb_d1;
s_logic_reset_d2 <= s_logic_reset_d1;
s_logic_reset_d3 <= s_logic_reset_d2;
s_logic_reset <= s_logic_reset_d2 and ( not s_logic_reset_d3);
end if;
end process p_reset;
logic_reset_o <= s_logic_reset;
logic_clocks_locked_o <= s_locked_bufpll and s_locked_pll;
ext_clk_obuf : IOBUFDS
generic map (
IOSTANDARD => "BLVDS_25")
port map (
O => s_extclk, -- Buffer output
IO => extclk_p_b, -- Diff_p inout (connect directly to top-level port)
IOB => extclk_n_b, -- Diff_n inout (connect directly to top-level port)
I => s_DUT_Clk_o, -- Buffer input
T => s_clk_is_ext_buf -- 3-state enable input, high=input, low=output
);
ddr_for_extclk_output : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => s_DUT_Clk_o, -- 1-bit output data
C0 => clk_logic_xtal_i, -- 1-bit clock input
C1 => not clk_logic_xtal_i, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => '1', -- 1-bit data input (associated with C0)
D1 => '0', -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
--When an ODDR2 primitive is used in conjunction with a 3-state output, the T control pin must
--also use an ODDR2 primitive configured in the same mode as the ODDR2 primitive used for data
--output.
ddr_for_40MHz_tristate : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => s_clk_is_ext_buf, -- 1-bit output data
C0 => clk_logic_xtal_i, -- 1-bit clock input
C1 => not clk_logic_xtal_i, --not s_clk160_internal, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => not s_clk_is_xtal, -- 1-bit data input (associated with C0)
D1 => '0', --not s_clk_is_xtal, -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
--! Clock selection
clock_mux : BUFGMUX
generic map (
CLK_SEL_TYPE => "SYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
)
port map (
O => s_DUT_Clk, -- 1-bit output: Clock buffer output
I0 => s_extclkG, -- 1-bit input: Clock buffer input (S=0)
I1 => clk_logic_xtal_i, -- 1-bit input: Clock buffer input (S=1)
S => s_clk_is_xtal -- 1-bit input: Clock buffer select
);
extclk_buf : BUFG
port map(
O => s_extclkG,
I => s_extclk);
-- IBUFG_inst : IBUFG
-- generic map (
-- IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
-- IOSTANDARD => "DEFAULT")
-- port map (
-- O => s_Reset, -- Clock buffer output
-- I => Reset_i -- Clock buffer input (connect directly to top-level port)
-- );
--! Clocking primitive
-------------------------------------
--! Instantiation of the PLL primitive
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
--CLK_FEEDBACK => "CLKOUT0", --"CLKFBOUT",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 16,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 1, -- 1-->2 move from 640 to 320
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 4, -- 4-->8 move from 160 to 80
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 16, -- 16--> 32 move from 40 to 20
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 25.000,
REF_JITTER => 0.010)
port map(
-- Output clocks
CLKFBOUT => s_clkfbout,
CLKOUT0 => s_clk640,
CLKOUT1 => s_clk160,
CLKOUT2 => s_clk40,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
-- Status and control signals
LOCKED => s_locked_pll,
-- RST => s_logic_clk_rst,
RST => s_reset_pll,
-- Input clock control
-- CLKFBIN => s_clkfbout_buf,
CLKFBIN => s_clkfbout,
CLKIN => clk_logic_xtal_i);
s_reset_pll <= Reset_i or s_logic_reset;
-- Buffer the 16x clock and generate the ISERDES strobe signal
BUFPLL_inst : BUFPLL
generic map (
DIVIDE => 4)
port map (
IOCLK => s_clk640_internal, -- 1-bit output: Output I/O clock
LOCK => s_locked_bufpll, -- 1-bit output: Synchronized LOCK output
SERDESSTROBE => strobe_16x_logic_O, -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
GCLK => s_clk160_internal, -- 1-bit input: BUFG clock input
LOCKED => s_locked_pll, -- 1-bit input: LOCKED input from PLL
PLLIN => s_clk640 -- 1-bit input: Clock input from PLL
);
clk_16x_logic_o <= s_clk640_internal;
DUT_clk_o <= s_DUT_clk;
-- Generate a copy of the
-- purpose: generates a strobe in time with rising edge of s_clk
-- type : combinational
-- inputs : s_clk160 , s_clk
-- outputs: strobe_4x_logic_o
-- Can't use a clock signal as a combinatorial signal. Hence the baroque
-- method of generating a strobe. Add a mechanism to restart if the '1' gets
-- lost ....
generate_4x_strobe: process (s_clk160)-- , s_clk40_out)
begin -- process generate_4x_strobe
if rising_edge(s_clk160) then
if s_logic_reset = '1' then
s_strobe_generator <= "1000";
s_logic_clk_generator <= "1100";
else
s_strobe_generator <= s_strobe_generator(2 downto 0) & s_strobe_generator(3);
s_logic_clk_generator <= s_logic_clk_generator(2 downto 0) & s_logic_clk_generator(3);
end if;
end if;
end process generate_4x_strobe;
strobe_4x_logic_o <= s_strobe_generator(3);
s_clk40_out <= s_logic_clk_generator(3);
-- Try fbout out again....
-- buffer feedback clock
-------------------------------------
--clkf_buf : BUFG
--port map(
-- O => s_clkfbout_buf,
-- I => s_clkfbout);
---
-- clkf_buf : BUFIO2FB
-- port map (
-- O => s_clkfbout_buf, -- 1-bit output: Output feedback clock (connect to feedback input of DCM/PLL)
-- I => s_clk640_internal -- 1-bit input: Feedback clock input (connect to input port)
-- );
-- buffer 160MHz (4x) clock
--------------------------------------
clk160_o_buf : BUFG
port map(
O => s_clk160_internal,
I => s_clk160);
clk_4x_logic_o <= s_clk160_internal;
-- -- buffer 40MHz (1x) clock
-- --------------------------------------
-- clk40_o_buf : BUFG
-- port map(
-- O => s_clk40_internal,
-- I => s_clk40);
-- clk_logic_o <= s_clk40_out;
END ARCHITECTURE rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/common/pulseClockDomainCrossing_rtl.vhd 0000664 0000000 0000000 00000006217 12415504633 0031313 0 ustar 00root root 0000000 0000000 --=============================================================================
--! @file pulseClockDomainCrossing_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture worklib.pulseClockDomainCrossing.rtl
--
--! @brief Takes a pulse synchronized with one clock and produces a
--! pulse synchronized to another clock.
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date September/2012
--
--! @version v0.1
--
--! @details A "ring" of D-type flip-flops is used to transfer a strobe
--! from the input clock domain to the output clock domain and then back again.
--! The time taken to transit from input to output is approximately
--! two clock cycles of clock_output_i .
--! After an additional two cycles of clk_input_i another pulse can be sent
--!
--!
--! Dependencies:\n
--!
--! References:\n
--!
--! Modified by:\n
--! Author:
-------------------------------------------------------------------------------
--! \n\nLast changes:\n
-------------------------------------------------------------------------------
--! @todo \n
--! \n
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity pulseClockDomainCrossing is
port (
clk_input_i : in std_logic; --! clock for input
pulse_i : in std_logic; --! input pulse. Active high
clk_output_i: in std_logic; --! clock for output
pulse_o : out std_logic --! Single cycle pulse synchronized to clock_output_i
);
end pulseClockDomainCrossing;
architecture rtl of pulseClockDomainCrossing is
signal s_pulse_out , s_pulse_out_d1 , s_pulse_out_d2 , s_pulse_out_d3 , s_pulse_out_d4 , s_pulse_back_d1 , s_pulse_back_d2: std_logic := '0';
begin -- rtl
-- purpose: registers and flip-flop on clk_input_i
p_input_clock_logic: process (clk_input_i)
begin
if rising_edge(clk_input_i) then
-- Register signals coming from output clock domain back to the
-- input clock domain
s_pulse_back_d1 <= s_pulse_out_d2;
s_pulse_back_d2 <= s_pulse_back_d1;
-- JK flip-flop
if (s_pulse_back_d2 = '1') then
s_pulse_out <= '0';
elsif (pulse_i = '1') then
s_pulse_out <= '1';
end if;
end if;
end process p_input_clock_logic;
-- purpose: registers and flip-flop on clk_output_o
p_output_clock_logic: process (clk_output_i)
begin
if rising_edge(clk_output_i) then
-- Register signal on input clock domain onto output clock domain
s_pulse_out_d1 <= s_pulse_out;
s_pulse_out_d2 <= s_pulse_out_d1;
s_pulse_out_d3 <= s_pulse_out_d2;
s_pulse_out_d4 <= s_pulse_out_d3;
-- Generate single clock-cycle pulse on pulse_o
pulse_o <= s_pulse_out_d3 and ( not s_pulse_out_d4 );
end if;
end process p_output_clock_logic;
end rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/common/registerCounter_rtl.vhd 0000664 0000000 0000000 00000010137 12415504633 0027527 0 ustar 00root root 0000000 0000000 --=============================================================================
--! @file registerCounter_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture worklib.registerCounter.rtl
--
--! @brief Regularly transfers the input to the output.\n
--! One clock for input , one clock for output\n
--! Can't just put entire bus through a couple of register stages,\n
--! Since this will just swap meta-stability issues for race issues.
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 24/Nov/12
--
--! @version v0.1
--
--! @details A six stage "ring oscillator" is used to generate two strobes.
--! One reads data into a register. The other registers the data to the output
--! Three stages are clocked on clk_write_i , three stages are clocked on clk_read_i
--! We could use gray-scale and put through registers, but this method
--! should work well enough at the expense of latency.\n
--! \n
--! The time taken for an edge to travel round the complete loop is
--! 2 cycles of clk_read_i and 2 cycles of clk_write_i plus two intervals
--! that depend on the relative phase of clk_read_i and clk_write_i
--!
--!
--!
--! Dependencies:\n
--!
--! References:\n
--!
--! Modified by:\n
--! Author:
--! David Cussans, 26/2/14 - Added registers to output to aid timing closure.
-------------------------------------------------------------------------------
--! \n\nLast changes:\n
-------------------------------------------------------------------------------
--! @todo \n
--! \n
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity registerCounter is
generic (
g_DATA_WIDTH : positive := 15); -- ! Width of counter
port (
clk_input_i : in std_logic; -- ! clock for input
data_i : in std_logic_vector(g_DATA_WIDTH-1 downto 0); -- ! data to transfer to output
data_o : out std_logic_vector(g_DATA_WIDTH-1 downto 0); -- ! Data now in clk_read_i domain
clk_output_i : in std_logic); -- ! clock for output
end registerCounter;
architecture rtl of registerCounter is
signal s_ring_d0 , s_ring_d1 , s_ring_d2 , s_ring_d3 , s_ring_d4, s_ring_d5: std_logic := '0'; -- stages in "ring oscillator" used to generate strobes
signal s_registered_data : std_logic_vector(data_i'range) := ( others => '0'); -- ! Register to store data between clock domains
signal s_read_strobe , s_write_strobe : std_logic := '0'; -- ! Strobes high to register data from input and to output
begin -- rtl
-- purpose: part of "ring oscillator" transfering strobe between clock domains
-- type : combinational
-- inputs : clk_read_i
-- outputs:
p_gen_capture_strobe: process (clk_input_i)
begin -- process p_gen_capture_strobe
if rising_edge(clk_input_i) then
s_ring_d0 <= not s_ring_d5;
s_ring_d1 <= s_ring_d0;
s_ring_d2 <= s_ring_d1;
if s_read_strobe = '1' then
s_registered_data <= data_i;
end if;
end if;
end process p_gen_capture_strobe;
s_read_strobe <= s_ring_d1 xor s_ring_d2; --! Generate a strobe with
--width one clk_read_i
-- purpose: part of "ring oscillator" transfering strobe between clock domains
-- type : combinational
-- inputs : clk_output_i
-- outputs:
p_gen_output_strobe: process (clk_output_i)
begin -- process p_gen_output_strobe
if rising_edge(clk_output_i) then
s_ring_d3 <= s_ring_d2;
s_ring_d4 <= s_ring_d3;
s_ring_d5 <= s_ring_d4;
if s_write_strobe = '1' then
data_o <= s_registered_data;
end if;
end if;
end process p_gen_output_strobe;
s_write_strobe <= s_ring_d4 xor s_ring_d5; --! Generate a strobe
--
end rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/common/serdes_1_to_n_SDR.vhd 0000664 0000000 0000000 00000030427 12415504633 0026722 0 ustar 00root root 0000000 0000000 ------------------------------------------------------------------------------/
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------/
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: top_nto1_ddr_diff_rx.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: June 1 2009
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: Example differential input receiver for DDR clock and data using 2 x BUFIO2
-- Serdes factor and number of data lines are set by constants in the code
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
--
------------------------------------------------------------------------------/
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and signalulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-------------------------------------------------------
--! @file
--! @brief Serdes 1 to n SDR
--! @author Alvaro Dosil
-------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity serdes_1_to_n_SDR is
generic ( g_S : integer := 4); --! Parameter to set the serdes factor 1..8
port( clk_i : in std_logic; --! Fast clock to sample data (640MHz)
hclk_i : in std_logic; --! A quarter frequency clock (160MHz)
reset_i : in std_logic; --! reset signal
Data_i : in std_logic; --! 1-Bit Input data
strobe_i : in std_logic; --! Iserdes strobe_i
Data_o : out std_logic_vector(2*g_S-1 downto 0) --! data output
);
end serdes_1_to_n_SDR;
architecture Behavioral of serdes_1_to_n_SDR is
signal s_Data_i_d_m : std_logic; -- Data_i delayed master
signal s_Data_i_d_2m : std_logic; -- Data_i delayed master second signal
signal s_Data_i_d_s : std_logic; -- Data_i delayed slave
signal s_Data_i_d_2s : std_logic; -- Data_i delayed slave second signal
signal s_Data_o : std_logic_vector(2*g_S-1 downto 0);
--signal s_clk_b : std_logic;
--signal s_ISERDES_STROBE : std_logic;
begin
---- Generate the ISERDES strobe signal
--
-- BUFPLL_inst : BUFPLL
-- generic map (
-- DIVIDE => 4)
-- port map (
-- IOCLK => s_clk_b, -- 1-bit output: Output I/O clock
-- LOCK => open, -- 1-bit output: Synchronized LOCK output
-- SERDESSTROBE => s_ISERDES_STROBE, -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
-- GCLK => hclk_i, -- 1-bit input: BUFG clock input
-- LOCKED => locked_pll_i, -- 1-bit input: LOCKED input from PLL
-- PLLIN => clk_i -- 1-bit input: Clock input from PLL
-- );
IODELAY2_M : IODELAY2
generic map (
COUNTER_WRAPAROUND => "WRAPAROUND", -- "STAY_AT_LIMIT" or "WRAPAROUND"
DATA_RATE => "SDR", -- "SDR" or "DDR"
DELAY_SRC => "IDATAIN", -- "IO", "ODATAIN" or "IDATAIN"
IDELAY_MODE => "NORMAL", -- "NORMAL" or "PCI"
IDELAY_TYPE => "FIXED", -- "FIXED", "DEFAULT", "VARIABLE_FROM_ZERO", "VARIABLE_FROM_HALF_MAX"
-- or "DIFF_PHASE_DETECTOR"
IDELAY_VALUE => 0, -- Amount of taps for fixed input delay (0-255)
IDELAY2_VALUE => 0, -- Delay value when IDELAY_MODE="PCI" (0-255)
ODELAY_VALUE => 0, -- Amount of taps fixed output delay (0-255)
SERDES_MODE => "NONE" -- "NONE", "MASTER" or "SLAVE"
-- SIM_TAPDELAY_VALUE=> 43 -- Per tap delay used for simulation in ps
)
port map (
BUSY => open, -- 1-bit output: Busy output after CAL
DATAOUT => s_Data_i_d_m, -- 1-bit output: Delayed data output to ISERDES/input register
DATAOUT2 => s_Data_i_d_2m, -- 1-bit output: Delayed data output to general FPGA fabric
DOUT => open, -- 1-bit output: Delayed data output
TOUT => open, -- 1-bit output: Delayed 3-state output
CAL => '0', -- 1-bit input: Initiate calibration input
CE => '0', -- 1-bit input: Enable INC input
CLK => '0', -- 1-bit input: Clock input
IDATAIN => Data_i, -- 1-bit input: Data input (connect to top-level port or I/O buffer)
INC => '0', -- 1-bit input: Increment / decrement input
IOCLK0 => '0', -- 1-bit input: Input from the I/O clock network
IOCLK1 => '0', -- 1-bit input: Input from the I/O clock network
ODATAIN => '0', -- 1-bit input: Output data input from output register or OSERDES2.
RST => reset_i, -- 1-bit input: reset_i to zero or 1/2 of total delay period
T => '0' -- 1-bit input: 3-state input signal
);
IODELAY2_S : IODELAY2
generic map (
COUNTER_WRAPAROUND => "WRAPAROUND", -- "STAY_AT_LIMIT" or "WRAPAROUND"
DATA_RATE => "SDR", -- "SDR" or "DDR"
DELAY_SRC => "IDATAIN", -- "IO", "ODATAIN" or "IDATAIN"
IDELAY_MODE => "NORMAL", -- "NORMAL" or "PCI"
IDELAY_TYPE => "FIXED", -- "FIXED", "DEFAULT", "VARIABLE_FROM_ZERO", "VARIABLE_FROM_HALF_MAX"
-- or "DIFF_PHASE_DETECTOR"
IDELAY_VALUE => 10,--29, -- Amount of taps for fixed input delay (0-255) 10->0.75nS, 11->0.825nS
IDELAY2_VALUE => 0, -- Delay value when IDELAY_MODE="PCI" (0-255)
ODELAY_VALUE => 0, -- Amount of taps fixed output delay (0-255)
SERDES_MODE => "NONE" -- "NONE", "MASTER" or "SLAVE"
--SIM_TAPDELAY_VALUE => 43 -- Per tap delay used for simulation in ps
)
port map (
BUSY => open, -- 1-bit output: Busy output after CAL
DATAOUT => s_Data_i_d_s, -- 1-bit output: Delayed data output to ISERDES/input register
DATAOUT2 => s_Data_i_d_2s, -- 1-bit output: Delayed data output to general FPGA fabric
DOUT => open, -- 1-bit output: Delayed data output
TOUT => open, -- 1-bit output: Delayed 3-state output
CAL => '0', -- 1-bit input: Initiate calibration input
CE => '0', -- 1-bit input: Enable INC input
CLK => '0', -- 1-bit input: Clock input
IDATAIN => Data_i, -- 1-bit input: Data input (connect to top-level port or I/O buffer)
INC => '0', -- 1-bit input: Increment / decrement input
IOCLK0 => '0', -- 1-bit input: Input from the I/O clock network
IOCLK1 => '0', -- 1-bit input: Input from the I/O clock network
ODATAIN => '0', -- 1-bit input: Output data input from output register or OSERDES2.
RST => reset_i, -- 1-bit input: reset_i to zero or 1/2 of total delay period
T => '0' -- 1-bit input: 3-state input signal
);
ISERDES2_M : ISERDES2
generic map (
BITSLIP_ENABLE => FALSE, -- Enable Bitslip Functionality (TRUE/FALSE)
DATA_RATE => "SDR", -- Data-rate ("SDR" or "DDR")
DATA_WIDTH => g_S, -- Parallel data width selection (2-8)
INTERFACE_TYPE => "NETWORKING_PIPELINED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED"
SERDES_MODE => "NONE" -- "NONE", "MASTER" or "SLAVE"
)
port map (
-- Q1 - Q4: 1-bit (each) output Registered outputs to FPGA logic
Q1 => s_Data_o(1),
Q2 => s_Data_o(3),
Q3 => s_Data_o(5),
Q4 => s_Data_o(7),
--SHIFTOUT => SHIFTOUTsig, -- 1-bit output Cascade output signal for master/slave I/O
VALID => open, -- 1-bit output Output status of the phase detector
BITSLIP => '0', -- 1-bit input Bitslip enable input
CE0 => '1', -- 1-bit input Clock enable input
CLK0 => clk_i, -- 1-bit input I/O clock network input
CLK1 => '0', -- 1-bit input Secondary I/O clock network input
CLKDIV => hclk_i, -- 1-bit input FPGA logic domain clock input
D => s_Data_i_d_m, -- 1-bit input Input data
IOCE => strobe_i, -- 1-bit input Data strobe_i input
RST => reset_i, -- 1-bit input Asynchronous reset_i input
SHIFTIN => '0' -- 1-bit input Cascade input signal for master/slave I/O
);
ISERDES2_S : ISERDES2
generic map (
BITSLIP_ENABLE => FALSE, -- Enable Bitslip Functionality (TRUE/FALSE)
DATA_RATE => "SDR", -- Data-rate ("SDR" or "DDR")
DATA_WIDTH => g_S, -- Parallel data width selection (2-8)
INTERFACE_TYPE => "NETWORKING_PIPELINED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED"
SERDES_MODE => "NONE" -- "NONE", "MASTER" or "SLAVE"
)
port map (
-- Q1 - Q4: 1-bit (each) output Registered outputs to FPGA logic
Q1 => s_Data_o(0),
Q2 => s_Data_o(2),
Q3 => s_Data_o(4),
Q4 => s_Data_o(6),
--SHIFTOUT => SHIFTOUTsig, -- 1-bit output Cascade output signal for master/slave I/O
VALID => open, -- 1-bit output Output status of the phase detector
BITSLIP => '0', -- 1-bit input Bitslip enable input
CE0 => '1', -- 1-bit input Clock enable input
CLK0 => clk_i, -- 1-bit input I/O clock network input
CLK1 => '0', -- 1-bit input Secondary I/O clock network input
CLKDIV => hclk_i, -- 1-bit input FPGA logic domain clock input
D => s_Data_i_d_s, -- 1-bit input Input data
IOCE => strobe_i, -- 1-bit input Data strobe_i input
RST => reset_i, -- 1-bit input Asynchronous reset_i input
SHIFTIN => '0' -- 1-bit input Cascade input signal for master/slave I/O
);
reg_out : process(hclk_i)
begin
if rising_edge(hclk_i) then
Data_o <= s_Data_o;
end if;
end process;
end Behavioral;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/common/sync_reg.vhd 0000664 0000000 0000000 00000002567 12415504633 0025303 0 ustar 00root root 0000000 0000000 ----------------------------------------------------------------------------------
-- Company: Universidade de Santiago de Compostela
-- Engineer: Alvaro Dosil
--
-- Create Date: 15/08/2012
-- Module Name: Conf_Regs - Behavioral
-- Revision 1.00 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
-------------------------------------------------------
--! @file
--! @brief Synchronization module 32b
--! @author Alvaro Dosil
-------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sync_reg is
generic(g_Data_width : positive := 32);
port(
clk_i : in std_logic; --! synchronous clock
Async_i : in std_logic_vector(g_Data_width-1 downto 0); --! Asynchronous input data
Sync_o : out std_logic_vector(g_Data_width-1 downto 0)); --! Synchronous output data
end sync_reg;
--! @brief
--! @details Synchronize words (n bits)of data
architecture Behavioral of sync_reg is
signal s_async_i : std_logic_vector(g_Data_width-1 downto 0);
signal s_sync_o : std_logic_vector(g_Data_width-1 downto 0);
begin
loop0: for i in 0 to g_Data_width-1 generate
begin
reg: entity work.Reg_2clks
port map(
clk_i => clk_i,
async_i => s_async_i(i),
sync_o => s_sync_o(i));
end generate;
s_async_i <= Async_i;
Sync_o <= s_sync_o;
end Behavioral;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/common/synchronizeRegisters_rtl.vhd 0000664 0000000 0000000 00000010166 12415504633 0030610 0 ustar 00root root 0000000 0000000 --=============================================================================
--! @file synchronizeRegisters_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture worklib.synchronizeRegisters.rtl
--
--! @brief Regularly transfers the input to the output.\n
--! One clock for input , one clock for output\n
--! Can't just put entire bus through a couple of register stages,\n
--! Since this will just swap meta-stability issues for race issues.
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 24/Nov/12
--
--! @version v0.1
--
--! @details A six stage "ring oscillator" is used to generate two strobes.
--! One reads data into a register. The other registers the data to the output
--! Three stages are clocked on clk_write_i , three stages are clocked on clk_read_i
--! The time taken for an edge to travel round the complete loop is
--! 2 cycles of clk_read_i and 2 cycles of clk_write_i plus two intervals
--! that depend on the relative phase of clk_read_i and clk_write_i
--!
--! Based on registerCounters
--!
--! Dependencies:\n
--!
--! References:\n
--!
--! Modified by:\n
--! Author:
--! David Cussans, 26/2/14 - Added registers to output to aid timing closure.
-------------------------------------------------------------------------------
--! \n\nLast changes:\n
-------------------------------------------------------------------------------
--! @todo \n
--! \n
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use work.fmcTLU.all;
use work.ipbus_reg_types.all;
entity synchronizeRegisters is
generic (
--g_DATA_WIDTH : positive := 15;
g_NUM_REGISTERS : positive := 1); -- ! Width of counter
port (
clk_input_i : in std_logic; -- ! clock for input
data_i : in ipb_reg_v(g_NUM_REGISTERS-1 downto 0); -- ! array of registers to transfer to output
data_o : out ipb_reg_v(g_NUM_REGISTERS-1 downto 0); -- ! Data now in clk_output_i domain
clk_output_i : in std_logic); -- ! clock for output
end synchronizeRegisters;
architecture rtl of synchronizeRegisters is
signal s_ring_d0 , s_ring_d1 , s_ring_d2 , s_ring_d3 , s_ring_d4, s_ring_d5: std_logic := '0'; -- stages in "ring oscillator" used to generate strobes
signal s_registered_data : ipb_reg_v(data_i'range) := ( others => ( others => '0')); -- ! Register to store data between clock domains
signal s_read_strobe , s_write_strobe : std_logic := '0'; -- ! Strobes high to register data from input and to output
begin -- rtl
-- purpose: part of "ring oscillator" transfering strobe between clock domains
-- type : combinational
-- inputs : clk_read_i
-- outputs:
p_gen_capture_strobe: process (clk_input_i)
begin -- process p_gen_capture_strobe
if rising_edge(clk_input_i) then
s_ring_d0 <= not s_ring_d5;
s_ring_d1 <= s_ring_d0;
s_ring_d2 <= s_ring_d1;
if s_read_strobe = '1' then
s_registered_data <= data_i;
end if;
end if;
end process p_gen_capture_strobe;
s_read_strobe <= s_ring_d1 xor s_ring_d2; --! Generate a strobe with
--width one clk_read_i
-- purpose: part of "ring oscillator" transfering strobe between clock domains
-- type : combinational
-- inputs : clk_output_i
-- outputs:
p_gen_output_strobe: process (clk_output_i)
begin -- process p_gen_output_strobe
if rising_edge(clk_output_i) then
s_ring_d3 <= s_ring_d2;
s_ring_d4 <= s_ring_d3;
s_ring_d5 <= s_ring_d4;
if s_write_strobe = '1' then
data_o <= s_registered_data;
end if;
end if;
end process p_gen_output_strobe;
s_write_strobe <= s_ring_d4 xor s_ring_d5; --! Generate a strobe
--
end rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/common/triggerInputs_rtl.vhd 0000664 0000000 0000000 00000036517 12415504633 0027223 0 ustar 00root root 0000000 0000000 --=============================================================================
--! @file triggerInputs_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.triggerInputs.rtl
--
--! @brief Measures arrival time of trigger pulses using two deserializers
--! clocked on 14x clock ( 640MHz) \n
--! Based on TDC code by Alvaro Dosil\n
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--!
--
--! @date 15:43:57 11/08/12
--
--! @version v0.1
--
--! @details
--! IPBus address 0 = control and status
--! bit0 = reset serdes
--! bit1 = reset counter
--! bit2 = calibrate IDELAYs
--! bit3 = not connected
--!
--! bit4 = Thresh discr IDelay(0) status prompt
--! bit5 = Thresh discr IDelay(0) status delayed
--! bit6 = Thresh discr IDelay(1) status prompt
--! bit7 = Thresh discr IDelay(1) status delayed
--! bit8 = Thresh discr IDelay(2) status prompt
--! bit9 = Thresh discr IDelay(2) status delayed
--! bit10= Thresh discr IDelay(3) status prompt
--! bit11= Thresh discr IDelay(3) status delayed
--!
--! bit12= CFD discr IDelay(0) status prompt
--! bit13= CFD discr IDelay(0) status delayed
--! bit14= CFD discr IDelay(1) status prompt
--! bit15= CFD discr IDelay(1) status delayed
--! bit16= CFD discr IDelay(2) status prompt
--! bit17= CFD discr IDelay(2) status delayed
--! bit18= CFD discr IDelay(3) status prompt
--! bit19= CFD discr IDelay(3) status delayed
--!
--! bit20= Thresh deserialized data monitor(0)
--! bit21= Thresh deserialized data monitor(1)
--! bit22= Thresh deserialized data monitor(2)
--! bit23= Thresh deserialized data monitor(3)
--! bit24= CFD deserialized data monitor(0)
--! bit25= CFD deserialized data monitor(1)
--! bit26= CFD deserialized data monitor(2)
--! bit27= CFD deserialized data monitor(3)
--!
--! IPBus address 1 = edge rising(0) counter
--! IPBus address 2 = edge rising(1) counter
--! IPBus address 3 = edge rising(2) counter
--! IPBus address 4 = edge rising(3) counter
--!
--! Dependencies:\n
--!
--! References:\n
--!
--! Modified by: Alvaro Dosil , alvaro.dosil@usc.es \n
--! Author:
-------------------------------------------------------------------------------
--! \n\nLast changes:\n
-------------------------------------------------------------------------------
--! @todo Implement a periodic calibration sequence \n
--! \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
use work.ipbus_reg_types.all;
USE work.fmcTLU.all;
library unisim ;
use unisim.vcomponents.all;
ENTITY triggerInputs IS
GENERIC(
g_NUM_INPUTS : natural := 1;
g_IPBUS_WIDTH : positive := 32
);
PORT(
cfd_discr_p_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);--! Inputs from constant-fraction discriminators
cfd_discr_n_i : IN std_logic_vector (g_NUM_INPUTS-1 downto 0);--! Input from CFD
clk_4x_logic : IN std_logic; --! Rising edge active. By default = 4*40MHz = 160MHz
strobe_4x_logic_i : IN std_logic; --! Pulses high once every 4 cycles of clk_4x_logic
threshold_discr_p_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); --! inputs from threshold comparators
threshold_discr_n_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); --! inputs from threshold comparators
reset_i : IN std_logic;
trigger_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! trigger arrival time ( w.r.t. logic_strobe)
trigger_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);--! Goes high on leading edge of trigger, in sync with clk_4x_logic_i
trigger_debug_o : OUT std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0); --! Copy of input trigger level. High bits CFD, Low threshold
edge_rising_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! edge arrival time ( w.r.t. logic_strobe)
edge_falling_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! edge arrival time ( w.r.t. logic_strobe)
edge_rising_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); --! High when rising edge. Syncronous with clk_4x_logic_i
edge_falling_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); --! High when falling edge
ipbus_clk_i : IN std_logic;
ipbus_reset_i : IN std_logic;
ipbus_i : IN ipb_wbus; --! Signals from IPBus core to slave
ipbus_o : OUT ipb_rbus; --! signals from slave to IPBus core
clk_16x_logic_i : IN std_logic; --! 640MHz clock ( 16x 40MHz )
strobe_16x_logic_i : IN std_logic --! Pulses one cycle every 4 of 16x clock.
);
-- Declarations
END ENTITY triggerInputs ;
--
ARCHITECTURE rtl OF triggerInputs IS
signal s_rst_iserdes : std_logic := '0'; --! Reset ISERDES and IDELAY
signal s_threshold_discr_input , s_cfd_discr_input : std_logic_vector(g_NUM_INPUTS-1 downto 0); --! inputs from comparator
type t_deserialized_trigger_data_array is array ( natural range <> ) of std_logic_vector(7 downto 0); --
signal s_deserialized_threshold_data, s_deserialized_threshold_data_d , s_deserialized_cfd_data, s_deserialized_cfd_data_d : t_deserialized_trigger_data_array(g_NUM_INPUTS-1 downto 0);
type t_deserialized_trigger_data_array_l is array ( natural range <> ) of std_logic_vector(8 downto 0); --
signal s_deserialized_threshold_data_l , s_deserialized_cfd_data_l : t_deserialized_trigger_data_array_l(g_NUM_INPUTS-1 downto 0);
signal s_cfd_trigger_times : t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);
signal s_CFD_rising_edge : std_logic_vector(g_NUM_INPUTS-1 downto 0);
signal s_CFD_falling_edge : std_logic_vector(g_NUM_INPUTS-1 downto 0);
signal s_threshold_previous_late_bit : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0'); -- last bit to arrive from previous 4
signal s_CFD_previous_late_bit : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0'); -- last bit to arrive from previous 4
signal s_ipbus_ack : std_logic := '0'; -- used to produce a delayed IPBus ack signal
signal s_edge_rising_times: t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! edge arrival time ( w.r.t. logic_strobe)
signal s_edge_falling_times: t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! edge arrival time ( w.r.t. logic_strobe)
signal s_edge_rising: std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); --! High when rising edge
signal s_edge_falling: std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); --! High when falling edge
constant c_N_CTRL : positive := 1;
constant c_N_STAT : positive := g_NUM_INPUTS+1 ;
signal s_status_to_ipbus , s_sync_status_to_ipbus: ipb_reg_v(c_N_STAT-1 downto 0);
signal s_control_from_ipbus , s_sync_control_from_ipbus: ipb_reg_v(c_N_CTRL-1 downto 0);
-- signal s_reset_reg , s_status_reg: std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
signal s_counter_reset, s_calibrate_idelay: std_logic := '0';
BEGIN
-----------------------------------------------------------------------------
-- IPBus interface
-----------------------------------------------------------------------------
-- Can't get ipbus_syncreg_v to meet timing. So use non-syncronized followed
-- by synchronizer.
ipbus_registers: entity work.ipbus_ctrlreg_v
generic map (
N_STAT => c_N_STAT )
port map(
clk=> ipbus_clk_i,
reset => ipbus_reset_i ,
ipbus_in => ipbus_i,
ipbus_out => ipbus_o,
d=> s_sync_status_to_ipbus,
q=> s_control_from_ipbus,
stb => open
);
-- sync data from I/O logic to IPBus
sync_registers: entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => c_N_STAT )
port map (
clk_input_i => clk_4x_logic,
data_i => s_status_to_ipbus,
data_o => s_sync_status_to_ipbus,
clk_output_i => ipbus_clk_i);
-- sync data from I/O logic to IPBus
sync_ipbus: entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => c_N_CTRL )
port map (
clk_input_i => ipbus_clk_i,
data_i => s_control_from_ipbus,
data_o => s_sync_control_from_ipbus,
clk_output_i => clk_4x_logic);
-- Map the control registers...
-- Register that controls IODELAY and ISERDES reset is at address 0
s_rst_iserdes <= reset_i or s_sync_control_from_ipbus(0)(0);
s_counter_reset <= s_sync_control_from_ipbus(0)(1);
s_calibrate_idelay <= s_sync_control_from_ipbus(0)(2);
s_status_to_ipbus(0)(0) <= s_rst_iserdes;
s_status_to_ipbus(0)(1) <= s_counter_reset;
s_status_to_ipbus(0)(2) <= s_calibrate_idelay;
-- Connect up unused lines in status regiser to 0.
s_status_to_ipbus(0)(3) <= '0';
s_status_to_ipbus(0)(g_IPBUS_WIDTH-1 downto 28) <= (others => '0');
-----------------------------------------------------------------------------
-- Connect up trigger inputs to deserializers and a LUT to determine
-- arrival time
-----------------------------------------------------------------------------
trigger_input_loop: for triggerInput in 0 to (g_NUM_INPUTS-1) generate
thresholdInputBuffer: IBUFDS
generic map (
DIFF_TERM => true,
IBUF_LOW_PWR => false,
IOSTANDARD => "LVDS_25")
port map (
O => s_threshold_discr_input(triggerInput),
I => threshold_discr_p_i(triggerInput),
IB => threshold_discr_n_i(triggerInput)
);
thresholdDeserializer: entity work.dualSERDES_1to4
port map (
reset_i => s_rst_iserdes,
--calibrate_i => s_calibrate_idelay,
data_i => s_threshold_discr_input(triggerInput),
fastClk_i => clk_16x_logic_i,
fabricClk_i => clk_4x_logic,
strobe_i => strobe_16x_logic_i,
data_o => s_deserialized_threshold_data(triggerInput),
status_o => s_status_to_ipbus(0)(5+(2*triggerInput) downto 4+(2*triggerInput))
);
--s_deserialized_threshold_data_l(triggerInput) <= s_deserialized_threshold_data(triggerInput)(3 downto 0) & s_deserialized_threshold_data_d(triggerInput)(7 downto 3);
s_deserialized_threshold_data_l(triggerInput) <= s_deserialized_threshold_data(triggerInput) & s_threshold_previous_late_bit(triggerInput);
thresholdLUT : entity work.arrivalTimeLUT
port map (
clk_4x_logic_i => clk_4x_logic,
strobe_4x_logic_i => strobe_4x_logic_i,
deserialized_data_i => s_deserialized_threshold_data_l(triggerInput),
first_rising_edge_time_o => s_edge_rising_times(triggerInput),
last_falling_edge_time_o => s_edge_falling_times(triggerInput),
rising_edge_o => s_edge_rising(triggerInput),
falling_edge_o => s_edge_falling(triggerInput),
multiple_edges_o => open
);
-- The leading edge may be a high-->low or a low-->high transition (
-- depending on polarity of input signal. ). For now assume that leading
-- edge is low-->high and connect trigger times and trigger output accordingly.
-- In the future have this selectable.
edge_rising_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
edge_falling_times_o(triggerInput) <= s_edge_falling_times(triggerInput);
edge_rising_o(triggerInput) <= s_edge_rising(triggerInput);
edge_falling_o(triggerInput) <= s_edge_falling(triggerInput);
trigger_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
trigger_o(triggerInput) <= s_edge_rising(triggerInput);
CFDInputBuffer: IBUFDS
generic map (
DIFF_TERM => true,
IBUF_LOW_PWR => false,
IOSTANDARD => "LVDS_25")
port map (
O => s_CFD_discr_input(triggerInput),
I => CFD_discr_p_i(triggerInput),
IB => CFD_discr_n_i(triggerInput)
);
CFDDeserializer: entity work.dualSERDES_1to4
port map (
reset_i => s_rst_iserdes,
--calibrate_i => s_calibrate_idelay,
data_i => s_CFD_discr_input(triggerInput),
fastClk_i => clk_16x_logic_i,
fabricClk_i => clk_4x_logic,
strobe_i => strobe_16x_logic_i,
data_o => s_deserialized_CFD_data(triggerInput),
status_o => s_status_to_ipbus(0)(13+(2*triggerInput) downto 12+(2*triggerInput))
);
--s_deserialized_CFD_data(triggerInput) <= (others=>'0');
s_deserialized_CFD_data_l(triggerInput) <= s_deserialized_CFD_data(triggerInput) & s_CFD_previous_late_bit(triggerInput);
CFDLUT : entity work.arrivalTimeLUT
port map (
clk_4x_logic_i => clk_4x_logic,
strobe_4x_logic_i => strobe_4x_logic_i,
deserialized_data_i => s_deserialized_CFD_data_l(triggerInput),
first_rising_edge_time_o => s_cfd_trigger_times(triggerInput),
last_falling_edge_time_o => open,
rising_edge_o => s_CFD_rising_edge(triggerInput),
falling_edge_o => s_CFD_falling_edge(triggerInput),
multiple_edges_o => open
);
p_register_delayed_bits : process ( clk_4x_logic )
begin
if rising_edge(clk_4x_logic) then
s_threshold_previous_late_bit(triggerInput) <= s_deserialized_threshold_data(triggerInput)(7);
--s_deserialized_threshold_data_d(triggerInput) <= s_deserialized_threshold_data(triggerInput);
s_CFD_previous_late_bit(triggerInput) <= s_deserialized_CFD_data(triggerInput)(7);
-- Monitor output of serdes - just look at one per serdes
-- Don't care about latency so put a couple of registers in to aid
-- timing closure.
s_status_to_ipbus(0)(20+triggerInput) <= s_threshold_previous_late_bit(triggerInput);
s_status_to_ipbus(0)(24+triggerInput) <= s_CFD_previous_late_bit(triggerInput);
end if ;
end process;
--! Instantiate counter for output triggers.
--! Input I is connected to address I+1
cmp_inputTriggerCounter : entity work.counterWithReset
generic map (
g_COUNTER_WIDTH => g_IPBUS_WIDTH)
port map (
clock_i => clk_4x_logic,
reset_i => s_counter_reset,
enable_i => s_edge_rising(triggerInput),
result_o => s_status_to_ipbus(triggerInput+1));
end generate trigger_input_loop;
--trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_CFD_discr_input;
--trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_edge_rising;
--! Monitor output of deserializer
-- trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_status_to_ipbus(0)(23 downto 20);
--trigger_debug_o( (g_NUM_INPUTS-1) downto 0) <= s_edge_rising;
trigger_debug_o( (g_NUM_INPUTS-1) downto 0) <= s_threshold_discr_input;
trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_edge_rising;
END ARCHITECTURE rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/common/triggerLogic_rtl.vhd 0000664 0000000 0000000 00000032076 12415504633 0026772 0 ustar 00root root 0000000 0000000 --=============================================================================
--! @file triggerLogic_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.triggerLogic.rtl
--
--! @brief Produces triggers from either trigger inputs or internal generator\n
--! IPBus address map:\n
--! 0x00000000 RO - Number of triggers issued since last reset.\n
--! 0x00000001 RO - Number of possible triggers since last reset (i.e. pre-veto triggers)\n
--! 0x00000010 RW - Interval between internal triggers in ticks of logic_strobe_i\n
--! 0x00000011 RW - trigger mask ( 1 bit per input )\n
--! 0x00000100 RW - bit-0 - internal trigger veto. Set to halt vetos.\n
--! 0x00000101 RO - state of external veto
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 16:06:19 11/09/12
--
--! @version v0.1
--
--! @details
--!
--!
--! Dependencies:\n
--!
--! References:\n
--!
--! Modified by: Alvaro Dosil , alvaro.dosil@usc.es \n
--! Author:
-------------------------------------------------------------------------------
--! \n\nLast changes:\n
--! Move all IPBus stuff into ipbus_syncreg_v , which also handles clock domain
--! crossing. 20/Feb/2014 , David Cussans
-------------------------------------------------------------------------------
--! @todo \n
--! \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
use work.ipbus_reg_types.all;
USE work.fmcTLU.all;
ENTITY triggerLogic IS
GENERIC(
g_NUM_INPUTS : positive := 4;
g_IPBUS_WIDTH : positive := 32
);
PORT(
clk_4x_logic_i : IN std_logic; -- ! Rising edge active
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus; -- Signals from IPBus core to slave
ipbus_reset_i : IN std_logic;
logic_reset_i : IN std_logic; -- active high. Synchronous with clk_4x_logic
logic_strobe_i : IN std_logic; -- ! Pulses high once every 4 cycles of clk_4x_logic
trigger_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when trigger from input connector active
trigger_times_i : IN t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! trigger arrival time
veto_i : IN std_logic; -- ! Halts triggers when high
trigger_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when trigger from input connector active and enabled
trigger_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! trigger arrival time
event_number_o : OUT std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); -- starts at one. Increments for each post_veto_trigger
ipbus_o : OUT ipb_rbus; -- signals from slave to IPBus core
post_veto_trigger_o : OUT std_logic; -- ! goes high when trigger passes
pre_veto_trigger_o : OUT std_logic;
trigger_active_o : OUT std_logic --! Goes high when triggers are active ( ie. not veoted)
);
-- Declarations
END ENTITY triggerLogic ;
--
ARCHITECTURE rtl OF triggerLogic IS
--! vector that stores trigger output for each combination of trigger inputs.
signal s_trigger_inputs_enabled , s_trigger_inputs_enabled_ipb : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := x"00000001";--(others=>'1');
signal s_external_trigger , s_internal_veto , s_internal_veto_ipb : std_logic := '0';
signal s_internal_trigger_interval: std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); -- setting s_internal_trigger_interval to zero means no internal triggers
signal s_pre_veto_trigger_counter , s_post_veto_trigger_counter : unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); -- ! counters for triggers before and after veto
signal s_pre_veto_trigger_counter_ipb , s_post_veto_trigger_counter_ipb : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); -- ! counters for triggers before and after veto, on ipbus clock domain
signal s_triggers : std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0) := (others=>'0');
signal s_trigger_times : t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0) := (others=>(others=>'0'));
signal s_internal_trigger, s_internal_trigger_d : std_logic := '0'; -- ! Strobes high for one clock cycle at intervals of s_internal_trigger_interval cycles
-- signal s_internal_trigger_timer : unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); -- counter for internal trigger generation
signal s_internal_trigger_timer , s_internal_trigger_timer_d : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); -- counter for internal trigger generation and counter delay
signal s_internal_trigger_active , s_internal_trigger_active_d, s_internal_trigger_active_ipb : std_logic := '0'; -- ! Goes high when internal trigger is running.
signal s_ipbus_ack : std_logic := '0'; -- used to produce a delayed IPBus ack signal
-- signal s_logic_reset , s_logic_reset_ipb : std_logic := '0'; -- ! Take high to reset counters etc.
signal s_pre_veto_trigger ,s_post_veto_trigger : std_logic := '0'; -- ! Can't read from an output port so keep internal copy
signal s_AND_Window : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); --! Time window for the trigger coincidence
signal s_AND_Mask, s_AND_Mask_ipb : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); --! Mask to select the trigger inputs in coincidence
signal s_OR_Mask : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
signal s_AND_trigger: std_logic := '0';
signal s_OR_trigger: std_logic := '0';
constant c_N_CTRL : positive := 8;
constant c_N_STAT : positive := 8;
signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
signal s_control_from_ipbus,s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
signal s_veto_word : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
signal s_external_veto_word : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
BEGIN
-----------------------------------------------------------------------------
-- IPBus interface
-----------------------------------------------------------------------------
ipbus_registers: entity work.ipbus_ctrlreg_v
generic map(
N_CTRL => c_N_CTRL,
N_STAT => c_N_STAT
)
port map(
clk => ipbus_clk_i,
reset=> '0',--ipbus_reset_i ,
ipbus_in=> ipbus_i,
ipbus_out=> ipbus_o,
d=> s_sync_status_to_ipbus,
q=> s_control_from_ipbus,
stb=> open
);
-- Synchronize registers from logic clock to ipbus.
sync_status: entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => c_N_STAT )
port map (
clk_input_i => clk_4x_logic_i,
data_i => s_status_to_ipbus,
data_o => s_sync_status_to_ipbus,
clk_output_i => ipbus_clk_i);
-- Synchronize registers from logic clock to ipbus.
sync_ctrl: entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => c_N_CTRL )
port map (
clk_input_i => ipbus_clk_i,
data_i => s_control_from_ipbus,
data_o => s_sync_control_from_ipbus,
clk_output_i => clk_4x_logic_i);
-- Map the control registers
-- workaround to match the number of clock cycles with the configured interval
s_internal_trigger_interval <= x"00000000" when s_sync_control_from_ipbus(2)'0');
s_status_to_ipbus(6) <= s_AND_Mask;
s_status_to_ipbus(7) <= s_AND_Window;
-----------------------------------------------------------------------------
-- Generate triggers
-----------------------------------------------------------------------------
s_AND_Mask <= s_AND_Mask_ipb and s_trigger_inputs_enabled;
s_OR_Mask <= (not s_AND_Mask) and s_trigger_inputs_enabled; -- Inputs not selected for coincidence will work as OR triggers.
--s_OR_trigger <= '0' when (s_OR_Mask(trigger_i'range) and trigger_i) = std_logic_vector(to_unsigned(0,trigger_i'length)) else
-- '1';
-- Trigger Filtering
s_external_trigger <= '0' when (s_trigger_inputs_enabled(trigger_i'range) and trigger_i) = std_logic_vector(to_unsigned(0,trigger_i'length)) else
'1';
s_triggers <= trigger_i and s_trigger_inputs_enabled(trigger_i'range);
trig_masks : process(trigger_times_i, s_trigger_inputs_enabled)
begin
for i in 0 to g_NUM_INPUTS-1 loop
s_trigger_times(i)(4 downto 3) <= trigger_times_i(i)(4 downto 3);
if s_trigger_inputs_enabled(i)='1' then
s_trigger_times(i)(2 downto 0) <= trigger_times_i(i)(2 downto 0);
else
s_trigger_times(i)(2 downto 0) <= "000";
end if;
end loop;
end process;
trigger_o <= s_triggers;
trigger_times_o <= s_trigger_times;
-- --! Trigger coincidence logic
-- coincicence_logic : entity work.coincidences
-- generic map(
-- g_nInputs => g_NUM_INPUTS,
-- g_IPBUS_WIDTH => g_IPBUS_WIDTH
-- )
-- Port map(
-- trigger_i => trigger_i,
-- data_i => trigger_times_i,
-- clk_i => clk_4x_logic_i,
-- rst_i => logic_reset_i,
-- Window_i => s_AND_Window,
-- mask_i => s_AND_Mask,
-- trigger_o => s_AND_trigger,
-- data_first_trig_o => open,
-- data_o => trigger_times_o
-- );
--s_external_trigger <= s_OR_trigger; -- or s_AND_trigger;
--! Produce triggers....
trigGen : process ( clk_4x_logic_i )
begin
if rising_edge(clk_4x_logic_i) then
s_post_veto_trigger <= (s_external_trigger or s_internal_trigger) and (not ( s_internal_veto or veto_i) );
s_pre_veto_trigger <= (s_external_trigger or s_internal_trigger);
end if;
end process;
pre_veto_trigger_o <= s_pre_veto_trigger ;
post_veto_trigger_o <= s_post_veto_trigger;
trigger_active_o <= s_post_veto_trigger;
--! Internal trigger generator
p_internal_triggers: process (clk_4x_logic_i )
begin -- process p_internal_triggers
if rising_edge(clk_4x_logic_i) then
if (s_internal_trigger_interval = x"00000000") then
s_internal_trigger_active <= '0';
else
s_internal_trigger_active <= '1';
end if;
s_internal_trigger_active_d <= s_internal_trigger_active; -- signal delayed
s_internal_trigger_timer_d <= s_internal_trigger_timer; -- Signal delayed
end if;
end process p_internal_triggers;
s_internal_trigger <= '1' when (s_internal_trigger_timer = ( x"00000000" )) and (s_internal_trigger_timer_d = ( x"00000001" ))
else '0';
-- Use a coregen counter to allow timing constraints to be met.
c_internal_triggers: entity work.internalTriggerGenerator
PORT MAP (
clk => clk_4x_logic_i,
ce => s_internal_trigger_active,
load => s_internal_trigger or (s_internal_trigger_active and not s_internal_trigger_active_d),
l => s_internal_trigger_interval,
q => s_internal_trigger_timer
);
-----------------------------------------------------------------------------
-- Count triggers
-----------------------------------------------------------------------------
p_trigger_counter: process (clk_4x_logic_i )
begin -- process p_trigger_counter
if rising_edge(clk_4x_logic_i) then
if logic_reset_i = '1' then
s_post_veto_trigger_counter <= ( others => '0');
elsif s_post_veto_trigger = '1' then
s_post_veto_trigger_counter <= s_post_veto_trigger_counter + 1;
end if;
if logic_reset_i = '1' then
s_pre_veto_trigger_counter <= ( others => '0');
elsif s_pre_veto_trigger = '1' then
s_pre_veto_trigger_counter <= s_pre_veto_trigger_counter + 1;
end if;
end if;
end process p_trigger_counter;
event_number_o <= std_logic_vector(s_post_veto_trigger_counter);
END ARCHITECTURE rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/test/ 0000775 0000000 0000000 00000000000 12415504633 0022444 5 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/test/DUTInterfaces_rtl.vhd 0000664 0000000 0000000 00000023012 12415504633 0026466 0 ustar 00root root 0000000 0000000 --=============================================================================
--! @file DUTInterfaces_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.DUTInterfaces.rtl
--
--! @brief \n
--! \n
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 15:09:50 11/09/12
--
--! @version v0.1
--
--! @details
--! Address map:\n
--! 5-bit decoded
--! 0x00000000 - DUT interface mode, two bits per DUT. Up to 12 inputs XXXXXXXXBBAA99887766554433221100\n
--! - mode: 0 = EUDET mode , 1 = synchronous ( LHC / Timepix ) , 2,3=reserved
--!
--
--!
--! Dependencies:\n
--!
--! References:\n
--!
--! Modified by:\n
--! Author:
-------------------------------------------------------------------------------
--! \n\nLast changes:\n
-------------------------------------------------------------------------------
--! @todo Indicate if the DUT works under AIDA/EUDET style\n
--! \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
use work.ipbus_reg_types.all;
library unisim;
use unisim.VComponents.all;
ENTITY DUTInterfaces IS
GENERIC(
g_NUM_DUTS : positive := 3;
g_IPBUS_WIDTH : positive := 32
);
PORT(
--busy_from_dut_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
--busy_from_dut_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
clk_4x_logic_i : IN std_logic;
clk_from_dut_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
clk_from_dut_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus; -- Signals from IPBus core to slave
ipbus_reset_i : IN std_logic;
strobe_4x_logic_i : IN std_logic; -- ! goes high every 4th clock cycle
trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);
trigger_i : IN std_logic; -- goes high when trigger logic issues a trigger
--shutter_i : IN std_logic; -- goes high when trigger logic issues a shutter
ipbus_o : OUT ipb_rbus; -- signals from slave to IPBus core
--reset_or_clk_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
--reset_or_clk_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
--trigger_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
--trigger_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
--shutter_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Shutter output
--shutter_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Shutter output
output_0_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_0_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_1_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_1_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_2_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_2_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_3_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_3_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
veto_o : OUT std_logic -- goes high when one or more DUT are busy
);
-- Declarations
END ENTITY DUTInterfaces ;
--
ARCHITECTURE rtl OF DUTInterfaces IS
signal s_intermediate_busy_or : std_logic_vector(g_NUM_DUTS downto 0); -- OR tree
signal s_veto : std_logic;
signal s_strobe_4x_logic_d1, clk_2x_logic : std_logic;
signal s_busy_from_dut , s_clk_from_dut , s_reset_or_clk_to_dut , s_trigger_to_dut , s_shutter_to_dut: std_logic_vector(g_NUM_DUTS-1 downto 0);
signal s_DUT_mask : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0'); --! Mask for the DUTs not used
signal s_EnableOutput : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
constant c_N_CTRL : positive := 2;
constant c_N_STAT : positive := 2;
signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
signal s_control_from_ipbus,s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
BEGIN
-- Dummy code.
s_intermediate_busy_or(0) <= '0';
--s_busy_from_dut(g_NUM_DUTS-1 downto 0) <= (others=>'0');
-----------------------------------------------------------------------------
-- IPBus interface
-----------------------------------------------------------------------------
ipbus_registers: entity work.ipbus_ctrlreg_v
generic map(
N_CTRL => c_N_CTRL,
N_STAT => c_N_STAT
)
port map(
clk => ipbus_clk_i,
reset=> '0',--ipbus_reset_i ,
ipbus_in=> ipbus_i,
ipbus_out=> ipbus_o,
d=> s_sync_status_to_ipbus,
q=> s_control_from_ipbus,
stb=> open
);
-- Synchronize registers from logic clock to ipbus.
sync_status: entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => c_N_STAT )
port map (
clk_input_i => clk_4x_logic_i,
data_i => s_status_to_ipbus,
data_o => s_sync_status_to_ipbus,
clk_output_i => ipbus_clk_i);
-- Synchronize registers from logic clock to ipbus.
sync_ctrl: entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => c_N_CTRL )
port map (
clk_input_i => ipbus_clk_i,
data_i => s_control_from_ipbus,
data_o => s_sync_control_from_ipbus,
clk_output_i => clk_4x_logic_i);
-- Map the control registers
s_DUT_mask <= s_sync_control_from_ipbus(0)(g_NUM_DUTS-1 downto 0);
s_EnableOutput <= s_sync_control_from_ipbus(1);
-- Map the status registers
s_status_to_ipbus(0) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-g_NUM_DUTS)) & s_DUT_mask;
s_status_to_ipbus(1) <= s_EnableOutput;
-- purpose: Writes in the positive pin of the signals an 80MHz clock and the strobe_4x_logic_i in the negative one.
--The output signals (one signal is an lvds pair) can be enabled independently in the s_EnableOutput via IPBus.
-- type : combinational
-- inputs : clk_2x_logic , strobe_4x_logic_i, s_EnableOutput
-- outputs: output_0_p, output_0_n, output_1_p, output_1_n, output_2_p, output_2_n, output_3_p, output_3_n
duts: for dut in 1 to g_NUM_DUTS generate
output_0_p_inst : OBUF
port map (
O => output_0_p(dut-1),
I => s_EnableOutput(0) and clk_2x_logic -- Buffer input
);
output_0_n_inst : OBUF
port map (
O => output_0_n(dut-1),
I => s_EnableOutput(0) and strobe_4x_logic_i -- Buffer input
);
output_1_p_inst : OBUF
port map (
O => output_1_p(dut-1),
I => s_EnableOutput(1) and clk_2x_logic -- Buffer input
);
output_1_n_inst : OBUF
port map (
O => output_1_n(dut-1),
I => s_EnableOutput(1) and strobe_4x_logic_i -- Buffer input
);
output_2_p_inst : OBUF
port map (
O => output_2_p(dut-1),
I => s_EnableOutput(2) and clk_2x_logic -- Buffer input
);
output_2_n_inst : OBUF
port map (
O => output_2_n(dut-1),
I => s_EnableOutput(2) and strobe_4x_logic_i -- Buffer input
);
output_3_p_inst : OBUF
port map (
O => output_3_p(dut-1),
I => s_EnableOutput(3) and clk_2x_logic -- Buffer input
);
output_3_n_inst : OBUF
port map (
O => output_3_n(dut-1),
I => s_EnableOutput(3) and strobe_4x_logic_i -- Buffer input
);
s_intermediate_busy_or(dut) <= s_intermediate_busy_or(dut-1) or
(s_busy_from_dut(dut-1) and
s_DUT_mask(dut-1));
end generate duts;
s_veto <= s_intermediate_busy_or(g_NUM_DUTS);
clk_2x_logic <= s_strobe_4x_logic_d1 or strobe_4x_logic_i; --80 MHz clock
-- purpose: register for internal signals and output signals
-- type : combinational
-- inputs : clk_4x_logic_i , strobe_4x_logic_i , s_veto
-- outputs: veto_o
register_signals: process (clk_4x_logic_i)-- , strobe_4x_logic_i , s_veto)
begin -- process register_signals
if rising_edge(clk_4x_logic_i) then
veto_o <= s_veto;
s_strobe_4x_logic_d1 <= strobe_4x_logic_i;
s_reset_or_clk_to_dut <= ( others => (s_strobe_4x_logic_d1 or strobe_4x_logic_i));
s_trigger_to_dut <= ( others => trigger_i );
--shutter_to_dut <= ( others => shutter_i );
end if;
end process register_signals;
END ARCHITECTURE rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/test/clock_divider_s6.v 0000775 0000000 0000000 00000001176 12415504633 0026054 0 ustar 00root root 0000000 0000000 `timescale 1ns / 1ps
module clock_divider_s6(
input clk,
output d25,
output d28
);
wire [6:0] q;
reg [5:0] qr = 0;
reg [2:0] ctr = 0;
//wire unconnected; // horrid hack
assign q[0] = 1'b1;
generate
genvar i;
for(i=1; i<=5; i=i+1) begin: gen_sr
SRLC32E #(
.INIT(32'h80000000)
) sr_0 (
.Q(q[i]),
.A(5'b11111),
.CE(q[i-1] & ~qr[i-1]),
.CLK(clk),
.D(q[i])
);
always @(posedge clk)
begin
qr[i] <= q[i];
end
end
endgenerate
assign d25 = q[5];
always @(posedge clk)
begin
if(q[5] & ~qr[5]) ctr <= ctr + 1;
end
assign d28 = ctr[2];
endmodule
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/test/clocks_s6_extphy.vhd 0000775 0000000 0000000 00000003504 12415504633 0026443 0 ustar 00root root 0000000 0000000 -- clocks_s6_extphy
--
-- Generates a 125MHz ethernet clock and 31MHz ipbus clock from the 200MHz reference
-- Includes reset logic for ipbus
--
-- Dave Newbold, April 2011
--
-- $Id$
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.VComponents.all;
entity clocks_s6_extphy is port(
sysclk_p, sysclk_n: in std_logic;
clko_125: out std_logic;
clko_ipb: out std_logic;
locked: out std_logic;
rsto_125: out std_logic;
rsto_ipb: out std_logic;
onehz: out std_logic
);
end clocks_s6_extphy;
architecture rtl of clocks_s6_extphy is
signal clk_ipb_i, clk_ipb_b, clk_125_i, clk_125_b, sysclk: std_logic;
signal d25, d25_d, dcm_locked: std_logic;
signal rst: std_logic := '1';
component clock_divider_s6 port(
clk: in std_logic;
d25: out std_logic;
d28: out std_logic
);
end component;
begin
ibufgds0: IBUFGDS port map(
i => sysclk_p,
ib => sysclk_n,
o => sysclk
);
bufg_125: BUFG port map(
i => clk_125_i,
o => clk_125_b
);
clko_125 <= clk_125_b;
bufg_ipb: BUFG port map(
i => clk_ipb_i,
o => clk_ipb_b
);
clko_ipb <= clk_ipb_b;
dcm0: DCM_CLKGEN
generic map(
CLKIN_PERIOD => 5.0,
CLKFX_MULTIPLY => 5,
CLKFX_DIVIDE => 8,
CLKFXDV_DIVIDE => 4
)
port map(
clkin => sysclk,
clkfx => clk_125_i,
clkfxdv => clk_ipb_i,
locked => dcm_locked,
rst => '0'
);
clkdiv: clock_divider_s6 port map(
clk => sysclk,
d25 => d25,
d28 => onehz
);
process(sysclk)
begin
if rising_edge(sysclk) then
d25_d <= d25;
if d25='1' and d25_d='0' then
rst <= not dcm_locked;
end if;
end if;
end process;
locked <= dcm_locked;
process(clk_ipb_b)
begin
if rising_edge(clk_ipb_b) then
rsto_ipb <= rst;
end if;
end process;
process(clk_125_b)
begin
if rising_edge(clk_125_b) then
rsto_125 <= rst;
end if;
end process;
end rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/test/dtype_fd.vhdl 0000664 0000000 0000000 00000001217 12415504633 0025122 0 ustar 00root root 0000000 0000000 ----- CELL dtype_fd -----
--
--@file
--
--@brief Aims to be the same as the Xilinx "FD" primitive -
-- D-Type flip-flop
--
-- Modified from D-type example in VHDL book.
-- See Xilinx spartan6_scm.pdf
--
-- David Cussans, Feb 2011
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity dtype_fd is
port(
Q : out std_logic; --! Output
CLK : in std_logic; --! Clock - rising edge active
D : in std_logic --! Input
);
end dtype_fd;
architecture rtl of dtype_fd is
begin
VITALBehavior : process(CLK)
begin
if rising_edge(CLK) then
Q <= D ;
end if;
end process;
end rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/test/dtype_fdpe.vhdl 0000664 0000000 0000000 00000001576 12415504633 0025457 0 ustar 00root root 0000000 0000000 ----- CELL dtype_fdpe -----
--
--@file
--
--@brief Aims to be the same as the Xilinx "FDPE" primitive -
-- D-Type flip-flop with asynchronous set.
--
-- Modified from D-type example in VHDL book.
-- See Xilinx spartan6_scm.pdf
--
-- David Cussans, Feb 2011
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- use IEEE.VITAL_Timing.all;
entity dtype_fdpe is
port(
Q : out std_logic; --! Output
CLK : in std_logic; --! Clock - rising edge active
D : in std_logic; --! Input
CE : in std_logic; --! Clock enable
PRE : in std_logic --! Asynchronous preload
);
end dtype_fdpe;
architecture dtype_V of dtype_fdpe is
begin
VITALBehavior : process(CLK, PRE , CE)
begin
if (PRE = '1') then
Q <= '1';
elsif ( rising_edge(CLK) and CE = '1' ) then
Q <= D ;
end if;
end process;
end dtype_V;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/test/dtype_fdr.vhdl 0000664 0000000 0000000 00000003235 12415504633 0025306 0 ustar 00root root 0000000 0000000
--! @file dtype_fdr.vhdl
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group --
-- --
-------------------------------------------------------------------------------
--
-- unit name: dtype_fdr
--
--! @brief Aims to be the same as the Xilinx "FD" primitive - D-Type flip-flop
--
--
--! @author David.Cussans@bristol.ac.uk
--
--! @date 7/May/2011
--
--! @version 0.1
--
--! @details -- Modified from D-type example in VHDL book.
--! See Xilinx spartan6_scm.pdfOutput goes high when input goes high ( asyncnronous to system clock).
--
--! Dependencies:\n
--!
--! References:\n
--! \n
--!
--!
--! Modified by:\n
--! Author:
-------------------------------------------------------------------------------
--! \n\nLast changes:\n
--! \n
--!
-------------------------------------------------------------------------------
--! @todo \n
--! \n
--
-------------------------------------------------------------------------------
entity dtype_fdr is
port(
Q : out std_logic; --! Output
CLK : in std_logic; --! Clock - rising edge active
RST : in std_logic; --! Active high, synchronous
D : in STD_LOGIC --! Input
);
end dtype_fdr;
architecture rtl of dtype_fdr is
begin
VITALBehavior : process(CLK)
begin
if rising_edge(CLK) then
if (RST = '1') then
Q <= '0';
else
Q <= D ;
end if;
end if;
end process;
end rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/test/dtype_fds.vhdl 0000664 0000000 0000000 00000003243 12415504633 0025306 0 ustar 00root root 0000000 0000000
--! @file dtype_fds.vhdl
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group --
-- --
-------------------------------------------------------------------------------
--
-- unit name: dtype_fds
--
--! @brief Aims to be the same as the Xilinx "FDS" primitive - D-Type flip-flop
--
--
--! @author David.Cussans@bristol.ac.uk
--
--! @date 7/May/2011
--
--! @version 0.1
--
--! @details -- Modified from D-type example in VHDL book.
--! See Xilinx spartan6_scm.pdf
--! Output goes high when input goes high ( asyncnronous to system clock).
--
--! Dependencies:\n
--!
--! References:\n
--! \n
--!
--!
--! Modified by:\n
--! Author:
-------------------------------------------------------------------------------
--! \n\nLast changes:\n
--! \n
--!
-------------------------------------------------------------------------------
--! @todo \n
--! \n
--
-------------------------------------------------------------------------------
entity dtype_fds is
port(
Q : out std_logic; --! Output
CLK : in std_logic; --! Clock - rising edge active
SET : in std_logic; --! Active high, synchronous
D : in STD_LOGIC --! Input
);
end dtype_fds;
architecture rtl of dtype_fds is
begin
VITALBehavior : process(CLK)
begin
if rising_edge(CLK) then
if (SET = '1') then
Q <= '1';
else
Q <= D ;
end if;
end if;
end process;
end rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/test/fmc-tlu_sp601_pulse_shaper.vhdl 0000775 0000000 0000000 00000004031 12415504633 0030376 0 ustar 00root root 0000000 0000000 --@file
--
--@brief Top level for AIDA Mini-TLU in FMC format using IPBUS.
--
-- David Cussans, February 2011
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--! Use library for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.vcomponents.all;
entity fmc_tlu_sp601 is
port (
SYSCLK_N , SYSCLK_P : in std_logic; --! 200MHz crystal clock
D : in std_logic; --! pulse input
Q : out std_logic; --! pulse_output
RST : in std_logic; --! active high. Syncronous
pulse_length : in std_logic_vector(3 downto 0) --!
--Dummy
--to
--avoid pruning
);
end fmc_tlu_sp601;
architecture rtl of fmc_tlu_sp601 is
-- constant MASK_WIDTH : integer := 16; -- Number of registers in shift-reg
component pulse_shaper
port (
D_a_i : in std_logic; --! Input pulse
Q_a_o : out std_logic; --! output pulse
CLK_i : in std_logic; --! Clock , rising edge active
RST_i : in std_logic; --! Active high. Synchronous
PULSE_LENGTH_i : in std_logic_vector(3 downto 0)); -- ! Load with desired
-- width of pulse.
end component;
signal buffered_clock : std_logic := '0';
begin -- rtl
-- buf_sysclk : IBUFGDS
-- port map (
-- I => sysclk_p,
-- IB => sysclk_n,
-- O => buffered_clock);
-- for simulation bodge up by connecting buffered_clock to sysclk_p
buffered_clock <= sysclk_p;
shaper : pulse_shaper
port map (
D_a_i => D,
Q_a_o => Q,
RST_i => RST,
CLK_i => buffered_clock,
pulse_length_i => pulse_length);
end rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/test/fmc_tlu_sp601_tb.vhdl 0000664 0000000 0000000 00000010632 12415504633 0026374 0 ustar 00root root 0000000 0000000 --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:24:12 02/25/2011
-- Design Name:
-- Module Name: /afs/phy.bris.ac.uk/cad/designs/fmc-mtlu/trunk/firmware/synthesis/ise/mTLU/fmc_tlu_sp601_tb.vhd
-- Project Name: mTLU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: fmc_tlu_sp601
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.Math_real.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY fmc_tlu_sp601_tb IS
END fmc_tlu_sp601_tb;
ARCHITECTURE behavior OF fmc_tlu_sp601_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fmc_tlu_sp601
PORT(
SYSCLK_N : IN std_logic;
SYSCLK_P : IN std_logic;
D : IN std_logic;
Q : OUT std_logic;
RST: in std_logic;
pulse_length : IN std_logic_vector(3 downto 0)
);
END COMPONENT;
component pulse_shaper_scorer
port (
clk_i : in std_logic; -- ! system clock
pulse_in_a_i : in std_logic; -- ! input ( unstretched) pulse
pulse_out_a_i : in std_logic; -- ! stretched pulse (output of pulse_stretcher)
pulse_length_i : in std_logic_vector --! Parameter to pulse_strecher
);
end component;
--min and max can be swapped quite happily
procedure rand_int( variable seed1, seed2 : inout positive;
min, max : in integer;
result : out integer) is
variable rand : real;
begin
uniform(seed1, seed2, rand);
result := integer(real(min) + (rand * (real(max)-real(min)) ) );
end procedure;
--Inputs
signal SYSCLK_N : std_logic := '0';
signal SYSCLK_P : std_logic := '0';
signal SYSCLK : std_logic := '0';
signal D : std_logic := '0';
signal RST : std_logic := '0';
signal pulse_length : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal Q : std_logic;
constant sysclk_period : time := 10.0 ns;
constant averagePulseWidth : real := 3.0;
constant averagePulseLow : real := 500.0;
BEGIN
--! set pulse length to 7(?) clock cycles + internal
-- pulse_length <= "0100" ;
--! set pulse length to 5 clock cycles + internal
pulse_length <= "0001" ;
-- Instantiate the Unit Under Test (UUT)
uut: fmc_tlu_sp601 PORT MAP (
SYSCLK_N => SYSCLK_N,
SYSCLK_P => SYSCLK_P,
D => D,
Q => Q,
RST => RST,
pulse_length => pulse_length
);
--! Instantiate "scorer" process
--! Examine signals and check for errors
scorer: pulse_shaper_scorer
port map (
clk_i => sysclk ,
pulse_in_a_i => D,
pulse_out_a_i => Q,
pulse_length_i => pulse_length
);
-- Clock process definitions
sysclk_process :process
begin
sysclk <= '0';
wait for sysclk_period/2;
sysclk <= '1';
wait for sysclk_period/2;
end process;
sysclk_n <= not sysclk;
sysclk_p <= sysclk;
-- Stimulus process
stim_proc: process
variable seed1 , seed2 : POSITIVE;
variable PulseWidth , PulseLow : time ;
variable Rand : real;
begin
D <= '0';
RST <= '1';
-- hold reset state for 100 ns.
wait for 100 ns;
RST <= '0';
wait for sysclk_period*10;
-- insert stimulus here
for I in 1 to 50 loop
D<= '1';
-- wait for random pulse width
uniform(seed1, seed2, Rand);
PulseWidth := Rand * averagePulseWidth * sysclk_period;
wait for PulseWidth;
D<= '0';
-- wait for random gap between pulses
uniform(seed1, seed2, Rand);
PulseLow := Rand * averagePulseLow * sysclk_period;
wait for PulseLow;
end loop;
wait;
end process;
END;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/test/fmc_tlu_top_sp601.vhd 0000664 0000000 0000000 00000011121 12415504633 0026407 0 ustar 00root root 0000000 0000000 --=============================================================================
--! @file fmc_tlu_top_sp601.vhd
--=============================================================================
-- @brief Top-level design for ipbus Maroc test . You must edit this file to set the IP and MAC addresses
--
--! @details Based on ipbus_demo_sp601 by Dave Newbold, 23/2/11
--! This version is for xc6slx16 on Xilinx SP601 eval board
--! Uses the s6 soft TEMAC core with GMII inteface to an external Gb PHY
--! You will need a license for the core
--
--! @author David Cussans, 31/07/12
--
-- Top-level design for trigger logic unit with IPBus readout
--
-- This version is for xc6slx16 on Xilinx SP601 eval board
-- Uses the s6 soft TEMAC core with GMII inteface to an external Gb PHY
-- You will need a license for the core
--
-- You must edit this file to set the IP and MAC addresses
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ipbus.ALL;
use work.ipbus_bus_decl.all;
use work.emac_hostbus_decl.all;
--! Use UNISIM for Xilix primitives
Library UNISIM;
use UNISIM.vcomponents.all;
entity fmc_tlu_top is port(
sysclk_p, sysclk_n : in STD_LOGIC;
leds: out STD_LOGIC_VECTOR(3 downto 0);
gmii_gtx_clk, gmii_tx_en, gmii_tx_er : out STD_LOGIC;
gmii_txd : out STD_LOGIC_VECTOR(7 downto 0);
gmii_rx_clk, gmii_rx_dv, gmii_rx_er: in STD_LOGIC;
gmii_rxd : in STD_LOGIC_VECTOR(7 downto 0);
phy_rstb : out STD_LOGIC;
dip_switch: in std_logic_vector(3 downto 0);
-- Main I2C signals
i2c_sda_io: inout std_logic;
i2c_scl_io: inout std_logic;
);
end top;
architecture rtl of top is
--
signal clk125, ipb_clk, locked, rst_125, rst_ipb, onehz : STD_LOGIC;
signal ipb_clk_n : STD_LOGIC;
signal mac_txd, mac_rxd : STD_LOGIC_VECTOR(7 downto 0);
signal mac_txdvld, mac_txack, mac_rxclko, mac_rxdvld, mac_rxgoodframe, mac_rxbadframe : STD_LOGIC;
signal ipb_master_out : ipb_wbus;
signal ipb_master_in : ipb_rbus;
signal mac_addr: std_logic_vector(47 downto 0);
signal ip_addr: std_logic_vector(31 downto 0);
signal hostbus_in: emac_hostbus_in;
signal hostbus_out: emac_hostbus_out;
-- signals for main I2C
signal i2c_sda_oen_s: std_logic;
signal i2c_scl_oen_s: std_logic;
begin
-- DCM clock generation for internal bus, ethernet
clocks: entity work.clocks_s6_extphy port map(
sysclk_p => sysclk_p,
sysclk_n => sysclk_n,
clko_125 => clk125,
clko_ipb => ipb_clk,
locked => locked,
rsto_125 => rst_125,
rsto_ipb => rst_ipb,
onehz => onehz
);
leds <= ('0', '0', locked, onehz);
-- Ethernet MAC core and PHY interface
-- In this version, consists of hard MAC core and GMII interface to external PHY
-- Can be replaced by any other MAC / PHY combination
eth: entity work.eth_s6_gmii port map(
clk125 => clk125,
rst => rst_125,
gmii_gtx_clk => gmii_gtx_clk,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_txd => gmii_txd,
gmii_rx_clk => gmii_rx_clk,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_rxd => gmii_rxd,
txd => mac_txd,
txdvld => mac_txdvld,
txack => mac_txack,
rxd => mac_rxd,
rxclko => mac_rxclko,
rxdvld => mac_rxdvld,
rxgoodframe => mac_rxgoodframe,
rxbadframe => mac_rxbadframe,
hostbus_in => hostbus_in,
hostbus_out => hostbus_out
);
phy_rstb <= '1';
-- ipbus control logic
ipbus: entity work.ipbus_ctrl_udponly port map(
ipb_clk => ipb_clk,
rst_ipb => rst_ipb,
rst_macclk => rst_125,
mac_txclk => clk125,
mac_rxclk => mac_rxclko,
mac_rxd => mac_rxd,
mac_rxdvld => mac_rxdvld,
mac_rxgoodframe => mac_rxgoodframe,
mac_rxbadframe => mac_rxbadframe,
mac_txd => mac_txd,
mac_txdvld => mac_txdvld,
mac_txack => mac_txack,
ipb_out => ipb_master_out,
ipb_in => ipb_master_in,
mac_addr => mac_addr,
ip_addr => ip_addr
);
mac_addr <= X"020ddba115" & dip_switch & X"0"; -- Careful here, arbitrary addresses do not always work
ip_addr <= X"c0a8c8" & dip_switch & X"0"; -- 192.168.200.X
-- ipbus slaves live in the entity below, and can expose top-level ports
-- The ipbus fabric is instantiated within.
slaves: entity work.slaves port map(
ipb_clk => ipb_clk,
rst => rst_ipb,
ipb_in => ipb_master_out,
ipb_out => ipb_master_in,
-- Top level ports from here
hostbus_out => hostbus_in,
hostbus_in => hostbus_out,
gpio => open,
-- Main I2C signals
i2c_scl_i => i2c_scl_io ,
i2c_scl_oen_o => i2c_scl_oen_s ,
i2c_sda_i => i2c_sda_io,
i2c_sda_oen_o => i2c_sda_oen_s,
);
-- For main I2C bus, need to put in a tri-state....
i2c_scl_io <= '0' when (i2c_scl_oen_s = '0') else 'Z';
i2c_sda_io <= '0' when (i2c_sda_oen_s = '0') else 'Z';
end rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/test/i2c_chipscope_debug.cdc 0000664 0000000 0000000 00000003244 12415504633 0027002 0 ustar 00root root 0000000 0000000 #ChipScope Core Inserter Project File Version 3.0
#Tue Jul 23 13:58:01 BST 2013
Project.device.designInputFile=/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/fmcTLU/fmcTLU_v1/top_extphy_cs.ngc
Project.device.designOutputFile=/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/fmcTLU/fmcTLU_v1/top_extphy_cs.ngc
Project.device.deviceFamily=18
Project.device.enableRPMs=true
Project.device.outputDirectory=/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/fmcTLU/fmcTLU_v1/_ngo
Project.device.useSRL16=true
Project.filter.dimension=7
Project.filter<0>=*i2c*
Project.filter<1>=*sda*
Project.filter<2>=i2c*
Project.filter<3>=ipbus_clk*
Project.filter<4>=*wb_clk*
Project.filter<5>=wb_clk*
Project.filter<6>=
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataDepth=1024
Project.unit<0>.dataEqualsTrigger=true
Project.unit<0>.dataPortWidth=8
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=false
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=1
Project.unit<0>.triggerMatchCountWidth<0><0>=0
Project.unit<0>.triggerMatchType<0><0>=1
Project.unit<0>.triggerPortCount=1
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortWidth<0>=8
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=0
Project.unit<0>.type=ilapro
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/test/ipbus_addr_decode.vhd 0000775 0000000 0000000 00000003121 12415504633 0026566 0 ustar 00root root 0000000 0000000 -- Address decode logic for ipbus fabric
--
-- This file has been AUTOGENERATED from the address table - do not hand edit
--
-- We assume the synthesis tool is clever enough to recognise exclusive conditions
-- in the if statement.
--
-- Dave Newbold, February 2011
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use work.ipbus.all;
package ipbus_addr_decode is
function ipbus_addr_sel(signal addr : in std_logic_vector(31 downto 0)) return integer;
end ipbus_addr_decode;
package body ipbus_addr_decode is
function ipbus_addr_sel(signal addr : in std_logic_vector(31 downto 0)) return integer is
variable sel : integer;
begin
if std_match(addr, "--------------------------000-00") then
sel := 0; -- statusReg / base 00000000 / mask 00000000
elsif std_match(addr, "--------------------------000-01") then
sel := 1; -- controlReg / base 00000001 / mask 00000000
elsif std_match(addr, "--------------------------000-10") then
sel := 2; -- pulser / base 00000002 / mask 00000000
elsif std_match(addr, "--------------------------001---") then
sel := 3; -- cbcI2C / base 00000008 / mask 00000007
elsif std_match(addr, "--------------------------010---") then
sel := 4; -- mainI2C / base 00000010 / mask 00000007
elsif std_match(addr, "--------------------------011---") then
sel := 5; -- captureBuffer / base 00000018 / mask 00000007
elsif std_match(addr, "--------------------------100-0-") then
sel := 6; -- emac_hostbus / base 00000020 / mask 00000001
else
sel := 99;
end if;
return sel;
end ipbus_addr_sel;
end ipbus_addr_decode;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/test/ipbus_ver.vhd 0000775 0000000 0000000 00000002073 12415504633 0025152 0 ustar 00root root 0000000 0000000 -- Version register, returns a fixed value
--
-- To be replaced by a more coherent versioning mechanism later
--
-- Dave Newbold, August 2011
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ipbus.all;
entity ipbus_ver is
port(
ipbus_in: in ipb_wbus;
ipbus_out: out ipb_rbus
);
end ipbus_ver;
architecture rtl of ipbus_ver is
begin
ipbus_out.ipb_rdata <= X"a5cd" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out.ipb_ack <= ipbus_in.ipb_strobe;
ipbus_out.ipb_err <= '0';
end rtl;
-- Build log
--
-- build 0x1000 : 22/08/11 : Starting build ID
-- build 0x1001 : 29/08/11 : Version for SPI testing
-- build 0x1002 : 27/09/11 : Bug fixes, new transactor code; v1.3 candidate
-- build 0x1003 : buggy
-- build 0x1004 : 18/10/11 : New mini-t top level, bug fixes, 1.3 codebase
-- build 0x1005 : 20/10/11 : ipbus address config testing in mini-t
-- build 0x1006 : 26/10/11 : trying with jumbo frames
-- build 0x1007 : 27/10/11 : new slaves / address map + rhino frames
-- build 0x1008 : 31/10/11 : rhino frames + multibus demo
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/test/pulse_shaper.vhdl 0000664 0000000 0000000 00000013402 12415504633 0026015 0 ustar 00root root 0000000 0000000 --=============================================================================
--! @file pulse_shaper.vhdl
--=============================================================================
--! Standard library
Library IEEE;
--! Standard logic package
use IEEE.STD_LOGIC_1164.all;
--! Xilinx library
Library UNISIM;
--! Xilinx component
use UNISIM.vcomponents.all;
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group --
-- --
-------------------------------------------------------------------------------
--
-- unit name: pulse_shaper
--
--! @brief Output goes high when input goes high ( asyncnronous to system clock).
--! Output goes low again a controllable number of clock cycles later,
--! synchronous with the rising edge of the clock.
--! Gap of at least one clock cycle before output goes high again.
--
--! @author David.Cussans@bristol.ac.uk
--
--! @date 7/May/2011
--
--! @version 0.1
--
--! @details Output won't retrigger if input is still high at end of pulse.
--! Length of pulse (in clock cycles) is pulse_length+4
--
--! Dependencies:\n
--! dtype_fdpe
--! dtype_fdr
--! dtype_fds
--!
--! References:\n
--! \n
--!
--!
--! Modified by:\n
--! Author:
-------------------------------------------------------------------------------
--! \n\nLast changes:\n
--! \n
--!
--
-------------------------------------------------------------------------------
--! @todo Broaden pulse fed into set/reset flip-flop \n
--
-------------------------------------------------------------------------------
entity pulse_shaper is
port (
D_a_i : in std_logic; --! Input pulse
Q_a_o : out std_logic; --! output pulse
CLK_i : in std_logic; --! Clock , rising edge active
RST_i : in std_logic; --! Hold high for PULSE_LENGTH+4
PULSE_LENGTH_i : in std_logic_vector(3 downto 0) --! length of output pulse
);
end pulse_shaper;
architecture rtl of pulse_shaper is
component dtype_fdpe
port(
Q : out std_logic; --! Output
CLK : in std_logic; --! Clock - rising edge active
D : in std_logic; --! Input
CE : in std_logic; --! Clock enable
PRE : in std_logic --! Asynchronous preload
);
end component;
component dtype_fd
port(
Q : out std_logic; --! Output
CLK : in std_logic; --! Clock - rising edge active
D : in std_logic --! Input
);
end component;
component dtype_fds
port(
Q : out std_logic; --! Output
CLK : in std_logic; --! Clock - rising edge active
SET : in std_logic; --! Active high. Synchronous
D : in std_logic --! Input
);
end component;
component dtype_fdr
port(
Q : out std_logic; --! Output
CLK : in std_logic; --! Clock - rising edge active
RST : in std_logic; --! Active high. Synchronous
D : in std_logic --! Input
);
end component;
signal s_vetoed_pulse_a : std_logic := '0'; --! input signal after internal veto
signal s_async_pulse_a : std_logic := '0'; -- ! Output from pre-settable D-type
signal s_srl_ce , s_srl_d , s_srl_q : std_logic := '0'; -- ! Input, output from shift reg.
signal s_Q_d1 , s_Q_d2 , s_Q_d3 : std_logic := '0'; --! Output, delayed by one clock. Used to form veto.
signal s_D_d1 , s_D_d2 : std_logic := '0'; --! Input, delayed by one clock. Used to form veto.
begin -- rtl
--! Input to SRL16 pulses high for one cycle on rising edge. Goes high on RST
s_srl_d <= s_Q_d2 and (not s_Q_d3);
--! Clock the SRL if the output is high ( or if the output of the SRL is high.... )
s_srl_ce <= s_Q_d2 or s_srl_q ;
SRL16E_inst : SRL16E
generic map (
INIT => X"0000")
port map (
Q => S_SRL_Q, -- SRL data output
A0 => PULSE_LENGTH_i(0), -- Select[0] input
A1 => PULSE_LENGTH_i(1), -- Select[1] input
A2 => PULSE_LENGTH_i(2), -- Select[2] input
A3 => PULSE_LENGTH_i(3), -- Select[3] input
CE => S_SRL_CE, -- Clock enable input
CLK => CLK_i, --Clock input
D => S_SRL_D -- SRL data input
);
--! In order for a pulse to get to the PREset input, the output must be low
--! and the input must be low. Goes low on RST high
s_vetoed_pulse_a <= D_a_i and (not s_Q_d2) and (not s_D_d2);
Q_a_o <= s_async_pulse_a; --! Connect output of FDPE to output.
--! Async. set, sync clear.
async_reg: dtype_fdpe
port map (
Q => s_async_pulse_a,
D => '0', --! Clock in zero when shift reg. spits out a '1'
CLK => CLK_i,
CE => S_SRL_Q,
PRE => s_vetoed_pulse_a ) ;
q_reg1 : dtype_fdr --! Delay the output signal
port map (
Q => s_Q_d1,
D => s_async_pulse_a,
RST => RST_i,
CLK => CLK_i
) ;
--! Delay the output signal
q_reg2 : dtype_fds
port map (
Q => s_Q_d2,
D => s_Q_d1,
SET => RST_i, --! Take high on reset.
CLK => CLK_i
) ;
--! Delay the output signal
q_reg3 : dtype_fdr
port map (
Q => s_Q_d3,
D => s_Q_d2,
RST => RST_i, --! Take low on reset
CLK => CLK_i
) ;
d_reg1 : dtype_fd --! Delay the input
port map (
Q => s_D_d1,
D => D_a_i,
CLK => CLK_i
) ;
d_reg2 : dtype_fds --! Delay the input
port map (
Q => s_D_d2,
D => s_D_d1,
SET => RST_i,
CLK => CLK_i
) ;
end rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/test/pulse_shaper_async_dtypes.vhdl 0000664 0000000 0000000 00000006220 12415504633 0030602 0 ustar 00root root 0000000 0000000 ----- CELL pulse_shaper -----
--
--@file
--
--@brief Output goes high when input goes high ( asyncnronous to system clock).
--! Output goes low again a controllable number of clock cycles later,
--! synchronous with the rising edge of the clock.
--! Gap of at least one clock cycle before output goes high again.
--! Pile-up will result in timing errors ( veto-cleared sync. with clock )
--
--! Output won't retrigger if input is still high at end of pulse.
--
--! Fill top bits of PULSE_MASK
--! For example for a pulse width of 4.X clock cycles load '1111000000000000'
--
-- David Cussans, Feb 2011
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity pulse_shaper_async_dtypes is
generic (
MASK_WIDTH : integer := 16); --! Width of shift register and hence maximum width of pulse
port (
D : in std_logic; --! Input pulse
Q : out std_logic; --! output pulse
CLK : in std_logic; --! Clock , rising edge active
PULSE_MASK : in std_logic_vector(MASK_WIDTH-1 downto 0)); -- ! preload for shift-register. Fill with number of '1's that the ouput pulse should be
end pulse_shaper_async_dtypes;
architecture rtl of pulse_shaper_async_dtypes is
component dtype_fdpe
port(
Q : out std_logic; --! Output
CLK : in std_logic; --! Clock - rising edge active
D : in std_logic; --! Input
CE : in std_logic; --! Clock enable
PRE : in std_logic --! Asynchronous preload
);
end component;
signal shift_reg : std_logic_vector(MASK_WIDTH downto 0) := ( others => '0' ); --! shift register holding '1's to be shifted out
signal preload : std_logic_vector(MASK_WIDTH-1 downto 0) := ( others => '0' ); --! Mask register holding '1's to be shifted out
signal vetoed_pulse : std_logic := '0'; --! input signal after internal veto
signal Q_R1 , Q_R2 , D_R1 : std_logic := '0'; --! Output, input delayed by one clock. Used
--to form veto.
begin -- rtl
shift_reg(0) <= '0'; --! Shift in zero at start of SReg.
--! Generate a shift register out of flip-flops.
--! Unfortunately SRL16 , SRL32 don't have async. load.
SR : for bit in 0 to MASK_WIDTH-1 generate
preload(bit) <= (vetoed_pulse and pulse_mask(bit));
dtype : dtype_fdpe
port map (
Q => shift_reg(bit+1),
D => shift_reg(bit),
CLK => CLK,
CE => '1',
PRE => preload(bit)) ;
end generate SR ;
Q <= shift_reg(MASK_WIDTH); --! Take output from end of SR.
q_reg : dtype_fdpe --! Delay the output signal
port map (
Q => Q_R1,
D => shift_reg(MASK_WIDTH),
CLK => CLK,
CE => '1',
PRE => '0') ;
d_reg : dtype_fdpe --! Delay the input signal
port map (
Q => D_R1,
D => D,
CLK => CLK,
CE => '1',
PRE => '0') ;
--! Arrgh... problems with glitching if veto immediately.
-- put in a transparent latch or something to force some delay???
vetoed_pulse <= D and (not shift_reg(MASK_WIDTH) ) and (not Q_R1) and (not D_R1);
end rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/test/pulse_shaper_scorer.vhdl 0000664 0000000 0000000 00000003625 12415504633 0027400 0 ustar 00root root 0000000 0000000 --=============================================================================
--! @file pulse_stretcher_scorer.vhdl
--=============================================================================
--! Standard library
Library IEEE;
--! Standard logic package
use IEEE.STD_LOGIC_1164.all;
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group --
-- --
-------------------------------------------------------------------------------
--
-- unit name: pulse_stretcher_scoer
--
--! @brief Checks that pulse_shaper is behaving correctly.
--! Check for Output goes high when input goes high ( asyncnronous to system clock).
--! Output goes low again a controllable number of clock cycles later,
--! synchronous with the rising edge of the clock.
--! Gap of at least one clock cycle before output goes high again.
--
--! @author David.Cussans@bristol.ac.uk
--
--! @date 7/May/2011
--
--! @version 0.1
--
--! @details
--
--
--! Dependencies:\n
--!
--! References:\n
--! \n
--!
--!
--! Modified by:\n
--! Author:
-------------------------------------------------------------------------------
--! \n\nLast changes:\n
--! \n
--!
--
-------------------------------------------------------------------------------
--! @todo \n
--
-------------------------------------------------------------------------------
entity pulse_shaper_scorer is
port (
clk_i : in std_logic; -- ! system clock
pulse_in_a_i : in std_logic; -- ! input ( unstretched) pulse
pulse_out_a_i : in std_logic -- ! stretched pulse (output of pulse_stretcher)
pulse_length_i : in std_logic_vector; --! Parameter to pulse_strecher
);
end pulse_shaper_scorer;
architecture rtl of pulse_shaper_scorer is
begin -- rtl
end rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/test/slaves.vhd 0000775 0000000 0000000 00000012210 12415504633 0024443 0 ustar 00root root 0000000 0000000 -- The ipbus slaves live in this entity - modify according to requirements
--
-- Ports can be added to give ipbus slaves access to the chip top level.
--
-- Dave Newbold, February 2011
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.ipbus.ALL;
use work.emac_hostbus_decl.all;
entity slaves is port(
ipb_clk, rst : in STD_LOGIC;
ipb_in : in ipb_wbus;
ipb_out : out ipb_rbus;
-- Top level ports from here
hostbus_out: out emac_hostbus_in;
hostbus_in: in emac_hostbus_out;
-- GPIO
gpio : out STD_LOGIC_VECTOR(3 downto 0);
-- Main I2C signals
i2c_scl_i: in std_logic;
i2c_scl_oen_o: out std_logic;
i2c_sda_i: in std_logic;
i2c_sda_oen_o: out std_logic;
-- CBC I2C signals
cbc_i2c_sda_enb_o: out std_logic; --! Active low. SDA pulled low when enb is high
cbc_i2c_scl_o: out std_logic; --! I2C Clock output.
cbc_i2c_sda_i : in std_logic;
-- CBC "fast" signals
cbc_trg_o, ext_trg_o, cbc_reset_o: out std_logic;
cbc_data_i: in std_logic
);
end slaves;
architecture rtl of slaves is
constant NSLV: positive := 7;
signal ipbw: ipb_wbus_array(NSLV-1 downto 0);
signal ipbr, ipbr_d: ipb_rbus_array(NSLV-1 downto 0);
signal cbc_i2c_scl_o_int: std_logic;
signal ctrl_reg: std_logic_vector(31 downto 0);
signal s_pulse_reg : std_logic_vector(31 downto 0); -- ! pulsed control signals
signal s_cbc_reset : std_logic := '0'; -- ! Active high. Driven from cbcstuff
signal s_cap_trg : std_logic := '0'; -- ! Starts capture of incoming data into capture buffer
begin
fabric: entity work.ipbus_fabric
generic map(NSLV => NSLV)
port map(
ipb_clk => ipb_clk,
rst => rst,
ipb_in => ipb_in,
ipb_out => ipb_out,
ipb_to_slaves => ipbw,
ipb_from_slaves => ipbr
);
-- Slave 0: version register
slave0: entity work.ipbus_ver
port map(
ipbus_in => ipbw(0),
ipbus_out => ipbr(0));
-- Slave 1: 32b register
slave1: entity work.ipbus_reg
generic map(addr_width => 0)
port map(
clk => ipb_clk,
reset => rst,
ipbus_in => ipbw(1),
ipbus_out => ipbr(1),
q => ctrl_reg
);
s_cbc_reset <= ctrl_reg(16);
cbc_reset_o <= s_cbc_reset;
-- Slave 2: 32b pulser
slave2: entity work.ipbus_pulser
port map(
clk_i => ipb_clk,
reset_i => rst,
ipbus_i => ipbw(2),
ipbus_o => ipbr(2),
q_o => s_pulse_reg
);
-- CBC clock and trigger signals. Connected to slave-1 ( 32 bit register )
cbcstuff: entity work.cbc_logic
port map(
clk_i => ipb_clk,
cbc_trg_o => cbc_trg_o,
ext_trg_o => ext_trg_o,
cap_trg_o => s_cap_trg,
go_p_i => s_pulse_reg(0),
delay_i => unsigned(ctrl_reg(31 downto 24)),
trg_patt_i => ctrl_reg(22 downto 20)
);
-- Slave 3: I2C core connected to CBC
slave3: entity work.i2c_master_top
generic map (
ARST_LVL => 0
)
port map(
wb_clk_i => ipb_clk,
wb_rst_i => rst,
arst_i => '1', --! Active low reset.
wb_adr_i => ipbw(3).ipb_addr(2 downto 0),
wb_dat_i => ipbw(3).ipb_wdata(7 downto 0),
wb_dat_o => ipbr(3).ipb_rdata(7 downto 0),
wb_we_i => ipbw(3).ipb_write,
wb_stb_i => ipbw(3).ipb_strobe,
wb_cyc_i => '1',
wb_ack_o => ipbr(3).ipb_ack,
wb_inta_o => open,
scl_pad_i => cbc_i2c_scl_o_int,
scl_pad_o => open,
scl_padoen_o => cbc_i2c_scl_o_int,
sda_pad_i => cbc_i2c_sda_i,
sda_pad_o => open,
sda_padoen_o => cbc_i2c_sda_enb_o
);
cbc_i2c_scl_o <= cbc_i2c_scl_o_int;
ipbr(3).ipb_rdata(31 downto 8) <= (others => '0');
-- Slave 4: I2C core connected to main I2C
slave4: entity work.i2c_master_top
generic map (
ARST_LVL => 0
)
port map(
wb_clk_i => ipb_clk,
wb_rst_i => rst,
arst_i => '1', --! Active low reset.
wb_adr_i => ipbw(4).ipb_addr(2 downto 0),
wb_dat_i => ipbw(4).ipb_wdata(7 downto 0),
wb_dat_o => ipbr(4).ipb_rdata(7 downto 0),
wb_we_i => ipbw(4).ipb_write,
wb_stb_i => ipbw(4).ipb_strobe,
wb_cyc_i => '1',
wb_ack_o => ipbr(4).ipb_ack,
wb_inta_o => open,
scl_pad_i => i2c_scl_i,
scl_pad_o => open,
scl_padoen_o => i2c_scl_oen_o,
sda_pad_i => i2c_sda_i,
sda_pad_o => open,
sda_padoen_o => i2c_sda_oen_o
);
ipbr(4).ipb_rdata(31 downto 8) <= (others => '0');
-- Slave 5: Capture register.
slave5 : entity work.ipbus_capture_buffer
generic map (
g_DATA_WIDTH => 32, --! Width of WB bus
g_RAM_ADDRESS_WIDTH => 3) --! size of RAM = 2^ram_address_width
port map (
-- Wishbone signals
ipbus_clk_i => ipb_clk,
ipbus_i => ipbw(5),
ipbus_o => ipbr(5),
-- Data to capture.
reset_i => s_cbc_reset,
cap_clk_i => ipb_clk,
cap_d_i => cbc_data_i,
cap_go_i => s_cap_trg,
cap_edge_i => ctrl_reg(8)
);
-- Slave 6: MAC host interface
slave6: entity work.ipbus_emac_hostbus
port map(
clk => ipb_clk,
reset => rst,
ipbus_in => ipbw(6),
ipbus_out => ipbr(6),
hostbus_out => hostbus_out,
hostbus_in => hostbus_in);
end rtl;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/test/sp601_FMC_mTLU.ucf 0000664 0000000 0000000 00000017232 12415504633 0025407 0 ustar 00root root 0000000 0000000 NET sysclk_p_i LOC = K15 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE | TNM_NET = tnm_sysclk;
NET sysclk_n_i LOC = K16 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
TIMESPEC TS_sysclk = PERIOD tnm_sysclk 200MHz;
# remove for now
#NET Reset_i LOC=P4; ## Global Reset
#NET ipb_clk TNM_NET = tnm_ipb_clk;
#NET clk125 TNM_NET = tnm_clk125;
#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
# NET clocks/rst* TIG;
NET I6/s_clk_is_xtal TIG;
NET leds_o<0> LOC=E13 | IOSTANDARD=LVCMOS25;
NET leds_o<1> LOC=C14 | IOSTANDARD=LVCMOS25;
NET leds_o<2> LOC=C4 | IOSTANDARD=LVCMOS25;
NET leds_o<3> LOC=A4 | IOSTANDARD=LVCMOS25;
NET dip_switch_i<0> LOC=D14;
NET dip_switch_i<1> LOC=E12;
NET dip_switch_i<2> LOC=F12;
NET dip_switch_i<3> LOC=V13;
# Ethernet PHY
TIMEGRP TG_gmii_tx=PADS("gmii_tx*");
TIMEGRP TG_gmii_tx OFFSET = OUT AFTER sysclk_p_i REFERENCE_PIN "gmii_gtx_clk_o" RISING;
NET gmii_gtx_clk_o LOC=A9 | IOSTANDARD=LVCMOS25 | SLEW=FAST;
NET gmii_txd_o<0> LOC=F8 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<1> LOC=G8 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<2> LOC=A6 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<3> LOC=B6 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<4> LOC=E6 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<5> LOC=F7 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<6> LOC=A5 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<7> LOC=C5 | IOSTANDARD=LVCMOS25;
NET gmii_tx_en_o LOC=B8 | IOSTANDARD=LVCMOS25;
NET gmii_tx_er_o LOC=A8 | IOSTANDARD=LVCMOS25;
NET gmii_rx_clk_i LOC=L16 | IOSTANDARD=LVCMOS25 | TNM_NET= "gmii_rx_clk_i";
TIMESPEC "TS_GMII_RX_CLK_I" = PERIOD "gmii_rx_clk_i" 125MHz;
OFFSET = IN 2.5ns VALID 3ns BEFORE gmii_rx_clk_i;
NET gmii_rxd_i<0> LOC=M14 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<1> LOC=U18 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<2> LOC=U17 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<3> LOC=T18 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<4> LOC=T17 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<5> LOC=N16 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<6> LOC=N15 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<7> LOC=P18 | IOSTANDARD=LVCMOS25;
NET gmii_rx_dv_i LOC=N18 | IOSTANDARD=LVCMOS25;
NET gmii_rx_er_i LOC=P17 | IOSTANDARD=LVCMOS25;
NET phy_rstb_o LOC=L13 | IOSTANDARD=LVCMOS25;
# Main I2C bus
NET "I2C_SCL_B" LOC = "P11"; ## C30 on FMC
NET "I2C_SDA_B" LOC = "N10"; ## C31 on FMC
#
# I/O to devices under test
#NET "BUSY_P_I<0>" LOC = "D12"; ## "FMC_LA06_P" , C10 on FMC
#NET "BUSY_N_I<0>" LOC = "C12"; ## "FMC_LA06_N" , C11 on FMC
#NET "BUSY_P_I<1>" LOC = "U11"; ## "FMC_LA28_P" , H31 on FMC
#NET "BUSY_N_I<1>" LOC = "V11"; ## "FMC_LA28_N" , H32 on FMC
#NET "BUSY_P_I<2>" LOC = "E7"; ## "FMC_LA07_P" , H13 on FMC
#NET "BUSY_N_I<2>" LOC = "E8"; ## "FMC_LA07_N" , H14 on FMC
#NET "TRIGGERS_P_O<0>" LOC = "D8"; ## "FMC_LA10_P" , C14 on FMC
##NET "TRIGGERS_N_O<0>" LOC = "C8"; ## "FMC_LA10_N" , C15 on FMC
#NET "TRIGGERS_P_O<1>" LOC = "U15"; ## "FMC_LA32_P" , H37 on FMC
##NET "TRIGGERS_N_O<1>" LOC = "V15"; ## "FMC_LA32_N" , H38 on FMC
#NET "TRIGGERS_P_O<2>" LOC = "G11"; ## "FMC_LA09_P" , D14 on FMC
##NET "TRIGGERS_N_O<2>" LOC = "F10"; ## "FMC_LA09_N" , D15 on FMC
# Remove for now.
#NET "SHUTTERS_P_O<0>" LOC = "N7"; ## "FMC_LA20_P" , G21 on FMC
##NET "SHUTTERS_N_O<0>" LOC = "P8"; ## "FMC_LA20_N" , G22 on FMC
#NET "SHUTTERS_P_O<1>" LOC = "R10"; ## "FMC_LA18_CC_P" , C22 on FMC
##NET "SHUTTERS_N_O<1>" LOC = "T10"; ## "FMC_LA18_CC_N" , C23 on FMC
#NET "SHUTTERS_P_O<2>" LOC = "N6"; ## "FMC_LA19_P" , H22 on FMC
##NET "SHUTTERS_N_O<2>" LOC = "P6"; ## "FMC_LA19_N" , H23 on FMC
#NET "DUT_CLK_P_I<0>" LOC = "T6"; ## "FMC_LA31_P" , G33 on FMC , "DUT_CLK_P_I<0>
#NET "DUT_CLK_N_I<0>" LOC = "V6"; ## "FMC_LA31_N" , G34 on FMC , DUT_CLK_N<0>
#NET "DUT_CLK_P_I<1>" LOC = "U8"; ## "FMC_LA24_P" , H28 on FMC , CONT_P<1>
#NET "DUT_CLK_N_I<1>" LOC = "V8"; ## "FMC_LA24_N" , H29 on FMC , CONT_N<1>
#NET "DUT_CLK_P_I<2>" LOC = "F11"; ## "FMC_LA08_P" , G12 on FMC , CONT_P<2>
#NET "DUT_CLK_N_I<2>" LOC = "E11"; ## "FMC_LA08_N" , G13 on FMC , CONT_N<2>
#NET "RESET_OR_CLK_P_O<0>" LOC = "M10"; ## "FMC_LA33_P" , G36 on FMC , CONT_P<0>
##NET "RESET_OR_CLK_N_O<0>" LOC = "N9"; ## "FMC_LA33_N" , G37 on FMC , CONT_N<0>
#NET "RESET_OR_CLK_P_O<1>" LOC = "T4"; ## "FMC_LA21_P" , H25 on FMC , CLK_P<1>
##NET "RESET_OR_CLK_N_O<1>" LOC = "V4"; ## "FMC_LA21_N" , H26 on FMC , CLK_QN<1>
#NET "RESET_OR_CLK_P_O<2>" LOC = "B16"; ## "FMC_LA04_P" , H10 on FMC , CLK_P<2>
##NET "RESET_OR_CLK_N_O<2>" LOC = "A16"; ## "FMC_LA04_N" , H11 on FMC , CLK_N<2>
# Trigger Inputs
# Constant-fraction-discrimiator comparator outputs
#NET "CFD_DISCR_P_I<0>" LOC = "D9"; ## "FMC_LA00_CC_P" , G6 on FMC
#NET "CFD_DISCR_N_I<0>" LOC = "C9"; ## "FMC_LA00_CC_N" , G7 on FMC
#
#NET "CFD_DISCR_P_I<1>" LOC = "B2"; ## "FMC_LA14_P" , C18 on FMC
#NET "CFD_DISCR_N_I<1>" LOC = "A2"; ## "FMC_LA14_N" , C19 on FMC
#
#NET "CFD_DISCR_P_I<2>" LOC = "B14"; ## "FMC_LA05_P" , D11 on FMC
#NET "CFD_DISCR_N_I<2>" LOC = "A14"; ## "FMC_LA05_N" , D12 on FMC
#
#NET "CFD_DISCR_P_I<3>" LOC = "B11"; ## "FMC_LA13_P" , D17 on FMC
#NET "CFD_DISCR_N_I<3>" LOC = "A11"; ## "FMC_LA13_N" , D18 on FMC
# Threshold comparator outputs
NET "THRESHOLD_DISCR_P_I<0>" LOC = "D11"; ## "FMC_LA01_CC_P" , D8 on FMC
NET "THRESHOLD_DISCR_N_I<0>" LOC = "C11"; ## "FMC_LA01_CC_N" , D9 on FMC
NET "THRESHOLD_DISCR_P_I<1>" LOC = "C13"; ## "FMC_LA03_P" , G9 on FMC
NET "THRESHOLD_DISCR_N_I<1>" LOC = "A13"; ## "FMC_LA03_N" , G10 on FMC
NET "THRESHOLD_DISCR_P_I<2>" LOC = "D6"; ## "FMC_LA12_P" , G15 on FMC
NET "THRESHOLD_DISCR_N_I<2>" LOC = "C6"; ## "FMC_LA12_N" , G16 on FMC
NET "THRESHOLD_DISCR_P_I<3>" LOC = "C7"; ## "FMC_LA16_P" , G18 on FMC
NET "THRESHOLD_DISCR_N_I<3>" LOC = "A7"; ## "FMC_LA16_N" , G19 on FMC
#NET "SPARE_P<2>" LOC = "R8"; ## "FMC_LA17_CC_P" , D20 on FMC
#NET "SPARE_N<2>" LOC = "T8"; ## "FMC_LA17_CC_N" , D21 on FMC
#NET "SPARE_P<1>" LOC = "T12"; ## "FMC_LA30_P" , H34 on FMC
#NET "SPARE_N<1>" LOC = "V12"; ## "FMC_LA30_N" , H35 on FMC
NET "EXTCLK_P_B" LOC = "C10"; ## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"
NET "EXTCLK_N_B" LOC = "A10"; ## "FMC_CLK0_M2C_N" , H5 on FMC , "FRONT_PANEL_CLK_N"
#NET "HDMI_POWER_ENABLE1" LOC = "C15"; ## "FMC_LA02_P" , H7 on FMC
#NET "HDMI_POWER_ENABLE2" LOC = "A15"; ## "FMC_LA02_N" , H8 on FMC
# GPIO pins for debugging.
#NET "GPIO_HDR<0>" LOC = "N17"; ## 1 on J13 (thru series R100 200 ohm)
#NET "GPIO_HDR<1>" LOC = "M18"; ## 3 on J13 (thru series R102 200 ohm)
#NET "GPIO_HDR<2>" LOC = "A3"; ## 5 on J13 (thru series R101 200 ohm)
#NET "GPIO_HDR<3>" LOC = "L15"; ## 7 on J13 (thru series R103 200 ohm)
#NET "GPIO_HDR<4>" LOC = "F15"; ## 2 on J13 (thru series R99 200 ohm)
#NET "GPIO_HDR<5>" LOC = "B4"; ## 4 on J13 (thru series R98 200 ohm)
#NET "GPIO_HDR<6>" LOC = "F13"; ## 6 on J13 (thru series R97 200 ohm)
#NET "GPIO_HDR<7>" LOC = "P12"; ## 8 on J13 (thru series R96 20
NET "output_0_p[0]" LOC = D8;
NET "output_0_p[1]" LOC = U15;
NET "output_0_p[2]" LOC = G11;
NET "output_0_n[0]" LOC = C8;
NET "output_0_n[1]" LOC = V15;
NET "output_0_n[2]" LOC = F10;
NET "output_1_p[0]" LOC = T6;
NET "output_1_p[1]" LOC = U8;
NET "output_1_p[2]" LOC = F11;
NET "output_1_n[0]" LOC = V6;
NET "output_1_n[1]" LOC = V8;
NET "output_1_n[2]" LOC = E11;
NET "output_2_p[0]" LOC = M10;
NET "output_2_p[1]" LOC = T4;
NET "output_2_p[2]" LOC = B16;
NET "output_2_n[0]" LOC = N9;
NET "output_2_n[1]" LOC = V4;
NET "output_2_n[2]" LOC = A16;
NET "output_3_p[0]" LOC = D12;
NET "output_3_p[1]" LOC = U11;
NET "output_3_p[2]" LOC = E7;
NET "output_3_n[0]" LOC = C12;
NET "output_3_n[1]" LOC = V11;
NET "output_3_n[2]" LOC = E8; fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/test/sp601_FMC_mTLU_v1a.ucf 0000664 0000000 0000000 00000023613 12415504633 0026156 0 ustar 00root root 0000000 0000000 #
# UCF for version 1a of updated mini-TLU
#
NET "sysclk_p_i" TNM_NET = "tnm_sysclk";
NET "sysclk_p_i" LOC = K15;
NET "sysclk_p_i" IOSTANDARD = LVDS_25;
NET "sysclk_p_i" DIFF_TERM = "TRUE";
NET "sysclk_n_i" LOC = K16;
NET "sysclk_n_i" IOSTANDARD = LVDS_25;
NET "sysclk_n_i" DIFF_TERM = "TRUE";
TIMESPEC TS_sysclk = PERIOD "tnm_sysclk" 200 MHz;
# remove for now
#NET Reset_i LOC=P4; ## Global Reset
#NET ipb_clk TNM_NET = tnm_ipb_clk;
#NET clk125 TNM_NET = tnm_clk125;
#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
# NET clocks/rst* TIG;
NET "I6/s_clk_is_xtal" TIG;
NET "leds_o[0]" LOC = E13;
NET "leds_o[0]" IOSTANDARD = LVCMOS25;
NET "leds_o[1]" LOC = C14;
NET "leds_o[1]" IOSTANDARD = LVCMOS25;
NET "leds_o[2]" LOC = C4;
NET "leds_o[2]" IOSTANDARD = LVCMOS25;
NET "leds_o[3]" LOC = A4;
NET "leds_o[3]" IOSTANDARD = LVCMOS25;
NET "dip_switch_i[0]" LOC = D14;
NET "dip_switch_i[1]" LOC = E12;
NET "dip_switch_i[2]" LOC = F12;
NET "dip_switch_i[3]" LOC = V13;
# Ethernet PHY
TIMEGRP TG_gmii_tx = PADS("gmii_tx*");
TIMEGRP "TG_gmii_tx" OFFSET = OUT AFTER "sysclk_p_i" REFERENCE_PIN "gmii_gtx_clk_o" RISING;
NET "gmii_gtx_clk_o" LOC = A9;
NET "gmii_gtx_clk_o" IOSTANDARD = LVCMOS25;
NET "gmii_gtx_clk_o" SLEW = FAST;
NET "gmii_txd_o[0]" LOC = F8;
NET "gmii_txd_o[0]" IOSTANDARD = LVCMOS25;
NET "gmii_txd_o[1]" LOC = G8;
NET "gmii_txd_o[1]" IOSTANDARD = LVCMOS25;
NET "gmii_txd_o[2]" LOC = A6;
NET "gmii_txd_o[2]" IOSTANDARD = LVCMOS25;
NET "gmii_txd_o[3]" LOC = B6;
NET "gmii_txd_o[3]" IOSTANDARD = LVCMOS25;
NET "gmii_txd_o[4]" LOC = E6;
NET "gmii_txd_o[4]" IOSTANDARD = LVCMOS25;
NET "gmii_txd_o[5]" LOC = F7;
NET "gmii_txd_o[5]" IOSTANDARD = LVCMOS25;
NET "gmii_txd_o[6]" LOC = A5;
NET "gmii_txd_o[6]" IOSTANDARD = LVCMOS25;
NET "gmii_txd_o[7]" LOC = C5;
NET "gmii_txd_o[7]" IOSTANDARD = LVCMOS25;
NET "gmii_tx_en_o" LOC = B8;
NET "gmii_tx_en_o" IOSTANDARD = LVCMOS25;
NET "gmii_tx_er_o" LOC = A8;
NET "gmii_tx_er_o" IOSTANDARD = LVCMOS25;
NET "gmii_rx_clk_i" TNM_NET = "gmii_rx_clk_i";
NET "gmii_rx_clk_i" LOC = L16;
NET "gmii_rx_clk_i" IOSTANDARD = LVCMOS25;
TIMESPEC TS_GMII_RX_CLK_I = PERIOD "gmii_rx_clk_i" 125 MHz;
OFFSET = IN 2 ns VALID 3 ns BEFORE "gmii_rx_clk_i";
NET "gmii_rxd_i[0]" LOC = M14;
NET "gmii_rxd_i[0]" IOSTANDARD = LVCMOS25;
NET "gmii_rxd_i[1]" LOC = U18;
NET "gmii_rxd_i[1]" IOSTANDARD = LVCMOS25;
NET "gmii_rxd_i[2]" LOC = U17;
NET "gmii_rxd_i[2]" IOSTANDARD = LVCMOS25;
NET "gmii_rxd_i[3]" LOC = T18;
NET "gmii_rxd_i[3]" IOSTANDARD = LVCMOS25;
NET "gmii_rxd_i[4]" LOC = T17;
NET "gmii_rxd_i[4]" IOSTANDARD = LVCMOS25;
NET "gmii_rxd_i[5]" LOC = N16;
NET "gmii_rxd_i[5]" IOSTANDARD = LVCMOS25;
NET "gmii_rxd_i[6]" LOC = N15;
NET "gmii_rxd_i[6]" IOSTANDARD = LVCMOS25;
NET "gmii_rxd_i[7]" LOC = P18;
NET "gmii_rxd_i[7]" IOSTANDARD = LVCMOS25;
NET "gmii_rx_dv_i" LOC = N18;
NET "gmii_rx_dv_i" IOSTANDARD = LVCMOS25;
NET "gmii_rx_er_i" LOC = P17;
NET "gmii_rx_er_i" IOSTANDARD = LVCMOS25;
NET "phy_rstb_o" LOC = L13;
NET "phy_rstb_o" IOSTANDARD = LVCMOS25;
# Main I2C bus
## C30 on FMC
NET "i2c_scl_b" LOC = P11;
## C31 on FMC
NET "i2c_sda_b" LOC = N10;
#
# I/O to devices under test
#NET "BUSY_N_I<0>" LOC = "P7"; ## "FMC_LA19_N" , H23 on FMC
#NET "BUSY_N_I<1>" LOC = "A2"; ## "FMC_LA14_N" , C19 on FMC
#NET "BUSY_N_I<2>" LOC = "C6"; ## "FMC_LA12_N" , G16 on FMC
## "FMC_LA19_P" , H22 on FMC
#NET "busy_p_i[0]" LOC = N6;
## "FMC_LA14_P" , C18 on FMC
#NET "busy_p_i[1]" LOC = B2;
## "FMC_LA12_P" , G15 on FMC
#NET "busy_p_i[2]" LOC = D6;
#NET "TRIGGERS_N_O<0>" LOC = "P8"; ## "FMC_LA20_N" , G22 on FMC
#NET "TRIGGERS_N_O<1>" LOC = "A13"; ## "FMC_LA03_N" , G10 on FMC
#NET "TRIGGERS_N_O<2>" LOC = "A7"; ## "FMC_LA16_N" , G19 on FMC
## "FMC_LA20_P" , G21 on FMC
#NET "triggers_p_o[0]" LOC = N7;
## "FMC_LA03_P" , G9 on FMC
#NET "triggers_p_o[1]" LOC = C13;
## "FMC_LA16_P" , G18 on FMC
#NET "triggers_p_o[2]" LOC = C7;
# Remove shutters ( also known as SPARE ) for now
#NET "SPARE_N_O<1>" LOC = "E11"; ## "FMC_LA08_N" , G13 on FMC
#NET "SPARE_N_O<2>" LOC = "A12"; ## "FMC_LA11_N" , H17 on FMC
#NET "SPARE_P_O<1>" LOC = "F11"; ## "FMC_LA08_P" , G12 on FMC
#NET "SPARE_P_O<2>" LOC = "B12"; ## "FMC_LA11_P" , H16 on FMC
# Labelled DUT_CLK on schematic for RJ45, CLK on HDMI
#NET "DUT_CLK_N_I<0>" LOC = "V4"; ## "FMC_LA21_N" , H26 on FMC
#NET "DUT_CLK_N_I<1>" LOC = "T11"; ## "FMC_LA27_N" , C27 on FMC
#NET "DUT_CLK_N_I<2>" LOC = "A15"; ## "FMC_LA02_N" , H8 on FMC
## "FMC_LA27_P" , C26 on FMC
## "FMC_LA02_P" , H7 on FMC
## "FMC_LA21_P" , H25 on FMC
# Labelled CONT on schematic.
#NET "RESET_OR_CLK_N_O<0>" LOC = "T7"; ## "FMC_LA22_N" , G25 on FMC
#NET "RESET_OR_CLK_N_O<1>" LOC = "T10"; ## "FMC_LA18_CC_N" , C23 on FMC
#NET "RESET_OR_CLK_N_O<2>" LOC = "E8"; ## "FMC_LA07_N" , H14 on FMC
## "FMC_LA22_P" , G24 on FMC
#NET "reset_or_clk_p_o[0]" LOC = R7;
## "FMC_LA18_CC_P" , C22 on FMC
#NET "reset_or_clk_p_o[1]" LOC = R10;
## "FMC_LA07_P" , H13 on FMC
#NET "reset_or_clk_p_o[2]" LOC = E7;
# Trigger Inputs
# Constant-fraction-discrimiator comparator outputs
## "FMC_LA32_N" , H38 on FMC
NET "cfd_discr_n_i[0]" LOC = V15;
## "FMC_LA30_N" , H35 on FMC
NET "cfd_discr_n_i[1]" LOC = V12;
## "FMC_LA28_N" , H32 on FMC
NET "cfd_discr_n_i[2]" LOC = V11;
## "FMC_LA24_N" , H29 on FMC
NET "cfd_discr_n_i[3]" LOC = V8;
## "FMC_LA32_P" , H37 on FMC
NET "cfd_discr_p_i[0]" LOC = U15;
## "FMC_LA30_P" , H34 on FMC
NET "cfd_discr_p_i[1]" LOC = T12;
## "FMC_LA28_P" , H31 on FMC
NET "cfd_discr_p_i[2]" LOC = U11;
## "FMC_LA24_P" , H28 on FMC
NET "cfd_discr_p_i[3]" LOC = U8;
# Threshold comparator outputs
## "FMC_LA33_N" , G37 on FMC
NET "threshold_discr_n_i[0]" LOC = N9;
## "FMC_LA31_N" , G34 on FMC
NET "threshold_discr_n_i[1]" LOC = V6;
## "FMC_LA29_N" , G31 on FMC
NET "threshold_discr_n_i[2]" LOC = N8;
## "FMC_LA25_N" , G28 on FMC
NET "threshold_discr_n_i[3]" LOC = N11;
## "FMC_LA33_P" , G36 on FMC
NET "threshold_discr_p_i[0]" LOC = M10;
## "FMC_LA31_P" , G33 on FMC
NET "threshold_discr_p_i[1]" LOC = T6;
## "FMC_LA29_P" , G30 on FMC
NET "threshold_discr_p_i[2]" LOC = M8;
## "FMC_LA25_P" , G27 on FMC
NET "threshold_discr_p_i[3]" LOC = M11;
############
# External clock pins
## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"
NET "extclk_p_b" LOC = C10;
## "FMC_CLK0_M2C_N" , H5 on FMC , "FRONT_PANEL_CLK_N"
NET "extclk_n_b" LOC = A10;
#NET "HDMI_POWER_ENABLE1" LOC = "B16"; ## "FMC_LA04_P" , H10 on FMC
#NET "HDMI_POWER_ENABLE2" LOC = "F9"; ## "FMC_LA15_N" , H20 on FMC
# GPIO pins for debugging.
## 1 on J13 (thru series R100 200 ohm)
#NET "gpio_hdr[0]" LOC = N17;
## 3 on J13 (thru series R102 200 ohm)
#NET "gpio_hdr[1]" LOC = M18;
## 5 on J13 (thru series R101 200 ohm)
#NET "gpio_hdr[2]" LOC = A3;
## 7 on J13 (thru series R103 200 ohm)
#NET "gpio_hdr[3]" LOC = L15;
## 2 on J13 (thru series R99 200 ohm)
#NET "gpio_hdr[4]" LOC = F15;
## 4 on J13 (thru series R98 200 ohm)
#NET "gpio_hdr[5]" LOC = B4;
## 6 on J13 (thru series R97 200 ohm)
#NET "gpio_hdr[6]" LOC = F13;
## 8 on J13 (thru series R96 20
#NET "gpio_hdr[7]" LOC = P12;
#NET "busy_p_i[2]" PULLDOWN;
#NET "busy_p_i[1]" PULLDOWN;
#NET "busy_p_i[0]" PULLDOWN;
# PlanAhead Generated miscellaneous constraints
NET "I4/ipbus/udp_if/clock_crossing_if/enable_buf[1]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/rarp_buf[1]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/we_buf[1]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/rst_ipb_buf[1]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/rst_ipb_buf[0]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/we_buf[0]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/pkt_done_read_buf[2]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/pkt_done_read_buf[1]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/pkt_done_write_buf[2]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/pkt_done_write_buf[1]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/rarp_buf[0]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/enable_buf[0]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/req_send_buf[2]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/req_send_buf[1]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/req_send_buf[0]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/busy_up_buf[2]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/busy_up_buf[1]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/busy_down_buf[2]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/busy_down_buf[1]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/pkt_done_write_buf[0]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/pkt_done_read_buf[0]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/busy_up_buf[0]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/busy_down_buf[0]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/rx_read_buf_buf[1]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/rx_read_buf_buf[0]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/tx_write_buf_buf[1]" KEEP = "TRUE";
NET "I4/ipbus/udp_if/clock_crossing_if/tx_write_buf_buf[0]" KEEP = "TRUE";
# PlanAhead Generated physical constraints
NET "output_0_p[0]" LOC = N7;
NET "output_0_p[1]" LOC = C13;
NET "output_0_p[2]" LOC = C7;
NET "output_0_n[0]" LOC = P8;
NET "output_0_n[1]" LOC = A13;
NET "output_0_n[2]" LOC = A7;
NET "output_1_p[0]" LOC = R11;
NET "output_1_p[1]" LOC = C15;
NET "output_1_p[2]" LOC = T4;
NET "output_1_n[0]" LOC = T11;
NET "output_1_n[1]" LOC = A15;
NET "output_1_n[2]" LOC = V4;
NET "output_2_p[0]" LOC = R7;
NET "output_2_p[1]" LOC = R10;
NET "output_2_p[2]" LOC = E7;
NET "output_2_n[0]" LOC = T7;
NET "output_2_n[1]" LOC = T10;
NET "output_2_n[2]" LOC = E8;
NET "output_3_p[0]" LOC = N6;
NET "output_3_p[1]" LOC = B2;
NET "output_3_p[2]" LOC = D6;
NET "output_3_n[0]" LOC = P7;
NET "output_3_n[1]" LOC = A2;
NET "output_3_n[2]" LOC = C6;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/test/sp605_FMC_mTLU.ucf 0000664 0000000 0000000 00000016501 12415504633 0025411 0 ustar 00root root 0000000 0000000 NET sysclk_p_i LOC = K21 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE | TNM_NET = tnm_sysclk;
NET sysclk_n_i LOC = K22 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
TIMESPEC TS_sysclk = PERIOD tnm_sysclk 200MHz;
#NET Reset_i LOC=F3; ## Global Reset
#NET ipb_clk TNM_NET = tnm_ipb_clk;
#NET clk125 TNM_NET = tnm_clk125;
#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
# NET clocks/rst* TIG;
NET leds_o<0> LOC=D17 | IOSTANDARD=LVCMOS25;
NET leds_o<1> LOC=AB4 | IOSTANDARD=LVCMOS25;
NET leds_o<2> LOC=D21 | IOSTANDARD=LVCMOS25;
NET leds_o<3> LOC=W15 | IOSTANDARD=LVCMOS25;
NET dip_switch_i<0> LOC=C18;
NET dip_switch_i<1> LOC=Y6;
NET dip_switch_i<2> LOC=W6;
NET dip_switch_i<3> LOC=E4;
# Ethernet PHY
TIMEGRP TG_gmii_tx=PADS("gmii_tx*");
TIMEGRP TG_gmii_tx OFFSET = OUT AFTER sysclk_p_i REFERENCE_PIN "gmii_gtx_clk_o" RISING;
NET gmii_gtx_clk_o LOC=AB7 |IOSTANDARD=LVCMOS25 | SLEW=FAST;
NET gmii_txd_o<0> LOC=U10 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<1> LOC=T10 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<2> LOC=AB8 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<3> LOC=AA8 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<4> LOC=AB9 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<5> LOC=Y9 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<6> LOC=Y12 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<7> LOC=W12 |IOSTANDARD=LVCMOS25;
NET gmii_tx_en_o LOC=T8 |IOSTANDARD=LVCMOS25;
NET gmii_tx_er_o LOC=U8 |IOSTANDARD=LVCMOS25;
NET gmii_rx_clk_i LOC=P20 |IOSTANDARD=LVCMOS25 |TNM_NET= "gmii_rx_clk";
TIMESPEC "TS_GMII_RX_CLK_I" = PERIOD "gmii_rx_clk_i" 125MHz;
OFFSET = IN 2.5ns VALID 3ns BEFORE gmii_rx_clk_i;
NET gmii_rxd_i<0> LOC=P19 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<1> LOC=Y22 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<2> LOC=Y21 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<3> LOC=W22 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<4> LOC=W20 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<5> LOC=V22 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<6> LOC=V21 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<7> LOC=U22 |IOSTANDARD=LVCMOS25;
NET gmii_rx_dv_i LOC=T22 |IOSTANDARD=LVCMOS25;
NET gmii_rx_er_i LOC=U20 |IOSTANDARD=LVCMOS25;
NET phy_rstb_o LOC=J22 |IOSTANDARD=LVCMOS25;
# Main I2C bus
#NET i2c_scl_io LOC=P11 | IOSTANDARD=LVCMOS25;
#NET i2c_sda_io LOC=N10 | IOSTANDARD=LVCMOS25;
NET "I2C_SDA_B" LOC = "R22"; ## C30 on FMC
NET "I2C_SCL_B" LOC = "T21"; ## C31 on FMC
#
# I/O to devices under test
#NET "BUSY_P_I<0>" LOC = "D4"; ## "FMC_LA06_P" , C10 on FMC
#NET "BUSY_N_I<0>" LOC = "D5"; ## "FMC_LA06_N" , C11 on FMC
#NET "BUSY_P_I<1>" LOC = "AA16"; ## "FMC_LA28_P" , H31 on FMC
#NET "BUSY_N_I<1>" LOC = "AB16"; ## "FMC_LA28_N" , H32 on FMC
#NET "BUSY_P_I<2>" LOC = "B2"; ## "FMC_LA07_P" , H13 on FMC
#NET "BUSY_N_I<2>" LOC = "A2"; ## "FMC_LA07_N" , H14 on FMC
#NET "TRIGGERS_P_O<0>" LOC = "H10"; ## "FMC_LA10_P" , C14 on FMC
#NET "TRIGGERS_N_O<0>" LOC = "H11"; ## "FMC_LA10_N" , C15 on FMC
#NET "TRIGGERS_P_O<1>" LOC = "W17"; ## "FMC_LA32_P" , H37 on FMC
#NET "TRIGGERS_N_O<1>" LOC = "Y18"; ## "FMC_LA32_N" , H38 on FMC
#NET "TRIGGERS_P_O<2>" LOC = "F7"; ## "FMC_LA09_P" , D14 on FMC
#NET "TRIGGERS_N_O<2>" LOC = "F8"; ## "FMC_LA09_N" , D15 on FMC
#NET "SHUTTERS_P_O<0>" LOC = "R9"; ## "FMC_LA20_P" , G21 on FMC
#NET "SHUTTERS_N_O<0>" LOC = "R8"; ## "FMC_LA20_N" , G22 on FMC
#NET "SHUTTERS_P_O<1>" LOC = "T12"; ## "FMC_LA18_CC_P" , C22 on FMC
#NET "SHUTTERS_N_O<1>" LOC = "U12"; ## "FMC_LA18_CC_N" , C23 on FMC
#NET "SHUTTERS_P_O<2>" LOC = "R11"; ## "FMC_LA19_P" , H22 on FMC
#NET "SHUTTERS_N_O<2>" LOC = "T11"; ## "FMC_LA19_N" , H23 on FMC
#NET "DUT_CLK_P_I<0>" LOC = "U16"; ## "FMC_LA31_P" , G33 on FMC , "DUT_CLK_P_I<0>
#NET "DUT_CLK_N_I<0>" LOC = "V15"; ## "FMC_LA31_N" , G34 on FMC , DUT_CLK_N<0>
#NET "DUT_CLK_P_I<1>" LOC = "AA14"; ## "FMC_LA24_P" , H28 on FMC , CONT_P<1>
#NET "DUT_CLK_N_I<1>" LOC = "AB14"; ## "FMC_LA24_N" , H29 on FMC , CONT_N<1>
#NET "DUT_CLK_P_I<2>" LOC = "B20"; ## "FMC_LA08_P" , G12 on FMC , CONT_P<2>
#NET "DUT_CLK_N_I<2>" LOC = "A20"; ## "FMC_LA08_N" , G13 on FMC , CONT_N<2>
#NET "RESET_OR_CLK_P_O<0>" LOC = "Y17"; ## "FMC_LA33_P" , G36 on FMC , CONT_P<0>
##NET "RESET_OR_CLK_N_O<0>" LOC = "AB17"; ## "FMC_LA33_N" , G37 on FMC , CONT_N<0>
#NET "RESET_OR_CLK_P_O<1>" LOC = "V11"; ## "FMC_LA21_P" , H25 on FMC , CLK_P<1>
##NET "RESET_OR_CLK_N_O<1>" LOC = "W11"; ## "FMC_LA21_N" , H26 on FMC , CLK_QN<1>
#NET "RESET_OR_CLK_P_O<2>" LOC = "C19"; ## "FMC_LA04_P" , H10 on FMC , CLK_P<2>
##NET "RESET_OR_CLK_N_O<2>" LOC = "A19"; ## "FMC_LA04_N" , H11 on FMC , CLK_N<2>
# Trigger inputs
# first constant-fraction-discrimiator comparator outputs
NET "CFD_DISCR_P_I<0>" LOC = "G9"; ## "FMC_LA00_CC_P" , G6 on FMC
NET "CFD_DISCR_N_I<0>" LOC = "F10"; ## "FMC_LA00_CC_N" , G7 on FMC
NET "CFD_DISCR_P_I<1>" LOC = "C17"; ## "FMC_LA14_P" , C18 on FMC
NET "CFD_DISCR_N_I<1>" LOC = "A17"; ## "FMC_LA14_N" , C19 on FMC
NET "CFD_DISCR_P_I<2>" LOC = "H13"; ## "FMC_LA12_P" , C22 on FMC
NET "CFD_DISCR_N_I<2>" LOC = "G13"; ## "FMC_LA12_N" , C23 on FMC
NET "CFD_DISCR_P_I<3>" LOC = "C5"; ## "FMC_LA16_P" , C26 on FMC
NET "CFD_DISCR_N_I<3>" LOC = "A5"; ## "FMC_LA16_N" , C27 on FMC
#NET "CFD_DISCR_P_I<2>" LOC = "T12"; ## "FMC_LA18_CC_P" , C22 on FMC
#NET "CFD_DISCR_N_I<2>" LOC = "U12"; ## "FMC_LA18_CC_N" , C23 on FMC
#NET "CFD_DISCR_P_I<3>" LOC = "AA10"; ## "FMC_LA27_P" , C26 on FMC
#NET "CFD_DISCR_N_I<3>" LOC = "AB10"; ## "FMC_LA27_N" , C27 on FMC
# then threshold comparator outputs
# N.B. These differ from v1 of schematics, since the original choice couldn't be routed.
NET "THRESHOLD_DISCR_P_I<0>" LOC = "F14"; ## "FMC_LA01_CC_P" , D8 on FMC
#NET "THRESHOLD_DISCR_N_I<0>" LOC = "F15"; ## "FMC_LA01_CC_N" , D9 on FMC
NET "THRESHOLD_DISCR_P_I<1>" LOC = "G16"; ## "FMC_LA13_P" , D17 on FMC
#NET "THRESHOLD_DISCR_N_I<1>" LOC = "F17"; ## "FMC_LA13_N" , D18 on FMC
NET "THRESHOLD_DISCR_P_I<2>" LOC = "D18"; ## "FMC_LA15_P" , H19 on FMC
#NET "THRESHOLD_DISCR_N_I<2>" LOC = "D19"; ## "FMC_LA15_N" , H20 on FMC
NET "THRESHOLD_DISCR_P_I<3>" LOC = "H14"; ## "FMC_LA11_P" , H16 on FMC
#NET "THRESHOLD_DISCR_N_I<3>" LOC = "G15"; ## "FMC_LA11_N" , H17 on FMC
#NET "SPARE_P<2>" LOC = "Y11"; ## "FMC_LA17_CC_P" , D20 on FMC
#NET "SPARE_N<2>" LOC = "AB11"; ## "FMC_LA17_CC_N" , D21 on FMC
#NET "SPARE_P<1>" LOC = "Y15"; ## "FMC_LA30_P" , H34 on FMC
#NET "SPARE_N<1>" LOC = "AB15"; ## "FMC_LA30_N" , H35 on FMC
NET "EXTCLK_P_B" LOC = "H12"; ## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"
NET "EXTCLK_N_B" LOC = "G11"; ## "FMC_CLK0_M2C_N" , H5 on FMC , "FRONT_PANEL_CLK_N"
#NET "HDMI_POWER_ENABLE1" LOC = "G8"; ## "FMC_LA02_P" , H7 on FMC
#NET "HDMI_POWER_ENABLE2" LOC = "F9"; ## "FMC_LA02_N" , H8 on FMC
NET "output_0_p[0]" LOC = H10;
NET "output_0_p[1]" LOC = W17;
NET "output_0_p[2]" LOC = F7;
NET "output_0_n[0]" LOC = H11;
NET "output_0_n[1]" LOC = Y18;
NET "output_0_n[2]" LOC = F8;
NET "output_1_p[0]" LOC = U16;
NET "output_1_p[1]" LOC = V11;
NET "output_1_p[2]" LOC = C19;
NET "output_1_n[0]" LOC = V15;
NET "output_1_n[1]" LOC = W11;
NET "output_1_n[2]" LOC = A19;
NET "output_2_p[0]" LOC = Y17;
NET "output_2_p[1]" LOC = AA14;
NET "output_2_p[2]" LOC = B20;
NET "output_2_n[0]" LOC = AB17;
NET "output_2_n[1]" LOC = AB14;
NET "output_2_n[2]" LOC = A20;
NET "output_3_p[0]" LOC = D4;
NET "output_3_p[1]" LOC = AA16;
NET "output_3_p[2]" LOC = B2;
NET "output_3_n[0]" LOC = D5;
NET "output_3_n[1]" LOC = AB16;
NET "output_3_n[2]" LOC = A2; fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/test/sp605_FMC_mTLU_v1a.ucf 0000664 0000000 0000000 00000016516 12415504633 0026166 0 ustar 00root root 0000000 0000000 NET sysclk_p_i LOC = K21 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE | TNM_NET = tnm_sysclk;
NET sysclk_n_i LOC = K22 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
TIMESPEC TS_sysclk = PERIOD tnm_sysclk 200MHz;
#NET Reset_i LOC=F3; ## Global Reset
#NET ipb_clk TNM_NET = tnm_ipb_clk;
#NET clk125 TNM_NET = tnm_clk125;
#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
# NET clocks/rst* TIG;
NET leds_o<0> LOC=D17 | IOSTANDARD=LVCMOS25;
NET leds_o<1> LOC=AB4 | IOSTANDARD=LVCMOS25;
NET leds_o<2> LOC=D21 | IOSTANDARD=LVCMOS25;
NET leds_o<3> LOC=W15 | IOSTANDARD=LVCMOS25;
NET dip_switch_i<0> LOC=C18;
NET dip_switch_i<1> LOC=Y6;
NET dip_switch_i<2> LOC=W6;
NET dip_switch_i<3> LOC=E4;
# Ethernet PHY
TIMEGRP TG_gmii_tx=PADS("gmii_tx*");
TIMEGRP TG_gmii_tx OFFSET = OUT AFTER sysclk_p_i REFERENCE_PIN "gmii_gtx_clk_o" RISING;
NET gmii_gtx_clk_o LOC=AB7 |IOSTANDARD=LVCMOS25 | SLEW=FAST;
NET gmii_txd_o<0> LOC=U10 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<1> LOC=T10 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<2> LOC=AB8 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<3> LOC=AA8 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<4> LOC=AB9 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<5> LOC=Y9 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<6> LOC=Y12 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<7> LOC=W12 |IOSTANDARD=LVCMOS25;
NET gmii_tx_en_o LOC=T8 |IOSTANDARD=LVCMOS25;
NET gmii_tx_er_o LOC=U8 |IOSTANDARD=LVCMOS25;
NET gmii_rx_clk_i LOC=P20 |IOSTANDARD=LVCMOS25 |TNM_NET= "gmii_rx_clk";
TIMESPEC "TS_GMII_RX_CLK_I" = PERIOD "gmii_rx_clk_i" 125MHz;
OFFSET = IN 2.5ns VALID 3ns BEFORE gmii_rx_clk_i;
NET gmii_rxd_i<0> LOC=P19 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<1> LOC=Y22 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<2> LOC=Y21 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<3> LOC=W22 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<4> LOC=W20 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<5> LOC=V22 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<6> LOC=V21 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<7> LOC=U22 |IOSTANDARD=LVCMOS25;
NET gmii_rx_dv_i LOC=T22 |IOSTANDARD=LVCMOS25;
NET gmii_rx_er_i LOC=U20 |IOSTANDARD=LVCMOS25;
NET phy_rstb_o LOC=J22 |IOSTANDARD=LVCMOS25;
# Main I2C bus
#NET i2c_scl_io LOC=P11 | IOSTANDARD=LVCMOS25;
#NET i2c_sda_io LOC=N10 | IOSTANDARD=LVCMOS25;
NET "I2C_SDA_B" LOC = "R22"; ## C30 on FMC
NET "I2C_SCL_B" LOC = "T21"; ## C31 on FMC
#
# I/O to devices under test
#NET "BUSY_P_I<0>" LOC = "D4"; ## "FMC_LA06_P" , C10 on FMC
#NET "BUSY_N_I<0>" LOC = "D5"; ## "FMC_LA06_N" , C11 on FMC
#NET "BUSY_P_I<1>" LOC = "AA16"; ## "FMC_LA28_P" , H31 on FMC
#NET "BUSY_N_I<1>" LOC = "AB16"; ## "FMC_LA28_N" , H32 on FMC
#NET "BUSY_P_I<2>" LOC = "B2"; ## "FMC_LA07_P" , H13 on FMC
#NET "BUSY_N_I<2>" LOC = "A2"; ## "FMC_LA07_N" , H14 on FMC
#NET "TRIGGERS_P_O<0>" LOC = "H10"; ## "FMC_LA10_P" , C14 on FMC
#NET "TRIGGERS_N_O<0>" LOC = "H11"; ## "FMC_LA10_N" , C15 on FMC
#NET "TRIGGERS_P_O<1>" LOC = "W17"; ## "FMC_LA32_P" , H37 on FMC
#NET "TRIGGERS_N_O<1>" LOC = "Y18"; ## "FMC_LA32_N" , H38 on FMC
#NET "TRIGGERS_P_O<2>" LOC = "F7"; ## "FMC_LA09_P" , D14 on FMC
#NET "TRIGGERS_N_O<2>" LOC = "F8"; ## "FMC_LA09_N" , D15 on FMC
#NET "SHUTTERS_P_O<0>" LOC = "R9"; ## "FMC_LA20_P" , G21 on FMC
#NET "SHUTTERS_N_O<0>" LOC = "R8"; ## "FMC_LA20_N" , G22 on FMC
#NET "SHUTTERS_P_O<1>" LOC = "T12"; ## "FMC_LA18_CC_P" , C22 on FMC
#NET "SHUTTERS_N_O<1>" LOC = "U12"; ## "FMC_LA18_CC_N" , C23 on FMC
#NET "SHUTTERS_P_O<2>" LOC = "R11"; ## "FMC_LA19_P" , H22 on FMC
#NET "SHUTTERS_N_O<2>" LOC = "T11"; ## "FMC_LA19_N" , H23 on FMC
#NET "DUT_CLK_P_I<0>" LOC = "U16"; ## "FMC_LA31_P" , G33 on FMC , "DUT_CLK_P_I<0>
#NET "DUT_CLK_N_I<0>" LOC = "V15"; ## "FMC_LA31_N" , G34 on FMC , DUT_CLK_N<0>
#NET "DUT_CLK_P_I<1>" LOC = "AA14"; ## "FMC_LA24_P" , H28 on FMC , CONT_P<1>
#NET "DUT_CLK_N_I<1>" LOC = "AB14"; ## "FMC_LA24_N" , H29 on FMC , CONT_N<1>
#NET "DUT_CLK_P_I<2>" LOC = "B20"; ## "FMC_LA08_P" , G12 on FMC , CONT_P<2>
#NET "DUT_CLK_N_I<2>" LOC = "A20"; ## "FMC_LA08_N" , G13 on FMC , CONT_N<2>
#NET "RESET_OR_CLK_P_O<0>" LOC = "Y17"; ## "FMC_LA33_P" , G36 on FMC , CONT_P<0>
##NET "RESET_OR_CLK_N_O<0>" LOC = "AB17"; ## "FMC_LA33_N" , G37 on FMC , CONT_N<0>
#NET "RESET_OR_CLK_P_O<1>" LOC = "V11"; ## "FMC_LA21_P" , H25 on FMC , CLK_P<1>
##NET "RESET_OR_CLK_N_O<1>" LOC = "W11"; ## "FMC_LA21_N" , H26 on FMC , CLK_QN<1>
#NET "RESET_OR_CLK_P_O<2>" LOC = "C19"; ## "FMC_LA04_P" , H10 on FMC , CLK_P<2>
##NET "RESET_OR_CLK_N_O<2>" LOC = "A19"; ## "FMC_LA04_N" , H11 on FMC , CLK_N<2>
# Trigger inputs
# first constant-fraction-discrimiator comparator outputs
#NET "CFD_DISCR_P_I<0>" LOC = "W17"; ## "FMC_LA00_CC_P" , G6 on FMC
#NET "CFD_DISCR_N_I<0>" LOC = "Y18"; ## "FMC_LA00_CC_N" , G7 on FMC
#NET "CFD_DISCR_P_I<1>" LOC = "Y15"; ## "FMC_LA14_P" , C18 on FMC
#NET "CFD_DISCR_N_I<1>" LOC = "AB15"; ## "FMC_LA14_N" , C19 on FMC
#NET "CFD_DISCR_P_I<2>" LOC = "AA16"; ## "FMC_LA12_P" , C22 on FMC
#NET "CFD_DISCR_N_I<2>" LOC = "AB16"; ## "FMC_LA12_N" , C23 on FMC
#NET "CFD_DISCR_P_I<3>" LOC = "AA14"; ## "FMC_LA16_P" , C26 on FMC
#NET "CFD_DISCR_N_I<3>" LOC = "AB14"; ## "FMC_LA16_N" , C27 on FMC
##NET "CFD_DISCR_P_I<2>" LOC = "T12"; ## "FMC_LA18_CC_P" , C22 on FMC
##NET "CFD_DISCR_N_I<2>" LOC = "U12"; ## "FMC_LA18_CC_N" , C23 on FMC
##NET "CFD_DISCR_P_I<3>" LOC = "AA10"; ## "FMC_LA27_P" , C26 on FMC
##NET "CFD_DISCR_N_I<3>" LOC = "AB10"; ## "FMC_LA27_N" , C27 on FMC
# then threshold comparator outputs
# N.B. These differ from v1 of schematics, since the original choice couldn't be routed.
NET "THRESHOLD_DISCR_P_I<0>" LOC = "F14"; ## "FMC_LA01_CC_P" , D8 on FMC
#NET "THRESHOLD_DISCR_N_I<0>" LOC = "F15"; ## "FMC_LA01_CC_N" , D9 on FMC
NET "THRESHOLD_DISCR_P_I<1>" LOC = "G16"; ## "FMC_LA13_P" , D17 on FMC
#NET "THRESHOLD_DISCR_N_I<1>" LOC = "F17"; ## "FMC_LA13_N" , D18 on FMC
NET "THRESHOLD_DISCR_P_I<2>" LOC = "D18"; ## "FMC_LA15_P" , H19 on FMC
#NET "THRESHOLD_DISCR_N_I<2>" LOC = "D19"; ## "FMC_LA15_N" , H20 on FMC
NET "THRESHOLD_DISCR_P_I<3>" LOC = "H14"; ## "FMC_LA11_P" , H16 on FMC
#NET "THRESHOLD_DISCR_N_I<3>" LOC = "G15"; ## "FMC_LA11_N" , H17 on FMC
#NET "SPARE_P<2>" LOC = "Y11"; ## "FMC_LA17_CC_P" , D20 on FMC
#NET "SPARE_N<2>" LOC = "AB11"; ## "FMC_LA17_CC_N" , D21 on FMC
#NET "SPARE_P<1>" LOC = "Y15"; ## "FMC_LA30_P" , H34 on FMC
#NET "SPARE_N<1>" LOC = "AB15"; ## "FMC_LA30_N" , H35 on FMC
NET "EXTCLK_P_B" LOC = "H12"; ## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"
NET "EXTCLK_N_B" LOC = "G11"; ## "FMC_CLK0_M2C_N" , H5 on FMC , "FRONT_PANEL_CLK_N"
#NET "HDMI_POWER_ENABLE1" LOC = "G8"; ## "FMC_LA02_P" , H7 on FMC
#NET "HDMI_POWER_ENABLE2" LOC = "F9"; ## "FMC_LA02_N" , H8 on FMC
NET "output_0_p[0]" LOC = R9;
NET "output_0_p[1]" LOC = B18;
NET "output_0_p[2]" LOC = C5;
NET "output_0_n[0]" LOC = R8;
NET "output_0_n[1]" LOC = A18;
NET "output_0_n[2]" LOC = A5;
NET "output_1_p[0]" LOC = AA10;
NET "output_1_p[1]" LOC = G8;
NET "output_1_p[2]" LOC = V11;
NET "output_1_n[0]" LOC = AB10;
NET "output_1_n[1]" LOC = F9;
NET "output_1_n[2]" LOC = W11;
NET "output_2_p[0]" LOC = V7;
NET "output_2_p[1]" LOC = T12;
NET "output_2_p[2]" LOC = B2;
NET "output_2_n[0]" LOC = W8;
NET "output_2_n[1]" LOC = U12;
NET "output_2_n[2]" LOC = A2;
NET "output_3_p[0]" LOC = R11;
NET "output_3_p[1]" LOC = C17;
NET "output_3_p[2]" LOC = H13;
NET "output_3_n[0]" LOC = T11;
NET "output_3_n[1]" LOC = A17;
NET "output_3_n[2]" LOC = G13; fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl/test/top_extphy_struct.vhd 0000664 0000000 0000000 00000074017 12415504633 0026767 0 ustar 00root root 0000000 0000000 -- VHDL Entity work.top_extphy.symbol
--
-- Created:
-- by - phdgc.users (fortis.phy.bris.ac.uk)
-- at - 16:06:33 01/24/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2012.2b (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY top_extphy IS
GENERIC(
g_NUM_DUTS : positive := 3;
g_NUM_TRIG_INPUTS : positive := 4;
g_NUM_EXT_SLAVES : positive := 10; --! Number of slaves outside IPBus interface
g_EVENT_DATA_WIDTH : positive := 64;
g_IPBUS_WIDTH : positive := 32;
g_NUM_EDGE_INPUTS : positive := 4;
g_SPILL_COUNTER_WIDTH : positive := 12
);
PORT(
--busy_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
--busy_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Busy lines from DUTs ( active high )
cfd_discr_n_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
cfd_discr_p_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
dip_switch_i : IN std_logic_vector (3 DOWNTO 0);
dut_clk_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
dut_clk_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
gmii_rx_clk_i : IN std_logic;
gmii_rx_dv_i : IN std_logic;
gmii_rx_er_i : IN std_logic;
gmii_rxd_i : IN std_logic_vector (7 DOWNTO 0);
sysclk_n_i : IN std_logic; --! 200 MHz xtal clock
sysclk_p_i : IN std_logic;
threshold_discr_n_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
threshold_discr_p_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
gmii_gtx_clk_o : OUT std_logic;
gmii_tx_en_o : OUT std_logic;
gmii_tx_er_o : OUT std_logic;
gmii_txd_o : OUT std_logic_vector (7 DOWNTO 0);
gpio_hdr : OUT std_logic_vector (7 DOWNTO 0);
leds_o : OUT std_logic_vector (3 DOWNTO 0);
phy_rstb_o : OUT std_logic;
-- reset_or_clk_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
-- reset_or_clk_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
-- triggers_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
-- triggers_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Trigger lines to DUT
extclk_n_b : OUT std_logic;
extclk_p_b : OUT std_logic; --! either external clock in, or a clock being driven out
output_0_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_0_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_1_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_1_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_2_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_2_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_3_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_3_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
i2c_scl_b : INOUT std_logic;
i2c_sda_b : INOUT std_logic
);
-- Declarations
END ENTITY top_extphy ;
--=============================================================================
--! @file top_extphy_struct.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL -- VHDL Architecture work.top_extphy.struct
--
--! @brief \n
--! \n
--
--! @author David Cussans , David.Cussans@bristol.ac.uk ( phdgc.users (fortis.phy.bris.ac.uk))
--
--! @date 16:18:26 01/24/14
--
--! @version v0.1
--
--! @details
--!
--!
--! Dependencies:\n
--!
--! References:\n
--!
--! Modified by:\n
--! Author:
-------------------------------------------------------------------------------
--! \n\nLast changes:\n
-------------------------------------------------------------------------------
--! @todo \n
--! \n
--
--------------------------------------------------------------------------------
--
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2012.2b (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY work;
USE work.ipbus.all;
USE work.emac_hostbus_decl.all;
USE work.fmcTLU.all;
LIBRARY unisim;
USE unisim.vcomponents.all;
ARCHITECTURE struct OF top_extphy IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL buffer_full_o : std_logic; --! Goes high when event buffer almost full
SIGNAL clk_16x_logic : std_logic; -- 640MHz clock
SIGNAL clk_4x_logic : std_logic; --! normally 160MHz
SIGNAL clk_logic_xtal : std_logic; -- ! 40MHz clock from onboard xtal
SIGNAL data_strobe : std_logic; -- goes high when data ready to load into event buffer
SIGNAL edge_fall_i : std_logic_vector(g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when falling edge
SIGNAL edge_fall_time_i : t_triggerTimeArray(g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
SIGNAL edge_rise_i : std_logic_vector(g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when rising edge
SIGNAL edge_rise_time_i : t_triggerTimeArray(g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
SIGNAL event_data : std_logic_vector(g_EVENT_DATA_WIDTH-1 DOWNTO 0);
SIGNAL event_number_o : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0); -- starts at one. Increments for each post_veto_trigger
SIGNAL ipbr : ipb_rbus_array(g_NUM_EXT_SLAVES-1 DOWNTO 0); --! IPBus read signals
SIGNAL ipbus_clk : std_logic;
SIGNAL ipbus_reset : std_logic;
SIGNAL ipbus_rst : std_logic; -- ! IPBus reset to slaves
SIGNAL ipbw : ipb_wbus_array(g_NUM_EXT_SLAVES-1 DOWNTO 0); --! IBus write signals
SIGNAL logic_clocks_reset : std_logic; -- Goes high to reset counters etc. Sync with clk_4x_logic
SIGNAL logic_reset : std_logic; -- Goes high to reset counters etc. Sync with clk_4x_logic
SIGNAL overall_trigger : std_logic; --! goes high to load trigger data
SIGNAL overall_veto : std_logic; --! Halts triggers when high
SIGNAL s_i2c_scl_enb : std_logic;
SIGNAL s_i2c_sda_enb : std_logic;
SIGNAL shutter_cnt_i : std_logic_vector(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0);
SIGNAL shutter_i : std_logic;
SIGNAL spill_cnt_i : std_logic_vector(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0);
SIGNAL spill_i : std_logic;
SIGNAL strobe_16x_logic : std_logic; --! Pulses one cycle every 4 of 16x clock.
SIGNAL strobe_4x_logic : std_logic; -- one pulse every 4 cycles of clk_4x
SIGNAL trigger_cnt_i : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0);
SIGNAL trigger_count : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0);
SIGNAL trigger_times : t_triggerTimeArray(g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- ! trigger arrival time ( w.r.t. logic_strobe)
SIGNAL triggers : std_logic_vector(g_NUM_TRIG_INPUTS-1 DOWNTO 0);
SIGNAL veto_o : std_logic; --! goes high when one or more DUT are busy
-- Component Declarations
COMPONENT DUTInterfaces
GENERIC (
g_NUM_DUTS : positive := 3;
g_IPBUS_WIDTH : positive := 32
);
PORT (
--busy_from_dut_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
--busy_from_dut_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
clk_4x_logic_i : IN std_logic ;
clk_from_dut_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
clk_from_dut_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
ipbus_clk_i : IN std_logic ;
ipbus_i : IN ipb_wbus ; -- Signals from IPBus core TO slave
ipbus_reset_i : IN std_logic ;
strobe_4x_logic_i : IN std_logic ; -- ! goes high every 4th clock cycle
trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);
trigger_i : IN std_logic ; -- goes high when trigger logic issues a trigger
--shutter_i : IN std_logic; -- goes high when trigger logic issues a shutter
ipbus_o : OUT ipb_rbus ; -- signals from slave TO IPBus core
-- reset_or_clk_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
-- reset_or_clk_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
-- trigger_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
-- trigger_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
--shutter_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Shutter output
--shutter_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Shutter output
output_0_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_0_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_1_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_1_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_2_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_2_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_3_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
output_3_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
veto_o : OUT std_logic -- goes high when one or more DUT are busy
);
END COMPONENT DUTInterfaces;
COMPONENT IPBusInterface
GENERIC (
NUM_EXT_SLAVES : positive := 5
);
PORT (
gmii_rx_clk_i : IN std_logic ;
gmii_rx_dv_i : IN std_logic ;
gmii_rx_er_i : IN std_logic ;
gmii_rxd_i : IN std_logic_vector (7 DOWNTO 0);
ipbr_i : IN ipb_rbus_array (NUM_EXT_SLAVES-1 DOWNTO 0); -- ! IPBus read signals
sysclk_n_i : IN std_logic ;
sysclk_p_i : IN std_logic ; -- ! 200 MHz xtal clock
clocks_locked_o : OUT std_logic ;
gmii_gtx_clk_o : OUT std_logic ;
gmii_tx_en_o : OUT std_logic ;
gmii_tx_er_o : OUT std_logic ;
gmii_txd_o : OUT std_logic_vector (7 DOWNTO 0);
ipb_clk_o : OUT std_logic ; -- ! IPBus clock TO slaves
ipb_rst_o : OUT std_logic ; -- ! IPBus reset TO slaves
ipbw_o : OUT ipb_wbus_array (NUM_EXT_SLAVES-1 DOWNTO 0); -- ! IBus write signals
onehz_o : OUT std_logic ;
phy_rstb_o : OUT std_logic ;
dip_switch_i : IN std_logic_vector (3 DOWNTO 0);
clk_logic_xtal_o : OUT std_logic
);
END COMPONENT IPBusInterface;
COMPONENT eventBuffer
GENERIC (
g_EVENT_DATA_WIDTH : positive := 64;
g_IPBUS_WIDTH : positive := 32;
g_WRITE_COUNTER_WIDTH : positive := 13;
g_READ_COUNTER_WIDTH : positive := 14
);
PORT (
clk_4x_logic_i : IN std_logic ;
data_strobe_i : IN std_logic ; -- Indicates data TO transfer
event_data_i : IN std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
ipbus_clk_i : IN std_logic ;
ipbus_i : IN ipb_wbus ;
ipbus_reset_i : IN std_logic ;
strobe_4x_logic_i : IN std_logic ;
trigger_count_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not yet used.
buffer_full_o : OUT std_logic ; --! Goes high when event buffer almost full
ipbus_o : OUT ipb_rbus ;
logic_reset_i : IN std_logic -- reset buffers when high. Synch withclk_4x_logic
);
END COMPONENT eventBuffer;
COMPONENT eventFormatter
GENERIC (
g_EVENT_DATA_WIDTH : positive := 64;
g_IPBUS_WIDTH : positive := 32;
g_COUNTER_TRIG_WIDTH : positive := 32;
g_COUNTER_WIDTH : positive := 12;
g_EVTTYPE_WIDTH : positive := 4; -- Width of the event type word
--g_NUM_INPUT_TYPES : positive := 4; -- Number of different input types (trigger, shutter, edge...)
g_NUM_EDGE_INPUTS : positive := 4; -- Number of edge inputs
g_NUM_TRIG_INPUTS : positive := 5 -- Number of trigger inputs
);
PORT (
clk_4x_logic_i : IN std_logic ; -- ! Rising edge active
ipbus_clk_i : IN std_logic ;
logic_strobe_i : IN std_logic ; -- ! Pulses high once every 4 cycles of clk_4x_logic
logic_reset_i : IN std_logic ; -- goes high TO reset counters. Synchronous with clk_4x_logic
trigger_i : IN std_logic ; --! goes high TO load trigger data. One cycle of clk_4x_logic
trigger_times_i : IN t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- Array of trigger times ( w.r.t. logic_strobe)
trigger_inputs_fired_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- high for each input that "fired"
trigger_cnt_i : IN std_logic_vector (g_COUNTER_TRIG_WIDTH-1 DOWNTO 0);
shutter_i : IN std_logic ;
shutter_cnt_i : IN std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
spill_i : IN std_logic ;
spill_cnt_i : IN std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
edge_rise_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when rising edge
edge_fall_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when falling edge
edge_rise_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
edge_fall_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
ipbus_i : IN ipb_wbus ;
ipbus_o : OUT ipb_rbus ;
data_strobe_o : OUT std_logic ; -- goes high when data ready TO load into event buffer
event_data_o : OUT std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
event_number_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);
trigger_count_o : OUT std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0)
);
END COMPONENT eventFormatter;
COMPONENT i2c_master
PORT (
i2c_scl_i : IN std_logic ;
i2c_sda_i : IN std_logic ;
ipbus_clk_i : IN std_logic ;
ipbus_i : IN ipb_wbus ; -- Signals from IPBus core TO slave
ipbus_reset_i : IN std_logic ;
i2c_scl_enb_o : OUT std_logic ;
i2c_sda_enb_o : OUT std_logic ;
ipbus_o : OUT ipb_rbus -- signals from slave TO IPBus core
);
END COMPONENT i2c_master;
COMPONENT logic_clocks
PORT (
ipbus_clk_i : IN std_logic ;
ipbus_i : IN ipb_wbus ;
ipbus_reset_i : IN std_logic ;
Reset_i : IN std_logic ;
clk_logic_xtal_i : IN std_logic ; -- ! 40MHz clock from onboard xtal
clk_16x_logic_o : OUT std_logic ; -- 640MHz clock
clk_4x_logic_o : OUT std_logic ; -- 160MHz clock
ipbus_o : OUT ipb_rbus ;
strobe_16x_logic_o : OUT std_logic ; -- strobes once every 4 cycles of clk_16x
strobe_4x_logic_o : OUT std_logic ; -- one pulse every 4 cycles of clk_4x
extclk_p_b : OUT std_logic ; -- either external clock in, or a clock being driven out
extclk_n_b : OUT std_logic ;
clk_logic_o : OUT std_logic ;
logic_clocks_locked_o : OUT std_logic ;
logic_reset_o : OUT std_logic -- Goes high TO reset counters etc. Sync with clk_4x_logic
);
END COMPONENT logic_clocks;
COMPONENT triggerInputs
GENERIC (
g_NUM_INPUTS : natural := 1
);
PORT (
cfd_discr_p_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);
cfd_discr_n_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);
clk_4x_logic : IN std_logic ; -- ! Rising edge active
strobe_4x_logic_i : IN std_logic ; -- ! Pulses high once every 4 cycles of clk_4x_logic
threshold_discr_p_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! inputs from threshold comparators
threshold_discr_n_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! inputs from threshold comparators
trigger_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); -- ! trigger arrival time ( w.r.t. logic_strobe)
trigger_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when trigger active
trigger_debug_o : OUT std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0); -- ! Copy of input trigger level. High bits CFD, Low threshold
edge_rising_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); -- ! edge arrival time ( w.r.t. logic_strobe)
edge_falling_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); -- ! edge arrival time ( w.r.t. logic_strobe)
edge_rising_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when rising edge
edge_falling_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when falling edge
ipbus_clk_i : IN std_logic ;
ipbus_reset_i : IN std_logic ;
ipbus_i : IN ipb_wbus ; -- Signals from IPBus core TO slave
ipbus_o : OUT ipb_rbus ; -- signals from slave TO IPBus core
clk_16x_logic_i : IN std_logic ; --! 640MHz clock ( 16x 40MHz )
strobe_16x_logic_i : IN std_logic --! Pulses one cycle every 4 of 16x clock.
);
END COMPONENT triggerInputs;
COMPONENT triggerLogic
GENERIC (
g_NUM_INPUTS : positive := 4;
g_IPBUS_WIDTH : positive := 32
);
PORT (
clk_4x_logic_i : IN std_logic ; -- ! Rising edge active
ipbus_clk_i : IN std_logic ;
ipbus_i : IN ipb_wbus ; -- Signals from IPBus core TO slave
ipbus_reset_i : IN std_logic ;
logic_reset_i : IN std_logic ; -- active high. Synchronous with clk_4x_logic
logic_strobe_i : IN std_logic ; -- ! Pulses high once every 4 cycles of clk_4x_logic
trigger_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when trigger from input conector active
veto_i : IN std_logic ; -- ! Halts triggers when high
event_number_o : OUT std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); -- starts at one. Increments for each post_veto_trigger
ipbus_o : OUT ipb_rbus ; -- signals from slave TO IPBus core
post_veto_trigger_o : OUT std_logic ; -- ! goes high when trigger passes
pre_veto_trigger_o : OUT std_logic ;
trigger_active_o : OUT std_logic --! Goes high when triggers are active ( ie. not veoted)
);
END COMPONENT triggerLogic;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : DUTInterfaces USE ENTITY work.DUTInterfaces;
FOR ALL : IPBusInterface USE ENTITY work.IPBusInterface;
FOR ALL : eventBuffer USE ENTITY work.eventBuffer;
FOR ALL : eventFormatter USE ENTITY work.eventFormatter;
FOR ALL : i2c_master USE ENTITY work.i2c_master;
FOR ALL : logic_clocks USE ENTITY work.logic_clocks;
FOR ALL : triggerInputs USE ENTITY work.triggerInputs;
FOR ALL : triggerLogic USE ENTITY work.triggerLogic;
-- pragma synthesis_on
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 1 i2c_tristate
-- eb1 1
i2c_scl_b <= '0' when (s_i2c_scl_enb = '0') else 'Z';
i2c_sda_b <= '0' when (s_i2c_sda_enb = '0') else 'Z';
-- ModuleWare code(v1.12) for instance 'I9' of 'gnd'
logic_clocks_reset <= '0';
-- ModuleWare code(v1.12) for instance 'I10' of 'gnd'
--trigger_cnt_i <= (OTHERS => '0');
trigger_cnt_i <= event_number_o;
-- ModuleWare code(v1.12) for instance 'I11' of 'gnd'
spill_i <= '0';
-- ModuleWare code(v1.12) for instance 'I12' of 'gnd'
spill_cnt_i <= (OTHERS => '0');
-- ModuleWare code(v1.12) for instance 'I13' of 'gnd'
shutter_i <= '0';
-- ModuleWare code(v1.12) for instance 'I14' of 'gnd'
shutter_cnt_i <= (OTHERS => '0');
-- ModuleWare code(v1.12) for instance 'I8' of 'sor'
overall_veto <= buffer_full_o OR veto_o;
-- Instance port mappings.
I0 : DUTInterfaces
GENERIC MAP (
g_NUM_DUTS => g_NUM_DUTS,
g_IPBUS_WIDTH => g_IPBUS_WIDTH
)
PORT MAP (
--busy_from_dut_n_i => (others=>'0'), --busy_n_i,
--busy_from_dut_p_i => (others=>'0'), --busy_p_i,
clk_4x_logic_i => clk_4x_logic,
clk_from_dut_n_i => dut_clk_n_i,
clk_from_dut_p_i => dut_clk_p_i,
ipbus_clk_i => ipbus_clk,
ipbus_i => ipbw(0),
ipbus_reset_i => ipbus_reset,
strobe_4x_logic_i => strobe_4x_logic,
trigger_counter_i => trigger_count,
trigger_i => overall_trigger,
ipbus_o => ipbr(0),
-- reset_or_clk_to_dut_n_o => reset_or_clk_n_o,
-- reset_or_clk_to_dut_p_o => reset_or_clk_p_o,
-- trigger_to_dut_n_o => triggers_n_o,
-- trigger_to_dut_p_o => triggers_p_o,
output_0_p => output_0_p,
output_0_n => output_0_n,
output_1_p => output_1_p,
output_1_n => output_1_n,
output_2_p => output_2_p,
output_2_n => output_2_n,
output_3_p => output_3_p,
output_3_n => output_3_n,
veto_o => veto_o
);
I4 : IPBusInterface
GENERIC MAP (
NUM_EXT_SLAVES => g_NUM_EXT_SLAVES
)
PORT MAP (
gmii_rx_clk_i => gmii_rx_clk_i,
gmii_rx_dv_i => gmii_rx_dv_i,
gmii_rx_er_i => gmii_rx_er_i,
gmii_rxd_i => gmii_rxd_i,
ipbr_i => ipbr,
sysclk_n_i => sysclk_n_i,
sysclk_p_i => sysclk_p_i,
clocks_locked_o => leds_o(2),
gmii_gtx_clk_o => gmii_gtx_clk_o,
gmii_tx_en_o => gmii_tx_en_o,
gmii_tx_er_o => gmii_tx_er_o,
gmii_txd_o => gmii_txd_o,
ipb_clk_o => ipbus_clk,
ipb_rst_o => ipbus_rst,
ipbw_o => ipbw,
onehz_o => leds_o(3),
phy_rstb_o => phy_rstb_o,
dip_switch_i => dip_switch_i,
clk_logic_xtal_o => clk_logic_xtal
);
I5 : eventBuffer
GENERIC MAP (
g_EVENT_DATA_WIDTH => g_EVENT_DATA_WIDTH,
g_IPBUS_WIDTH => g_IPBUS_WIDTH,
g_WRITE_COUNTER_WIDTH => 13,
g_READ_COUNTER_WIDTH => 14
)
PORT MAP (
clk_4x_logic_i => clk_4x_logic,
data_strobe_i => data_strobe,
event_data_i => event_data,
ipbus_clk_i => ipbus_clk,
ipbus_i => ipbw(3),
ipbus_reset_i => ipbus_reset,
strobe_4x_logic_i => strobe_4x_logic,
trigger_count_i => trigger_count,
buffer_full_o => buffer_full_o,
ipbus_o => ipbr(3),
logic_reset_i => logic_reset
);
I2 : eventFormatter
GENERIC MAP (
g_EVENT_DATA_WIDTH => g_EVENT_DATA_WIDTH,
g_IPBUS_WIDTH => g_IPBUS_WIDTH,
g_COUNTER_TRIG_WIDTH => g_IPBUS_WIDTH,
g_COUNTER_WIDTH => 12,
g_EVTTYPE_WIDTH => 4, -- Width of the event type word
--g_NUM_INPUT_TYPES : positive := 4; -- Number of different input types (trigger, shutter, edge...)
g_NUM_EDGE_INPUTS => g_NUM_EDGE_INPUTS, -- Number of edge inputs
g_NUM_TRIG_INPUTS => g_NUM_TRIG_INPUTS -- Number of trigger inputs
)
PORT MAP (
clk_4x_logic_i => clk_4x_logic,
ipbus_clk_i => ipbus_clk,
logic_strobe_i => strobe_4x_logic,
logic_reset_i => logic_reset,
trigger_i => overall_trigger,
trigger_times_i => trigger_times,
trigger_inputs_fired_i => triggers,
trigger_cnt_i => trigger_cnt_i,
shutter_i => shutter_i,
shutter_cnt_i => shutter_cnt_i,
spill_i => spill_i,
spill_cnt_i => spill_cnt_i,
edge_rise_i => edge_rise_i,
edge_fall_i => edge_fall_i,
edge_rise_time_i => edge_rise_time_i,
edge_fall_time_i => edge_fall_time_i,
ipbus_i => ipbw(9),
ipbus_o => ipbr(9),
data_strobe_o => data_strobe,
event_data_o => event_data,
event_number_i => event_number_o,
trigger_count_o => trigger_count
);
I7 : i2c_master
PORT MAP (
i2c_scl_i => i2c_scl_b,
i2c_sda_i => i2c_sda_b,
ipbus_clk_i => ipbus_clk,
ipbus_i => ipbw(5),
ipbus_reset_i => ipbus_reset,
i2c_scl_enb_o => s_i2c_scl_enb,
i2c_sda_enb_o => s_i2c_sda_enb,
ipbus_o => ipbr(5)
);
I6 : logic_clocks
PORT MAP (
ipbus_clk_i => ipbus_clk,
ipbus_i => ipbw(4),
ipbus_reset_i => ipbus_reset,
Reset_i => logic_clocks_reset,
clk_logic_xtal_i => clk_logic_xtal,
clk_16x_logic_o => clk_16x_logic,
clk_4x_logic_o => clk_4x_logic,
ipbus_o => ipbr(4),
strobe_16x_logic_o => strobe_16x_logic,
strobe_4x_logic_o => strobe_4x_logic,
extclk_p_b => extclk_p_b,
extclk_n_b => extclk_n_b,
clk_logic_o => OPEN,
logic_clocks_locked_o => leds_o(1),
logic_reset_o => logic_reset
);
I1 : triggerInputs
GENERIC MAP (
g_NUM_INPUTS => g_NUM_TRIG_INPUTS
)
PORT MAP (
cfd_discr_p_i => cfd_discr_p_i,
cfd_discr_n_i => cfd_discr_n_i,
clk_4x_logic => clk_4x_logic,
strobe_4x_logic_i => strobe_4x_logic,
threshold_discr_p_i => threshold_discr_p_i,
threshold_discr_n_i => threshold_discr_n_i,
trigger_times_o => trigger_times,
trigger_o => triggers,
trigger_debug_o => OPEN, --gpio_hdr,
edge_rising_times_o => OPEN,
edge_falling_times_o => OPEN,
edge_rising_o => OPEN,
edge_falling_o => OPEN,
ipbus_clk_i => ipbus_clk,
ipbus_reset_i => ipbus_reset,
ipbus_i => ipbw(1),
ipbus_o => ipbr(1),
clk_16x_logic_i => clk_16x_logic,
strobe_16x_logic_i => strobe_16x_logic
);
I3 : triggerLogic
GENERIC MAP (
g_NUM_INPUTS => g_NUM_TRIG_INPUTS,
g_IPBUS_WIDTH => g_IPBUS_WIDTH
)
PORT MAP (
clk_4x_logic_i => clk_4x_logic,
ipbus_clk_i => ipbus_clk,
ipbus_i => ipbw(2),
ipbus_reset_i => ipbus_reset,
logic_reset_i => logic_reset,
logic_strobe_i => strobe_4x_logic,
trigger_i => triggers,
veto_i => overall_veto,
event_number_o => event_number_o,
ipbus_o => ipbr(2),
post_veto_trigger_o => overall_trigger,
pre_veto_trigger_o => OPEN,
trigger_active_o => leds_o(0)
);
gpio_hdr(0) <= overall_trigger;
--gpio_hdr(1) <= clk_4x_logic;
END ARCHITECTURE struct;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/ 0000775 0000000 0000000 00000000000 12415504633 0023345 5 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/ 0000775 0000000 0000000 00000000000 12415504633 0025013 5 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU.hdp 0000664 0000000 0000000 00000002610 12415504633 0027155 0 ustar 00root root 0000000 0000000 [DesignChecker]
work = $HDS_PROJECT_DIR/fmc_mTLU_lib/designcheck
[ModelSim]
work = $HDS_PROJECT_DIR/fmc_mTLU_lib/work
[QuestaSim]
simprim = /software/CAD/Xilinx/14.3_64b/14.3/ISE_DS/ISE/vhdl/questasim/10.0d/lin64/simprim
unisim = /software/CAD/Xilinx/14.3_64b/14.3/ISE_DS/ISE/vhdl/questasim/10.0d/lin64/unisim
xilinxcorelib = /software/CAD/Xilinx/14.3_64b/14.3/ISE_DS/ISE/vhdl/questasim/10.0d/lin64/xilinxcorelib
[XilinxISE]
work = $HDS_PROJECT_DIR/fmc_mTLU_lib/ise
[hdl]
exemplar = $HDS_HOME/examples/exemplar/hdl
hds_package_library = $HDS_HOME/hdl_libs/hds_package_library/hdl
renoir_package_library = $HDS_HOME/hdl_libs/renoir_package_library/hdl
work = $HDS_PROJECT_DIR/fmc_mTLU_lib/hdl
[hds]
exemplar = $HDS_HOME/examples/exemplar/hds
hds_package_library = $HDS_HOME/hdl_libs/hds_package_library/hds
renoir_package_library = $HDS_HOME/hdl_libs/renoir_package_library/hds
work = $HDS_PROJECT_DIR/fmc_mTLU_lib/hds
[hds_settings]
default_library = work
design_root = work.top_extphy(struct)top_extphy/struct.bd
project_description = Firmware for AIDA Mini-TLU in FMC format
version = 2
[library_files_inclusion]
simprim = all
unisim = all
work = specify
xilinxcorelib = all
[library_type]
exemplar = regular
hds_package_library = regular
renoir_package_library = regular
simprim = downstream_only
unisim = downstream_only
work = regular
xilinxcorelib = downstream_only
[shared]
others = $HDS_TEAM_HOME/shared.hdp
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/ 0000775 0000000 0000000 00000000000 12415504633 0027307 5 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ 0000775 0000000 0000000 00000000000 12415504633 0030056 5 ustar 00root root 0000000 0000000 DUTInterfaces_rtl.vhd.rlnk 0000664 0000000 0000000 00000000077 12415504633 0034774 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd IPBusInterface_rtl.vhd.rlnk 0000664 0000000 0000000 00000000100 12415504633 0035122 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/arp.v.rlnk 0000664 0000000 0000000 00000000162 12415504633 0031773 0 ustar 00root root 0000000 0000000 /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/arp.v arrivalTimeLUT_rtl.vhd.rlnk 0000664 0000000 0000000 00000000100 12415504633 0035163 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/bus_arb.vhd.rlnk 0000664 0000000 0000000 00000000170 12415504633 0033141 0 ustar 00root root 0000000 0000000 /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/bus_arb.vhd dualSERDES_1to4_rtl.vhd.rlnk 0000664 0000000 0000000 00000000101 12415504633 0035022 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/dualSERDES_1to4_rtl.vhd emac_hostbus_decl.vhd.rlnk 0000664 0000000 0000000 00000000205 12415504633 0035107 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ethernet/hdl/emac_hostbus_decl.vhd eth_s6_1000basex.vhd.rlnk 0000664 0000000 0000000 00000000204 12415504633 0034316 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ethernet/hdl/eth_s6_1000basex.vhd eth_s6_gmii.vhd.rlnk 0000664 0000000 0000000 00000000177 12415504633 0033651 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ethernet/hdl/eth_s6_gmii.vhd eventBuffer_rtl.vhd.rlnk 0000664 0000000 0000000 00000000075 12415504633 0034605 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd eventFormatter_rtl.vhd.rlnk 0000664 0000000 0000000 00000000100 12415504633 0035324 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd 0000664 0000000 0000000 00000001723 12415504633 0032557 0 ustar 00root root 0000000 0000000 --=============================================================================
--! @file fmcTLU_pkg.vhd
--=============================================================================
---
--! @brief VHDL Package Header fmc_mTLU_lib.fmcTLU
--
--! @author phdgc
--! @date 16:44:31 11/08/12
--
-- using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE fmcTLU IS
constant c_NUM_TIME_BITS : natural := 5;
constant c_NUM_TRIG_INPUTS : natural := 4;
constant c_EVENT_DATA_WIDTH : natural := 32;
constant c_DATA_WIDTH : natural := 32;
--subtype t_triggerTime is std_logic_vector(c_NUM_TIME_BITS-1 downto 0);
--type t_triggerTimeArray is array(natural range <>) of t_triggerTime;
type t_triggerTimeArray is array(natural range <>) of std_logic_vector(c_NUM_TIME_BITS-1 downto 0) ;
type t_registerArray is array(natural range <>) of std_logic_vector(c_DATA_WIDTH-1 downto 0) ;
END fmcTLU;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg_body.vhd0000664 0000000 0000000 00000000624 12415504633 0033573 0 ustar 00root root 0000000 0000000 --=============================================================================
--! @file fmcTLU_pkg_body.vhd
--=============================================================================
---
--! @brief VHDL Package Body fmc_mTLU_lib.fmcTLU
--
--! @author phdgc
--! @date 16:45:08 11/08/12
--
-- using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
PACKAGE BODY fmcTLU IS
END fmcTLU;
gbe_rxpacketbuffer.v.rlnk 0000664 0000000 0000000 00000000201 12415504633 0034754 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/gbe_rxpacketbuffer.v gbe_txpacketbuffer.v.rlnk 0000664 0000000 0000000 00000000201 12415504633 0034756 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/gbe_txpacketbuffer.v i2c_master_rtl.vhd.rlnk 0000664 0000000 0000000 00000000074 12415504633 0034361 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/i2c_master_rtl.vhd fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/icmp.v.rlnk 0000664 0000000 0000000 00000000163 12415504633 0032142 0 ustar 00root root 0000000 0000000 /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/icmp.v ip_checksum_8bit.v.rlnk 0000664 0000000 0000000 00000000177 12415504633 0034360 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/ip_checksum_8bit.v ipbus_bus_decl.vhd.rlnk 0000664 0000000 0000000 00000000177 12415504633 0034436 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/ipbus_bus_decl.vhd fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ipbus_ctrl.vhd.rlnk0000664 0000000 0000000 00000000173 12415504633 0033675 0 ustar 00root root 0000000 0000000 /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/ipbus_ctrl.vhd ipbus_ctrl_decl.vhd.rlnk 0000664 0000000 0000000 00000000200 12415504633 0034574 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/ipbus_ctrl_decl.vhd ipbus_ctrl_udponly.vhd.rlnk 0000664 0000000 0000000 00000000203 12415504633 0035362 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/ipbus_ctrl_udponly.vhd ipbus_fabric.vhd.rlnk 0000664 0000000 0000000 00000000175 12415504633 0034102 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/ipbus_fabric.vhd ipbus_package.vhd.rlnk 0000664 0000000 0000000 00000000176 12415504633 0034250 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/ipbus_package.vhd fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ipbus_v_defs.v.rlnk0000664 0000000 0000000 00000000173 12415504633 0033663 0 ustar 00root root 0000000 0000000 /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/ipbus_v_defs.v logic_clocks_rtl.vhd.rlnk 0000664 0000000 0000000 00000000076 12415504633 0034766 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd mac_arbiter.vhd.rlnk 0000664 0000000 0000000 00000000177 12415504633 0033724 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ethernet/hdl/mac_arbiter.vhd mac_arbiter_decl.vhd.rlnk 0000664 0000000 0000000 00000000204 12415504633 0034702 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ethernet/hdl/mac_arbiter_decl.vhd packet_handler.v.rlnk 0000664 0000000 0000000 00000000175 12415504633 0034102 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/packet_handler.v sub_packetbuffer.v.rlnk 0000664 0000000 0000000 00000000177 12415504633 0034452 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/sub_packetbuffer.v sub_packetreq.v.rlnk 0000664 0000000 0000000 00000000174 12415504633 0033765 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/sub_packetreq.v sub_packetresp.v.rlnk 0000664 0000000 0000000 00000000175 12415504633 0034150 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/sub_packetresp.v fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_rtl.vhd 0000664 0000000 0000000 00000005124 12415504633 0033647 0 ustar 00root root 0000000 0000000 --=============================================================================
--! @file top_extphy_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.top_extphy.rtl
--
--! @brief \n
--! \n
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 15:11:55 11/09/12
--
--! @version v0.1
--
--! @details
--!
--!
--! Dependencies:\n
--!
--! References:\n
--!
--! Modified by:\n
--! Author:
-------------------------------------------------------------------------------
--! \n\nLast changes:\n
-------------------------------------------------------------------------------
--! @todo \n
--! \n
--
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY top_extphy IS
GENERIC(
NUM_DUTS : positive := 3;
NUM_TRIG_INPUTS : positive := 4
);
PORT(
busy_i : IN std_logic_vector (NUM_DUTS-1 DOWNTO 0);
cfd_discr_i : IN std_logic_vector (NUM_TRIG_INPUTS-1 DOWNTO 0);
dut_clk : IN std_logic_vector (NUM_DUTS-1 DOWNTO 0);
gmii_rx_clk_i : IN std_logic;
gmii_rx_dv_i : IN std_logic;
gmii_rx_er_i : IN std_logic;
gmii_rxd_i : IN std_logic_vector (7 DOWNTO 0);
sysclk_n_i : IN std_logic;
sysclk_p_i : IN std_logic; -- ! 200 MHz xtal clock
threshold_discr_i : IN std_logic_vector (NUM_TRIG_INPUTS-1 DOWNTO 0);
gmii_gtx_clk_o : OUT std_logic;
gmii_tx_en_o : OUT std_logic;
gmii_tx_er_o : OUT std_logic;
gmii_txd_o : OUT std_logic_vector (7 DOWNTO 0);
i2c_scl_o : OUT std_logic;
leds_o : OUT std_logic_vector (3 DOWNTO 0);
phy_rstb_o : OUT std_logic;
reset_or_clk_o : OUT std_logic_vector (NUM_DUTS-1 DOWNTO 0);
triggers_o : OUT std_logic_vector (NUM_DUTS-1 DOWNTO 0);
i2c_sda_d : INOUT std_logic
);
-- Declarations
END ENTITY top_extphy ;
--
ARCHITECTURE rtl OF top_extphy IS
BEGIN
END ARCHITECTURE rtl;
top_extphy_struct.vhd 0000664 0000000 0000000 00000076303 12415504633 0034322 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl -- VHDL Entity work.top_extphy.symbol
--
-- Created:
-- by - phdgc.users (fortis.phy.bris.ac.uk)
-- at - 16:06:33 01/24/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2012.2b (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY top_extphy IS
GENERIC(
g_NUM_DUTS : positive := 3;
g_NUM_TRIG_INPUTS : positive := 4;
g_NUM_EXT_SLAVES : positive := 11; --! Number of slaves outside IPBus interface
g_EVENT_DATA_WIDTH : positive := 64;
g_IPBUS_WIDTH : positive := 32;
g_NUM_EDGE_INPUTS : positive := 4;
g_SPILL_COUNTER_WIDTH : positive := 12
);
PORT(
busy_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
busy_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Busy lines from DUTs ( active high )
cfd_discr_n_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
cfd_discr_p_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
dip_switch_i : IN std_logic_vector (3 DOWNTO 0);
gmii_rx_clk_i : IN std_logic;
gmii_rx_dv_i : IN std_logic;
gmii_rx_er_i : IN std_logic;
gmii_rxd_i : IN std_logic_vector (7 DOWNTO 0);
sysclk_n_i : IN std_logic; --! 200 MHz xtal clock
sysclk_p_i : IN std_logic;
threshold_discr_n_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
threshold_discr_p_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
reset_i : IN std_logic;
gmii_gtx_clk_o : OUT std_logic;
gmii_tx_en_o : OUT std_logic;
gmii_tx_er_o : OUT std_logic;
gmii_txd_o : OUT std_logic_vector (7 DOWNTO 0);
gpio_hdr : OUT std_logic_vector (7 DOWNTO 0);
leds_o : OUT std_logic_vector (3 DOWNTO 0);
phy_rstb_o : OUT std_logic;
dut_clk_n_o : INOUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
dut_clk_p_o : INOUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
reset_or_clk_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
reset_or_clk_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
triggers_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
triggers_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Trigger lines to DUT
extclk_n_b : INOUT std_logic;
extclk_p_b : INOUT std_logic; --! either external clock in, or a clock being driven out
i2c_scl_b : INOUT std_logic;
i2c_sda_b : INOUT std_logic
);
-- Declarations
END ENTITY top_extphy ;
--=============================================================================
--! @file top_extphy_struct.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL -- VHDL Architecture work.top_extphy.struct
--
--! @brief \n
--! \n
--
--! @author David Cussans , David.Cussans@bristol.ac.uk ( phdgc.users (fortis.phy.bris.ac.uk))
--
--! @date 16:18:26 01/24/14
--
--! @version v0.1
--
--! @details
--!
--!
--! Dependencies:\n
--!
--! References:\n
--!
--! Modified by:\n
--! Author:
-------------------------------------------------------------------------------
--! \n\nLast changes:\n
-------------------------------------------------------------------------------
--! @todo \n
--! \n
--
--------------------------------------------------------------------------------
--
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2012.2b (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY work;
USE work.ipbus.all;
USE work.emac_hostbus_decl.all;
USE work.fmcTLU.all;
LIBRARY unisim;
USE unisim.vcomponents.all;
ARCHITECTURE struct OF top_extphy IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL buffer_full_o : std_logic; --! Goes high when event buffer almost full
SIGNAL clk_16x_logic : std_logic; -- 640MHz clock
SIGNAL clk_4x_logic : std_logic; --! normally 160MHz
SIGNAL clk_logic_xtal : std_logic; -- ! 40MHz clock from onboard xtal
SIGNAL s_DUT_clk : std_logic; -- ! Clock to DUT
SIGNAL data_strobe : std_logic; -- goes high when data ready to load into event buffer
SIGNAL edge_fall_i : std_logic_vector(g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when falling edge
SIGNAL edge_fall_time_i : t_triggerTimeArray(g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
SIGNAL edge_rise_i : std_logic_vector(g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when rising edge
SIGNAL edge_rise_time_i : t_triggerTimeArray(g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
SIGNAL event_data : std_logic_vector(g_EVENT_DATA_WIDTH-1 DOWNTO 0);
SIGNAL event_number_o : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0); -- starts at one. Increments for each post_veto_trigger
SIGNAL ipbr : ipb_rbus_array(g_NUM_EXT_SLAVES-1 DOWNTO 0); --! IPBus read signals
SIGNAL ipbus_clk : std_logic;
SIGNAL ipbus_reset : std_logic;
SIGNAL ipbus_rst : std_logic; -- ! IPBus reset to slaves
SIGNAL ipbw : ipb_wbus_array(g_NUM_EXT_SLAVES-1 DOWNTO 0); --! IBus write signals
SIGNAL logic_clocks_reset : std_logic; -- Goes high to reset counters etc. Sync with clk_4x_logic
SIGNAL logic_reset : std_logic; -- Goes high to reset counters etc. Sync with clk_4x_logic
SIGNAL overall_trigger : std_logic; --! goes high to load trigger data
SIGNAL overall_veto : std_logic; --! Halts triggers when high
SIGNAL postVeto_trigger_times : t_triggerTimeArray(g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- ! trigger arrival time ( w.r.t. logic_strobe)
SIGNAL s_rst_buffer : std_logic;
SIGNAL s_AIDAhandshake : std_logic;
SIGNAL s_i2c_scl_enb : std_logic;
SIGNAL s_i2c_sda_enb : std_logic;
SIGNAL shutter_cnt_i : std_logic_vector(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0);
SIGNAL shutter_i : std_logic;
SIGNAL spill_cnt_i : std_logic_vector(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0);
SIGNAL spill_i : std_logic;
SIGNAL strobe_16x_logic : std_logic; --! Pulses one cycle every 4 of 16x clock.
SIGNAL strobe_4x_logic : std_logic; -- one pulse every 4 cycles of clk_4x
SIGNAL trigger_cnt_i : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0);
SIGNAL trigger_count : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0);
SIGNAL trigger_times : t_triggerTimeArray(g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- ! trigger arrival time ( w.r.t. logic_strobe)
SIGNAL triggers : std_logic_vector(g_NUM_TRIG_INPUTS-1 DOWNTO 0);
SIGNAL postVeto_triggers : std_logic_vector(g_NUM_TRIG_INPUTS-1 DOWNTO 0);
SIGNAL veto_o : std_logic; --! goes high when one or more DUT are busy
SIGNAL s_Trig_TO_DUT : std_logic;
SIGNAL s_rst_or_clk_to_dut: std_logic;
-- Component Declarations
COMPONENT DUTInterfaces
GENERIC (
g_NUM_DUTS : positive := 3;
g_IPBUS_WIDTH : positive := 32
);
PORT (
busy_from_dut_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
busy_from_dut_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
clk_4x_logic_i : IN std_logic ;
ipbus_clk_i : IN std_logic ;
ipbus_i : IN ipb_wbus ; -- Signals from IPBus core TO slave
ipbus_reset_i : IN std_logic ;
strobe_4x_logic_i : IN std_logic ; -- ! goes high every 4th clock cycle
--trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);
trigger_i : IN std_logic ; -- goes high when trigger logic issues a trigger
clk_to_dut_i : IN std_logic ; -- ! clock to DUT
reset_or_clk_to_dut_i : IN std_logic ; -- ! Either reset line or trigger
AIDAhandshake_i : IN std_logic ; -- AIDA/EUDET
ipbus_o : OUT ipb_rbus ; -- signals from slave TO IPBus core
clk_to_dut_n_o : INOUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
clk_to_dut_p_o : INOUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
reset_or_clk_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
reset_or_clk_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
trigger_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
trigger_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
veto_o : OUT std_logic -- goes high when one or more DUT are busy
);
END COMPONENT DUTInterfaces;
COMPONENT IPBusInterface
GENERIC (
NUM_EXT_SLAVES : positive := 5
);
PORT (
gmii_rx_clk_i : IN std_logic ;
gmii_rx_dv_i : IN std_logic ;
gmii_rx_er_i : IN std_logic ;
gmii_rxd_i : IN std_logic_vector (7 DOWNTO 0);
ipbr_i : IN ipb_rbus_array (NUM_EXT_SLAVES-1 DOWNTO 0); -- ! IPBus read signals
sysclk_n_i : IN std_logic ;
sysclk_p_i : IN std_logic ; -- ! 200 MHz xtal clock
clocks_locked_o : OUT std_logic ;
gmii_gtx_clk_o : OUT std_logic ;
gmii_tx_en_o : OUT std_logic ;
gmii_tx_er_o : OUT std_logic ;
gmii_txd_o : OUT std_logic_vector (7 DOWNTO 0);
ipb_clk_o : OUT std_logic ; -- ! IPBus clock TO slaves
ipb_rst_o : OUT std_logic ; -- ! IPBus reset TO slaves
ipbw_o : OUT ipb_wbus_array (NUM_EXT_SLAVES-1 DOWNTO 0); -- ! IBus write signals
onehz_o : OUT std_logic ;
phy_rstb_o : OUT std_logic ;
dip_switch_i : IN std_logic_vector (3 DOWNTO 0);
clk_logic_xtal_o : OUT std_logic
);
END COMPONENT IPBusInterface;
COMPONENT eventBuffer
GENERIC (
g_EVENT_DATA_WIDTH : positive := 64;
g_IPBUS_WIDTH : positive := 32;
g_WRITE_COUNTER_WIDTH : positive := 15;
g_READ_COUNTER_WIDTH : positive := 16
);
PORT (
clk_4x_logic_i : IN std_logic ;
data_strobe_i : IN std_logic ; -- Indicates data TO transfer
event_data_i : IN std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
ipbus_clk_i : IN std_logic ;
ipbus_i : IN ipb_wbus ;
ipbus_reset_i : IN std_logic ;
strobe_4x_logic_i : IN std_logic ;
--trigger_count_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not used yet.
rst_fifo_o : OUT std_logic; --! rst signal to first level fifos
buffer_full_o : OUT std_logic ; --! Goes high when event buffer almost full
ipbus_o : OUT ipb_rbus ;
logic_reset_i : IN std_logic -- reset buffers when high. Synch withclk_4x_logic
);
END COMPONENT eventBuffer;
COMPONENT eventFormatter
GENERIC (
g_EVENT_DATA_WIDTH : positive := 64;
g_IPBUS_WIDTH : positive := 32;
g_COUNTER_TRIG_WIDTH : positive := 32;
g_COUNTER_WIDTH : positive := 12;
g_EVTTYPE_WIDTH : positive := 4; -- Width of the event type word
--g_NUM_INPUT_TYPES : positive := 4; -- Number of different input types (trigger, shutter, edge...)
g_NUM_EDGE_INPUTS : positive := 4; -- Number of edge inputs
g_NUM_TRIG_INPUTS : positive := 5 -- Number of trigger inputs
);
PORT (
clk_4x_logic_i : IN std_logic ; -- ! Rising edge active
ipbus_clk_i : IN std_logic ;
logic_strobe_i : IN std_logic ; -- ! Pulses high once every 4 cycles of clk_4x_logic
logic_reset_i : IN std_logic ; -- goes high TO reset counters. Synchronous with clk_4x_logic
rst_fifo_i : IN std_logic; --! Reset fifos
buffer_full_i : IN std_logic; -- Buffer full signal from main buffer
trigger_i : IN std_logic ; --! goes high TO load trigger data. One cycle of clk_4x_logic
trigger_times_i : IN t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- Array of trigger times ( w.r.t. logic_strobe)
trigger_inputs_fired_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- high for each input that "fired"
trigger_cnt_i : IN std_logic_vector (g_COUNTER_TRIG_WIDTH-1 DOWNTO 0);
shutter_i : IN std_logic ;
shutter_cnt_i : IN std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
spill_i : IN std_logic ;
spill_cnt_i : IN std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
edge_rise_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when rising edge
edge_fall_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when falling edge
edge_rise_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
edge_fall_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
ipbus_i : IN ipb_wbus ;
ipbus_o : OUT ipb_rbus ;
data_strobe_o : OUT std_logic ; -- goes high when data ready TO load into event buffer
event_data_o : OUT std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
event_number_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);
trigger_count_o : OUT std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0)
);
END COMPONENT eventFormatter;
COMPONENT i2c_master
PORT (
i2c_scl_i : IN std_logic ;
i2c_sda_i : IN std_logic ;
ipbus_clk_i : IN std_logic ;
ipbus_i : IN ipb_wbus ; -- Signals from IPBus core TO slave
ipbus_reset_i : IN std_logic ;
i2c_scl_enb_o : OUT std_logic ;
i2c_sda_enb_o : OUT std_logic ;
ipbus_o : OUT ipb_rbus -- signals from slave TO IPBus core
);
END COMPONENT i2c_master;
COMPONENT logic_clocks
PORT (
ipbus_clk_i : IN std_logic ;
ipbus_i : IN ipb_wbus ;
ipbus_reset_i : IN std_logic ;
Reset_i : IN std_logic ;
clk_logic_xtal_i : IN std_logic ; -- ! 40MHz clock from onboard xtal
clk_16x_logic_o : OUT std_logic ; -- 640MHz clock
clk_4x_logic_o : OUT std_logic ; -- 160MHz clock
ipbus_o : OUT ipb_rbus ;
strobe_16x_logic_o : OUT std_logic ; -- strobes once every 4 cycles of clk_16x
strobe_4x_logic_o : OUT std_logic ; -- one pulse every 4 cycles of clk_4x
extclk_p_b : INOUT std_logic ; -- either external clock in, or a clock being driven out
extclk_n_b : INOUT std_logic ;
DUT_clk_o : OUT std_logic ;
logic_clocks_locked_o : OUT std_logic ;
logic_reset_o : OUT std_logic -- Goes high TO reset counters etc. Sync with clk_4x_logic
);
END COMPONENT logic_clocks;
COMPONENT triggerInputs
GENERIC (
g_NUM_INPUTS : natural := 1
);
PORT (
cfd_discr_p_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);
cfd_discr_n_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);
clk_4x_logic : IN std_logic ; -- ! Rising edge active
strobe_4x_logic_i : IN std_logic ; -- ! Pulses high once every 4 cycles of clk_4x_logic
threshold_discr_p_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! inputs from threshold comparators
threshold_discr_n_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! inputs from threshold comparators
reset_i : IN std_logic;
trigger_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); -- ! trigger arrival time ( w.r.t. logic_strobe)
trigger_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when trigger active
trigger_debug_o : OUT std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0); -- ! Copy of input trigger level. High bits CFD, Low threshold
edge_rising_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); -- ! edge arrival time ( w.r.t. logic_strobe)
edge_falling_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); -- ! edge arrival time ( w.r.t. logic_strobe)
edge_rising_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when rising edge
edge_falling_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when falling edge
ipbus_clk_i : IN std_logic ;
ipbus_reset_i : IN std_logic ;
ipbus_i : IN ipb_wbus ; -- Signals from IPBus core TO slave
ipbus_o : OUT ipb_rbus ; -- signals from slave TO IPBus core
clk_16x_logic_i : IN std_logic ; --! 640MHz clock ( 16x 40MHz )
strobe_16x_logic_i : IN std_logic --! Pulses one cycle every 4 of 16x clock.
);
END COMPONENT triggerInputs;
COMPONENT triggerLogic
GENERIC (
g_NUM_INPUTS : positive := 4;
g_IPBUS_WIDTH : positive := 32
);
PORT (
clk_4x_logic_i : IN std_logic ; -- ! Rising edge active
ipbus_clk_i : IN std_logic ;
ipbus_i : IN ipb_wbus ; -- Signals from IPBus core TO slave
ipbus_reset_i : IN std_logic ;
logic_reset_i : IN std_logic ; -- active high. Synchronous with clk_4x_logic
logic_strobe_i : IN std_logic ; -- ! Pulses high once every 4 cycles of clk_4x_logic
trigger_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when trigger from input connector active
trigger_times_i : IN t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! trigger arrival time
veto_i : IN std_logic ; -- ! Halts triggers when high
trigger_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when trigger from input connector active and input enabled
trigger_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! trigger arrival time
event_number_o : OUT std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); -- starts at one. Increments for each post_veto_trigger
ipbus_o : OUT ipb_rbus ; -- signals from slave TO IPBus core
post_veto_trigger_o : OUT std_logic ; -- ! goes high when trigger passes
pre_veto_trigger_o : OUT std_logic ;
trigger_active_o : OUT std_logic --! Goes high when triggers are active ( ie. not veoted)
);
END COMPONENT triggerLogic;
COMPONENT handshakes
GENERIC(
g_IPBUS_WIDTH : positive := 32
);
PORT(
clk_i : IN std_logic;
Trigger_i : IN std_logic;
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus;
ipbus_reset_i : IN std_logic;
ipbus_o : OUT ipb_rbus;
logic_reset_i : IN std_logic; -- reset buffers when high. Synch withclk_4x_logic
Busy_i : IN std_logic;
AIDAhandshake_o : OUT std_logic; -- running an AIDA handshake or the old EUDET handshake
Trigger_o : OUT std_logic;
rst_or_clk_o : OUT std_logic
);
END COMPONENT handshakes;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : DUTInterfaces USE ENTITY work.DUTInterfaces;
FOR ALL : IPBusInterface USE ENTITY work.IPBusInterface;
FOR ALL : eventBuffer USE ENTITY work.eventBuffer;
FOR ALL : eventFormatter USE ENTITY work.eventFormatter;
FOR ALL : i2c_master USE ENTITY work.i2c_master;
FOR ALL : logic_clocks USE ENTITY work.logic_clocks;
FOR ALL : triggerInputs USE ENTITY work.triggerInputs;
FOR ALL : triggerLogic USE ENTITY work.triggerLogic;
FOR ALL : handshakes USE ENTITY work.handshakes;
-- pragma synthesis_on
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 1 i2c_tristate
-- eb1 1
i2c_scl_b <= '0' when (s_i2c_scl_enb = '0') else 'Z';
i2c_sda_b <= '0' when (s_i2c_sda_enb = '0') else 'Z';
-- ModuleWare code(v1.12) for instance 'I9' of 'gnd'
logic_clocks_reset <= '0';
-- ModuleWare code(v1.12) for instance 'I10' of 'gnd'
--trigger_cnt_i <= (OTHERS => '0');
trigger_cnt_i <= event_number_o;
-- ModuleWare code(v1.12) for instance 'I11' of 'gnd'
spill_i <= '0';
-- ModuleWare code(v1.12) for instance 'I12' of 'gnd'
spill_cnt_i <= (OTHERS => '0');
-- ModuleWare code(v1.12) for instance 'I13' of 'gnd'
shutter_i <= '0';
-- ModuleWare code(v1.12) for instance 'I14' of 'gnd'
shutter_cnt_i <= (OTHERS => '0');
-- ModuleWare code(v1.12) for instance 'I8' of 'sor'
overall_veto <= buffer_full_o; -- OR veto_o;
-- Instance port mappings.
I0 : DUTInterfaces
GENERIC MAP (
g_NUM_DUTS => g_NUM_DUTS,
g_IPBUS_WIDTH => g_IPBUS_WIDTH
)
PORT MAP (
busy_from_dut_n_i => busy_n_i,
busy_from_dut_p_i => busy_p_i,
clk_4x_logic_i => clk_4x_logic,
ipbus_clk_i => ipbus_clk,
ipbus_i => ipbw(0),
ipbus_reset_i => ipbus_reset,
strobe_4x_logic_i => strobe_4x_logic,
--trigger_counter_i => trigger_count,
clk_to_dut_i => s_DUT_clk,
trigger_i => s_Trig_TO_DUT, --overall_trigger,
reset_or_clk_to_dut_i => s_rst_or_clk_to_dut,
AIDAhandshake_i => s_AIDAhandshake, -- RJ45 DUT clock as output/input (1/0)
ipbus_o => ipbr(0),
clk_to_dut_n_o => dut_clk_n_o,
clk_to_dut_p_o => dut_clk_p_o,
reset_or_clk_to_dut_n_o => reset_or_clk_n_o,
reset_or_clk_to_dut_p_o => reset_or_clk_p_o,
trigger_to_dut_n_o => triggers_n_o,
trigger_to_dut_p_o => triggers_p_o,
veto_o => veto_o
);
I4 : IPBusInterface
GENERIC MAP (
NUM_EXT_SLAVES => g_NUM_EXT_SLAVES
)
PORT MAP (
gmii_rx_clk_i => gmii_rx_clk_i,
gmii_rx_dv_i => gmii_rx_dv_i,
gmii_rx_er_i => gmii_rx_er_i,
gmii_rxd_i => gmii_rxd_i,
ipbr_i => ipbr,
sysclk_n_i => sysclk_n_i,
sysclk_p_i => sysclk_p_i,
clocks_locked_o => leds_o(2),
gmii_gtx_clk_o => gmii_gtx_clk_o,
gmii_tx_en_o => gmii_tx_en_o,
gmii_tx_er_o => gmii_tx_er_o,
gmii_txd_o => gmii_txd_o,
ipb_clk_o => ipbus_clk,
ipb_rst_o => ipbus_rst,
ipbw_o => ipbw,
onehz_o => leds_o(3),
phy_rstb_o => phy_rstb_o,
dip_switch_i => dip_switch_i,
clk_logic_xtal_o => clk_logic_xtal
);
I5 : eventBuffer
GENERIC MAP (
g_EVENT_DATA_WIDTH => g_EVENT_DATA_WIDTH,
g_IPBUS_WIDTH => g_IPBUS_WIDTH,
g_WRITE_COUNTER_WIDTH => 15,
g_READ_COUNTER_WIDTH => 16
)
PORT MAP (
clk_4x_logic_i => clk_4x_logic,
data_strobe_i => data_strobe,
event_data_i => event_data,
ipbus_clk_i => ipbus_clk,
ipbus_i => ipbw(3),
ipbus_reset_i => ipbus_reset,
strobe_4x_logic_i => strobe_4x_logic,
--trigger_count_i => trigger_count,
rst_fifo_o => s_rst_buffer,
buffer_full_o => buffer_full_o,
ipbus_o => ipbr(3),
logic_reset_i => logic_reset or reset_i
);
I2 : eventFormatter
GENERIC MAP (
g_EVENT_DATA_WIDTH => g_EVENT_DATA_WIDTH,
g_IPBUS_WIDTH => g_IPBUS_WIDTH,
g_COUNTER_TRIG_WIDTH => g_IPBUS_WIDTH,
g_COUNTER_WIDTH => 12,
g_EVTTYPE_WIDTH => 4, -- Width of the event type word
--g_NUM_INPUT_TYPES : positive := 4; -- Number of different input types (trigger, shutter, edge...)
g_NUM_EDGE_INPUTS => g_NUM_EDGE_INPUTS, -- Number of edge inputs
g_NUM_TRIG_INPUTS => g_NUM_TRIG_INPUTS -- Number of trigger inputs
)
PORT MAP (
clk_4x_logic_i => clk_4x_logic,
ipbus_clk_i => ipbus_clk,
logic_strobe_i => strobe_4x_logic,
logic_reset_i => logic_reset or reset_i,
rst_fifo_i => s_rst_buffer,
buffer_full_i => buffer_full_o,
trigger_i => overall_trigger,
trigger_times_i => postVeto_trigger_times,
trigger_inputs_fired_i => postVeto_triggers,
trigger_cnt_i => trigger_cnt_i,
shutter_i => shutter_i,
shutter_cnt_i => shutter_cnt_i,
spill_i => spill_i,
spill_cnt_i => spill_cnt_i,
edge_rise_i => edge_rise_i,
edge_fall_i => edge_fall_i,
edge_rise_time_i => edge_rise_time_i,
edge_fall_time_i => edge_fall_time_i,
ipbus_i => ipbw(9),
ipbus_o => ipbr(9),
data_strobe_o => data_strobe,
event_data_o => event_data,
event_number_i => event_number_o,
trigger_count_o => trigger_count
);
I7 : i2c_master
PORT MAP (
i2c_scl_i => i2c_scl_b,
i2c_sda_i => i2c_sda_b,
ipbus_clk_i => ipbus_clk,
ipbus_i => ipbw(5),
ipbus_reset_i => ipbus_reset,
i2c_scl_enb_o => s_i2c_scl_enb,
i2c_sda_enb_o => s_i2c_sda_enb,
ipbus_o => ipbr(5)
);
I6 : logic_clocks
PORT MAP (
ipbus_clk_i => ipbus_clk,
ipbus_i => ipbw(4),
ipbus_reset_i => ipbus_reset,
Reset_i => logic_clocks_reset,
clk_logic_xtal_i => clk_logic_xtal,
clk_16x_logic_o => clk_16x_logic,
clk_4x_logic_o => clk_4x_logic,
ipbus_o => ipbr(4),
strobe_16x_logic_o => strobe_16x_logic,
strobe_4x_logic_o => strobe_4x_logic,
extclk_p_b => extclk_p_b,
extclk_n_b => extclk_n_b,
DUT_clk_o => s_DUT_clk,
logic_clocks_locked_o => leds_o(1),
logic_reset_o => logic_reset
);
I1 : triggerInputs
GENERIC MAP (
g_NUM_INPUTS => g_NUM_TRIG_INPUTS
)
PORT MAP (
cfd_discr_p_i => cfd_discr_p_i,
cfd_discr_n_i => cfd_discr_n_i,
clk_4x_logic => clk_4x_logic,
strobe_4x_logic_i => strobe_4x_logic,
threshold_discr_p_i => threshold_discr_p_i,
threshold_discr_n_i => threshold_discr_n_i,
reset_i => reset_i,
trigger_times_o => trigger_times,
trigger_o => triggers,
trigger_debug_o => gpio_hdr,
edge_rising_times_o => OPEN,
edge_falling_times_o => OPEN,
edge_rising_o => OPEN,
edge_falling_o => OPEN,
ipbus_clk_i => ipbus_clk,
ipbus_reset_i => ipbus_reset,
ipbus_i => ipbw(1),
ipbus_o => ipbr(1),
clk_16x_logic_i => clk_16x_logic,
strobe_16x_logic_i => strobe_16x_logic
);
I3 : triggerLogic
GENERIC MAP (
g_NUM_INPUTS => g_NUM_TRIG_INPUTS,
g_IPBUS_WIDTH => g_IPBUS_WIDTH
)
PORT MAP (
clk_4x_logic_i => clk_4x_logic,
ipbus_clk_i => ipbus_clk,
ipbus_i => ipbw(2),
ipbus_reset_i => ipbus_reset,
logic_reset_i => logic_reset or reset_i,
logic_strobe_i => strobe_4x_logic,
trigger_i => triggers,
trigger_times_i => trigger_times,
veto_i => overall_veto,
trigger_o => postVeto_triggers,
trigger_times_o => postVeto_trigger_times,
event_number_o => event_number_o,
ipbus_o => ipbr(2),
post_veto_trigger_o => overall_trigger,
pre_veto_trigger_o => OPEN,
trigger_active_o => leds_o(0)
);
I8 : handshakes
GENERIC MAP(
g_IPBUS_WIDTH => g_IPBUS_WIDTH
)
PORT MAP(
clk_i => s_DUT_clk,
Trigger_i => overall_trigger,
ipbus_clk_i => ipbus_clk,
ipbus_i => ipbw(10),
ipbus_reset_i => ipbus_reset,
ipbus_o => ipbr(10),
logic_reset_i => logic_reset or reset_i,
Busy_i => veto_o,
AIDAhandshake_o => s_AIDAhandshake,
Trigger_o => s_Trig_TO_DUT,
rst_or_clk_o => s_rst_or_clk_to_dut
);
END ARCHITECTURE struct;
fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/transactor.vhd.rlnk0000664 0000000 0000000 00000000173 12415504633 0033707 0 ustar 00root root 0000000 0000000 /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/transactor.vhd transactor_rx.vhd.rlnk 0000664 0000000 0000000 00000000176 12415504633 0034344 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/transactor_rx.vhd transactor_sm.vhd.rlnk 0000664 0000000 0000000 00000000176 12415504633 0034332 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/transactor_sm.vhd transactor_tx.vhd.rlnk 0000664 0000000 0000000 00000000176 12415504633 0034346 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/transactor_tx.vhd triggerInputs_rtl.vhd.rlnk 0000664 0000000 0000000 00000000077 12415504633 0035202 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd triggerLogic_rtl.vhd.rlnk 0000664 0000000 0000000 00000000076 12415504633 0034754 0 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl /tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/udp_shim.vhd.rlnk 0000664 0000000 0000000 00000000171 12415504633 0033335 0 ustar 00root root 0000000 0000000 /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/udp_shim.vhd fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/ 0000775 0000000 0000000 00000000000 12415504633 0030065 5 ustar 00root root 0000000 0000000 fmc-mtlu-copy_ADosil_branch_r156/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.cache.dat 0000664 0000000 0000000 00000103500 12415504633 0031677 0 ustar 00root root 0000000 0000000 HDS library cache 2012.2b (Build 5) work S emac_hostbus_decl.vhd.rlnk P^ S
VHDL_TEXT - eth_s6_1000basex.vhd.rlnk P^
VHDL_TEXT - eth_s6_gmii.vhd.rlnk P^
VHDL_TEXT - mac_arbiter.vhd.rlnk P^
VHDL_TEXT - mac_arbiter_decl.vhd.rlnk P^
VHDL_TEXT - i2c_master_top.vhd.rlnk R ء 3
VHDL_TEXT - arp.v.rlnk Pe
VERILOG_TEXT - bus_arb.vhd.rlnk Pe
VHDL_TEXT - gbe_rxpacketbuffer.v.rlnk Pe O
VERILOG_TEXT - ipbus_v_defs.v Pe gbe_txpacketbuffer.v.rlnk Pe g
VERILOG_TEXT - ipbus_v_defs.v Pe icmp.v.rlnk Pe 4
VERILOG_TEXT - ip_checksum_8bit.v.rlnk Pe
VERILOG_TEXT - ipbus_bus_decl.vhd.rlnk Pe
VHDL_TEXT - ipbus_ctrl.vhd.rlnk Pe
VHDL_TEXT - ipbus_ctrl_decl.vhd.rlnk Pe
VHDL_TEXT - ipbus_ctrl_udponly.vhd.rlnk Pe X
VHDL_TEXT - ipbus_fabric.vhd.rlnk Pe Y
VHDL_TEXT - ipbus_package.vhd.rlnk Pe i
VHDL_TEXT - ipbus_v_defs.v.rlnk Pe 1
VERILOG_TEXT - packet_handler.v.rlnk Pe
VERILOG_TEXT - ipbus_v_defs.v Pe sub_packetbuffer.v.rlnk Pe
VERILOG_TEXT - ipbus_v_defs.v Pe sub_packetreq.v.rlnk Pe ~
VERILOG_TEXT - ipbus_v_defs.v Pe sub_packetresp.v.rlnk Pe
VERILOG_TEXT - ipbus_v_defs.v Pe transactor.vhd.rlnk Pe
VHDL_TEXT - transactor_rx.vhd.rlnk Pe /
VHDL_TEXT - transactor_sm.vhd.rlnk Pe
VHDL_TEXT - transactor_tx.vhd.rlnk Pe
VHDL_TEXT - udp_shim.vhd.rlnk Pe W
VHDL_TEXT - @d@u@t@interfaces/rtl.bd P}~ 2 BLOCK_DIAGRAM - DUTInterfaces_rtl.vhd PZ @d@u@t@interfaces/symbol.sb Q SYMBOL - @i@p@bus@interface/rtl.bd P} h BLOCK_DIAGRAM - IPBusInterface_rtl.vhd P[ @i@p@bus@interface/symbol.sb P- SYMBOL - DUTInterfaces_rtl.vhd Q r
VHDL_TEXT - IPBusInterface_rtl.vhd Q
VHDL_TEXT - arp/fsm.sm P}~ B STATE_MACHINE - s/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/arp.v Pe arp/struct.bd P} BLOCK_DIAGRAM - s/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/arp.v Pe arrival@time@l@u@t/symbol.sb P gD SYMBOL - arrivalTimeLUT_rtl.vhd Q 1)
VHDL_TEXT - clocks_s6_extphy.vhd PĿ
VHDL_TEXT - clocks_s6_extphy/rtl.bd P}~ BLOCK_DIAGRAM - clocks_s6_extphy.vhd P2 dual@s@e@r@d@e@s_1to4/symbol.sb P [ SYMBOL - dualSERDES_1to4_rtl.vhd Q]^ 10
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VHDL_TEXT - eventFormatter_rtl.vhd Q IM
VHDL_TEXT - fmcTLU_pkg.vhd P H
VHDL_TEXT - fmcTLU_pkg_body.vhd P
VHDL_TEXT - gbe_rxpacketbuffer/struct.bd P} . BLOCK_DIAGRAM - /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/gbe_rxpacketbuffer.v Pe ipbus_v_defs.v gbe_txpacketbuffer/struct.bd P} ǥ BLOCK_DIAGRAM - /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/gbe_txpacketbuffer.v Pe ipbus_v_defs.v i2c_master/symbol.sb Qe Z SYMBOL - i2c_master_rtl.vhd R
VHDL_TEXT - i2c_master_top/symbol.sb P w SYMBOL - icmp/struct.bd P} BLOCK_DIAGRAM - t/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/icmp.v Pe ipbus_addr_decode.vhd Q]^
VHDL_TEXT - ipbus_ctrl_udponly/rtl.bd P} BLOCK_DIAGRAM - /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/ipbus_ctrl_udponly.vhd Pe ipbus_emac_hostbus.vhd P<