In the older, EUDET, version of the \gls{tlu} the direction of the signals on the \verb|HDMI*| connectors were pre-defined. The new hardware has the ability to switch each \gls{lvds} pair between input and output.\\
The function and direction of each \gls{lvds} pair depends on the interface mode chosen. Table \ref{tab:DUTInterfaceModes} lists the different interface modes and section~\ref{sec:InterfaceModes} describes them in more detail. See chapter~\ref{ch:hwDUT} for details of how \gls{lvds} pairs are mapped onto physical \gls{hdmi} pins.
The function and direction of each \gls{lvds} pair depends on the interface mode chosen. Section~\ref{sec:InterfaceModes} describes the different interface modes in more detail. See chapter~\ref{ch:hwDUT} for details of how \gls{lvds} pairs are mapped onto physical \gls{hdmi} pins.
%separate lines for signals going into the \gls{tlu} and signals out of the \gls{tlu}. See section~\ref{ch:hw\gls{dut}} for further details. \\
There are four different handshake modes, described below:
When operating within the AIDA2020 scope, the \gls{tlu} can be operated in one of four different handshake modes, described in the remaining of this chapter.
\subsection{Trigger/Busy (EUDET) Mode}
This mode is designed to allow the \gls{tlu} and \gls{dut} clocks to be asynchronous and to have any frequency relationship.\\
After the \gls{tlu} detects an input trigger, the TRIGGER signal to the \gls{dut} is asserted and the \gls{tlu} vetoes further triggers.\\
The \gls{dut} responds by asserting the BUSY line to the \gls{tlu}.
...
...
@@ -20,17 +19,18 @@ When the \gls{tlu} detects that the BUSY has been de-asserted it re-enables trig
Figure \ref{fig:eudet-trigger-busy} shows signal timing for this interface mode.
\subsection{Trigger/Busy Handshake With Trigger Number}
This interface mode is an extension of the Trigger/Busy handshake.\\
After the \gls{dut} detects that the \gls{tlu} has de-asserted the TRIGGER line it can cause the \gls{tlu} to clock out the current trigger number by toggling the DUT-Clock line. Figure ~\ref{fig:eudet-trigger-busy-trignumber} shows the signal timing for this interface mode.
After the \gls{dut} detects that the \gls{tlu} has de-asserted the TRIGGER line it can cause the \gls{tlu} to clock out the current trigger number by toggling the \gls{dut} clock line. The number is clocked \gls{lsb} first.\\
Figure~\ref{fig:eudet-trigger-busy-trignumber} shows the signal timing for this interface mode.
\caption{Trigger/Busy Interface Mode With Trigger Number }
\label{fig:eudet-trigger-busy-trignumber}
\end{figure}
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...
@@ -38,20 +38,22 @@ After the \gls{dut} detects that the \gls{tlu} has de-asserted the TRIGGER line
\subsection{Synchronous (AIDA) Mode}
In synchronous mode (also known as AIDA mode) the \gls{tlu} sends a clock (by default 40MHz) to the \gls{dut}.\\
When the \gls{tlu} produces a trigger, the trigger line from \gls{tlu} to \gls{dut} is asserted for one cycle of the clock. In order to synchronize time-stamps between \gls{tlu} to \gls{dut} a single cycle timestamp reset signal is issued at the start of each run.\\
The \gls{dut} can veto triggers at any point by asserting the BUSY line. Figure~\ref{fig:aida-handshake} shows the signal timing for this interface mode.
The \gls{dut} can veto triggers at any point by asserting the BUSY line.\\
Figure~\ref{fig:aida-handshake} shows the signal timing for this interface mode.
This is a modification of the synchronous/AIDA mode.\\
Immediately after the \gls{tlu} issues a trigger, it clocks out the trigger number (\gls{lsb} first) on the Sync/T0 line. Figure~\ref{fig:aida-handshake-with-trigger} shows the signal timing for this interface mode.
Immediately after the \gls{tlu} issues a trigger, it clocks out the trigger number (\gls{lsb} first) on the Sync/T0 line.\\
Figure~\ref{fig:aida-handshake-with-trigger} shows the signal timing for this interface mode.
The six inputs on the \gls{tlu} can be used to generate a global trigger that is then issued to all the \gls{dut}s.\\
Each input has a programmable voltage discriminator that can be configured in the range [-1.3 : 1.3]~V.\\
Each input has a programmable voltage discriminator that can be configured in the range [-1.3 : +1.3]~V.\\
All the inputs are protected by clamping diodes that limit the input voltage in the range [-5 : +5]~V.\\
The discriminators are followed by edge-finding and TDC logic. Currently only negative edges are registered. A future firmware version will implement user-selectable positive or negative edge detection.\\
The discriminators are followed by edge-finding and \gls{tdc} logic. Currently only negative edges are registered. A future firmware version will implement user-selectable positive or negative edge detection.\\
The output of the edge finding logic is fed into logic to stretch and delay the pulses by a controllable amount. The stretched and delayed trigger pulses are fed into a look-up table that generates the triggers. Figure~\ref{fig:aida-tlu-trigger-path} illustrates the path of the trigger signals through the \gls{tlu}.
The TLU has six trigger inputs than can be used to generate a valid trigger event. The number of possible different trigger combinations is $2^6=64$ so a 64-bit word can be used to decide the valid combinations. In the hardware the 64-bit word is split into two 32-bit words (indicated as \gls{msb} and \gls{lsb} word) and the rules to generate the trigger can be specified by the user by writing in the two 32-bit registers \verb|TriggerPattern_highW| and \verb|TriggerPattern_lowW|: the first stores the 32 most significative bits of the trigger word, the latter stores the least significative bits.\\
The user can select any combination of the trigger inputs and declare it a valid trigger pattern by setting a 1 in the corresponding trigger configuration word.
The \gls{tlu} has six trigger inputs than can be used to generate a valid trigger event. The number of possible different trigger combinations is $2^6=64$ so a 64-bit word can be used to decide the valid combinations. In the hardware the 64-bit word is split into two 32-bit words (indicated as \gls{msb} and \gls{lsb} word) and the rules to generate the trigger can be specified by the user by writing in the two 32-bit IPBus registers \verb|TriggerPattern_highW| and \verb|TriggerPattern_lowW|: the first stores the 32 most significative bits of the trigger word, the latter stores the least significative bits.\\
The user can select any combination of the trigger inputs and declare it a valid trigger pattern by setting a 1 in the corresponding trigger configuration word. Multiple 1s indicate that the corresponding patterns are OR-ed.\\
Tables~\ref{tab:trigconfigLow} and ~\ref{tab:trigconfigHigh} show an example of how to determine the trigger configuration words: whenever a valid trigger combination is encountered, the user should put a 1 in the corresponding row under the PATTERN column. The pattern thus obtained is the required word to write in the configuration register.\\
It is important to note that this solution allows the user to set veto pattern as well: for instance if only word 31 from table~\ref{tab:trigconfigLow} were picked, then the \gls{tlu} would only register a trigger when the combination $\overline{I_{5}}$ * $I_{4}$ * $I_{3}$ * $I_{2}$ * $I_{1}$ * $I_{0}$ was presented at its inputs. In other words, in this specific case $I_{5}$ would act as a veto signal and the \gls{tlu} would \textbf{not} produce a global trigger if $I_{5}$=1.
% Please add the following required packages to your document preamble:
% \usepackage{multirow}
\begin{table}[]
\centering
\caption{Example of configuration word for the least significative bits of the trigger registers: the only valid configuration is represented by $\overline{I_{5}}$ + $I_{4}$ + $I_{3}$ + $I_{2}$ + $I_{1}$ + $I_{0}$, i.e. a trigger is accepted if all the inputs, except $I_{5}$, present a logic 1 at the same time. The user would then write the resulting word 0x80000000 in the TriggerPattern\_lowW register.}
\caption{Example of configuration word for the least significative bits of the trigger registers: the only valid configuration is represented by $\overline{I_{5}}$ + $I_{4}$ + $I_{3}$ + $I_{2}$ + $I_{1}$ + $I_{0}$, i.e. a trigger is accepted if all the inputs, except $I_{5}$, present a logic 1 at the same time. The user would then write the resulting word 0x80000000 in the TriggerPattern\_lowW register.}
\label{tab:trigconfigLow}
\end{table}
\begin{table}[]
\centering
\caption{Example of the most significative word of the register: a valid trigger is obtained when the inputs show the same configuration as row DEC 36, 37, 38, 39, 41, 43 and 63. These configuration are in logic OR with that presented in table~\ref{tab:trigconfigLow}. The resulting configuration word is 0x80000AF0.}
\caption{Example of the most significative word of the register: a valid trigger is obtained when the inputs show the same configuration as row DEC 36, 37, 38, 39, 41, 43 and 63. These configuration are in logic OR with that presented in table~\ref{tab:trigconfigLow}. The resulting configuration word is 0x80000AF0.}
\label{tab:trigconfigHigh}
\end{table}
\noindent The default configuration in the firmware is Hi=~0xFFFFFFFF, Low=~0xFFFEFFFE, which means that as long as any trigger input fires, a trigger will be generated. These words are loaded in the \gls{fpga} every time a new image is programmed.\\
\begin{alertinfo}{Trigger logic definition}
The user should pay attention to what trigger logic they want to define in order to avoid confusion in the data.\\
A ``1'' in the logic table means that the corresponding input must be active to produce a valid trigger. Similarly, a ``0'' indicates that the corresponding input must be inactive (i.e. is a veto, not an ignore). Any change in input configuration will cause the logic to re-assess the trigger status. The following section gives a brief example.\\
A ``1'' in the logic table means that the corresponding input must be active to produce a valid trigger. Similarly, a ``0'' indicates that the corresponding input must be inactive (i.e. is a veto, not an ignore). Any change in input configuration will cause the logic to re-assess the trigger status.\\ Section~\ref{{ch:trigexamples}} provides a few examples.\\
\end{alertinfo}
\begin{alertinfo}{Bit 0 meaning}
A 1 in the lowest bit of the \gls{lsb} word indicates that $\overline{I_{5}}$ * $\overline{I_{4}}$ * $\overline{I_{3}}$ * $\overline{I_{2}}$ * $\overline{I_{1}}$ * $\overline{I_{0}}$ is a valid trigger combination, so the \gls{tlu} will produce a trigger when all the inputs are inactive (i.e. even if all the inputs are unplugged). Apart from very specific cases, this is generally not a desired behaviour.
A 1 in the lowest bit of the \gls{lsb} word indicates that $\overline{I_{5}}$ * $\overline{I_{4}}$ * $\overline{I_{3}}$ * $\overline{I_{2}}$ * $\overline{I_{1}}$ * $\overline{I_{0}}$ is a valid trigger combination, so the \gls{tlu} will produce a trigger when all the inputs are inactive (i.e. even if all the inputs are unplugged).\\
Except for a few very specific cases, this is generally not a desirable behaviour.
A lightweight script is available to help configuring the \gls{tlu} trigger.\\
The file can be found in the:\\
\verb|./Documentation/Misc|\\
folder of the \gls{ohwr} documentation repository (\href{https://ohwr.org/project/fmc-mtlu}{AIDA-2020 TLU}).\\
The script is written in Python 3.x and it should be possible to run it in stand-alone mode on any machine by simply using the command\\
\verb|Python trigger_configuration_helper|\\
This will create an interactive sell; when started, the shell will ask a series of questions to the user and then generates the two 32-bit words that need to be written in the trigger registers.\\
This will create an interactive shell; when started, the shell will ask a series of questions to the user and then generates the two 32-bit words that need to be written in the trigger registers.\\
The script is only meant to be a quick and simple way to generate the configuration words without having to dwell too much in the details provided in section~\ref{ch:triggerLogic}. This means that it can only offer a limited set of configurations that should, nonetheless, be enough for most of the user cases.\\
To take advantage of the full flexibility of the \gls{tlu} trigger and generate more advanced configurations (such as mutually excluding trigger inputs) the user should refer to section~\ref{ch:triggerLogic}.\\
To use the script:
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@@ -145,7 +144,7 @@ To use the script:
It is up to the user to program the \gls{tlu} with those values, in whichever method is preferred (EUDAQ, Python scripts, etc).
\end{alertinfo}
\subsubsection{Example of trigger configurations}
\subsubsection{Example of trigger configurations}\label{ch:trigexamples}
In this example we have connected a pulse generator to two inputs of the \gls{tlu}, namely \verb|IN_1| and \verb|IN_5|. The inputs fire with a small, random delay with respect to each other.\\
In order to ensure that the signals overlap adequately, we use the \emph{stretch} register (see chapter~\ref{ch:triggerLogic}) to increase the length of the pulses: we extend \emph{in0} to 10 clock cycles and \emph{in4} to 8 clock cycles, where the clock has a frequency of 160~MHz. The resulting signals are shown in figure~\ref{Fig:exampleExtendedTriggers}.
