Commit 1f56dbe4 authored by Paolo Baesso's avatar Paolo Baesso

Tidying up

parent d7cf5ec9
\chapter{DUT Signals}\label{ch:DUTsignals} \chapter{DUT Signals}\label{ch:DUTsignals}
In the older, EUDET, version of the \gls{tlu} the direction of the signals on the \verb|HDMI*| connectors were pre-defined. The new hardware has the ability to switch each \gls{lvds} pair between input and output.\\ In the older, EUDET, version of the \gls{tlu} the direction of the signals on the \verb|HDMI*| connectors were pre-defined. The new hardware has the ability to switch each \gls{lvds} pair between input and output.\\
The function and direction of each \gls{lvds} pair depends on the interface mode chosen. Section~\ref{sec:InterfaceModes} describes the different interface modes in more detail. See chapter~\ref{ch:hwDUT} for details of how \gls{lvds} pairs are mapped onto physical \gls{hdmi} pins. The function and direction of each \gls{lvds} pair depends on the interface mode chosen.\\
Section~\ref{sec:InterfaceModes} describes the different interface modes in more detail. See chapter~\ref{ch:hwDUT} for details of how \gls{lvds} pairs are mapped onto physical \gls{hdmi} pins.
%separate lines for signals going into the \gls{tlu} and signals out of the \gls{tlu}. See section~\ref{ch:hw\gls{dut}} for further details. \\ %separate lines for signals going into the \gls{tlu} and signals out of the \gls{tlu}. See section~\ref{ch:hw\gls{dut}} for further details. \\
......
...@@ -75,7 +75,8 @@ At the moment of shipping, each \gls{tlu} is pre-configured with the most recent ...@@ -75,7 +75,8 @@ At the moment of shipping, each \gls{tlu} is pre-configured with the most recent
\begin{enumerate} \begin{enumerate}
\item Ensure no \gls{usb} cable is plugged in the unit \item Ensure no \gls{usb} cable is plugged in the unit
\item Power the unit. The pre-configured firmware will automatically load. \item Power the unit. The pre-configured firmware will automatically load.
\item Plug an Ethernet cable in the RJ45 socket located on the back panel and connect it to the computer used to run the control software. Note that currently the unit uses a pre-defined IP address of 192.168.200.30. In future version of the firmware the address will be configurable. Try to ping the IP address of the unit: if the unit responds then the firmware is correctly loaded. \item Plug an Ethernet cable in the RJ45 socket located on the back panel and connect it to the computer used to run the control software. The socket is labeled \verb|IPBus| on figure~\ref{fig:tabletop} and figure~\ref{fig:rackmountpanels}.\\
Note that currently the unit uses a pre-defined IP address of 192.168.200.30. In future version of the firmware the address will be configurable. Try to ping the IP address of the unit: if the unit responds then the firmware is correctly loaded.
\item Use the control software to configure the unit. In particular, after each power up it is necessary to re-configure the clock chip. See chapter~\ref{ch:controlsw} for details on the software and chapter~\ref{ch:clock} for details on the clock chip. \item Use the control software to configure the unit. In particular, after each power up it is necessary to re-configure the clock chip. See chapter~\ref{ch:controlsw} for details on the software and chapter~\ref{ch:clock} for details on the clock chip.
\end{enumerate} \end{enumerate}
\begin{alertinfo}{Communication with the \gls{tlu}} \begin{alertinfo}{Communication with the \gls{tlu}}
...@@ -160,6 +161,7 @@ The same procedure can be repeated with the front frame, if necessary. In this c ...@@ -160,6 +161,7 @@ The same procedure can be repeated with the front frame, if necessary. In this c
\label{fig:dismantle} \label{fig:dismantle}
\end{figure} \end{figure}
\newpage
\section{Inspection (19"-rack unit)} \section{Inspection (19"-rack unit)}
Accessing the hardware on the 19"-unit is straightforward: simply remove the four M2.5 screws located on the top panel and slide the panel back. Please note that this unit has an internal AC-DC converter that can potentially store an harmful amount of energy even when powered-off and disconnected from the mains: always use care when accessing the unit. Accessing the hardware on the 19"-unit is straightforward: simply remove the four M2.5 screws located on the top panel and slide the panel back. Please note that this unit has an internal AC-DC converter that can potentially store an harmful amount of energy even when powered-off and disconnected from the mains: always use care when accessing the unit.
\begin{alertinfo}{Danger} \begin{alertinfo}{Danger}
......
\chapter{Clock}\label{ch:clock} \chapter{Clock}\label{ch:clock}
The \gls{tlu} can use various sources to produce a stable 40~MHz clock\footnote{For some applications a 50~MHz clock will be required instead}.\\ The \gls{tlu} can use various sources to produce a stable 40~MHz clock as required in the AIDA-2020 application\footnote{For some applications a 50~MHz clock will be required instead}.\\
A \gls{lvpecl} crystal provides the reference 50~MHz clock for a Si5345A jitter attenuator. The Si5345A can accept up to four clock sources and use them to generate the required output clocks.\\ The board hosts a high performance jitter attenuator/cleaner chip, the Si5345A.\\
In \brd the possible sources are: differential LEMO connector LM1\_9, one of the four \gls{hdmi} connectors (\verb|HDMI4|), a \gls{cdr} chip connected to the \gls{sfp} cage. The fourht input is used to provide a zero-delay feedback loop.\\ A \gls{lvpecl} crystal provides a reference 50~MHz clock for the Si5345A. In conjunction with the reference clock, the Si5345A can accept up to four clock sources and use them to generate the required output clocks distributed to the various \gls{dut}s.\\
In \brd the possible sources are: differential LEMO connector LM1\_9, one of the four \gls{hdmi} connectors (\verb|HDMI4|), a \gls{cdr} chip connected to the \gls{sfp} cage. The fourth input is used to provide a zero-delay feedback loop.\\
The low-jitter clock generated by the Si5345A can be distributed to up to ten recipients. In the \gls{tlu} these are: the four \gls{dut}s via \gls{hdmi} connectors, the differential LEMO cable, the \gls{fpga}, connector J1 as a differential pair (pins 4 and 6) and as a single ended signal (pin 8). The final output is connected to the zero-delay feedback loop. Note that it is possible to program the clock chip to generate a different frequency for each of its outputs.\\ The low-jitter clock generated by the Si5345A can be distributed to up to ten recipients. In the \gls{tlu} these are: the four \gls{dut}s via \gls{hdmi} connectors, the differential LEMO cable, the \gls{fpga}, connector J1 as a differential pair (pins 4 and 6) and as a single ended signal (pin 8). The final output is connected to the zero-delay feedback loop. Note that it is possible to program the clock chip to generate a different frequency for each of its outputs.\\
The \gls{dut}s can receive the clock either from the Si5435A or directly from the \gls{fpga}: when provided by the clock generator, the signal name is \verb|CLK\_TO\_DUT| and is enabled by signal \verb|ENABLE_CLK_TO_DUT|; when the signal is provided directly from the \gls{fpga} the line used is \verb|DUT_CLK_FROM_FPGA| and is enabled by \verb|ENABLE_DUT_CLK_FROM_FPGA|.\\ The \gls{dut}s can receive the clock either from the Si5435A or directly from the \gls{fpga}: when provided by the clock generator, the signal name is \verb|CLK\_TO\_DUT| and is enabled by signal \verb|ENABLE_CLK_TO_DUT|; when the signal is provided directly from the \gls{fpga} the line used is \verb|DUT_CLK_FROM_FPGA| and is enabled by \verb|ENABLE_DUT_CLK_FROM_FPGA|.\\
The firmware uses the clock generated by the Si5345A except for the block \verb|enclustra_ax3_pm3_infra| which relies on a crystal mounted on the Enclustra board to provide the IPBus functionalities (in this way, at power up the board can communicate via IPBus even if the Si5345A is not configured). The firmware uses the clock generated by the Si5345A except for the block \verb|enclustra_ax3_pm3_infra| which relies on a crystal mounted on the Enclustra board to provide the IPBus functionalities (in this way, at power up the board can communicate via IPBus even if the Si5345A is not configured).
\section{Input selection} \section{Input selection}
The Si5345 has four inputs that can be selected to provide the clock alignment; the selection can be automatic or user-defined. For further details on this aspect the user should consult the \href{https://www.silabs.com/documents/public/data-sheets/Si5345-44-42-D-DataSheet.pdf}{chip documentation}\footnote{https://www.silabs.com/documents/public/data-sheets/Si5345-44-42-D-DataSheet.pdf}. The Si5345A has four inputs that can be selected to provide the clock alignment; the selection can be automatic or user-defined. For further details on this aspect the user should consult the \href{https://www.silabs.com/documents/public/data-sheets/Si5345-44-42-D-DataSheet.pdf}{chip documentation}\footnote{https://www.silabs.com/documents/public/data-sheets/Si5345-44-42-D-DataSheet.pdf}.
\begin{table}[] \begin{table}[]
\small \small
...@@ -25,4 +26,4 @@ IN\_SEL & 0x052A {[}2:1{]} & \begin{tabular}[ ...@@ -25,4 +26,4 @@ IN\_SEL & 0x052A {[}2:1{]} & \begin{tabular}[
\section{Logic clocks registers}\label{ch:logicClock} \section{Logic clocks registers}\label{ch:logicClock}
LogicClocksCSR: in the new TLU the selection of the clock source is done by programming the Si5345. As a consequence, there is no reason to write to this register. Reading it back returns the status of the PLL on bit 0, so this should read 0x1. LogicClocksCSR: in the new TLU the selection of the clock source is done by programming the Si5345A. As a consequence, there is no reason to write to this register. Reading it back returns the status of the PLL on bit 0, so this should read 0x1.
\ No newline at end of file \ No newline at end of file
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment