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AIDA-2020 TLU
Commit 246fb335 authored by Alvaro Dosil's avatar Alvaro Dosil
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Created edge signals from lemo inputs

parent 98e89c3d
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Showing with 196 additions and 99 deletions
firmware/hdl/common/eventFormatter_rtl.vhd
View file @ 246fb335
......@@ -67,7 +67,7 @@ ENTITY eventFormatter IS
ipbus_clk_i : IN std_logic;
logic_strobe_i : IN std_logic; -- ! Pulses high once every 4 cycles of clk_4x_logic
logic_reset_i : IN std_logic; -- goes high to reset counters. Synchronous with clk_4x_logic
rst_fifo_i : IN std_logic; --! Reset fifos
rst_fifo_i : IN std_logic; --! Reset fifos
buffer_full_i : IN std_logic; -- Buffer full signal from main buffer
trigger_i : IN std_logic; --! goes high to load trigger data. One cycle of clk_4x_logic
......@@ -81,10 +81,12 @@ ENTITY eventFormatter IS
spill_i : IN std_logic;
spill_cnt_i : IN std_logic_vector(g_COUNTER_WIDTH-1 DOWNTO 0);
edge_rise_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when rising edge
edge_fall_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when falling edge
edge_rise_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
edge_fall_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
edge_rise_i : IN std_logic; -- ! High when at least one rising edge from input connector active and enabled
edge_fall_i : IN std_logic; -- ! High when at least one falling edge from input connector active and enabled
edges_rise_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when rising edge
edges_fall_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when falling edge
edge_rise_time_i : IN std_logic_vector(c_NUM_TIME_BITS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
edge_fall_time_i : IN std_logic_vector(c_NUM_TIME_BITS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
ipbus_i : IN ipb_wbus;
ipbus_o : OUT ipb_rbus;
......@@ -167,7 +169,8 @@ ARCHITECTURE rtl OF eventFormatter IS
signal s_enable_trigger : std_logic := '1'; -- Enable trigger record
signal s_enable_shutter : std_logic := '1'; -- Enable shutter record
signal s_enable_spill : std_logic := '1'; -- Enable spill record
signal s_enable_edges : std_logic_vector(g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- Enable edges record
--signal s_enable_edges : std_logic_vector(g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- Enable edges record
signal s_enable_edges : std_logic := '1'; -- Enable edges record
BEGIN
......@@ -213,7 +216,7 @@ BEGIN
s_enable_trigger <= s_enable_record(0);
s_enable_shutter <= s_enable_record(1);
s_enable_spill <= s_enable_record(2);
s_enable_edges <= s_enable_record(g_NUM_EDGE_INPUTS-1+3 downto 3);
s_enable_edges <= s_enable_record(3);
end if;
end process p_signals_clk_domain;
......@@ -337,48 +340,58 @@ BEGIN
(others=>'0');
s_var(1) <= shutter_cnt_i;
edge_formatting : for i in 0 to (g_NUM_EDGE_INPUTS-1) generate
s_evttype(i+2) <= "0101" when edge_rise_i(i) = '1' else
"0100" when edge_fall_i(i) = '1' else
(others=>'0');
s_var(i+2) <= std_logic_vector(to_unsigned(i,4)) & "000" & edge_rise_time_i(i) when edge_rise_i(i) = '1' else
std_logic_vector(to_unsigned(i,4)) & "000" & edge_fall_time_i(i) when edge_fall_i(i) = '1' else
(others=>'0');
end generate;
-- edge_formatting : for i in 0 to (g_NUM_EDGE_INPUTS-1) generate
-- s_evttype(i+2) <= "0101" when edge_rise_i = '1' else
-- "0100" when edge_fall_i = '1' else
-- (others=>'0');
-- s_var(i+2) <= std_logic_vector(to_unsigned(i,4)) & "000" & edge_rise_time_i(i) when edge_rise_i = '1' else
-- std_logic_vector(to_unsigned(i,4)) & "000" & edge_fall_time_i(i) when edge_fall_i = '1' else
-- (others=>'0');
-- end generate;
-- s_evttype(3+g_NUM_EDGE_INPUTS-1) <= "0111" when spill_i_d1 = '1' and spill_i_d2 = '0' else
-- "0110" when spill_i_d1 = '0' and spill_i_d2 = '1' else
-- (others=>'0');
-- s_var(3+g_NUM_EDGE_INPUTS-1) <= spill_cnt_i;
-- Edges
s_evttype(2) <= "0101" when edge_rise_i = '1' else
"0100" when edge_fall_i = '1' else
(others=>'0');
s_var(2) <= edges_rise_i & "000" & edge_rise_time_i when edge_rise_i = '1' else
edges_fall_i & "000" & edge_fall_time_i when edge_fall_i = '1' else
(others=>'0');
s_evttype(3+g_NUM_EDGE_INPUTS-1) <= "0111" when spill_i_d1 = '1' and spill_i_d2 = '0' else
"0110" when spill_i_d1 = '0' and spill_i_d2 = '1' else
(others=>'0');
s_var(3+g_NUM_EDGE_INPUTS-1) <= spill_cnt_i;
-- Spill
s_evttype(3) <= "0111" when spill_i_d1 = '1' and spill_i_d2 = '0' else
"0110" when spill_i_d1 = '0' and spill_i_d2 = '1' else
(others=>'0');
s_var(3) <= spill_cnt_i;
p_fifo_wr : process (clk_4x_logic_i)
p_fifo_shutter_wr : process (clk_4x_logic_i)
begin
if rising_edge(clk_4x_logic_i) then
s_FIFO_wr(1) <= shutter_i_d1 xor shutter_i_d2;
s_FIFO_wr(3+g_NUM_EDGE_INPUTS-1) <= spill_i_d1 xor spill_i_d2;
s_FIFO_wr(3) <= spill_i_d1 xor spill_i_d2;
s_FIFO_wr(2) <= (edge_rise_i or edge_fall_i) and s_enable_edges and not s_FIFO_full(2);
end if;
end process;
gen_fifo_wr_edge : for i in 0 to (g_NUM_EDGE_INPUTS-1) generate
p_fifo_wr : process (clk_4x_logic_i)
begin
if rising_edge(clk_4x_logic_i) then
s_FIFO_wr(i+2) <= (edge_rise_i(i) or edge_fall_i(i)) and s_enable_edges(i) and not s_FIFO_full(i+2);
end if;
end process;
end generate;
gen_FIFO_i : for i in 1 to 3+g_NUM_EDGE_INPUTS-1 generate
gen_FIFO_data : for i in 1 to 3 generate
begin
p_fifo_i_n : process (clk_4x_logic_i)
begin
if rising_edge(clk_4x_logic_i) then
s_FIFO_i(i) <= s_evttype(i) & s_var(i) & std_logic_vector(s_coarse_timestamp_h_d2) & std_logic_vector(s_coarse_timestamp_l_d2);
end if;
end process;
end generate gen_FIFO_i;
end generate;
-------------------------------------------------------------------------------
......
firmware/hdl/common/triggerLogic_rtl.vhd
View file @ 246fb335
This diff is collapsed.
firmware/scripts/aida_mini_tlu_addr_map.txt
View file @ 246fb335
......@@ -39,6 +39,7 @@ TriggerVetoW 0x00000064 0xffffffff 0 1
ORW 0x00000066 0xffffffff 0 1
ANDW 0x00000067 0xffffffff 0 1
StrechFormatW 0x00000068 0xffffffff 0 1
EdgeMaskW 0x00000069 0xffffffff 0 1
PostVetoTriggersR 0x00000070 0xffffffff 1 0
PreVetoTriggersR 0x00000071 0xffffffff 1 0
InternalTriggerIntervalR 0x00000072 0xffffffff 1 0
......@@ -48,6 +49,7 @@ ExternalTriggerVetoR 0x00000075 0xffffffff 1 0
ORR 0x00000076 0xffffffff 1 0
ANDR 0x00000077 0xffffffff 1 0
StrechFormatR 0x00000078 0xffffffff 1 0
EdgeMaskR 0x00000079 0xffffffff 1 0
*
* event buffer = 0x080
EventFifoData 0x00000080 0xffffffff 1 0
......
firmware/scripts/aida_mini_tlu_addr_map.txt~
View file @ 246fb335
......@@ -68,26 +68,6 @@ i2c_rx 0x000000C3 0x000000ff 1 0
i2c_cmd 0x000000C4 0x000000ff 0 1
i2c_status 0x000000C4 0x000000ff 1 0
*
* shutter generator = 0x100
ShutterLength 0x00000100 0xffffffff 1 1
ShutStartupDeadTime 0x00000101 0xffffffff 1 1
ShutInterpulseDeadTime 0x00000102 0xffffffff 1 1
ShutterDelay 0x00000103 0xffffffff 1 1
NMaxShutters 0x00000104 0xffffffff 1 1
ShutEvtNumber 0x00000105 0xffffffff 1 0
RstShutterCounter 0x00000106 0xffffffff 1 1
ShutRearmDeadTime 0x00000107 0xffffffff 1 1
*
* spill generator = 0x120
SpillLength 0x00000120 0xffffffff 1 1
SpillStartupDeadTime 0x00000121 0xffffffff 1 1
SpillInterpulseDeadTime 0x00000122 0xffffffff 1 1
SpillDelay 0x00000123 0xffffffff 1 1
NMaxSpills 0x00000124 0xffffffff 1 1
SpillEvtNumber 0x00000125 0xffffffff 1 0
RstSpillCounter 0x00000126 0xffffffff 1 1
SpillRearmDeadTime 0x00000127 0xffffffff 1 1
*
* Event formatter = 0x140
Enable_Record_Data 0x00000140 0xffffffff 1 1
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