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AIDA-2020 TLU
Commit 350d8df5 authored by Paolo Baesso's avatar Paolo Baesso
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Added option to ignore the BUSY signal from a DUT in both AIDA and EUDET mode.… 

Added option to ignore the BUSY signal from a DUT in both AIDA and EUDET mode. Needs some more testing in the lab
parent 82b60d18
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Showing with 14 additions and 6 deletions
.gitignore
View file @ 350d8df5
...@@ -7,11 +7,14 @@ ...@@ -7,11 +7,14 @@
/Data/* /Data/*
*.pyc *.pyc
.svn/* .svn/*
*.jou
*.str
## Backup files ## Backup files
*.py~ *.py~
*.md~ *.md~
*.sh~ *.sh~
*.*~
## Core latex/pdflatex auxiliary files: ## Core latex/pdflatex auxiliary files:
*.aux *.aux
......
TLU_v1e/hdl/dut/DUTInterface_AIDA_rtl.vhd
View file @ 350d8df5
...@@ -135,8 +135,11 @@ BEGIN ...@@ -135,8 +135,11 @@ BEGIN
s_strobe_4x_logic_d1 <= strobe_4x_logic_i; s_strobe_4x_logic_d1 <= strobe_4x_logic_i;
--busy_o <= ((not ignore_shutter_veto_i ) and (not shutter_to_dut_i)) or
-- ((dut_busy_i and DUT_mask_i ) and (not ignore_dut_busy_i) );
busy_o <= ((not ignore_shutter_veto_i ) and (not shutter_to_dut_i)) or busy_o <= ((not ignore_shutter_veto_i ) and (not shutter_to_dut_i)) or
((dut_busy_i and DUT_mask_i ) and (not ignore_dut_busy_i) ); ( (dut_busy_i and DUT_mask_i ) );
dut_clk_o <= s_dut_clk ; dut_clk_o <= s_dut_clk ;
dut_trigger_o <= DUT_mask_i and s_trigger_out; dut_trigger_o <= DUT_mask_i and s_trigger_out;
......
TLU_v1e/hdl/dut/DUTInterface_EUDET_rtl.vhd
View file @ 350d8df5
...@@ -62,6 +62,7 @@ architecture rtl of DUTInterface_EUDET is ...@@ -62,6 +62,7 @@ architecture rtl of DUTInterface_EUDET is
signal shift_reg_ce : std_logic; signal shift_reg_ce : std_logic;
signal dut_busy_r1 , dut_busy_r2 , dut_clk_r1 , dut_clk_r2 : std_logic; -- ! registered values signal dut_busy_r1 , dut_busy_r2 , dut_clk_r1 , dut_clk_r2 : std_logic; -- ! registered values
signal trigger_counter_copy : std_logic_vector(g_TRIGGER_DATA_WIDTH-1 downto 0); --! registered copy of event number
begin -- rtl begin -- rtl
...@@ -114,7 +115,7 @@ end process; ...@@ -114,7 +115,7 @@ end process;
-- type : combinational -- type : combinational
-- inputs : system_clk_i , trigger_counter_i -- inputs : system_clk_i , trigger_counter_i
-- outputs: serial_trig_data -- outputs: serial_trig_data
trig_data_driver: process (system_clk_i , trigger_counter_i , shift_reg_ce , trig_shift_reg , state) trig_data_driver: process (system_clk_i , trigger_counter_copy , shift_reg_ce , trig_shift_reg , state)
begin begin
if rising_edge( system_clk_i ) then if rising_edge( system_clk_i ) then
...@@ -131,7 +132,7 @@ end process; ...@@ -131,7 +132,7 @@ end process;
elsif (state = WAIT_FOR_BUSY_HIGH ) then elsif (state = WAIT_FOR_BUSY_HIGH ) then
-- only clock out bottom 15 bits of data. -- only clock out bottom 15 bits of data.
-- (replace fixed width with a mask at some stage ?) -- (replace fixed width with a mask at some stage ?)
trig_shift_reg <= "00000000000000000" & trigger_counter_i(14 downto 0); trig_shift_reg <= "00000000000000000" & trigger_counter_copy(14 downto 0);
serial_trig_data <= '0'; serial_trig_data <= '0';
end if; end if;
...@@ -150,6 +151,7 @@ end process; ...@@ -150,6 +151,7 @@ end process;
when IDLE => when IDLE =>
if ( trigger_i = '1') then -- respond to trigger going high if ( trigger_i = '1') then -- respond to trigger going high
next_state <= WAIT_FOR_BUSY_HIGH; -- wait for DUT to respond to busy next_state <= WAIT_FOR_BUSY_HIGH; -- wait for DUT to respond to busy
trigger_counter_copy <= trigger_counter_i; -- register the trigger number to shift it out
elsif ( (dut_clk_r2 = '1') and (enable_dut_veto_i = '1') ) then -- If DUT asserts DUT_CLK_I then veto triggers elsif ( (dut_clk_r2 = '1') and (enable_dut_veto_i = '1') ) then -- If DUT asserts DUT_CLK_I then veto triggers
next_state <= DUT_INITIATED_VETO; next_state <= DUT_INITIATED_VETO;
......
TLU_v1e/hdl/dut/DUTInterfaces_rtl.vhd
View file @ 350d8df5
...@@ -324,8 +324,8 @@ BEGIN ...@@ -324,8 +324,8 @@ BEGIN
s_DUT_aida_eudet_mode(dut) <= s_DUT_interface_mode(2*dut); s_DUT_aida_eudet_mode(dut) <= s_DUT_interface_mode(2*dut);
s_dut_enable_veto_eudet(dut) <= s_DUT_interface_mode_modifier(2*dut); s_dut_enable_veto_eudet(dut) <= s_DUT_interface_mode_modifier(2*dut);
-- Produce "OR" of veto/busy signals from DUTs -- Produce "OR" of veto/busy signals from DUTs, take into account IGNORE BUSY bit
s_intermediate_busy_or(dut+1) <= s_intermediate_busy_or(dut) or s_dut_veto(dut); s_intermediate_busy_or(dut+1) <= s_intermediate_busy_or(dut) or ( s_dut_veto(dut) and (not s_DUT_ignore_busy(dut) ) );
end generate dut_interfaces; end generate dut_interfaces;
......
TLU_v1e/hdl/top_enclustra_tlu_v1e.vhd
View file @ 350d8df5
...@@ -23,7 +23,7 @@ use work.ipbus.ALL; ...@@ -23,7 +23,7 @@ use work.ipbus.ALL;
entity top_tlu_v1e is entity top_tlu_v1e is
generic( generic(
constant FW_VERSION : unsigned(31 downto 0):= X"1e000007"; -- Firmware revision. Remember to change this as needed. constant FW_VERSION : unsigned(31 downto 0):= X"1e000008"; -- Firmware revision. Remember to change this as needed.
g_NUM_DUTS : positive := 4; -- <- was 3 g_NUM_DUTS : positive := 4; -- <- was 3
g_NUM_TRIG_INPUTS :positive := 6;-- <- was 4 g_NUM_TRIG_INPUTS :positive := 6;-- <- was 4
g_NUM_EDGE_INPUTS :positive := 6;-- <-- was 4 g_NUM_EDGE_INPUTS :positive := 6;-- <-- was 4
......
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