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AIDA-2020 TLU
Commit 9cecc3db authored by Paolo Baesso's avatar Paolo Baesso Committed by GitHub
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Merge pull request #15 from PaoloGB/documentation 

Documentation
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Documentation/Latex/AIDA_TLU_v1d.prj
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Main_TLU.tex
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*Main_TLU.tex
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*DUT_signals
*ch_TLU_triggerInputs
*ch_EventBuffer
*ch_TLU_Appendix
*ch_TLU_Functions
*ch_TLU_IPBusRegs
*ch_EUDAQParameters
*ch_EUDAQProducer
*ch_TLU_Appendix
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Documentation/Latex/Main_TLU.tex
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\usepackage{listings} %Include code
\usepackage{multirow}
\usepackage{datetime}
%\usepackage{svg}
\definecolor{infobackground}{RGB}{217,237,247}
\definecolor{infoforeground}{RGB}{58,135,173}
......@@ -180,10 +181,11 @@ Paolo Baesso - \monthname, \the\year\newline paolo.baesso@bristol.ac.uk
\include{DUT_signals}
\include{ch_TLU_triggerInputs}
\include{ch_EventBuffer}
\include{ch_TLU_Appendix}
\include{ch_TLU_Functions}
\include{ch_TLU_IPBusRegs}
\include{ch_EUDAQParameters}
\include{ch_EUDAQProducer}
\include{ch_TLU_Appendix}
%\begin{figure}[h]
% \centering
......
Documentation/Latex/ch_EUDAQParameters.tex
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......@@ -74,5 +74,5 @@ Not all parameters are needed; if one of the parameters is not present in the fi
\item[DUTIgnoreBusy] \verb|[unsigned int, 0xF]| This mask tells the \gls{tlu} to ignore the BUSY signal from a specific device, either in AIDA or EUDET mode. If the device is in AIDA mode, this means that further triggers will be issued while the device is busy. If the device is in EUDET mode, this means that the \gls{tlu} will not pause while they are in the handshake phase. In turn, this means that the device will likely receive events where the trigger number does not increase sequentially by one.
\item[DUTIgnoreShutterVeto] \verb|[unsigned int, 0x1]| Set bit to 1 to tell the \gls{dut} to ignore the shutter signal.
\item[EnableRecordData] \verb|[boolean, true]| if set to 1, enable the data recording in the \gls{tlu}.
\item[InternalTriggerInterval] \verb|[unsigned int, 0]| Defines the rate of the trigger generated internally by the \gls{tlu}: if 0, the internal triggers are disabled. Any other value produces internal triggers with a frequency of 160~MHz/value.
\item[InternalTriggerFreq] \verb|[unsigned int, 0]| Defines the rate of the trigger generated internally by the \gls{tlu}, in Hz: if 0, the internal triggers are disabled. Any other value activates the internal trigger generator with frequency equal to the parameter. Values above 160~MHz are coerced to 160~MHz.
\end{description}
\ No newline at end of file
Documentation/Latex/ch_EUDAQProducer.tex 0 → 100644
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\chapter{EUDAQ Producer}\label{ch:eudaqprod}
Current structure of a fmctlu producer event:
\lstset{language=XML}
\scriptsize
\begin{lstlisting}
<Event>
<Type>2149999981</Type>
<Extendword>171577627</Extendword>
<Description>Ex0Tg</Description>
<Flag>0x00000018</Flag>
<RunN>0</RunN>
<StreamN>0</StreamN>
<EventN>0</EventN>
<TriggerN>88</TriggerN>
<Timestamp>0x0000000000000000 -> 0x0000000000000000</Timestamp>
<Timestamp>0 -> 0</Timestamp>
<Block_Size>0</Block_Size>
<SubEvents>
<Size>1</Size>
<Event>
<Type>2149999981</Type>
<Extendword>3634980144</Extendword>
<Description>TluRawDataEvent</Description>
<Flag>0x00000010</Flag>
<RunN>96</RunN>
<StreamN>4008428646</StreamN>
<EventN>88</EventN>
<TriggerN>88</TriggerN>
<Timestamp>0x0000000105b44f91 -> 0x0000000105b44faa</Timestamp>
<Timestamp>4390670225 -> 4390670250</Timestamp>
<Tags>
<Tag>PARTICLES=89</Tag>
<Tag>SCALER0=93</Tag>
<Tag>SCALER1=93</Tag>
<Tag>SCALER2=0</Tag>
<Tag>SCALER3=0</Tag>
<Tag>SCALER4=0</Tag>
<Tag>SCALER5=0</Tag>
<Tag>TEST=110011</Tag>
<Tag>trigger=</Tag>
</Tags>
<Block_Size>0</Block_Size>
</Event>
</SubEvents>
</Event>
\end{lstlisting}
\normalsize
\begin{description}
\item[Type] ??
\item[ExtendWord] ??
\item[Description]
\item[Flag] Independent from producer. See the \href{https://github.com/eudaq/eudaq/blob/master/main/lib/core/include/eudaq/Event.hh#L87}{EUDAQ documentation} for details.
\item[RunN]
\item[StreamN]
\item[EventN]
\item[TriggerN] Both in the event and subevent this is written byt the producer with \verb|ev->SetTriggerN(trigger_n);|
\item[Timestamp] The event timestamp is currently always 0. The subevent timestamps is written by the producer \verb|ev->SetTimestamp(ts_ns, ts_ns+25, false);|. The top line (0x0000000105b44f91, in the example) is coarse time stamp multiplied by 25, so it represents the time in nanoseconds. The bottom one (4390670225) is the same number but written in decimal format instead of hexadecimal.
\item[PARTICLES] Number of pre-veto triggers recorded by the \gls{tlu}: the trigger logic can detect a valid trigger condition even when the unit is vetoed. In this case no trigger is issued to the \gls{dut}s but the number of such triggers is stored as number of particles. \verb|ev->SetTag("PARTICLES", std::to_string(pt));|
\item[SCALER\#] Number of triggers edges seen by the specific discriminator. \verb|ev->SetTag("SCALER", std::to_string(sl));|
\item[???] Event type from \gls{tlu} is missing?
\item[???] Input trig, i.e. the actual firing inputs should be in TRIGGER but there seems to be nothing there
\end{description}
Documentation/Latex/ch_EventBuffer.tex
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......@@ -10,3 +10,34 @@ Reading from \verb|EventFifoCSR| returns the following:
\item bit 4: \gls{fifo} programmable full flag
\item other bits: 0
\end{itemize}
The status register (SerdesRst) is as follows:
\begin{itemize}
\item bit 0: reset the ISERDES
\item bit 1: reset the trigger counters
\item bit 2: calibrate IDELAY: This seems to be disconnected at the moment.
\item bit 3: fixed to 0
\item bit 4, 5: status of \verb|thresholdDeserializer(Input0)|. When the IDELAY modules (prompt, delayed) have reached the correct delay, these two bits should read 00.
\item bit 6, 7: status of \verb|thresholdDeserializer(Input1)|
\item bit 8, 9: status of \verb|thresholdDeserializer(Input2)|
\item bit 10, 11: status of \verb|thresholdDeserializer(Input3)|
\item bit 12, 13: status of \verb|thresholdDeserializer(Input4)|
\item bit 14, 15: status of \verb|thresholdDeserializer(Input5)|
\item bit 16, 19: fixed to 0
\item bit 20: \verb|s_deserialized_threshold_data(Input0)(7)|
\item bit 21: \verb|s_deserialized_threshold_data(Input1)(7)|
\item bit 22: \verb|s_deserialized_threshold_data(Input2)(7)|
\item bit 23: \verb|s_deserialized_threshold_data(Input3)(7)|
\item bit 24: \verb|s_deserialized_threshold_data(Input4)(7)|
\item bit 25: \verb|s_deserialized_threshold_data(Input5)(7)|
\end{itemize}
9 bits are used to determine trigger edges. 8 are from the deserializers, 1 is added as the LSB and is the MSB from the previous word.
\begin{figure}
\centering
\includegraphics[width=.95\textwidth]{./Images/fifo_words.pdf}
\caption{Event structure}
\label{fig:fifo_event}
\end{figure}
Documentation/Latex/ch_TLU_Appendix.tex
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\chapter{Appendix}\label{ch:appendix}
\includepdf[link,pages={1}]{./Docs/PM3TopView.pdf}
\includepdf[link,pages=-, angle=90]{./Docs/Connections.pdf}
\ No newline at end of file
\includepdf[link,pages=-, angle=90]{./Docs/Connections.pdf}
\includepdf[link,pages=-, angle=90]{./Docs/schematics.pdf}
\ No newline at end of file
Documentation/Latex/ch_TLU_Hardware.tex
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......@@ -3,11 +3,11 @@ Board \brd is an evolution of the miniTLU designed at the \gls{uob}. The board s
\section{Inputs and interfaces}\label{ch:hwDUT}
\subsubsection{FMC}
The board must be plugged onto a \gls{fmc} carrier board with an \gls{fpga} in order to function correctly. The connection is achieved using a low pin count \gls{fmc} connector. The list of the pins used is provided in appendix at page~\pageref{ch:appendix}.\\
The board must be plugged onto a \gls{fmc} carrier board with an \gls{fpga} in order to function correctly. The connection is achieved using a low pin count \gls{fmc} connector. The list of the pins used and the corresponding signal within the \gls{fpga} are provided in appendix at page~\pageref{ch:appendix}.\\
\subsubsection{Device under test}\label{ch:dut}
The \gls{dut}s are connected to the \gls{tlu} using standard size \gls{hdmi} connectors\footnote{In the miniTLU hardware there were mini\gls{hdmi} connectors.}.\\
In this version of the hardware, up to four \gls{dut}s can be connected to the board. In this document the connectors will be referred to as \verb|HDMI1|, \verb|HDMI2|, \verb|HDMI3| and \verb|HDMI4|.\\
In the current version of the hardware, up to four \gls{dut}s can be connected to the board. In this document the connectors will be referred to as \verb|HDMI1|, \verb|HDMI2|, \verb|HDMI3| and \verb|HDMI4|.\\
The connectors expect 3.3~V \gls{lvds} signals and are bi-directional, i.e. any differential pair can be configured to be an output (signal from the TLU to the DUT) or an input (signals from the DUT to the TLU) by using half-duplex line transceivers. Figure~\ref{fig:LVDSTransceiver} illustrates how the differential pairs are connected to the transceivers.
\begin{alertinfo}{Note}
The input part of the transceiver is configured to be always on. This means that signals going \emph{into} the \gls{tlu} are always routed to the logic (\gls{fpga}). By contrast, the output transceivers have to be enabled and are off by default: signal sent from the logic to the \gls{dut}s cannot reach the devices unless the corresponding enable signal is active.
......@@ -47,9 +47,12 @@ The enable signals can be configured by programming two \gls{gpio} bus expanders
\centering
\includegraphics[width=.80\textwidth]{./Images/LVDS_transceiver.pdf}
\caption{Internal configuration of the HDMI pins for the DUTs. The path from the DUT to the FPGA is always active. The path from the FPGA to the DUT can be enabled or disabled by the user.}\label{fig:LVDSTransceiver}
\end{figure}
\end{figure}\\
In terms for functionalities, the four \gls{hdmi} connectors are identical with one exception: the clock signal from \verb|HDMI4| can be used as reference for the clock generator chip mounted on the hardware. For more details on this functionality refer to section~\ref{ch:clock}.
\subsubsection{SFP cage}
\brd hosts a \gls{sfp} cafe and a \gls{cdr} chip that can be used to decode a data stream over optical/copper interface. The data from the stream is routed to the \gls{fpga} while the clock can be fed to the Si5345 to provide a clock reference.
\section{Clock LEMO}
The board hosts a two-pin LEMO connector that can be used to provide a reference clock to the clock generator (see section~\ref{ch:clock}) or to output the clock from the \gls{tlu} to the external world, for instance to use it as a reference for another \gls{tlu}. The signal level is 3.3~V \gls{lvds}.\\
As for the differential pairs of the \gls{dut}s, the pins of this connector are wired to a transceiver configured to always accept the incoming signals. The outgoing direction must be enabled by using the \verb|ENABLE_CLK_TO_LEMO| signal, which can be configured using the bus expander described in in section~\ref{ch:i2c}.
......@@ -78,7 +81,8 @@ The correspondence between DAC slave and thresholds is shown in table~\ref{tab:D
\section{I$^{2}$C slaves}\label{ch:i2c}
The \gls{i2c} interface on the \brd can be used to configured several features of the board. Table~\ref{tab:I2C addresses} lists all the valid addresses and the corresponding slave on the board. The Enclustra lines refer to slaves located on the PM3 board; these slaves can be ignored with the exception of the bus expander. The Enclustra expander is used to enable/disable the \gls{i2c} lines going to the \gls{fmc} connector.
The \gls{i2c} interface on the \brd can be used to configured several features of the board.\\
Table~\ref{tab:I2C addresses} lists all the valid addresses and the corresponding slave on the board. The Enclustra lines refer to slaves located on the PM3 board; these slaves can be ignored with the exception of the bus expander. The Enclustra expander is used to enable/disable the \gls{i2c} lines going to the \gls{fmc} connector.
\begin{alertinfo}{Note}
After a power cycle the Enclustra expander is configured to disable the \gls{i2c} interface pins. This means that it is impossible to communicate to any \gls{i2c} slave on the \gls{tlu} until the expander has been enabled.\\
The interface is enable by setting bit 7 to 0 on register 0x01 of the Enclustra expander.
......@@ -95,7 +99,8 @@ The \gls{i2c} interface on the \brd can be used to configured several features o
IC5 & 24AA025E48T & EEPROM & 0x50 \\ \hline
IC6 & PCA9539PW & I2C Expander1 & 0x74 \\ \hline
IC7 & PCA9539PW & I2C Expander2 & 0x75 \\ \hline
IC8\_9 & Si5345A & Clock Generator & 0x68 \\ \hline
IC8 & ADN2814ACPZ & CDR & 0x60 \\ \hline
IC8\_9 & Si5345A & Clock Generator & 0x68 \\ \hline
\multicolumn{4}{|l|}{Enclustra slaves} \\ \hline
& & Enclustra Bus Expander & 0x21 \\ \hline
& & Enclustra System Monitor & 0x21 \\ \hline
......@@ -117,6 +122,9 @@ The identifier is always in the form: \verb|0xD8 80 39 XX XX XX| with the top th
\subsubsection{Bus expander}
The expanders are used as electronic switched to enable and disable individual lines. Each expander has two 8-bit banks; the values of the bits, as well as their direction (input/output) can be configured via the \gls{i2c} interface. For the purpose of the \gls{tlu}, all the expander pins should be configured as outputs since they must drive the enable signals on the \gls{dut} transceivers.
\subsubsection{Clock and data recovery chip}
The \gls{cdr} is used in conjunction with the \gls{sfp} cage to recover data and clock from the incoming bit stream. The functionality has not yet been implemented in the firmware so the \gls{i2c} slave can be ignored for now.
\subsubsection{Clock generator}
The clock for \brd can be generated using various external or internal references (see section~\ref{ch:clock} for further details). In order to reduce any jitter from the clock source and to provide a stable clock, the board hosts a Si5345 clock generator that needs to be configured via \gls{i2c} interface.\\
The configuration involves writing $\thicksim$380 register values. A configuration file, containing all the register addresses and the corresponding values, can be generated using the ClockBuilder tool available from \href{http://www.enclustra.com/en/home/}{Silicon Labs}.\\
......
Documentation/Latex/ch_TLU_Preparation.tex
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......@@ -4,6 +4,15 @@ The unit is designed to be used in High Energy Physics beam-tests and provides a
The current version of the hardware is an evolution of the \href{https://twiki.cern.ch/twiki/bin/view/MimosaTelescope/TLU}{EUDET-TLU} and the \href{https://www.ohwr.org/projects/fmc-mtlu/wiki}{miniTLU} and is shipped in a metallic case that includes an \gls{fpga} board and the \gls{tlu} \gls{pcb}: the \gls{fpga} is responsible for all the logic functions of the unit, while the \gls{pcb} contains the clock chip, discriminator and interface blocks needed to communicate with other devices.\\
The current version of the \gls{pcb} is \brd and is designed to plug onto a carrier \gls{fpga} board like any other \gls{fmc} mezzanine board, although its form factor does not comply with the ANSI-VITA-57-1 standard.\\
\section{Overview}
The AIDA \gls{tlu} provides timing and synchronization signals to test-beam readout hardware.\\
The hardware can provide an internally generated low-jitter 40~MHz clock or can accept and external clock reference.\\
It accepts the asynchronous trigger signals from up to six external sources, such as beam-scintillators, and generate synchronous signals (including global trigger or control signals) to send to up to four devices under tests. The logic function used to generate the trigger can be defined by the user among all the possible logic combinations of the inputs.\\
Depending on the chosen mode of operation, the \gls{tlu} can accept busy signals or other veto signals from \gls{dut}s and react accordingly, for instance avoinding any further trigger until all the busy signals have been de-asserted.\\
Whenever a global trigger is generated by the unit, a 48-bit time-stamp is attached to it. This time stamp is based on the 40~MHz clock. Additionally ???\\
The configuration parameters and data are sent and received via the \href{https://www.ohwr.org/projects/ipbus}{IPbus}. IPbus is a simple way to control and communicate TCA-based hardware via the UDP/IP protocol.
\section{FPGA}
The \gls{tlu} is shipped with an \gls{fpga} board already programmed with the latest version of the firmware needed to operate the unit.\\
The firmware developed at University of Bristol is targeted to work with the Enclustra AX3 board, which must be plugged onto a PM3 base, also produced by \href{http://www.enclustra.com/en/home/}{Enclustra}. The firmware is written on the \gls{fpga} using a \gls{jtag} interface. Typically a breakout board will be required to connect the Xilinx programming cable to the Enclustra PM3. All these components are included in the \gls{tlu} enclosure so the user can upload a new version of the firmware by simply connecting a \gls{usb}-B cable in the back panel of the unit.\\
......@@ -16,7 +25,7 @@ At the time of writing this work\footnote{Oct 2017} the AX3 is the only \gls{fpg
\section{Power}
The \gls{tlu} requires 12~V to operate. Power can be provided using the circular jack on the back panel of the unit.\\
During normal operation the current drawn by the unit is about ??A.
During normal operation the current drawn by the unit is about 0.5~A.
%\section{Preparation}
%Before powering the \gls{tlu} it is necessary to follow a few steps to ensure the board and the \gls{fpga} work correctly.\\
%
......
Documentation/Latex/ch_TLU_clock.tex
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......@@ -6,7 +6,7 @@ The \gls{dut}s can receive the clock either from the Si5435A or directly from th
The firmware uses the clock generated by the Si5345A except for the block \verb|enclustra_ax3_pm3_infra| which relies on a crystal mounted on the Enclustra board to provide the IPBus functionalities (in this way, at power up the board can communicate via IPBus even if the Si5345A is not configured).
\section{Input selection}
The Si5345 has four inputs that can be selected to provide the clock alignment; the selection can be automatic or user-defined.
The Si5345 has four inputs that can be selected to provide the clock alignment; the selection can be automatic or user-defined. For further details on this aspect the user should consult the chip documentation.
\begin{table}[]
\small
......
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