Commit 9d8addbe authored by Paolo Baesso's avatar Paolo Baesso

Tidy up folder and commit working copy

parent ebdc08aa
/TLU_v1e/work/TLU_v1e.runs/*
/EUDETdummy/work/*
/TLU_v1e/work/*
/TLU_v1c/work/*
/Enclustra_Example/*
/Enclustra_tests/
*.py~
*.pyc
......@@ -23,7 +23,7 @@ use work.ipbus.ALL;
entity top_EUDET_dummy is
generic(
constant FW_VERSION : unsigned(31 downto 0):= X"ffff0000"; -- Firmware revision. Remember to change this as needed.
constant FW_VERSION : unsigned(31 downto 0):= X"ffff0001"; -- Firmware revision. Remember to change this as needed.
g_NUM_DUTS : positive := 4; -- <- was 3
g_NUM_TRIG_INPUTS :positive := 6;-- <- was 4
g_NUM_EDGE_INPUTS :positive := 6;-- <-- was 4
......@@ -457,7 +457,7 @@ begin
-- mac_addr <= X"020ddba1151" & dip_sw; -- Careful here, arbitrary addresses do not always work
-- ip_addr <= X"c0a8c81" & dip_sw; -- 192.168.200.16+n
mac_addr <= X"020ddba1151d"; -- Careful here, arbitrary addresses do not always work
ip_addr <= X"c0a8c81d"; -- 192.168.200.16+n
ip_addr <= X"c0a8c81d"; -- 192.168.200.29
------------------------------------------
I1 : entity work.ipbus_ctrlreg_v
......@@ -724,7 +724,8 @@ begin
-- generate an instance of the Dummy DUT behind connector 0
DUT_Instance: Dummy_DUT
Port map (
CLK => clk_4x_logic,--160 Mhz clock
--CLK => clk_4x_logic,--160 Mhz clock
CLK => sysclk_40,
RST => cont_i(iDUT),-- coming from HDMI pin
Trigger => triggers_i(iDUT), --coming from HDMI pin
Busy => busy_o(iDUT), --going out on HDMI pin
......
This diff is collapsed.
......@@ -60,7 +60,7 @@ class MyPrompt(cmd.Cmd):
#################################################
if __name__ == "__main__":
EUDummy= EUDETdummy("tlu", "file://./EUDETdummyconnection.xml")
EUDummy= EUDETdummy("eudummy", "file://./EUDETdummyconnection.xml")
EUDummy.initialize()
logdata= True
......
......@@ -10,28 +10,14 @@ set_property PACKAGE_PIN P18 [get_ports i2c_sda_b]
create_clock -period 25.000 -name sysclk_40_i_p -waveform {0.000 12.500} [get_ports sysclk_40_i_p]
#set_property ASYNC_REG true [get_cells I1/sync_registers/s_ring_d4_reg]
#set_property ASYNC_REG true [get_cells I1/sync_registers/s_ring_d3_reg]
#set_property ASYNC_REG true [get_cells I1/sync_ipbus/s_ring_d0_reg]
#set_property ASYNC_REG true [get_cells I1/sync_ipbus/s_ring_d1_reg]
#set_clock_groups -asynchronous -group [get_clocks pll_base_inst_n_2] -group [get_clocks mmcm_n_8]
#set_property ASYNC_REG true [get_cells I1/sync_ipbus/s_ring_d3_reg]
#set_property ASYNC_REG true [get_cells I1/sync_ipbus/s_ring_d4_reg]
#set_property ASYNC_REG true [get_cells I6/s_logic_reset_d1_reg]
#set_property ASYNC_REG true [get_cells I6/s_logic_reset_d2_reg]
#set_property ASYNC_REG true [get_cells I1/sync_registers/s_ring_d1_reg]
#set_property ASYNC_REG true [get_cells I1/sync_registers/s_ring_d0_reg]
#set_clock_groups -asynchronous -group [get_clocks mmcm_n_8] -group [get_clocks pll_base_inst_n_2]
#Define clock groups and make them asynchronous with each other
set_clock_groups -asynchronous -group {clk_enclustra I_1 mmcm_n_10 mmcm_n_6 mmcm_n_8 clk_ipb_i} -group {sysclk_40_i_p I pll_base_inst_n_2 s_clk160}
set_clock_groups -asynchronous -group {clk_enclustra I I_1 mmcm_n_10 mmcm_n_6 mmcm_n_8 clk_ipb_i} -group {sysclk_40_i_p pll_base_inst_n_2 s_clk160}
# -------------------------------------------------------------------------------------------------
#DEBUG PROBES
......
......@@ -103,50 +103,5 @@ set_property PACKAGE_PIN G3 [get_ports {dut_clk_i[3]}]
connect_debug_port u_ila_0/probe3 [get_nets [list {I5/trigger_input_loop[0].cmp_inputTriggerCounter/rising_edge_o_reg}]]
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list I4/clk_4x_logic_o]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 6 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {I5/trigger_o[0]} {I5/trigger_o[1]} {I5/trigger_o[2]} {I5/trigger_o[3]} {I5/trigger_o[4]} {I5/trigger_o[5]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 6 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {postVetotrigger[0]} {postVetotrigger[1]} {postVetotrigger[2]} {postVetotrigger[3]} {postVetotrigger[4]} {postVetotrigger[5]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 6 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {triggers[0]} {triggers[1]} {triggers[2]} {triggers[3]} {triggers[4]} {triggers[5]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 6 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {I10/cmp_coincidence_logic/triggers_i[0]} {I10/cmp_coincidence_logic/triggers_i[1]} {I10/cmp_coincidence_logic/triggers_i[2]} {I10/cmp_coincidence_logic/triggers_i[3]} {I10/cmp_coincidence_logic/triggers_i[4]} {I10/cmp_coincidence_logic/triggers_i[5]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list I10/s_external_trigger_l]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list I10/s_external_trigger_p]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list clk_4x_logic]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk_4x_logic]
set_input_delay -clock [get_clocks [get_clocks -of_objects [get_pins I4/pll_base_inst/CLKOUT0]]] -rise -min 0.30 [get_ports -regexp -filter { NAME =~ ".*thresh.*" && DIRECTION == "IN" }]
set_input_delay -clock [get_clocks [get_clocks -of_objects [get_pins I4/pll_base_inst/CLKOUT0]]] -rise -max 0.400 [get_ports -regexp -filter { NAME =~ ".*thresh.*" && DIRECTION == "IN" }]
......@@ -49,12 +49,12 @@ begin
if rising_edge(clk_in) then -- rising clock edge
toggleme <= not toggleme;
d_clk_o(1) <= toggleme;
d_clk_o(2) <= '0';
d_clk_o(3) <= '0';
d_trg_o <= ('0' & '0' & '0' & '0');
d_busy_o <= ('0' & '0' & '0' & '0');
d_cont_o <= ('0' & '0' & '0' & '0');
d_spare_o <=('0' & '0' & '0' & '0');
d_clk_o(2) <= toggleme;
d_clk_o(3) <= toggleme;
d_trg_o <= (toggleme & toggleme & toggleme & toggleme);
d_busy_o <= (toggleme & toggleme & toggleme & toggleme);
d_cont_o <= (toggleme & toggleme & toggleme & toggleme);
d_spare_o <=(toggleme & toggleme & toggleme & toggleme);
end if;
d_clk_o(0) <= clk_in;
end process gen_clk;
......
......@@ -23,7 +23,7 @@ use work.ipbus.ALL;
entity top_tlu_v1e is
generic(
constant FW_VERSION : unsigned(31 downto 0):= X"abce0001"; -- Firmware revision. Remember to change this as needed.
constant FW_VERSION : unsigned(31 downto 0):= X"abce0006"; -- Firmware revision. Remember to change this as needed.
g_NUM_DUTS : positive := 4; -- <- was 3
g_NUM_TRIG_INPUTS :positive := 6;-- <- was 4
g_NUM_EDGE_INPUTS :positive := 6;-- <-- was 4
......@@ -406,11 +406,15 @@ begin
i2c_reset <= '1';
clk_gen_rst <= '1';
gpio <= strobe_8x_logic;
---gpio <= strobe_8x_logic;---
gpio <= veto_o;---
--gpio <= busy_i(1);---
--Set diff clock out to 0 because we cannot have the correct differential voltage output
sysclk_50_o_p <= '0';
sysclk_50_o_n <= '0';
--Set busy_o to 0 for now
busy_o <= std_logic_vector(to_unsigned(0, busy_o'length));
--busy_o <= '000000';
--sysclk_40_o_p <= sysclk;
------------------------------------------
......@@ -680,12 +684,12 @@ begin
-- dutout0: entity work.DUTs_outputs
-- port map(
-- clk_in => encl_clock50,
-- d_clk_o => dut_clk_o,
-- d_trg_o => triggers_o,
-- clk_in => clk_encl_buf,
-- d_clk_o => open, --dut_clk_o,
-- d_trg_o => open, --triggers_o,
-- d_busy_o => busy_o,
-- d_cont_o => cont_o,
-- d_spare_o => spare_o
-- d_cont_o => open, --cont_o,
-- d_spare_o => open --spare_o
-- );
-- clk50_o_fromEnclustra : clk_wiz_0
......
[Dolphin]
Timestamp=2017,2,17,15,3,7
ViewMode=1
# Si538x/4x Registers Export
#
# Part: Si5345
# Project File: P:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_toplevel_c\physical\ClockGen\TLU_Si5345-RevB-NEWTLU00-Project.slabtimeproj
# Design ID: NEWTLU01
# Includes Pre/Post Download Control Register Writes: Yes
# Die Revision: A2
# Creator: ClockBuilder Pro v2.12.1 [2016-12-15]
# Created On: 2017-02-17 15:16:26 GMT+00:00
Address,Data
0x0B24,0xD8
0x0B25,0x00
0x000B,0x68
0x0016,0x02
0x0017,0x1C
0x0018,0x00
0x0019,0xDD
0x001A,0xDF
0x002B,0x02
0x002C,0x0F
0x002D,0x55
0x002E,0x37
0x002F,0x00
0x0030,0x37
0x0031,0x00
0x0032,0x37
0x0033,0x00
0x0034,0x37
0x0035,0x00
0x0036,0x37
0x0037,0x00
0x0038,0x37
0x0039,0x00
0x003A,0x37
0x003B,0x00
0x003C,0x37
0x003D,0x00
0x003F,0xFF
0x0040,0x04
0x0041,0x0C
0x0042,0x0C
0x0043,0x0C
0x0044,0x0C
0x0045,0x0C
0x0046,0x32
0x0047,0x32
0x0048,0x32
0x0049,0x32
0x004A,0x32
0x004B,0x32
0x004C,0x32
0x004D,0x32
0x004E,0x55
0x004F,0x55
0x0051,0x03
0x0052,0x03
0x0053,0x03
0x0054,0x03
0x0055,0x03
0x0056,0x03
0x0057,0x03
0x0058,0x03
0x0059,0xFF
0x005A,0x00
0x005B,0x00
0x005C,0x00
0x005D,0x01
0x005E,0x00
0x005F,0x00
0x0060,0x00
0x0061,0x01
0x0062,0x00
0x0063,0x00
0x0064,0x00
0x0065,0x01
0x0066,0x00
0x0067,0x00
0x0068,0x00
0x0069,0x01
0x0092,0x00
0x0093,0x00
0x0095,0x00
0x0096,0x00
0x0098,0x00
0x009A,0x02
0x009B,0x30
0x009D,0x00
0x009E,0x20
0x00A0,0x00
0x00A2,0x02
0x00A8,0x89
0x00A9,0x70
0x00AA,0x07
0x00AB,0x00
0x00AC,0x00
0x0102,0x01
0x0108,0x06
0x0109,0x09
0x010A,0x33
0x010B,0x00
0x010D,0x06
0x010E,0x09
0x010F,0x33
0x0110,0x00
0x0112,0x06
0x0113,0x09
0x0114,0x33
0x0115,0x00
0x0117,0x06
0x0118,0x09
0x0119,0x33
0x011A,0x00
0x011C,0x06
0x011D,0x09
0x011E,0x33
0x011F,0x00
0x0121,0x06
0x0122,0x09
0x0123,0x33
0x0124,0x00
0x0126,0x06
0x0127,0x09
0x0128,0x33
0x0129,0x00
0x012B,0x06
0x012C,0x09
0x012D,0x33
0x012E,0x00
0x0130,0x06
0x0131,0x09
0x0132,0x33
0x0133,0x00
0x013A,0x06
0x013B,0xCC
0x013C,0x00
0x013D,0x00
0x013F,0x00
0x0140,0x00
0x0141,0x40
0x0142,0xFF
0x0202,0x00
0x0203,0x00
0x0204,0x00
0x0205,0x00
0x0206,0x00
0x0208,0x19
0x0209,0x00
0x020A,0x00
0x020B,0x00
0x020C,0x00
0x020D,0x00
0x020E,0x01
0x020F,0x00
0x0210,0x00
0x0211,0x00
0x0212,0x19
0x0213,0x00
0x0214,0x00
0x0215,0x00
0x0216,0x00
0x0217,0x00
0x0218,0x01
0x0219,0x00
0x021A,0x00
0x021B,0x00
0x021C,0x19
0x021D,0x00
0x021E,0x00
0x021F,0x00
0x0220,0x00
0x0221,0x00
0x0222,0x01
0x0223,0x00
0x0224,0x00
0x0225,0x00
0x0226,0x19
0x0227,0x00
0x0228,0x00
0x0229,0x00
0x022A,0x00
0x022B,0x00
0x022C,0x01
0x022D,0x00
0x022E,0x00
0x022F,0x00
0x0231,0x01
0x0232,0x01
0x0233,0x01
0x0234,0x01
0x0235,0x00
0x0236,0x00
0x0237,0x00
0x0238,0x00
0x0239,0xA9
0x023A,0x00
0x023B,0x00
0x023C,0x00
0x023D,0x00
0x023E,0xA0
0x024A,0x00
0x024B,0x00
0x024C,0x00
0x024D,0x00
0x024E,0x00
0x024F,0x00
0x0250,0x00
0x0251,0x00
0x0252,0x00
0x0253,0x00
0x0254,0x00
0x0255,0x00
0x0256,0x00
0x0257,0x00
0x0258,0x00
0x0259,0x00
0x025A,0x00
0x025B,0x00
0x025C,0x00
0x025D,0x00
0x025E,0x00
0x025F,0x00
0x0260,0x00
0x0261,0x00
0x0262,0x00
0x0263,0x00
0x0264,0x00
0x0268,0x00
0x0269,0x00
0x026A,0x00
0x026B,0x4E
0x026C,0x45
0x026D,0x57
0x026E,0x54
0x026F,0x4C
0x0270,0x55
0x0271,0x30
0x0272,0x31
0x0302,0x00
0x0303,0x00
0x0304,0x00
0x0305,0x80
0x0306,0x54
0x0307,0x00
0x0308,0x00
0x0309,0x00
0x030A,0x00
0x030B,0x80
0x030C,0x00
0x030D,0x00
0x030E,0x00
0x030F,0x00
0x0310,0x00
0x0311,0x00
0x0312,0x00
0x0313,0x00
0x0314,0x00
0x0315,0x00
0x0316,0x00
0x0317,0x00
0x0318,0x00
0x0319,0x00
0x031A,0x00
0x031B,0x00
0x031C,0x00
0x031D,0x00
0x031E,0x00
0x031F,0x00
0x0320,0x00
0x0321,0x00
0x0322,0x00
0x0323,0x00
0x0324,0x00
0x0325,0x00
0x0326,0x00
0x0327,0x00
0x0328,0x00
0x0329,0x00
0x032A,0x00
0x032B,0x00
0x032C,0x00
0x032D,0x00
0x032E,0x00
0x032F,0x00
0x0330,0x00
0x0331,0x00
0x0332,0x00
0x0333,0x00
0x0334,0x00
0x0335,0x00
0x0336,0x00
0x0337,0x00
0x0338,0x00
0x0339,0x1F
0x033B,0x00
0x033C,0x00
0x033D,0x00
0x033E,0x00
0x033F,0x00
0x0340,0x00
0x0341,0x00
0x0342,0x00
0x0343,0x00
0x0344,0x00
0x0345,0x00
0x0346,0x00
0x0347,0x00
0x0348,0x00
0x0349,0x00
0x034A,0x00
0x034B,0x00
0x034C,0x00
0x034D,0x00
0x034E,0x00
0x034F,0x00
0x0350,0x00
0x0351,0x00
0x0352,0x00
0x0353,0x00
0x0354,0x00
0x0355,0x00
0x0356,0x00
0x0357,0x00
0x0358,0x00
0x0359,0x00
0x035A,0x00
0x035B,0x00
0x035C,0x00
0x035D,0x00
0x035E,0x00
0x035F,0x00
0x0360,0x00
0x0361,0x00
0x0362,0x00
0x0487,0x00
0x0502,0x01
0x0508,0x14
0x0509,0x23
0x050A,0x0C
0x050B,0x0B
0x050C,0x03
0x050D,0x3F
0x050E,0x17
0x050F,0x2B
0x0510,0x09
0x0511,0x08
0x0512,0x03
0x0513,0x3F
0x0515,0x00
0x0516,0x00
0x0517,0x00
0x0518,0x00
0x0519,0xA4
0x051A,0x02
0x051B,0x00
0x051C,0x00
0x051D,0x00
0x051E,0x00
0x051F,0x80
0x0521,0x21
0x052A,0x05
0x052B,0x01
0x052C,0x0F
0x052D,0x03
0x052E,0x19
0x052F,0x19
0x0531,0x00
0x0532,0x42
0x0533,0x03
0x0534,0x00
0x0535,0x00
0x0536,0x0C
0x0537,0x00
0x0538,0x00
0x0539,0x00
0x0802,0x35
0x0803,0x05
0x0804,0x00
0x090E,0x02
0x0943,0x00
0x0949,0x0F
0x094A,0x0F
0x0A02,0x00
0x0A03,0x01
0x0A04,0x01
0x0A05,0x01
0x0B44,0x2F
0x0B46,0x00
0x0B47,0x00
0x0B48,0x00
0x0B4A,0x1E
0x0514,0x01
0x001C,0x01
0x0B24,0xDB
0x0B25,0x02
# Si538x/4x Registers Export
#
# Part: Si5345
# Project File: P:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_toplevel_c\physical\ClockGen\TLU_Si5345-RevB-NEWTLU00-Project.slabtimeproj
# Design ID: NEWTLU00
# Includes Pre/Post Download Control Register Writes: Yes
# Die Revision: A2
# Creator: ClockBuilder Pro v2.12.1 [2016-12-15]
# Created On: 2017-02-07 18:25:57 GMT+00:00
Address,Data
0x0B24,0xD8
0x0B25,0x00
0x000B,0x68
0x0016,0x02
0x0017,0x1C
0x0018,0xFF
0x0019,0xFF
0x001A,0xFF
0x002B,0x02
0x002C,0x00
0x002D,0x00
0x002E,0x00
0x002F,0x00
0x0030,0x00
0x0031,0x00
0x0032,0x00
0x0033,0x00
0x0034,0x00
0x0035,0x00
0x0036,0x00
0x0037,0x00
0x0038,0x00
0x0039,0x00
0x003A,0x00
0x003B,0x00
0x003C,0x00
0x003D,0x00
0x003F,0x00
0x0040,0x04
0x0041,0x00
0x0042,0x00
0x0043,0x00
0x0044,0x00
0x0045,0x0C
0x0046,0x00
0x0047,0x00
0x0048,0x00
0x0049,0x00
0x004A,0x00
0x004B,0x00
0x004C,0x00
0x004D,0x00
0x004E,0x00
0x004F,0x00
0x0051,0x00
0x0052,0x00
0x0053,0x00
0x0054,0x00
0x0055,0x00
0x0056,0x00
0x0057,0x00
0x0058,0x00
0x0059,0x00
0x005A,0x00
0x005B,0x00
0x005C,0x00
0x005D,0x00
0x005E,0x00
0x005F,0x00
0x0060,0x00
0x0061,0x00
0x0062,0x00
0x0063,0x00
0x0064,0x00
0x0065,0x00
0x0066,0x00
0x0067,0x00
0x0068,0x00
0x0069,0x00
0x0092,0x00
0x0093,0x00
0x0095,0x00
0x0096,0x00
0x0098,0x00
0x009A,0x00
0x009B,0x00
0x009D,0x00
0x009E,0x00
0x00A0,0x00
0x00A2,0x00
0x00A8,0x00
0x00A9,0x00
0x00AA,0x00
0x00AB,0x00
0x00AC,0x00
0x0102,0x01
0x0108,0x06
0x0109,0x09
0x010A,0x33
0x010B,0x00
0x010D,0x06
0x010E,0x09
0x010F,0x33
0x0110,0x00
0x0112,0x06
0x0113,0x09
0x0114,0x33
0x0115,0x00
0x0117,0x06
0x0118,0x09
0x0119,0x33
0x011A,0x00
0x011C,0x06
0x011D,0x09
0x011E,0x33
0x011F,0x00
0x0121,0x06
0x0122,0x09
0x0123,0x33
0x0124,0x00
0x0126,0x06
0x0127,0x09
0x0128,0x33
0x0129,0x00
0x012B,0x06
0x012C,0x09
0x012D,0x33
0x012E,0x00
0x0130,0x06
0x0131,0x09
0x0132,0x33
0x0133,0x00
0x013A,0x06
0x013B,0xCC
0x013C,0x00
0x013D,0x00
0x013F,0x00
0x0140,0x00
0x0141,0x40
0x0142,0xFF
0x0202,0x00
0x0203,0x00
0x0204,0x00
0x0205,0x00
0x0206,0x00