Commit ebdc08aa authored by Paolo Baesso's avatar Paolo Baesso

Removed work folders

parent b226d0ed
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*** Running vivado
with args -log tlu_event_fifo.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source tlu_event_fifo.tcl
****** Vivado v2016.4 (64-bit)
**** SW Build 1733598 on Wed Dec 14 22:35:42 MST 2016
**** IP Build 1731160 on Wed Dec 14 23:47:21 MST 2016
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
source tlu_event_fifo.tcl -notrace
Starting RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:26 . Memory (MB): peak = 1189.312 ; gain = 173.082 ; free physical = 131 ; free virtual = 15978
INFO: [Synth 8-638] synthesizing module 'tlu_event_fifo' [/users/phpgb/workspace/myFirmware/AIDA/TLU_v1e/work/TLU_v1e.srcs/sources_1/ip/tlu_event_fifo/synth/tlu_event_fifo.vhd:77]
INFO: [Synth 8-256] done synthesizing module 'tlu_event_fifo' (30#1) [/users/phpgb/workspace/myFirmware/AIDA/TLU_v1e/work/TLU_v1e.srcs/sources_1/ip/tlu_event_fifo/synth/tlu_event_fifo.vhd:77]
Finished RTL Elaboration : Time (s): cpu = 00:01:12 ; elapsed = 00:01:45 . Memory (MB): peak = 1404.148 ; gain = 387.918 ; free physical = 138 ; free virtual = 15783
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:01:12 ; elapsed = 00:01:46 . Memory (MB): peak = 1404.148 ; gain = 387.918 ; free physical = 137 ; free virtual = 15783
INFO: [Device 21-403] Loading part xc7a35tcsg324-1
Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1571.199 ; gain = 1.000 ; free physical = 132 ; free virtual = 15775
Finished Constraint Validation : Time (s): cpu = 00:01:24 ; elapsed = 00:02:13 . Memory (MB): peak = 1571.199 ; gain = 554.969 ; free physical = 132 ; free virtual = 15775
Finished Loading Part and Timing Information : Time (s): cpu = 00:01:24 ; elapsed = 00:02:13 . Memory (MB): peak = 1571.199 ; gain = 554.969 ; free physical = 132 ; free virtual = 15776
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:01:24 ; elapsed = 00:02:13 . Memory (MB): peak = 1571.199 ; gain = 554.969 ; free physical = 132 ; free virtual = 15776
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:25 ; elapsed = 00:02:14 . Memory (MB): peak = 1571.199 ; gain = 554.969 ; free physical = 126 ; free virtual = 15770
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:26 ; elapsed = 00:02:16 . Memory (MB): peak = 1571.199 ; gain = 554.969 ; free physical = 128 ; free virtual = 15748
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:35 ; elapsed = 00:02:30 . Memory (MB): peak = 1571.199 ; gain = 554.969 ; free physical = 103 ; free virtual = 15729
Finished Timing Optimization : Time (s): cpu = 00:01:36 ; elapsed = 00:02:30 . Memory (MB): peak = 1571.199 ; gain = 554.969 ; free physical = 121 ; free virtual = 15724
Finished Technology Mapping : Time (s): cpu = 00:01:36 ; elapsed = 00:02:31 . Memory (MB): peak = 1571.199 ; gain = 554.969 ; free physical = 136 ; free virtual = 15709
Finished IO Insertion : Time (s): cpu = 00:01:36 ; elapsed = 00:02:32 . Memory (MB): peak = 1571.199 ; gain = 554.969 ; free physical = 135 ; free virtual = 15708
Finished Renaming Generated Instances : Time (s): cpu = 00:01:36 ; elapsed = 00:02:32 . Memory (MB): peak = 1571.199 ; gain = 554.969 ; free physical = 135 ; free virtual = 15708
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:37 ; elapsed = 00:02:32 . Memory (MB): peak = 1571.199 ; gain = 554.969 ; free physical = 135 ; free virtual = 15708
Finished Renaming Generated Ports : Time (s): cpu = 00:01:37 ; elapsed = 00:02:32 . Memory (MB): peak = 1571.199 ; gain = 554.969 ; free physical = 135 ; free virtual = 15708
Finished Handling Custom Attributes : Time (s): cpu = 00:01:37 ; elapsed = 00:02:32 . Memory (MB): peak = 1571.199 ; gain = 554.969 ; free physical = 135 ; free virtual = 15708
Finished Renaming Generated Nets : Time (s): cpu = 00:01:37 ; elapsed = 00:02:32 . Memory (MB): peak = 1571.199 ; gain = 554.969 ; free physical = 135 ; free virtual = 15708
Report Cell Usage:
+------+-----------+------+
| |Cell |Count |
+------+-----------+------+
|1 |CARRY4 | 16|
|2 |LUT1 | 28|
|3 |LUT2 | 68|
|4 |LUT3 | 8|
|5 |LUT4 | 45|
|6 |LUT5 | 16|
|7 |LUT6 | 40|
|8 |MUXCY | 42|
|9 |RAMB18E1 | 1|
|10 |RAMB36E1 | 2|
|11 |RAMB36E1_1 | 12|
|12 |FDCE | 222|
|13 |FDPE | 28|
|14 |FDRE | 6|
+------+-----------+------+
Finished Writing Synthesis Report : Time (s): cpu = 00:01:37 ; elapsed = 00:02:32 . Memory (MB): peak = 1571.199 ; gain = 554.969 ; free physical = 135 ; free virtual = 15708
get_clocks: Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 1980.359 ; gain = 409.160 ; free physical = 106 ; free virtual = 15479
synth_design: Time (s): cpu = 00:01:36 ; elapsed = 00:02:33 . Memory (MB): peak = 1980.359 ; gain = 874.629 ; free physical = 131 ; free virtual = 15482
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
// Date : Thu Aug 17 13:46:40 2017
// Host : fortis.phy.bris.ac.uk running 64-bit Scientific Linux release 6.9 (Carbon)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ tlu_event_fifo_stub.v
// Design : tlu_event_fifo
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_1_3,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full,
almost_full, empty, almost_empty, rd_data_count, prog_full)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[63:0],wr_en,rd_en,dout[31:0],full,almost_full,empty,almost_empty,rd_data_count[13:0],prog_full" */;
input rst;
input wr_clk;
input rd_clk;
input [63:0]din;
input wr_en;
input rd_en;
output [31:0]dout;
output full;
output almost_full;
output empty;
output almost_empty;
output [13:0]rd_data_count;
output prog_full;
endmodule
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Thu Aug 17 13:46:41 2017
-- Host : fortis.phy.bris.ac.uk running 64-bit Scientific Linux release 6.9 (Carbon)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ tlu_event_fifo_stub.vhdl
-- Design : tlu_event_fifo
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 13 downto 0 );
prog_full : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[63:0],wr_en,rd_en,dout[31:0],full,almost_full,empty,almost_empty,rd_data_count[13:0],prog_full";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v13_1_3,Vivado 2016.4";
begin
end;
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*** Running vivado
with args -log internalTriggerGenerator.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source internalTriggerGenerator.tcl
****** Vivado v2016.4 (64-bit)
**** SW Build 1733598 on Wed Dec 14 22:35:42 MST 2016
**** IP Build 1731160 on Wed Dec 14 23:47:21 MST 2016
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
source internalTriggerGenerator.tcl -notrace
Starting RTL Elaboration : Time (s): cpu = 00:00:11 ; elapsed = 00:00:22 . Memory (MB): peak = 1187.309 ; gain = 171.086 ; free physical = 506 ; free virtual = 16050
INFO: [Synth 8-638] synthesizing module 'internalTriggerGenerator' [/users/phpgb/workspace/myFirmware/AIDA/TLU_v1e/work/TLU_v1e.srcs/sources_1/ip/internalTriggerGenerator/synth/internalTriggerGenerator.vhd:69]
INFO: [Synth 8-256] done synthesizing module 'internalTriggerGenerator' (6#1) [/users/phpgb/workspace/myFirmware/AIDA/TLU_v1e/work/TLU_v1e.srcs/sources_1/ip/internalTriggerGenerator/synth/internalTriggerGenerator.vhd:69]
Finished RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:25 . Memory (MB): peak = 1236.773 ; gain = 220.551 ; free physical = 455 ; free virtual = 16001
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:25 . Memory (MB): peak = 1236.773 ; gain = 220.551 ; free physical = 455 ; free virtual = 16001
INFO: [Device 21-403] Loading part xc7a35tcsg324-1
Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1549.934 ; gain = 1.000 ; free physical = 287 ; free virtual = 15846
Finished Constraint Validation : Time (s): cpu = 00:00:24 ; elapsed = 00:00:44 . Memory (MB): peak = 1549.934 ; gain = 533.711 ; free physical = 286 ; free virtual = 15845
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:24 ; elapsed = 00:00:44 . Memory (MB): peak = 1549.934 ; gain = 533.711 ; free physical = 286 ; free virtual = 15845
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:44 . Memory (MB): peak = 1549.934 ; gain = 533.711 ; free physical = 286 ; free virtual = 15845
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:24 ; elapsed = 00:00:44 . Memory (MB): peak = 1549.934 ; gain = 533.711 ; free physical = 286 ; free virtual = 15845
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:44 . Memory (MB): peak = 1549.934 ; gain = 533.711 ; free physical = 271 ; free virtual = 15830
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:34 ; elapsed = 00:00:57 . Memory (MB): peak = 1549.934 ; gain = 533.711 ; free physical = 229 ; free virtual = 15788
Finished Timing Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:57 . Memory (MB): peak = 1549.934 ; gain = 533.711 ; free physical = 221 ; free virtual = 15780
Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:57 . Memory (MB): peak = 1549.934 ; gain = 533.711 ; free physical = 220 ; free virtual = 15779
Finished IO Insertion : Time (s): cpu = 00:00:34 ; elapsed = 00:00:58 . Memory (MB): peak = 1549.934 ; gain = 533.711 ; free physical = 220 ; free virtual = 15778
Finished Renaming Generated Instances : Time (s): cpu = 00:00:34 ; elapsed = 00:00:58 . Memory (MB): peak = 1549.934 ; gain = 533.711 ; free physical = 220 ; free virtual = 15778
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:34 ; elapsed = 00:00:58 . Memory (MB): peak = 1549.934 ; gain = 533.711 ; free physical = 220 ; free virtual = 15778
Finished Renaming Generated Ports : Time (s): cpu = 00:00:34 ; elapsed = 00:00:58 . Memory (MB): peak = 1549.934 ; gain = 533.711 ; free physical = 220 ; free virtual = 15778
Finished Handling Custom Attributes : Time (s): cpu = 00:00:34 ; elapsed = 00:00:58 . Memory (MB): peak = 1549.934 ; gain = 533.711 ; free physical = 220 ; free virtual = 15778
Finished Renaming Generated Nets : Time (s): cpu = 00:00:34 ; elapsed = 00:00:58 . Memory (MB): peak = 1549.934 ; gain = 533.711 ; free physical = 220 ; free virtual = 15778
Report Cell Usage:
+------+-------+------+
| |Cell |Count |
+------+-------+------+
|1 |CARRY4 | 10|
|2 |LUT1 | 1|
|3 |LUT2 | 2|
|4 |LUT3 | 32|
|5 |LUT4 | 1|
|6 |LUT5 | 14|
|7 |FDRE | 67|
+------+-------+------+
Finished Writing Synthesis Report : Time (s): cpu = 00:00:34 ; elapsed = 00:00:58 . Memory (MB): peak = 1549.934 ; gain = 533.711 ; free physical = 220 ; free virtual = 15778
synth_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:48 . Memory (MB): peak = 1549.934 ; gain = 444.211 ; free physical = 200 ; free virtual = 15764
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2016.4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
// Date : Thu Aug 17 13:51:32 2017
// Host : fortis.phy.bris.ac.uk running 64-bit Scientific Linux release 6.9 (Carbon)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ internalTriggerGenerator_stub.v
// Design : internalTriggerGenerator
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "c_counter_binary_v12_0_10,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(CLK, CE, LOAD, L, Q)
/* synthesis syn_black_box black_box_pad_pin="CLK,CE,LOAD,L[31:0],Q[31:0]" */;
input CLK;
input CE;
input LOAD;
input [31:0]L;
output [31:0]Q;
endmodule
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Thu Aug 17 13:51:33 2017
-- Host : fortis.phy.bris.ac.uk running 64-bit Scientific Linux release 6.9 (Carbon)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ internalTriggerGenerator_stub.vhdl
-- Design : internalTriggerGenerator
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
CLK : in STD_LOGIC;
CE : in STD_LOGIC;
LOAD : in STD_LOGIC;
L : in STD_LOGIC_VECTOR ( 31 downto 0 );
Q : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "CLK,CE,LOAD,L[31:0],Q[31:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "c_counter_binary_v12_0_10,Vivado 2016.4";
begin
end;
*** Running vivado
with args -log mac_fifo_axi4.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source mac_fifo_axi4.tcl
****** Vivado v2016.4 (64-bit)
**** SW Build 1733598 on Wed Dec 14 22:35:42 MST 2016
**** IP Build 1731160 on Wed Dec 14 23:47:21 MST 2016
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
source mac_fifo_axi4.tcl -notrace
Starting RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:23 . Memory (MB): peak = 1188.312 ; gain = 172.086 ; free physical = 467 ; free virtual = 15985
INFO: [Synth 8-638] synthesizing module 'mac_fifo_axi4' [/users/phpgb/workspace/myFirmware/AIDA/TLU_v1e/work/TLU_v1e.srcs/sources_1/ip/mac_fifo_axi4/synth/mac_fifo_axi4.vhd:79]
INFO: [Synth 8-256] done synthesizing module 'mac_fifo_axi4' (27#1) [/users/phpgb/workspace/myFirmware/AIDA/TLU_v1e/work/TLU_v1e.srcs/sources_1/ip/mac_fifo_axi4/synth/mac_fifo_axi4.vhd:79]
Finished RTL Elaboration : Time (s): cpu = 00:01:05 ; elapsed = 00:01:27 . Memory (MB): peak = 1403.980 ; gain = 387.754 ; free physical = 249 ; free virtual = 15768
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:01:05 ; elapsed = 00:01:28 . Memory (MB): peak = 1403.980 ; gain = 387.754 ; free physical = 243 ; free virtual = 15762
INFO: [Device 21-403] Loading part xc7a35tcsg324-1
Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1533.031 ; gain = 1.000 ; free physical = 209 ; free virtual = 15755
Finished Constraint Validation : Time (s): cpu = 00:01:17 ; elapsed = 00:01:49 . Memory (MB): peak = 1533.031 ; gain = 516.805 ; free physical = 208 ; free virtual = 15754
Finished Loading Part and Timing Information : Time (s): cpu = 00:01:17 ; elapsed = 00:01:49 . Memory (MB): peak = 1533.031 ; gain = 516.805 ; free physical = 208 ; free virtual = 15754
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:01:17 ; elapsed = 00:01:49 . Memory (MB): peak = 1533.031 ; gain = 516.805 ; free physical = 208 ; free virtual = 15754
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:18 ; elapsed = 00:01:49 . Memory (MB): peak = 1533.031 ; gain = 516.805 ; free physical = 206 ; free virtual = 15752
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:19 ; elapsed = 00:01:51 . Memory (MB): peak = 1533.031 ; gain = 516.805 ; free physical = 182 ; free virtual = 15728
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:28 ; elapsed = 00:02:05 . Memory (MB): peak = 1533.031 ; gain = 516.805 ; free physical = 163 ; free virtual = 15716
Finished Timing Optimization : Time (s): cpu = 00:01:28 ; elapsed = 00:02:05 . Memory (MB): peak = 1533.031 ; gain = 516.805 ; free physical = 163 ; free virtual = 15716
Finished Technology Mapping : Time (s): cpu = 00:01:28 ; elapsed = 00:02:05 . Memory (MB): peak = 1533.031 ; gain = 516.805 ; free physical = 145 ; free virtual = 15698
Finished IO Insertion : Time (s): cpu = 00:01:29 ; elapsed = 00:02:06 . Memory (MB): peak = 1533.031 ; gain = 516.805 ; free physical = 144 ; free virtual = 15697
Finished Renaming Generated Instances : Time (s): cpu = 00:01:29 ; elapsed = 00:02:06 . Memory (MB): peak = 1533.031 ; gain = 516.805 ; free physical = 144 ; free virtual = 15697
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:29 ; elapsed = 00:02:06 . Memory (MB): peak = 1533.031 ; gain = 516.805 ; free physical = 144 ; free virtual = 15697
Finished Renaming Generated Ports : Time (s): cpu = 00:01:29 ; elapsed = 00:02:06 . Memory (MB): peak = 1533.031 ; gain = 516.805 ; free physical = 144 ; free virtual = 15697
Finished Handling Custom Attributes : Time (s): cpu = 00:01:29 ; elapsed = 00:02:06 . Memory (MB): peak = 1533.031 ; gain = 516.805 ; free physical = 144 ; free virtual = 15697
Finished Renaming Generated Nets : Time (s): cpu = 00:01:29 ; elapsed = 00:02:06 . Memory (MB): peak = 1533.031 ; gain = 516.805 ; free physical = 144 ; free virtual = 15697
Report Cell Usage:
+------+---------+------+
| |Cell |Count |
+------+---------+------+
|1 |LUT1 | 5|
|2 |LUT2 | 18|
|3 |LUT3 | 7|
|4 |LUT4 | 15|
|5 |LUT5 | 3|
|6 |LUT6 | 7|
|7 |RAMB18E1 | 1|
|8 |FDCE | 33|
|9 |FDPE | 21|
|10 |FDRE | 67|
|11 |FDSE | 6|
+------+---------+------+
Finished Writing Synthesis Report : Time (s): cpu = 00:01:29 ; elapsed = 00:02:06 . Memory (MB): peak = 1533.031 ; gain = 516.805 ; free physical = 144 ; free virtual = 15697
get_clocks: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1948.199 ; gain = 405.160 ; free physical = 124 ; free virtual = 15421
synth_design: Time (s): cpu = 00:01:28 ; elapsed = 00:02:00 . Memory (MB): peak = 1948.199 ; gain = 842.473 ; free physical = 125 ; free virtual = 15421
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
// Date : Thu Aug 17 14:07:28 2017
// Host : fortis.phy.bris.ac.uk running 64-bit Scientific Linux release 6.9 (Carbon)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mac_fifo_axi4_stub.v
// Design : mac_fifo_axi4
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_1_3,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(m_aclk, s_aclk, s_aresetn, s_axis_tvalid,
s_axis_tready, s_axis_tdata, s_axis_tlast, s_axis_tdest, s_axis_tuser, m_axis_tvalid,
m_axis_tready, m_axis_tdata, m_axis_tlast, m_axis_tdest, m_axis_tuser)
/* synthesis syn_black_box black_box_pad_pin="m_aclk,s_aclk,s_aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[7:0],s_axis_tlast,s_axis_tdest[3:0],s_axis_tuser[0:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[7:0],m_axis_tlast,m_axis_tdest[3:0],m_axis_tuser[0:0]" */;
input m_aclk;
input s_aclk;
input s_aresetn;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input s_axis_tlast;
input [3:0]s_axis_tdest;
input [0:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output m_axis_tlast;
output [3:0]m_axis_tdest;
output [0:0]m_axis_tuser;
endmodule
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Thu Aug 17 14:07:28 2017
-- Host : fortis.phy.bris.ac.uk running 64-bit Scientific Linux release 6.9 (Carbon)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mac_fifo_axi4_stub.vhdl
-- Design : mac_fifo_axi4
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tdest : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tdest : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "m_aclk,s_aclk,s_aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[7:0],s_axis_tlast,s_axis_tdest[3:0],s_axis_tuser[0:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[7:0],m_axis_tlast,m_axis_tdest[3:0],m_axis_tuser[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v13_1_3,Vivado 2016.4";
begin
end;
This diff is collapsed.
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2016.4 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0">
<HWSession Dir="hw_1" File="hw.xml"/>
</labtools>
This diff is collapsed.
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="/users/phpgb/workspace/myFirmware/AIDA/TLU_v1e/work/TLU_v1e.hw/hw_1/wave/hw_ila_data_1/hw_ila_data_1.wdb" id="1">
<top_modules>
</top_modules>
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="0fs"></ZoomStartTime>
<ZoomEndTime time="100001fs"></ZoomEndTime>
<Cursor1Time time="17000fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="175"></NameColumnWidth>
<ValueColumnWidth column_width="63"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="0" />
<wave_markers>
</wave_markers>
</wave_config>
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:c_counter_binary:12.0
// IP Revision: 10
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
internalTriggerGenerator your_instance_name (
.CLK(CLK), // input wire CLK
.CE(CE), // input wire CE
.LOAD(LOAD), // input wire LOAD
.L(L), // input wire [31 : 0] L
.Q(Q) // output wire [31 : 0] Q
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file internalTriggerGenerator.v when simulating
// the core, internalTriggerGenerator. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:c_counter_binary:12.0
-- IP Revision: 10
-- The following code must appear in the VHDL architecture header.
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT internalTriggerGenerator
PORT (
CLK : IN STD_LOGIC;
CE : IN STD_LOGIC;
LOAD : IN STD_LOGIC;
L : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : internalTriggerGenerator
PORT MAP (
CLK => CLK,
CE => CE,
LOAD => LOAD,
L => L,
Q => Q
);
-- INST_TAG_END ------ End INSTANTIATION Template ---------
-- You must compile the wrapper file internalTriggerGenerator.vhd when simulating
-- the core, internalTriggerGenerator. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
// Date : Thu Aug 17 13:51:34 2017
// Host : fortis.phy.bris.ac.uk running 64-bit Scientific Linux release 6.9 (Carbon)
// Command : write_verilog -force -mode synth_stub
// /users/phpgb/workspace/myFirmware/AIDA/TLU_v1e/work/TLU_v1e.srcs/sources_1/ip/internalTriggerGenerator/internalTriggerGenerator_stub.v
// Design : internalTriggerGenerator
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "c_counter_binary_v12_0_10,Vivado 2016.4" *)
module internalTriggerGenerator(CLK, CE, LOAD, L, Q)
/* synthesis syn_black_box black_box_pad_pin="CLK,CE,LOAD,L[31:0],Q[31:0]" */;
input CLK;
input CE;
input LOAD;
input [31:0]L;
output [31:0]Q;
endmodule
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Thu Aug 17 13:51:34 2017
-- Host : fortis.phy.bris.ac.uk running 64-bit Scientific Linux release 6.9 (Carbon)
-- Command : write_vhdl -force -mode synth_stub
-- /users/phpgb/workspace/myFirmware/AIDA/TLU_v1e/work/TLU_v1e.srcs/sources_1/ip/internalTriggerGenerator/internalTriggerGenerator_stub.vhdl
-- Design : internalTriggerGenerator
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity internalTriggerGenerator is
Port (
CLK : in STD_LOGIC;
CE : in STD_LOGIC;
LOAD : in STD_LOGIC;
L : in STD_LOGIC_VECTOR ( 31 downto 0 );
Q : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end internalTriggerGenerator;
architecture stub of internalTriggerGenerator is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "CLK,CE,LOAD,L[31:0],Q[31:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "c_counter_binary_v12_0_10,Vivado 2016.4";
begin
end;
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fifo_generator:13.1
// IP Revision: 3
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
mac_fifo_axi4 your_instance_name (
.m_aclk(m_aclk), // input wire m_aclk
.s_aclk(s_aclk), // input wire s_aclk
.s_aresetn(s_aresetn), // input wire s_aresetn
.s_axis_tvalid(s_axis_tvalid), // input wire s_axis_tvalid
.s_axis_tready(s_axis_tready), // output wire s_axis_tready
.s_axis_tdata(s_axis_tdata), // input wire [7 : 0] s_axis_tdata
.s_axis_tlast(s_axis_tlast), // input wire s_axis_tlast
.s_axis_tdest(s_axis_tdest), // input wire [3 : 0] s_axis_tdest
.s_axis_tuser(s_axis_tuser), // input wire [0 : 0] s_axis_tuser
.m_axis_tvalid(m_axis_tvalid), // output wire m_axis_tvalid
.m_axis_tready(m_axis_tready), // input wire m_axis_tready
.m_axis_tdata(m_axis_tdata), // output wire [7 : 0] m_axis_tdata
.m_axis_tlast(m_axis_tlast), // output wire m_axis_tlast
.m_axis_tdest(m_axis_tdest), // output wire [3 : 0] m_axis_tdest
.m_axis_tuser(m_axis_tuser) // output wire [0 : 0] m_axis_tuser
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file mac_fifo_axi4.v when simulating
// the core, mac_fifo_axi4. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.1
-- IP Revision: 3
-- The following code must appear in the VHDL architecture header.
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT mac_fifo_axi4
PORT (
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : mac_fifo_axi4
PORT MAP (
m_aclk => m_aclk,
s_aclk => s_aclk,
s_aresetn => s_aresetn,
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tlast => s_axis_tlast,
s_axis_tdest => s_axis_tdest,
s_axis_tuser => s_axis_tuser,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
m_axis_tlast => m_axis_tlast,
m_axis_tdest => m_axis_tdest,
m_axis_tuser => m_axis_tuser
);
-- INST_TAG_END ------ End INSTANTIATION Template ---------
-- You must compile the wrapper file mac_fifo_axi4.vhd when simulating
-- the core, mac_fifo_axi4. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
// Date : Thu Aug 17 14:07:30 2017
// Host : fortis.phy.bris.ac.uk running 64-bit Scientific Linux release 6.9 (Carbon)
// Command : write_verilog -force -mode synth_stub
// /users/phpgb/workspace/myFirmware/AIDA/TLU_v1e/work/TLU_v1e.srcs/sources_1/ip/mac_fifo_axi4/mac_fifo_axi4_stub.v
// Design : mac_fifo_axi4
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_1_3,Vivado 2016.4" *)
module mac_fifo_axi4(m_aclk, s_aclk, s_aresetn, s_axis_tvalid,
s_axis_tready, s_axis_tdata, s_axis_tlast, s_axis_tdest, s_axis_tuser, m_axis_tvalid,
m_axis_tready, m_axis_tdata, m_axis_tlast, m_axis_tdest, m_axis_tuser)
/* synthesis syn_black_box black_box_pad_pin="m_aclk,s_aclk,s_aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[7:0],s_axis_tlast,s_axis_tdest[3:0],s_axis_tuser[0:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[7:0],m_axis_tlast,m_axis_tdest[3:0],m_axis_tuser[0:0]" */;
input m_aclk;
input s_aclk;
input s_aresetn;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input s_axis_tlast;
input [3:0]s_axis_tdest;
input [0:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output m_axis_tlast;
output [3:0]m_axis_tdest;
output [0:0]m_axis_tuser;
endmodule
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Thu Aug 17 14:07:30 2017
-- Host : fortis.phy.bris.ac.uk running 64-bit Scientific Linux release 6.9 (Carbon)
-- Command : write_vhdl -force -mode synth_stub
-- /users/phpgb/workspace/myFirmware/AIDA/TLU_v1e/work/TLU_v1e.srcs/sources_1/ip/mac_fifo_axi4/mac_fifo_axi4_stub.vhdl
-- Design : mac_fifo_axi4
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mac_fifo_axi4 is
Port (
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tdest : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tdest : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end mac_fifo_axi4;
architecture stub of mac_fifo_axi4 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "m_aclk,s_aclk,s_aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[7:0],s_axis_tlast,s_axis_tdest[3:0],s_axis_tuser[0:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[7:0],m_axis_tlast,m_axis_tdest[3:0],m_axis_tuser[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v13_1_3,Vivado 2016.4";
begin
end;
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:tri_mode_ethernet_mac:9.0
// IP Revision: 6
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
temac_gbe_v9_rgmii your_instance_name (
.gtx_clk(gtx_clk), // input wire gtx_clk
.gtx_clk90(gtx_clk90), // input wire gtx_clk90
.glbl_rstn(glbl_rstn), // input wire glbl_rstn
.rx_axi_rstn(rx_axi_rstn), // input wire rx_axi_rstn
.tx_axi_rstn(tx_axi_rstn), // input wire tx_axi_rstn
.rx_statistics_vector(rx_statistics_vector), // output wire [27 : 0] rx_statistics_vector
.rx_statistics_valid(rx_statistics_valid), // output wire rx_statistics_valid
.rx_mac_aclk(rx_mac_aclk), // output wire rx_mac_aclk
.rx_reset(rx_reset), // output wire rx_reset
.rx_axis_mac_tdata(rx_axis_mac_tdata), // output wire [7 : 0] rx_axis_mac_tdata
.rx_axis_mac_tvalid(rx_axis_mac_tvalid), // output wire rx_axis_mac_tvalid
.rx_axis_mac_tlast(rx_axis_mac_tlast), // output wire rx_axis_mac_tlast
.rx_axis_mac_tuser(rx_axis_mac_tuser), // output wire rx_axis_mac_tuser
.tx_ifg_delay(tx_ifg_delay), // input wire [7 : 0] tx_ifg_delay
.tx_statistics_vector(tx_statistics_vector), // output wire [31 : 0] tx_statistics_vector
.tx_statistics_valid(tx_statistics_valid), // output wire tx_statistics_valid
.tx_mac_aclk(tx_mac_aclk), // output wire tx_mac_aclk
.tx_reset(tx_reset), // output wire tx_reset
.tx_axis_mac_tdata(tx_axis_mac_tdata), // input wire [7 : 0] tx_axis_mac_tdata
.tx_axis_mac_tvalid(tx_axis_mac_tvalid), // input wire tx_axis_mac_tvalid
.tx_axis_mac_tlast(tx_axis_mac_tlast), // input wire tx_axis_mac_tlast
.tx_axis_mac_tuser(tx_axis_mac_tuser), // input wire [0 : 0] tx_axis_mac_tuser
.tx_axis_mac_tready(tx_axis_mac_tready), // output wire tx_axis_mac_tready
.pause_req(pause_req), // input wire pause_req
.pause_val(pause_val), // input wire [15 : 0] pause_val
.speedis100(speedis100), // output wire speedis100
.speedis10100(speedis10100), // output wire speedis10100
.rgmii_txd(rgmii_txd), // output wire [3 : 0] rgmii_txd
.rgmii_tx_ctl(rgmii_tx_ctl), // output wire rgmii_tx_ctl
.rgmii_txc(rgmii_txc), // output wire rgmii_txc
.rgmii_rxd(rgmii_rxd), // input wire [3 : 0] rgmii_rxd
.rgmii_rx_ctl(rgmii_rx_ctl), // input wire rgmii_rx_ctl
.rgmii_rxc(rgmii_rxc), // input wire rgmii_rxc
.inband_link_status(inband_link_status), // output wire inband_link_status
.inband_clock_speed(inband_clock_speed), // output wire [1 : 0] inband_clock_speed
.inband_duplex_status(inband_duplex_status), // output wire inband_duplex_status
.rx_configuration_vector(rx_configuration_vector), // input wire [79 : 0] rx_configuration_vector
.tx_configuration_vector(tx_configuration_vector) // input wire [79 : 0] tx_configuration_vector
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file temac_gbe_v9_rgmii.v when simulating
// the core, temac_gbe_v9_rgmii. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:tri_mode_ethernet_mac:9.0
-- IP Revision: 6
-- The following code must appear in the VHDL architecture header.
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT temac_gbe_v9_rgmii
PORT (
gtx_clk : IN STD_LOGIC;
gtx_clk90 : IN STD_LOGIC;
glbl_rstn : IN STD_LOGIC;
rx_axi_rstn : IN STD_LOGIC;
tx_axi_rstn : IN STD_LOGIC;
rx_statistics_vector : OUT STD_LOGIC_VECTOR(27 DOWNTO 0);
rx_statistics_valid : OUT STD_LOGIC;
rx_mac_aclk : OUT STD_LOGIC;
rx_reset : OUT STD_LOGIC;
rx_axis_mac_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
rx_axis_mac_tvalid : OUT STD_LOGIC;
rx_axis_mac_tlast : OUT STD_LOGIC;
rx_axis_mac_tuser : OUT STD_LOGIC;
tx_ifg_delay : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
tx_statistics_vector : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
tx_statistics_valid : OUT STD_LOGIC;
tx_mac_aclk : OUT STD_LOGIC;
tx_reset : OUT STD_LOGIC;
tx_axis_mac_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
tx_axis_mac_tvalid : IN STD_LOGIC;
tx_axis_mac_tlast : IN STD_LOGIC;
tx_axis_mac_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
tx_axis_mac_tready : OUT STD_LOGIC;
pause_req : IN STD_LOGIC;
pause_val : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
speedis100 : OUT STD_LOGIC;
speedis10100 : OUT STD_LOGIC;
rgmii_txd : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rgmii_tx_ctl : OUT STD_LOGIC;
rgmii_txc : OUT STD_LOGIC;
rgmii_rxd : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rgmii_rx_ctl : IN STD_LOGIC;
rgmii_rxc : IN STD_LOGIC;
inband_link_status : OUT STD_LOGIC;
inband_clock_speed : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
inband_duplex_status : OUT STD_LOGIC;
rx_configuration_vector : IN STD_LOGIC_VECTOR(79 DOWNTO 0);
tx_configuration_vector : IN STD_LOGIC_VECTOR(79 DOWNTO 0)
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : temac_gbe_v9_rgmii
PORT MAP (
gtx_clk => gtx_clk,
gtx_clk90 => gtx_clk90,
glbl_rstn => glbl_rstn,
rx_axi_rstn => rx_axi_rstn,
tx_axi_rstn => tx_axi_rstn,
rx_statistics_vector => rx_statistics_vector,
rx_statistics_valid => rx_statistics_valid,
rx_mac_aclk => rx_mac_aclk,
rx_reset => rx_reset,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tuser => rx_axis_mac_tuser,
tx_ifg_delay => tx_ifg_delay,
tx_statistics_vector => tx_statistics_vector,
tx_statistics_valid => tx_statistics_valid,
tx_mac_aclk => tx_mac_aclk,
tx_reset => tx_reset,
tx_axis_mac_tdata => tx_axis_mac_tdata,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tuser => tx_axis_mac_tuser,
tx_axis_mac_tready => tx_axis_mac_tready,
pause_req => pause_req,
pause_val => pause_val,
speedis100 => speedis100,
speedis10100 => speedis10100,
rgmii_txd => rgmii_txd,
rgmii_tx_ctl => rgmii_tx_ctl,
rgmii_txc => rgmii_txc,
rgmii_rxd => rgmii_rxd,
rgmii_rx_ctl => rgmii_rx_ctl,
rgmii_rxc => rgmii_rxc,
inband_link_status => inband_link_status,
inband_clock_speed => inband_clock_speed,
inband_duplex_status => inband_duplex_status,
rx_configuration_vector => rx_configuration_vector,
tx_configuration_vector => tx_configuration_vector
);
-- INST_TAG_END ------ End INSTANTIATION Template ---------
-- You must compile the wrapper file temac_gbe_v9_rgmii.vhd when simulating
-- the core, temac_gbe_v9_rgmii. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
// Date : Thu Aug 17 17:25:22 2017
// Host : fortis.phy.bris.ac.uk running 64-bit Scientific Linux release 6.9 (Carbon)
// Command : write_verilog -force -mode synth_stub
// /users/phpgb/workspace/myFirmware/AIDA/TLU_v1e/work/TLU_v1e.srcs/sources_1/ip/temac_gbe_v9_rgmii/temac_gbe_v9_rgmii_stub.v
// Design : temac_gbe_v9_rgmii
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "tri_mode_ethernet_mac_v9_0_6,Vivado 2016.4" *)
module temac_gbe_v9_rgmii(gtx_clk, gtx_clk90, glbl_rstn, rx_axi_rstn,
tx_axi_rstn, rx_statistics_vector, rx_statistics_valid, rx_mac_aclk, rx_reset,
rx_axis_mac_tdata, rx_axis_mac_tvalid, rx_axis_mac_tlast, rx_axis_mac_tuser,
tx_ifg_delay, tx_statistics_vector, tx_statistics_valid, tx_mac_aclk, tx_reset,
tx_axis_mac_tdata, tx_axis_mac_tvalid, tx_axis_mac_tlast, tx_axis_mac_tuser,
tx_axis_mac_tready, pause_req, pause_val, speedis100, speedis10100, rgmii_txd, rgmii_tx_ctl,
rgmii_txc, rgmii_rxd, rgmii_rx_ctl, rgmii_rxc, inband_link_status, inband_clock_speed,
inband_duplex_status, rx_configuration_vector, tx_configuration_vector)
/* synthesis syn_black_box black_box_pad_pin="gtx_clk,gtx_clk90,glbl_rstn,rx_axi_rstn,tx_axi_rstn,rx_statistics_vector[27:0],rx_statistics_valid,rx_mac_aclk,rx_reset,rx_axis_mac_tdata[7:0],rx_axis_mac_tvalid,rx_axis_mac_tlast,rx_axis_mac_tuser,tx_ifg_delay[7:0],tx_statistics_vector[31:0],tx_statistics_valid,tx_mac_aclk,tx_reset,tx_axis_mac_tdata[7:0],tx_axis_mac_tvalid,tx_axis_mac_tlast,tx_axis_mac_tuser,tx_axis_mac_tready,pause_req,pause_val[15:0],speedis100,speedis10100,rgmii_txd[3:0],rgmii_tx_ctl,rgmii_txc,rgmii_rxd[3:0],rgmii_rx_ctl,rgmii_rxc,inband_link_status,inband_clock_speed[1:0],inband_duplex_status,rx_configuration_vector[79:0],tx_configuration_vector[79:0]" */;
input gtx_clk;
input gtx_clk90;
input glbl_rstn;
input rx_axi_rstn;
input tx_axi_rstn;
output [27:0]rx_statistics_vector;
output rx_statistics_valid;
output rx_mac_aclk;
output rx_reset;
output [7:0]rx_axis_mac_tdata;
output rx_axis_mac_tvalid;
output rx_axis_mac_tlast;
output rx_axis_mac_tuser;
input [7:0]tx_ifg_delay;
output [31:0]tx_statistics_vector;
output tx_statistics_valid;
output tx_mac_aclk;
output tx_reset;
input [7:0]tx_axis_mac_tdata;
input tx_axis_mac_tvalid;
input tx_axis_mac_tlast;
input tx_axis_mac_tuser;
output tx_axis_mac_tready;
input pause_req;
input [15:0]pause_val;
output speedis100;
output speedis10100;
output [3:0]rgmii_txd;
output rgmii_tx_ctl;
output rgmii_txc;
input [3:0]rgmii_rxd;
input rgmii_rx_ctl;
input rgmii_rxc;
output inband_link_status;
output [1:0]inband_clock_speed;
output inband_duplex_status;
input [79:0]rx_configuration_vector;
input [79:0]tx_configuration_vector;
endmodule
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Thu Aug 17 17:25:22 2017
-- Host : fortis.phy.bris.ac.uk running 64-bit Scientific Linux release 6.9 (Carbon)
-- Command : write_vhdl -force -mode synth_stub
-- /users/phpgb/workspace/myFirmware/AIDA/TLU_v1e/work/TLU_v1e.srcs/sources_1/ip/temac_gbe_v9_rgmii/temac_gbe_v9_rgmii_stub.vhdl
-- Design : temac_gbe_v9_rgmii
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity temac_gbe_v9_rgmii is
Port (
gtx_clk : in STD_LOGIC;
gtx_clk90 : in STD_LOGIC;
glbl_rstn : in STD_LOGIC;
rx_axi_rstn : in STD_LOGIC;
tx_axi_rstn : in STD_LOGIC;
rx_statistics_vector : out STD_LOGIC_VECTOR ( 27 downto 0 );
rx_statistics_valid : out STD_LOGIC;
rx_mac_aclk : out STD_LOGIC;
rx_reset : out STD_LOGIC;
rx_axis_mac_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
rx_axis_mac_tvalid : out STD_LOGIC;
rx_axis_mac_tlast : out STD_LOGIC;
rx_axis_mac_tuser : out STD_LOGIC;
tx_ifg_delay : in STD_LOGIC_VECTOR ( 7 downto 0 );
tx_statistics_vector : out STD_LOGIC_VECTOR ( 31 downto 0 );
tx_statistics_valid : out STD_LOGIC;
tx_mac_aclk : out STD_LOGIC;
tx_reset : out STD_LOGIC;
tx_axis_mac_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
tx_axis_mac_tvalid : in STD_LOGIC;
tx_axis_mac_tlast : in STD_LOGIC;
tx_axis_mac_tuser : in STD_LOGIC;
tx_axis_mac_tready : out STD_LOGIC;
pause_req : in STD_LOGIC;
pause_val : in STD_LOGIC_VECTOR ( 15 downto 0 );
speedis100 : out STD_LOGIC;
speedis10100 : out STD_LOGIC;
rgmii_txd : out STD_LOGIC_VECTOR ( 3 downto 0 );
rgmii_tx_ctl : out STD_LOGIC;
rgmii_txc : out STD_LOGIC;
rgmii_rxd : in STD_LOGIC_VECTOR ( 3 downto 0 );
rgmii_rx_ctl : in STD_LOGIC;
rgmii_rxc : in STD_LOGIC;
inband_link_status : out STD_LOGIC;
inband_clock_speed : out STD_LOGIC_VECTOR ( 1 downto 0 );
inband_duplex_status : out STD_LOGIC;
rx_configuration_vector : in STD_LOGIC_VECTOR ( 79 downto 0 );
tx_configuration_vector : in STD_LOGIC_VECTOR ( 79 downto 0 )
);
end temac_gbe_v9_rgmii;
architecture stub of temac_gbe_v9_rgmii is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "gtx_clk,gtx_clk90,glbl_rstn,rx_axi_rstn,tx_axi_rstn,rx_statistics_vector[27:0],rx_statistics_valid,rx_mac_aclk,rx_reset,rx_axis_mac_tdata[7:0],rx_axis_mac_tvalid,rx_axis_mac_tlast,rx_axis_mac_tuser,tx_ifg_delay[7:0],tx_statistics_vector[31:0],tx_statistics_valid,tx_mac_aclk,tx_reset,tx_axis_mac_tdata[7:0],tx_axis_mac_tvalid,tx_axis_mac_tlast,tx_axis_mac_tuser,tx_axis_mac_tready,pause_req,pause_val[15:0],speedis100,speedis10100,rgmii_txd[3:0],rgmii_tx_ctl,rgmii_txc,rgmii_rxd[3:0],rgmii_rx_ctl,rgmii_rxc,inband_link_status,inband_clock_speed[1:0],inband_duplex_status,rx_configuration_vector[79:0],tx_configuration_vector[79:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "tri_mode_ethernet_mac_v9_0_6,Vivado 2016.4";
begin
end;
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fifo_generator:13.1
// IP Revision: 3
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
tlu_event_fifo your_instance_name (
.rst(rst), // input wire rst
.wr_clk(wr_clk), // input wire wr_clk
.rd_clk(rd_clk), // input wire rd_clk
.din(din), // input wire [63 : 0] din
.wr_en(wr_en), // input wire wr_en
.rd_en(rd_en), // input wire rd_en
.dout(dout), // output wire [31 : 0] dout
.full(full), // output wire full
.almost_full(almost_full), // output wire almost_full
.empty(empty), // output wire empty
.almost_empty(almost_empty), // output wire almost_empty
.rd_data_count(rd_data_count), // output wire [13 : 0] rd_data_count
.prog_full(prog_full) // output wire prog_full
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file tlu_event_fifo.v when simulating
// the core, tlu_event_fifo. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.1
-- IP Revision: 3
-- The following code must appear in the VHDL architecture header.
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT tlu_event_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
prog_full : OUT STD_LOGIC
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : tlu_event_fifo
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
almost_full => almost_full,
empty => empty,
almost_empty => almost_empty,
rd_data_count => rd_data_count,
prog_full => prog_full
);
-- INST_TAG_END ------ End INSTANTIATION Template ---------
-- You must compile the wrapper file tlu_event_fifo.vhd when simulating
-- the core, tlu_event_fifo. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
// Date : Thu Aug 17 13:46:46 2017
// Host : fortis.phy.bris.ac.uk running 64-bit Scientific Linux release 6.9 (Carbon)
// Command : write_verilog -force -mode synth_stub
// /users/phpgb/workspace/myFirmware/AIDA/TLU_v1e/work/TLU_v1e.srcs/sources_1/ip/tlu_event_fifo/tlu_event_fifo_stub.v
// Design : tlu_event_fifo
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_1_3,Vivado 2016.4" *)
module tlu_event_fifo(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full,
almost_full, empty, almost_empty, rd_data_count, prog_full)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[63:0],wr_en,rd_en,dout[31:0],full,almost_full,empty,almost_empty,rd_data_count[13:0],prog_full" */;
input rst;
input wr_clk;
input rd_clk;
input [63:0]din;
input wr_en;
input rd_en;
output [31:0]dout;
output full;
output almost_full;
output empty;
output almost_empty;
output [13:0]rd_data_count;
output prog_full;
endmodule
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Thu Aug 17 13:46:46 2017
-- Host : fortis.phy.bris.ac.uk running 64-bit Scientific Linux release 6.9 (Carbon)
-- Command : write_vhdl -force -mode synth_stub
-- /users/phpgb/workspace/myFirmware/AIDA/TLU_v1e/work/TLU_v1e.srcs/sources_1/ip/tlu_event_fifo/tlu_event_fifo_stub.vhdl
-- Design : tlu_event_fifo
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tlu_event_fifo is
Port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 13 downto 0 );
prog_full : out STD_LOGIC
);
end tlu_event_fifo;
architecture stub of tlu_event_fifo is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[63:0],wr_en,rd_en,dout[31:0],full,almost_full,empty,almost_empty,rd_data_count[13:0],prog_full";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v13_1_3,Vivado 2016.4";
begin
end;
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