Commit fb4c9076 authored by Paolo Baesso's avatar Paolo Baesso

Updated trigger section. Clean-up

parent feddce19
\chapter{DUT Signals}\label{ch:DUTsignals}
In the older, EUDET, version of the \gls{tlu} the direction of the signals on the \verb|HDMI*| connectors were pre-defined. The new hardware has the ability to switch each LVDS pair between input and output. The function and direction of each LVDS pair depends on the interface mode chosen. Table \ref{tab:DUTInterfaceModes} lists the different interface modes and section~\ref{sec:InterfaceModes} describes them in more detail. See chapter~\ref{ch:hwDUT} for details of how LVDS pairs are mapped onto physical \gls{hdmi} pins.
In the older, EUDET, version of the \gls{tlu} the direction of the signals on the \verb|HDMI*| connectors were pre-defined. The new hardware has the ability to switch each \gls{lvds} pair between input and output.\\
The function and direction of each \gls{lvds} pair depends on the interface mode chosen. Table \ref{tab:DUTInterfaceModes} lists the different interface modes and section~\ref{sec:InterfaceModes} describes them in more detail. See chapter~\ref{ch:hwDUT} for details of how \gls{lvds} pairs are mapped onto physical \gls{hdmi} pins.
%separate lines for signals going into the \gls{tlu} and signals out of the \gls{tlu}. See section~\ref{ch:hw\gls{dut}} for further details. \\
......@@ -10,46 +11,47 @@ There are four different handshake modes, described below:
\subsection{Trigger/Busy (EUDET) Mode}
This mode is designed to allow the \gls{tlu} and \gls{dut} clocks to be asynchronous and to have any frequency relationship. After the \gls{tlu} detects an input trigger the TRIGGER signal to the \gls{dut} is asserted and the \gls{tlu} vetoes further triggers. The \gls{dut} responds by asserting the BUSY line to the \gls{tlu}. The \gls{tlu} detects that the BUSY line has been asserted and responds by de-asserting the trigger line. Finally the \gls{dut} responds by de-asserting the BUSY line. When the \gls{tlu} detects that the BUSY has been de-asserted it re-enables triggers. Figure \ref{fig:eudet-trigger-busy} shows signal timing for this interface mode.
\begin{figure}
This mode is designed to allow the \gls{tlu} and \gls{dut} clocks to be asynchronous and to have any frequency relationship.\\
After the \gls{tlu} detects an input trigger, the TRIGGER signal to the \gls{dut} is asserted and the \gls{tlu} vetoes further triggers.\\
The \gls{dut} responds by asserting the BUSY line to the \gls{tlu}.
The \gls{tlu} detects that the BUSY line has been asserted and responds by de-asserting the trigger line.
Finally the \gls{dut} responds by de-asserting the BUSY line.\\
When the \gls{tlu} detects that the BUSY has been de-asserted it re-enables triggers.\\
Figure \ref{fig:eudet-trigger-busy} shows signal timing for this interface mode.
\begin{figure}[h]
\centering
\includegraphics[width=0.95\linewidth]{./Images/aida-tlu-eudet-trigger-busy_01.pdf}
\caption{Trigger/Busy Interface Mode Timing}
\label{fig:eudet-trigger-busy}
\end{figure}
\subsection{Trigger/Busy Handshake With Trigger Number}
This interface mode is an extension of the Trigger/Busy handshake. After the \gls{dut} detects that the \gls{tlu} has de-asserted the TRIGGER line it can cause the \gls{tlu} to clock out the current trigger number by toggling the DUT-Clock line. Figure ~\ref{fig:eudet-trigger-busy-trignumber} shows the signal timing for this interface mode.
\end{figure}
\begin{figure}
\subsection{Trigger/Busy Handshake With Trigger Number}
This interface mode is an extension of the Trigger/Busy handshake.\\
After the \gls{dut} detects that the \gls{tlu} has de-asserted the TRIGGER line it can cause the \gls{tlu} to clock out the current trigger number by toggling the DUT-Clock line. Figure ~\ref{fig:eudet-trigger-busy-trignumber} shows the signal timing for this interface mode.
\begin{figure}[h]
\centering
\includegraphics[width=0.95\linewidth]{./Images/aida-tlu-eudet-trigger-busy_trignumber_01.pdf}
\caption{Trigger/Busy Interface Mode With Trigger Number }
\label{fig:eudet-trigger-busy-trignumber}
\end{figure}
\subsection{Synchronous (AIDA) Mode}
In synchronous mode (also known as AIDA mode) the \gls{tlu} sends a clock (by default 40MHz) to the \gls{dut}. When the \gls{tlu} produces a trigger the trigger line from \gls{tlu} to \gls{dut} is asserted for one cycle of the clock. In order to synchronize time-stamps between \gls{tlu} to \gls{dut} a single cycle timestamp reset signal is issued at the start of each run. The \gls{dut} can veto triggers at any point by asserting the BUSY line. Figure~\ref{fig:aida-handshake} shows the signal timing for this interface mode.
\end{figure}
\begin{figure}
\subsection{Synchronous (AIDA) Mode}
In synchronous mode (also known as AIDA mode) the \gls{tlu} sends a clock (by default 40MHz) to the \gls{dut}.\\
When the \gls{tlu} produces a trigger, the trigger line from \gls{tlu} to \gls{dut} is asserted for one cycle of the clock. In order to synchronize time-stamps between \gls{tlu} to \gls{dut} a single cycle timestamp reset signal is issued at the start of each run.\\
The \gls{dut} can veto triggers at any point by asserting the BUSY line. Figure~\ref{fig:aida-handshake} shows the signal timing for this interface mode.
\begin{figure}[h]
\centering
\includegraphics[width=0.95\linewidth]{./Images/aida-tlu-aida-interface_01.pdf}
\caption{Synchronous (AIDA) Interface Mode }
\label{fig:aida-handshake}
\end{figure}
\subsection{Synchronous Mode With Trigger Number}
This is a modification of the synchronous/AIDA mode. Immediately after the TLU issues a trigger it clocks out the trigger number (least significant bit first) on the Sync/T0 line. Figure~\ref{fig:aida-handshake-with-trigger} shows the signal timing for this interface mode.
\end{figure}
\begin{figure}
\subsection{Synchronous Mode With Trigger Number}
This is a modification of the synchronous/AIDA mode.\\
Immediately after the \gls{tlu} issues a trigger, it clocks out the trigger number (\gls{lsb} first) on the Sync/T0 line. Figure~\ref{fig:aida-handshake-with-trigger} shows the signal timing for this interface mode.
\begin{figure}[h]
\centering
\includegraphics[width=0.95\linewidth]{./Images/aida-tlu-aida-with-trigger-timing_01.pdf}
\caption{Synchronous (AIDA) Interface Mode With Trigger Number }
\label{fig:aida-handshake-with-trigger}
\end{figure}
\ No newline at end of file
\end{figure}
\ No newline at end of file
......@@ -11,7 +11,7 @@ Not all parameters are needed; if one of the parameters is not present in the fi
\begin{alertinfo}{Case sensitiveness}
All parameters names are case sensitive!\\
Please ensure to use the correct capitalization.\\
A misspelled parameter will be ignored and its default value will be used instead.
A misspelled parameter will be ignored and its default value will be used instead. EUDAQ does not provide any warning or feedback about this, so extra care should be used to avoid unexpected results.
\end{alertinfo}
\section{INI file}
......
......@@ -4,6 +4,7 @@ Board \brd is an evolution of the miniTLU designed at the \gls{uob}. The board s
\section{Inputs and interfaces}\label{ch:hwDUT}
\subsubsection{FMC}
The board must be plugged onto a \gls{fmc} carrier board with an \gls{fpga} in order to function correctly. The connection is achieved using a low pin count \gls{fmc} connector. The list of the pins used and the corresponding signal within the \gls{fpga} are provided in appendix at page~\pageref{ch:appendix}.\\
In normal conditions (such as a test beam) this connector is not accessible to users.
\subsubsection{Device under test}\label{ch:dut}
The \gls{dut}s are connected to the \gls{tlu} using standard size \gls{hdmi} connectors\footnote{In the miniTLU hardware these were mini \gls{hdmi} connectors.}.\\
......@@ -70,7 +71,7 @@ As for the differential pairs of the \gls{dut}s, the pins of this connector are
\section{Trigger inputs}
Board \brd can accept up to six trigger inputs over the LEMO connectors labelled \verb|IN_1|, \verb|IN_2|, \verb|IN_3|, \verb|IN_4|, \verb|IN_5| and \verb|IN_6|. The \brd uses internal high-speed\footnote{500$\pm$30~ps propagation delay.} discriminators to detect a valid trigger signal. The voltage thresholds can be adjusted independently for each input in a range from -1.3~V to +1.3~V with 40~$\mu$V resolution.\\
The adjustment is performed by writing to two 16-bit \gls{dac}s via \gls{i2c} interface as described in section~\ref{ch:i2c}.\\
The \gls{dac}s can either use an internal reference voltage of 2.5~V or an external one of 1.3~V provided by the \gls{tlu}: it is recommended to choose the external one by configuring the appropriate register in the devices.\\
The \gls{dac}s can either use an internal reference voltage of 2.5~V or an external one of 1.3~V provided by the \gls{tlu}: it is recommended to choose the external one by configuring the appropriate register in the devices. This is the default option when operating within the AIDA2020 framework.\\
The correspondence between DAC slave and thresholds is shown in table~\ref{tab:DACOutputs}.
\begin{table}[]
\centering
......
......@@ -78,7 +78,11 @@ At the moment of shipping, each \gls{tlu} is pre-configured with the most recent
\item Plug an Ethernet cable in the RJ45 socket located on the back panel and connect it to the computer used to run the control software. Note that currently the unit uses a pre-defined IP address of 192.168.200.30. In future version of the firmware the address will be configurable. Try to ping the IP address of the unit: if the unit responds then the firmware is correctly loaded.
\item Use the control software to configure the unit. In particular, after each power up it is necessary to re-configure the clock chip. See chapter~\ref{ch:controlsw} for details on the software and chapter~\ref{ch:clock} for details on the clock chip.
\end{enumerate}
\begin{alertinfo}{Communication with the \gls{tlu}}
The only way to communicate with the unit is over IPBus protocol and via the RJ45 connector located on the back panel of the \gls{tlu}.\\
\end{alertinfo}
\newpage
\section{FPGA and firmware}\label{ch:fpgahardware}
The firmware developed at University of Bristol is targeted to work with the Enclustra AX3 board, which must be plugged onto a PM3 base, also produced by \href{http://www.enclustra.com/en/home/}{Enclustra}. The firmware is loaded on the \gls{fpga} using a \gls{jtag} interface. Typically a breakout board will be required to connect the Xilinx programming cable to the Enclustra PM3. All these components are included in the \gls{tlu} enclosure so the user can upload a new version of the firmware by simply connecting a \gls{usb}-B cable in the back panel of the unit.\\
At the time of writing this document\footnote{\monthyeardate\today} the AX3 is the only \gls{fpga} for which a firmware has been developed.\\
......@@ -130,8 +134,9 @@ This will open a new window, shown in figure~\ref{fig:hw_eeprom}, from which it
Make sure that the options are set as shown in figure~\ref{fig:hw_eeprom}.\\
The firmware loaded this way will overwrite any pre-existing firmware and will be loaded automatically whenever the unit is powered up.
\newpage
\section{Inspection (table top unit)}\label{ch:inspection}
The top cover of the unit can only slide away when either the front or back frame are removed.
Accessing the internal electronics of the unit requires removing the top cover of the enclosure; this can only slide away when either the front or back frame are removed.
\begin{alertinfo}{Note}
Simply removing the corner screws on the panels will only allow to remove the plates but not accessing the inside of the unit.
\end{alertinfo}
......
\chapter{Trigger inputs}\label{ch:triggerinputs}
The six inputs on the \gls{tlu} can be used to generate a global trigger that is then issued to all the \gls{dut}s.\\
Each input has a programmable voltage discriminator that can be configured in the range [-1.3 : 1.3]~V.\\
All the inputs are protected by clamping diodes that limit the input voltage in the range [-5 : +5]~V. The discriminators are followed by edge-finding and TDC logic. The output of the edge finding logic is fed into logic to stretch and delay the pulses by a controllable amount. The stretched and delayed trigger pulses are fed into a look-up table that generates the triggers. Figure~\ref{fig:aida-tlu-trigger-path} illustrates the path of the trigger signals through the TLU.
All the inputs are protected by clamping diodes that limit the input voltage in the range [-5 : +5]~V.\\
The discriminators are followed by edge-finding and TDC logic. Currently only negative edges are registered. A future firmware version will implement user-selectable positive or negative edge detection.\\
The output of the edge finding logic is fed into logic to stretch and delay the pulses by a controllable amount. The stretched and delayed trigger pulses are fed into a look-up table that generates the triggers. Figure~\ref{fig:aida-tlu-trigger-path} illustrates the path of the trigger signals through the \gls{tlu}.
\begin{figure}
\centering
......@@ -155,14 +157,14 @@ In order to ensure that the signals overlap adequately, we use the \emph{stretch
We can now define the trigger logic to be used to assert a valid trigger: we only consider the lower 32-bits of the trigger word and see how different values can produce very different results.
\begin{itemize}
\item Trigger \gls{lsb} word= 0x00020000. This indicates that the only valid trigger combination occurs when both \verb|IN_1| and \verb|IN_5| are high. The valid trigger goes high 1 clock cycle after this condition is met and remains high up to 1 clock cycle after the condition is no longer valid. This is illustrated in figure~\ref{Fig:exampleTrig00020000}.
\begin{figure}
\begin{figure}[h]
\centering
\includegraphics[width=.99\textwidth]{./Images/Trigger0x00020000.png}
\caption{Trigger configuration 0x00020000. The valid trigger (blue) is asserted only when both signals are high. This condition occurs at frame 39. The trigger is asserted on the following frame.}
\label{Fig:exampleTrig00020000}
\end{figure}\\
\item Trigger \gls{lsb} word= 0x00020002. This indicates that a valid trigger is achieved in two separated configurations (in logic OR): when both inputs are high at the same time (as in the previous case) or if \verb|IN_1| is active on its own. This is illustrated in figure~\ref{Fig:exampleTrig00020002}. It can be seen that the valid trigger is asserted immediately one clock cycle after \verb|IN_1| is high and remains high as long as this condition is met. One might assume that specifying the combination with \verb|IN_5| is redundant, but the following example should show that this is not the case.
\begin{figure}
\begin{figure}[h]
\centering
\includegraphics[width=.99\textwidth]{./Images/Trigger0x00020002.png}
\caption{Trigger configuration 0x00020002. The valid trigger (blue) is asserted if \texttt{IN\_1} is high OR when \texttt{IN\_1} and \texttt{IN\_5} are both high at the same time.}
......@@ -170,7 +172,7 @@ We can now define the trigger logic to be used to assert a valid trigger: we onl
\end{figure}\\
\item Trigger \gls{lsb} word= 0x00000002. This indicates that the only valid configuration is the one where only \verb|IN_1| is high. It is important to understand that in this configuration all other inputs act as veto. This might produce unexpected results if the user is not careful\footnote{Specifically, pulse stretch, pulse delay and trigger logic must be configured correctly to avoid unwanted results.}.\\
In figure~\ref{Fig:exampleTrig00000002} it is possible to see that the logic produces two separated trigger valid pulses, both shorter than the ones in previous examples: the first one is due to \verb|IN_1| going high while \verb|IN_5| is low. As soon as \verb|IN_5| goes high, the trigger condition is no longer met. When \verb|IN_5| returns low, a trigger condition is met again because \verb|IN_1| is still high. In this specific case, the double pulse is caused by the different width of the pulses.
\begin{figure}
\begin{figure}[h]
\centering
\includegraphics[width=.99\textwidth]{./Images/Trigger0x00000002.png}
\caption{Trigger configuration 0x00000002. The valid trigger (blue) is asserted only when \texttt{IN\_1} is active on its own. As such, two separated trigger pulses are produced because \texttt{IN\_5} goes high and returns low before \texttt{IN\_1}.}
......@@ -179,10 +181,11 @@ We can now define the trigger logic to be used to assert a valid trigger: we onl
\end{itemize}
\section{Stretch and delay}
The trigger logic is designed to detect edge transitions\footnote{Currently only negative edges are registered. A future firmware version will implement user-selectable positive or negative edge detection.} at the trigger inputs and produce a pulse for each transition detected. The pulse has an initial duration of one clock cycle (f= 160~MHz, one cycle 6.25~ns) and occurs on the next rising edge of the 160~MHz internal clock.\\
Each pulse can be stretched and delayed in integer numbers of clock cycles to compensate for differences in cable length. Two separate 5-bit registers are used for the task: the value written in the registers will stretch/delay the pulse by a corresponding number of clock cycles.\\
The trigger logic is designed to detect edge transitions at the trigger inputs and produce a pulse for each transition detected.\\
The pulse has an initial duration of one clock cycle (f= 160~MHz, one cycle 6.25~ns) and occurs on the next rising edge of the 160~MHz internal clock.\\
Each pulse can be stretched and delayed in integer numbers of clock cycles (25~ns by default) to compensate for differences in cable length. Two separate 5-bit registers are used for the task: the value written in the registers will stretch/delay the pulse by a corresponding number of clock cycles.\\
Diagram~\ref{Fig:trigger_stretchdelay} shows the effect of the delay and stretch words on the trigger logic.
\begin{figure}
\begin{figure}[h]
\centering
\includegraphics[width=.95\textwidth]{./Images/tlu_trigger_logic.pdf}
%\includesvg[width=.90\textwidth]{./Images/tlu_trigger_logic.svg}
......
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