fmc-nanofip issueshttps://ohwr.org/project/fmc-nanofip/issues2023-06-08T12:32:22Zhttps://ohwr.org/project/fmc-nanofip/issues/62TPS7A49 packaging2023-06-08T12:32:22ZEvangelia GousiouTPS7A49 packagingAs suggested by Volker's analysis, consider DRB packaging that offers improved thermal resistance: 47.7°C/W
https://edms.cern.ch/document/2681112/1https://ohwr.org/project/fmc-nanofip/issues/59LED resistors power dissipation2023-06-08T12:36:34ZEvangelia GousiouLED resistors power dissipationR35, R38 are 0603 so their power dissipation should be around 30mW. Would it be possible to consider the option to use the 0805 package to have more margin?
I have calculated with the MIL-HDBK-217F the MTTF of a 100mW resistor working at 30mW while the ambient temperature is about 25°C and it is about 12.5 Years.
By reducing the stress level you could earn a couple of years more, so it should be evaluated the global failure rate contribution when all boards will be installed. [William]https://ohwr.org/project/fmc-nanofip/issues/58Stubs2022-03-08T17:54:09ZEvangelia GousiouStubsL8 has several abandoned “islands” and “stubs” which are the result of the automatic process so it should be better to pay a lot of attention and clean them up.
Foe example:
![image](/uploads/bb26cc9f227967ea9194acc001dfe299/image.png)https://ohwr.org/project/fmc-nanofip/issues/57Ground Loop2022-03-08T17:52:46ZEvangelia GousiouGround LoopL3 has a big ground loop because on the lower side of the PCB there is a leftover of a connection. I strongly recommend you to correct it.
![image](/uploads/6db6525e156f2c0c69e04193ca5917e6/image.png)https://ohwr.org/project/fmc-nanofip/issues/56Minor detail about straight traces2022-03-17T17:55:27ZEvangelia GousiouMinor detail about straight tracesThis is a minor detail but, for the traces below in the figure showing L3, if there is enough space, it may be better to make them straight to avoid any little problem during etching process of pcb manufacturing.
![image](/uploads/a855b409d3612fde16ba38059ae1b126/image.png)https://ohwr.org/project/fmc-nanofip/issues/55Separation of traces at least 3xWidth2022-03-17T17:50:06ZEvangelia GousiouSeparation of traces at least 3xWidthIf possible, for traces carrying dynamic signals, separation of traces at least 3xWidth of Signal is recommended. Especially for Rx and Tx signals , it is important to have this separation to avoid crosstalk. (Figure on the left from bottom layer, figure on the right from L3)
![image](/uploads/50f29ebe64f5656a8f00b259942c72c5/image.png)https://ohwr.org/project/fmc-nanofip/issues/54TPS7A4901DBR correct reference TPS7A4901DRBR2022-03-08T17:40:00ZEvangelia GousiouTPS7A4901DBR correct reference TPS7A4901DRBRTPS7A4901DBR correct reference is TPS7A4901D*R*BRhttps://ohwr.org/project/fmc-nanofip/issues/53Keep-out zones for copper planes for EMC2022-03-08T17:31:53ZEvangelia GousiouKeep-out zones for copper planes for EMCKeep-out zones for copper planes before and after transformer to avoid coupling of
common mode noise. Like in Alstom designs and in order to minimizing noise induced in GND and POWER planes from Common Mode on Fip wires.
Example from an Alstom board:
![image](/uploads/76bf381006b076a04fcd05ef991c664c/image.png)https://ohwr.org/project/fmc-nanofip/issues/52Sch: speed indicator2022-03-17T17:30:48ZEvangelia GousiouSch: speed indicatorFor 1M: R8 shall be present and R10 "do not mount".
In the same page: R30 does not have the "do not mount" square around.https://ohwr.org/project/fmc-nanofip/issues/51Rename TP11,12,13 -> TP1,2,32022-01-25T14:41:31ZEvangelia GousiouRename TP11,12,13 -> TP1,2,3TP11,12,13 are generic FPGA IOs and there is no clear description for them to be shown on the silkscreen; is there the possibility to reassign numbers to all TPs and rename TP11 -> TP1, TP12 -> TP2, TP13 -> TP3; this would require then TP1 P12V to change to another number.https://ohwr.org/project/fmc-nanofip/issues/50Layers coherent naming2022-01-18T16:37:33ZEvangelia GousiouLayers coherent namingRename F layer to T to be coherent with the Top Layer (ex: F.Courtyard/Adhesive/Fab -> T.Courtyard/Adhesive/Fab)https://ohwr.org/project/fmc-nanofip/issues/49Use of kicad plot for the pdf generation2022-01-18T16:39:21ZEvangelia GousiouUse of kicad plot for the pdf generationPrint outputs an image that is not searchablehttps://ohwr.org/project/fmc-nanofip/issues/48Change SW with pin compatible alternative2022-01-25T14:54:00ZEvangelia GousiouChange SW with pin compatible alternativeFor availability replace the A6H-8102 -> MCDHN-08F-Vhttps://ohwr.org/project/fmc-nanofip/issues/47Saturn calculations2022-03-09T12:02:05ZEvangelia GousiouSaturn calculationsto be addedhttps://ohwr.org/project/fmc-nanofip/issues/46Reliability FMC connector2022-03-08T17:37:08ZEvangelia GousiouReliability FMC connectorThe location of the digital lines on the FMC connector should be separated by the 12V input line (part D of the connector ) from a minimum of 2 n/c pins in all direction, so at least they have to be located on the F part, or better in the G or H parts). This action seems not possible for the JTAG lines and the reset, so a ground barrier should be added in between pins. This is a critical point because it is a weakness of the VITA standard pinout.
https://ohwr.org/project/nanofip/wikis/nanoFIP-redesignhttps://ohwr.org/project/fmc-nanofip/issues/45Reliability components placement2022-01-25T14:59:33ZEvangelia GousiouReliability components placementThe component placement should keep a separation of 1cm minimum of the components involved in the 5VDC power generation from the digital lines.
https://ohwr.org/project/nanofip/wikis/nanoFIP-redesignhttps://ohwr.org/project/fmc-nanofip/issues/44Reliability power supplies2022-03-08T17:42:01ZEvangelia GousiouReliability power supplies3.3V digital lines (16 input, 16 output, JTAG, config, reset etc..) should be located in a different layer in respect to the 12V and 5V layer, separated by a ground plane.
https://ohwr.org/project/nanofip/wikis/nanoFIP-redesignhttps://ohwr.org/project/fmc-nanofip/issues/43Remove W32022-01-25T14:41:09ZEvangelia GousiouRemove W3From [specs](https://ohwr.org/project/fmc-nanofip/wikis/Specification) W3 was placed for "board-to-board connection"; in principle this is not currently needed and could disturb signal integrity
![image](/uploads/9e70c2c7774cbfd1bf3eab65f3149480/image.png)Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-nanofip/issues/42Hw revision2022-01-25T14:39:56ZEvangelia GousiouHw revisionHW_REV to reflect the EDA version, i.e. v3: R61 mounted, R67: do not mount
![image](/uploads/2da963b100a7259817dbb87968374a42/image.png)Evangelia GousiouEvangelia Gousiouhttps://ohwr.org/project/fmc-nanofip/issues/41R78 and J2 seem to overlap2022-01-10T14:59:56ZChristos GentsosR78 and J2 seem to overlapIf the 3D model of J2 is accurate, there's an overlap with R78.
![2021-12-15-100306_1165x1045_scrot](/uploads/2c7e025f0104c7809c3387355bbd41dd/2021-12-15-100306_1165x1045_scrot.png)layout-v3.1