JTAG bypass jumper is incorrectly wired
The JTAG bypass jumper (W1) is supposed to exclude the nanoFIP FPGA from the JTAG chain going through the FMC connector. Currently the jumper shortens TDI and TDO pins of the FPGA, but it means it shortens the previous device TDO pin with the FPGA TDO pin. Instead, there should be 3-pin header either connecting the incoming FMC TDI pin with the FPGA pin or with the FMC TDO pin (see e.g. Xilinx SP601 schematics).