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fmc-nanofip
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Reliability power supplies
#44
· opened
Jan 11, 2022
by
Evangelia Gousiou
CLOSED
1
updated
Mar 08, 2022
Remove W3
#43
· opened
Jan 11, 2022
by
Evangelia Gousiou
CLOSED
1
updated
Jan 25, 2022
Hw revision
#42
· opened
Jan 11, 2022
by
Evangelia Gousiou
CLOSED
1
updated
Jan 25, 2022
R78 and J2 seem to overlap
#41
· opened
Dec 15, 2021
by
Christos Gentsos
layout-v3.1
CLOSED
1
updated
Jan 10, 2022
Using the DRB TPS7A49 variant (VSON package) might lead to better reliability
#40
· opened
Dec 14, 2021
by
Christos Gentsos
layout-v3.1
CLOSED
1
updated
Jan 10, 2022
FMC VREF_A_M2C should be not connected
#39
· opened
Dec 13, 2021
by
Grzegorz Daniluk
layout-v3.1
bug
CLOSED
2
updated
Jan 10, 2022
Bottom: power tracks could be wider (currently they are 0.2mm)
#38
· opened
Dec 13, 2021
by
Grzegorz Daniluk
layout-v3.1
CLOSED
1
updated
Jan 10, 2022
TPS7A49 (IC2, IC3, IC6) layout could be improved
#37
· opened
Dec 13, 2021
by
Grzegorz Daniluk
layout-v3.1
CLOSED
1
updated
Jan 10, 2022
L3: unconnected stub of VBUS polygon between two tracks
#36
· opened
Dec 13, 2021
by
Grzegorz Daniluk
layout-v3.1
CLOSED
0
updated
Jan 11, 2022
change silkscreen license text to CERN OHL-W v2
#35
· opened
Dec 13, 2021
by
Grzegorz Daniluk
layout-v3.1
CLOSED
1
updated
Jan 10, 2022
add more stitching vias to connect well different GND planes
#34
· opened
Dec 10, 2021
by
Grzegorz Daniluk
layout-v3.1
CLOSED
1
updated
Jan 10, 2022
L6: P1V5 polygon is spread over the whole PCB area with very few connections (vias)
#33
· opened
Dec 10, 2021
by
Grzegorz Daniluk
layout-v3.1
CLOSED
1
updated
Jan 11, 2022
missing _N suffix for JC_TRST (instead of over-line)
#32
· opened
Dec 10, 2021
by
Grzegorz Daniluk
layout-v3.1
CLOSED
1
updated
Jan 10, 2022
Replace TPS7A4901DGNT with TPS7A4901DRB
#31
· opened
Nov 04, 2021
by
Christos Gentsos
sch-v3.1
bug
CLOSED
1
updated
Dec 21, 2021
Configuration pull-ups powered by P3V3, the I/O banks are on Vadj
#30
· opened
Oct 04, 2021
by
Christos Gentsos
sch-v3.1
bug
CLOSED
0
updated
Oct 04, 2021
FIP signal bank powered by VBUS
#29
· opened
Oct 01, 2021
by
Christos Gentsos
sch-v3.1
bug
CLOSED
0
updated
Oct 04, 2021
settings.sch: update hw revision
#28
· opened
Jul 28, 2021
by
Grzegorz Daniluk
sch-v3.1
CLOSED
0
updated
Oct 04, 2021
Unused FMC pins
#27
· opened
Jul 28, 2021
by
Grzegorz Daniluk
sch-v3.1
CLOSED
1
updated
Oct 07, 2021
VBUS connected to JTAG (J1)?
#26
· opened
Jul 28, 2021
by
Grzegorz Daniluk
sch-v3.1
CLOSED
2
updated
Jul 28, 2021
FPGA I/O bank decoupling capacitors are still on P3V3
#25
· opened
Jul 26, 2021
by
Christos Gentsos
sch-v3.1
CLOSED
0
updated
Oct 04, 2021
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