Layout review
04 September 2017
Reviewed document
present:
- Denia Bouhired-Ferrag (BE-CO-HT)
- Dimitris Lampridis (BE-CO-HT)
- Kamil Kucel (EN-ACE-SU)
- Maciej Suminski (BE-CO-HT)
- Piotr Zdunek (TE-MPE-EP)
- Tomasz Wlostowski (BE-CO-HT)
General
The default clearance is set to 0, it should be verified. There are no
DRC violations when it is set to 0.1 mm, but there are some with 0.2 mm
setting.
TODO image 004/1
TOP layer
- TCK and TMS route could have a bigger gap between them to reduce
crosstalk.
TODO image002/1 006/1
L4 layer
- A part of P12V plane on L4 can be removed, as it has no other
connections, so there is no current flowing through it.
TODO image002
L5 layer
- There is a dangling track on L5.
TODO image004, 006
BTM layer
- Strangely shaped track on BTM layer.
TODO image010, 012
- LDO power in/out nets could be connected with more vias (currently there is only one via per net to connect to the corresponding planes). There could be more vias to connect the LDO to the ground plane too.
- IC2 and IC3 (LDOs) thermal pads should be directly connected go pad 4.
- Dangling track on next to R32.
TODO image 012/1
- Sharp angles on pad IC4 connections.
TODO image013
- No need to place jumper (SW1, SW2) references on silkscreen. Instead there could be a label indicating the jumper role (JTAG_DIS, JTAG_BYPAS).
- The jumper pin headers (W1, W2) could be changed to right-angled ones, to make them accessible without detaching the mezzanine.
- There could be a bigger gap between DAT_O* tracks to decrease coupling. The clearance is 0.2 mm, the coupling length is more or less 30 mm, for 1.6 mm PCB the standard distance to the closest plane is 2x 1080 Prepreg so it’s 0.156 mm. For this values and 10 ns rise time from the ProASIC3 the coupled voltage is 0.5V which is quite high.
TODO image09/21/22