- Wherever possible place inputs coming from the left side, outputs going to the right side.- Add wires for pins that have only a net label (so it is clear that they are connected).* Discuss with the users possibility of disabling the standalone interface, it will free up a lot of FMC pins.* There is an idea to develop nanoFIP gateware with serial (SPI?) interface instead of Wishbone/standalone.
- Check Microsemi note about RC termination for the clock signal.
JTAG, power, LEDs
+ Add a jumper shorting FPGA_TDI and FPGA_TDO to bypass the FPGA TAP in the FMC JTAG daisy-chain.+ Use one-shot trigger circuit with BC817 and a single NOT gate instead of NMOS/PMOS. Use the same type of NOT gate to invert one of the signals. If it is confirmed that there will be a new gateware revision, then drive the LEDs directly from the nanoFIP FPGA.+ Add a diode for the power-on-reset circuit (see FGClite). Add a note about the RC constant.- Add a note explaining pull-downs on the JTAG connector.- Check Microsemi note about capacitors for VJTAG and VPUMP.- Check whether it is necessary to connect Vpp to the JTAG connector (pin 7).
! Missing connection on pin 8 of IC2.* Check if LHC4913 comes in a different package, consider using it.
- Move the substation address pull-ups references so they do not touch the resistor boxes.
! *GND on the DB9 connector is not connected.*+ Add resistors to enable FielDrive test modes (not mounted by default).
FMC connector (LPC)
- Unique ID reading works correctly in DS18B20U under radiation. Temperature readings are incorrect at times, but this can be fixed in software. Consider mounting the IC by default.