4 September 2017
present:
- Denia Bouhired-Ferrag (BE-CO-HT)
- Dimitris Lampridis (BE-CO-HT)
- Kamil Kucel (EN-ACE-SU)
- Maciej Suminski (BE-CO-HT)
- Piotr Zdunek (TE-MPE-EP)
- Tomasz Wlostowski (BE-CO-HT)
General
- The default clearance is set to 0, it should be verified. There are
no DRC violations when it is set to 0.1 mm, but there are some with
0.2 mm
setting.
- There should be a license information placed on the silkscreen layer ("Licensed under CERN OHL v.1.2 https://www.ohwr.org/cernohl", might be split into two lines).
TOP layer
L4 layer
- A part of the P12V plane on L4 can be removed. It has no connections
in this area, so there is no current flowing through
it.
L5 layer
BTM layer
- LDO power in/out nets could be connected with more vias (currently there is only one via per net to connect to the corresponding planes). There could be more vias to connect the LDO to the ground plane too.
- IC2 and IC3 (LDOs) thermal pads should be directly connected go pad 4.
- There is no need to place jumper (SW1, SW2) references on
silkscreen. Instead there could be a label indicating the jumper
role (JTAG_DIS,
JTAG_BYPAS).
- The jumper pin headers (W1, W2) could be changed to the right-angled type, to make them accessible without detaching the mezzanine.
- There could be a bigger gap between DAT_O* tracks to decrease
coupling. The clearance is 0.2 mm, the coupling length is more or
less 30 mm, for 1.6 mm PCB the standard distance to the closest
plane is 2x 1080 Prepreg so it’s 0.156 mm. For this values and 10 ns
rise time from the ProASIC3 the coupled voltage is 0.5V which is
quite
high.