#Build: Synplify Pro D-2010.03, Build 093R, Feb 19 2010
#install: /afs/cern.ch/project/parc/elec/synplify/D-2010.03
#OS: Linux 
#Hostname: lxparc46.cern.ch

#Implementation: syn

#Fri Nov  4 11:35:03 2011

$ Start of Compile
#Fri Nov  4 11:35:03 2011

Synopsys VHDL Compiler, version comp500rc, Build 027R, built Feb 19 2010
Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved

@N:CD720 : std.vhd(123) | Setting time resolution to ns
@N: : top_tdc.vhd(29) | Top entity is set to top_tdc.
VHDL syntax check successful!
@N:CD630 : top_tdc.vhd(29) | Synthesizing work.top_tdc.rtl 
@W:CD638 : top_tdc.vhd(532) | Signal tdc_led_trig1 is undriven 
@W:CD638 : top_tdc.vhd(533) | Signal tdc_led_trig2 is undriven 
@W:CD638 : top_tdc.vhd(534) | Signal tdc_led_trig3 is undriven 
@W:CD638 : top_tdc.vhd(535) | Signal tdc_led_trig4 is undriven 
@W:CD638 : top_tdc.vhd(536) | Signal tdc_led_trig5 is undriven 
@W:CD638 : top_tdc.vhd(551) | Signal core_status is undriven 
@W:CD638 : top_tdc.vhd(619) | Signal load_tdc_config is undriven 
@W:CD638 : top_tdc.vhd(629) | Signal start_phase is undriven 
@W:CD638 : top_tdc.vhd(630) | Signal one_hz_phase is undriven 
@W:CD638 : top_tdc.vhd(637) | Signal irq_code is undriven 
@N:CD630 : countdown_counter.vhd(17) | Synthesizing work.countdown_counter.rtl 
Post processing for work.countdown_counter.rtl
@N:CD630 : free_counter.vhd(15) | Synthesizing work.free_counter.rtl 
Post processing for work.free_counter.rtl
@N:CD630 : gn4124_core_s6.vhd(41) | Synthesizing work.gn4124_core.rtl 
@W:CD326 : gn4124_core_s6.vhd(337) | Port rx_pllout_xs of entity work.serdes_1_to_n_clk_pll_s2_diff is unconnected
@W:CD326 : gn4124_core_s6.vhd(337) | Port rx_pll_lckd of entity work.serdes_1_to_n_clk_pll_s2_diff is unconnected
@W:CD638 : gn4124_core_s6.vhd(183) | Signal p_wr_rdy is undriven 
@N:CD630 : l2p_ser_s6.vhd(35) | Synthesizing work.l2p_ser.rtl 
@N:CD630 : serdes_n_to_1_s2_se.vhd(72) | Synthesizing work.serdes_n_to_1_s2_se.arch_serdes_n_to_1_s2_se 
@N:CD630 : unisim.vhd(10943) | Synthesizing unisim.obuf.syn_black_box 
Post processing for unisim.obuf.syn_black_box
@N:CD630 : unisim.vhd(14184) | Synthesizing unisim.oserdes2.syn_black_box 
Post processing for unisim.oserdes2.syn_black_box
@W:CD638 : serdes_n_to_1_s2_se.vhd(87) | Signal cascade_di is undriven 
@W:CD638 : serdes_n_to_1_s2_se.vhd(88) | Signal cascade_do is undriven 
@W:CD638 : serdes_n_to_1_s2_se.vhd(89) | Signal cascade_ti is undriven 
@W:CD638 : serdes_n_to_1_s2_se.vhd(90) | Signal cascade_to is undriven 
@W:CD638 : serdes_n_to_1_s2_se.vhd(91) | Signal mdataina is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 2 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 3 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 4 of signal mdatainb is undriven 
Post processing for work.serdes_n_to_1_s2_se.arch_serdes_n_to_1_s2_se
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d3 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d4 of instance oserdes_m is floating
@N:CD630 : serdes_n_to_1_s2_se.vhd(72) | Synthesizing work.serdes_n_to_1_s2_se.arch_serdes_n_to_1_s2_se 
@W:CD638 : serdes_n_to_1_s2_se.vhd(87) | Signal cascade_di is undriven 
@W:CD638 : serdes_n_to_1_s2_se.vhd(88) | Signal cascade_do is undriven 
@W:CD638 : serdes_n_to_1_s2_se.vhd(89) | Signal cascade_ti is undriven 
@W:CD638 : serdes_n_to_1_s2_se.vhd(90) | Signal cascade_to is undriven 
@W:CD638 : serdes_n_to_1_s2_se.vhd(91) | Signal mdataina is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 2 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 3 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 6 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 7 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 10 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 11 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 14 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 15 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 18 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 19 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 22 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 23 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 26 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 27 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 30 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 31 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 34 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 35 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 38 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 39 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 42 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 43 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 46 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 47 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 50 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 51 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 54 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 55 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 58 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 59 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 62 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 63 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_se.vhd(92) | Bit 64 of signal mdatainb is undriven 
Post processing for work.serdes_n_to_1_s2_se.arch_serdes_n_to_1_s2_se
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d3 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d4 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d3 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d4 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d3 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d4 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d3 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d4 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d3 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d4 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d3 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d4 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d3 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d4 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d3 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d4 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d3 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d4 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d3 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d4 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d3 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d4 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d3 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d4 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d3 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d4 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d3 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d4 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d3 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d4 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d3 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_se.vhd(197) | Input d4 of instance oserdes_m is floating
@N:CD630 : serdes_n_to_1_s2_diff.vhd(72) | Synthesizing work.serdes_n_to_1_s2_diff.arch_serdes_n_to_1_s2_diff 
@N:CD630 : unisim.vhd(10957) | Synthesizing unisim.obufds.syn_black_box 
Post processing for unisim.obufds.syn_black_box
@W:CD638 : serdes_n_to_1_s2_diff.vhd(88) | Signal cascade_di is undriven 
@W:CD638 : serdes_n_to_1_s2_diff.vhd(89) | Signal cascade_do is undriven 
@W:CD638 : serdes_n_to_1_s2_diff.vhd(90) | Signal cascade_ti is undriven 
@W:CD638 : serdes_n_to_1_s2_diff.vhd(91) | Signal cascade_to is undriven 
@W:CD638 : serdes_n_to_1_s2_diff.vhd(92) | Signal mdataina is undriven 
@W:CD639 : serdes_n_to_1_s2_diff.vhd(93) | Bit 2 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_diff.vhd(93) | Bit 3 of signal mdatainb is undriven 
@W:CD639 : serdes_n_to_1_s2_diff.vhd(93) | Bit 4 of signal mdatainb is undriven 
Post processing for work.serdes_n_to_1_s2_diff.arch_serdes_n_to_1_s2_diff
@W:CL167 : serdes_n_to_1_s2_diff.vhd(199) | Input d3 of instance oserdes_m is floating
@W:CL167 : serdes_n_to_1_s2_diff.vhd(199) | Input d4 of instance oserdes_m is floating
Post processing for work.l2p_ser.rtl
@N:CD630 : l2p_arbiter.vhd(32) | Synthesizing work.l2p_arbiter.rtl 
Post processing for work.l2p_arbiter.rtl
@N:CD630 : p2l_dma_master.vhd(34) | Synthesizing work.p2l_dma_master.behaviour 
@N:CD231 : p2l_dma_master.vhd(172) | Using onehot encoding for type p2l_dma_state_type (p2l_idle="10000")
@W:CD604 : p2l_dma_master.vhd(362) | OTHERS clause is not synthesized 
@W:CD638 : p2l_dma_master.vhd(137) | Signal dma_length_error is undriven 
@N:CD630 : fifo_64x512.vhd(43) | Synthesizing work.fifo_64x512.fifo_64x512_a 
@W:CD286 : fifo_64x512.vhd(43) | Creating black box for empty architecture fifo_64x512 
Post processing for work.fifo_64x512.fifo_64x512_a
Post processing for work.p2l_dma_master.behaviour
@W:CL169 : p2l_dma_master.vhd(458) | Pruning Register to_wb_fifo_byte_swap(1 downto 0)  
@W:CL111 : p2l_dma_master.vhd(458) | All reachable assignments to to_wb_fifo_din(62) assign '0', register removed by optimization
@W:CL111 : p2l_dma_master.vhd(458) | All reachable assignments to to_wb_fifo_din(63) assign '0', register removed by optimization
@W:CL190 : p2l_dma_master.vhd(527) | Optimizing register bit p2l_dma_adr_o(30) to a constant 0
@W:CL190 : p2l_dma_master.vhd(527) | Optimizing register bit p2l_dma_adr_o(31) to a constant 0
@W:CL260 : p2l_dma_master.vhd(527) | Pruning Register bit 31 of p2l_dma_adr_o(31 downto 0)  
@W:CL260 : p2l_dma_master.vhd(527) | Pruning Register bit 30 of p2l_dma_adr_o(31 downto 0)  
@N:CD630 : l2p_dma_master.vhd(33) | Synthesizing work.l2p_dma_master.behaviour 
@N:CD231 : l2p_dma_master.vhd(135) | Using onehot encoding for type l2p_dma_state_type (l2p_idle="10000000")
@W:CD604 : l2p_dma_master.vhd(472) | OTHERS clause is not synthesized 
@N:CD630 : fifo_32x512.vhd(43) | Synthesizing work.fifo_32x512.fifo_32x512_a 
@W:CD286 : fifo_32x512.vhd(43) | Creating black box for empty architecture fifo_32x512 
Post processing for work.fifo_32x512.fifo_32x512_a
Post processing for work.l2p_dma_master.behaviour
@W:CL169 : l2p_dma_master.vhd(215) | Pruning Register l2p_byte_swap(1 downto 0)  
@W:CL111 : l2p_dma_master.vhd(173) | All reachable assignments to addr_fifo_din(30) assign '0', register removed by optimization
@W:CL111 : l2p_dma_master.vhd(173) | All reachable assignments to addr_fifo_din(31) assign '0', register removed by optimization
@A: : l2p_dma_master.vhd(173) | Feedback mux created for signal addr_fifo_din[29:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area
@W:CL190 : l2p_dma_master.vhd(215) | Optimizing register bit l2p_len_header(6) to a constant 0
@W:CL190 : l2p_dma_master.vhd(215) | Optimizing register bit l2p_len_header(7) to a constant 0
@W:CL190 : l2p_dma_master.vhd(215) | Optimizing register bit l2p_len_header(8) to a constant 0
@W:CL190 : l2p_dma_master.vhd(215) | Optimizing register bit l2p_len_header(9) to a constant 0
@W:CL260 : l2p_dma_master.vhd(215) | Pruning Register bit 9 of l2p_len_header(9 downto 0)  
@W:CL260 : l2p_dma_master.vhd(215) | Pruning Register bit 8 of l2p_len_header(9 downto 0)  
@W:CL260 : l2p_dma_master.vhd(215) | Pruning Register bit 7 of l2p_len_header(9 downto 0)  
@W:CL260 : l2p_dma_master.vhd(215) | Pruning Register bit 6 of l2p_len_header(9 downto 0)  
@N:CD630 : dma_controller.vhd(31) | Synthesizing work.dma_controller.behaviour 
@N:CD231 : dma_controller.vhd(187) | Using onehot encoding for type dma_ctrl_state_type (dma_idle="1000000")
@W:CD604 : dma_controller.vhd(444) | OTHERS clause is not synthesized 
@W:CD638 : dma_controller.vhd(157) | Signal dma_stat is undriven 
@W:CD638 : dma_controller.vhd(167) | Signal dma_stat_load is undriven 
@N:CD630 : dma_controller_wb_slave.vhd(17) | Synthesizing work.dma_controller_wb_slave.syn 
Post processing for work.dma_controller_wb_slave.syn
@W:CL111 : dma_controller_wb_slave.vhd(177) | All reachable assignments to ack_sreg(9) assign '0', register removed by optimization
@W:CL190 : dma_controller_wb_slave.vhd(177) | Optimizing register bit ack_sreg(8) to a constant 0
@W:CL260 : dma_controller_wb_slave.vhd(177) | Pruning Register bit 8 of ack_sreg(8 downto 0)  
Post processing for work.dma_controller.behaviour
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(3) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(4) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(5) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(6) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(7) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(8) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(9) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(10) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(11) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(12) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(13) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(14) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(15) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(16) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(17) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(18) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(19) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(20) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(21) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(22) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(23) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(24) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(25) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(26) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(27) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(28) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(29) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(30) assign '0', register removed by optimization
@W:CL111 : dma_controller.vhd(251) | All reachable assignments to dma_stat_reg(31) assign '0', register removed by optimization
@N:CD630 : wbmaster32.vhd(35) | Synthesizing work.wbmaster32.behaviour 
@N:CD231 : wbmaster32.vhd(133) | Using onehot encoding for type wishbone_state_type (wb_idle="1000")
@N:CD231 : wbmaster32.vhd(154) | Using onehot encoding for type l2p_read_cpl_state_type (l2p_idle="100")
@W:CD604 : wbmaster32.vhd(285) | OTHERS clause is not synthesized 
@W:CD604 : wbmaster32.vhd(403) | OTHERS clause is not synthesized 
Post processing for work.wbmaster32.behaviour
@W:CL170 : wbmaster32.vhd(344) | Pruning bit <30> of wb_adr_t(30 downto 0) - not in use ... 
@W:CL170 : wbmaster32.vhd(344) | Pruning bit <29> of wb_adr_t(30 downto 0) - not in use ... 
@W:CL170 : wbmaster32.vhd(344) | Pruning bit <28> of wb_adr_t(30 downto 0) - not in use ... 
@W:CL170 : wbmaster32.vhd(344) | Pruning bit <27> of wb_adr_t(30 downto 0) - not in use ... 
@W:CL170 : wbmaster32.vhd(344) | Pruning bit <26> of wb_adr_t(30 downto 0) - not in use ... 
@W:CL170 : wbmaster32.vhd(344) | Pruning bit <25> of wb_adr_t(30 downto 0) - not in use ... 
@W:CL170 : wbmaster32.vhd(344) | Pruning bit <24> of wb_adr_t(30 downto 0) - not in use ... 
@W:CL170 : wbmaster32.vhd(344) | Pruning bit <23> of wb_adr_t(30 downto 0) - not in use ... 
@W:CL170 : wbmaster32.vhd(344) | Pruning bit <22> of wb_adr_t(30 downto 0) - not in use ... 
@W:CL170 : wbmaster32.vhd(344) | Pruning bit <21> of wb_adr_t(30 downto 0) - not in use ... 
@W:CL170 : wbmaster32.vhd(344) | Pruning bit <20> of wb_adr_t(30 downto 0) - not in use ... 
@W:CL170 : wbmaster32.vhd(344) | Pruning bit <19> of wb_adr_t(30 downto 0) - not in use ... 
@N:CD630 : p2l_decode32.vhd(31) | Synthesizing work.p2l_decode32.rtl 
@W:CD638 : p2l_decode32.vhd(98) | Signal p2l_packet_start_d is undriven 
@W:CD638 : p2l_decode32.vhd(114) | Signal p2l_d_first is undriven 
Post processing for work.p2l_decode32.rtl
@N:CD630 : p2l_des_s6.vhd(34) | Synthesizing work.p2l_des.rtl 
@N:CD630 : serdes_1_to_n_data_s2_se.vhd(74) | Synthesizing work.serdes_1_to_n_data_s2_se.arch_serdes_1_to_n_data_s2_se 
@N:CD630 : unisim.vhd(6062) | Synthesizing unisim.ibuf.syn_black_box 
Post processing for unisim.ibuf.syn_black_box
@N:CD630 : unisim.vhd(9014) | Synthesizing unisim.iodelay2.syn_black_box 
Post processing for unisim.iodelay2.syn_black_box
@N:CD630 : unisim.vhd(9185) | Synthesizing unisim.iserdes2.syn_black_box 
Post processing for unisim.iserdes2.syn_black_box
@W:CD638 : serdes_1_to_n_data_s2_se.vhd(95) | Signal ddly_s is undriven 
@W:CD638 : serdes_1_to_n_data_s2_se.vhd(96) | Signal cascade is undriven 
@W:CD638 : serdes_1_to_n_data_s2_se.vhd(97) | Signal busys is undriven 
@W:CD638 : serdes_1_to_n_data_s2_se.vhd(101) | Signal busyd is undriven 
@W:CD638 : serdes_1_to_n_data_s2_se.vhd(108) | Signal pd_edge is undriven 
@W:CD638 : serdes_1_to_n_data_s2_se.vhd(111) | Signal valid_data is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 0 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 1 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 2 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 3 of signal mdataout is undriven 
@W:CD638 : serdes_1_to_n_data_s2_se.vhd(119) | Signal incdec_data is undriven 
Post processing for work.serdes_1_to_n_data_s2_se.arch_serdes_1_to_n_data_s2_se
@W:CL240 : serdes_1_to_n_data_s2_se.vhd(119) | incdec_data is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : serdes_1_to_n_data_s2_se.vhd(111) | valid_data is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : serdes_1_to_n_data_s2_se.vhd(97) | busys is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL168 : serdes_1_to_n_data_s2_se.vhd(395) | Pruning instance loop0.0.loop3.iodelay_m - not in use ... 
@A: : serdes_1_to_n_data_s2_se.vhd(210) | Feedback mux created for signal inc_data_int. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area
@A: : serdes_1_to_n_data_s2_se.vhd(141) | Feedback mux created for signal rst_data. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area
@A: : serdes_1_to_n_data_s2_se.vhd(210) | Feedback mux created for signal ce_data[0:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area
@W:CL111 : serdes_1_to_n_data_s2_se.vhd(210) | All reachable assignments to valid_data_d assign '0', register removed by optimization
@W:CL111 : serdes_1_to_n_data_s2_se.vhd(210) | All reachable assignments to incdec_data_d assign '0', register removed by optimization
@W:CL111 : serdes_1_to_n_data_s2_se.vhd(210) | All reachable assignments to busy_data_d assign '0', register removed by optimization
@W:CL111 : serdes_1_to_n_data_s2_se.vhd(141) | All reachable assignments to mux(0) assign '1', register removed by optimization
@W:CL190 : serdes_1_to_n_data_s2_se.vhd(210) | Optimizing register bit flag to a constant 0
@W:CL169 : serdes_1_to_n_data_s2_se.vhd(210) | Pruning Register flag  
@N:CD630 : serdes_1_to_n_data_s2_se.vhd(74) | Synthesizing work.serdes_1_to_n_data_s2_se.arch_serdes_1_to_n_data_s2_se 
@W:CD638 : serdes_1_to_n_data_s2_se.vhd(95) | Signal ddly_s is undriven 
@W:CD638 : serdes_1_to_n_data_s2_se.vhd(96) | Signal cascade is undriven 
@W:CD638 : serdes_1_to_n_data_s2_se.vhd(97) | Signal busys is undriven 
@W:CD638 : serdes_1_to_n_data_s2_se.vhd(101) | Signal busyd is undriven 
@W:CD638 : serdes_1_to_n_data_s2_se.vhd(108) | Signal pd_edge is undriven 
@W:CD638 : serdes_1_to_n_data_s2_se.vhd(111) | Signal valid_data is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 0 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 1 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 2 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 3 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 8 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 9 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 10 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 11 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 16 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 17 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 18 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 19 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 24 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 25 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 26 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 27 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 32 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 33 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 34 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 35 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 40 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 41 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 42 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 43 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 48 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 49 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 50 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 51 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 56 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 57 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 58 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 59 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 64 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 65 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 66 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 67 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 72 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 73 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 74 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 75 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 80 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 81 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 82 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 83 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 88 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 89 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 90 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 91 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 96 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 97 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 98 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 99 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 104 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 105 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 106 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 107 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 112 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 113 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 114 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 115 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 120 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 121 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 122 of signal mdataout is undriven 
@W:CD639 : serdes_1_to_n_data_s2_se.vhd(114) | Bit 123 of signal mdataout is undriven 
@W:CD638 : serdes_1_to_n_data_s2_se.vhd(119) | Signal incdec_data is undriven 
Post processing for work.serdes_1_to_n_data_s2_se.arch_serdes_1_to_n_data_s2_se
@W:CL168 : serdes_1_to_n_data_s2_se.vhd(395) | Pruning instance loop0.15.loop3.iodelay_m - not in use ... 
@W:CL168 : serdes_1_to_n_data_s2_se.vhd(395) | Pruning instance loop0.14.loop3.iodelay_m - not in use ... 
@W:CL168 : serdes_1_to_n_data_s2_se.vhd(395) | Pruning instance loop0.13.loop3.iodelay_m - not in use ... 
@W:CL168 : serdes_1_to_n_data_s2_se.vhd(395) | Pruning instance loop0.12.loop3.iodelay_m - not in use ... 
@W:CL168 : serdes_1_to_n_data_s2_se.vhd(395) | Pruning instance loop0.11.loop3.iodelay_m - not in use ... 
@W:CL168 : serdes_1_to_n_data_s2_se.vhd(395) | Pruning instance loop0.10.loop3.iodelay_m - not in use ... 
@W:CL168 : serdes_1_to_n_data_s2_se.vhd(395) | Pruning instance loop0.9.loop3.iodelay_m - not in use ... 
@W:CL168 : serdes_1_to_n_data_s2_se.vhd(395) | Pruning instance loop0.8.loop3.iodelay_m - not in use ... 
@W:CL168 : serdes_1_to_n_data_s2_se.vhd(395) | Pruning instance loop0.7.loop3.iodelay_m - not in use ... 
@W:CL168 : serdes_1_to_n_data_s2_se.vhd(395) | Pruning instance loop0.6.loop3.iodelay_m - not in use ... 
@W:CL168 : serdes_1_to_n_data_s2_se.vhd(395) | Pruning instance loop0.5.loop3.iodelay_m - not in use ... 
@W:CL168 : serdes_1_to_n_data_s2_se.vhd(395) | Pruning instance loop0.4.loop3.iodelay_m - not in use ... 
@W:CL168 : serdes_1_to_n_data_s2_se.vhd(395) | Pruning instance loop0.3.loop3.iodelay_m - not in use ... 
@W:CL168 : serdes_1_to_n_data_s2_se.vhd(395) | Pruning instance loop0.2.loop3.iodelay_m - not in use ... 
@W:CL168 : serdes_1_to_n_data_s2_se.vhd(395) | Pruning instance loop0.1.loop3.iodelay_m - not in use ... 
@W:CL168 : serdes_1_to_n_data_s2_se.vhd(395) | Pruning instance loop0.0.loop3.iodelay_m - not in use ... 
@W:CL111 : serdes_1_to_n_data_s2_se.vhd(210) | All reachable assignments to busy_data_d assign '0', register removed by optimization
@A: : serdes_1_to_n_data_s2_se.vhd(210) | Feedback mux created for signal inc_data_int. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area
@A: : serdes_1_to_n_data_s2_se.vhd(141) | Feedback mux created for signal rst_data. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area
@A: : serdes_1_to_n_data_s2_se.vhd(210) | Feedback mux created for signal ce_data[15:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area
@W:CL111 : serdes_1_to_n_data_s2_se.vhd(210) | All reachable assignments to valid_data_d assign '0', register removed by optimization
@W:CL111 : serdes_1_to_n_data_s2_se.vhd(210) | All reachable assignments to incdec_data_d assign '0', register removed by optimization
@W:CL190 : serdes_1_to_n_data_s2_se.vhd(210) | Optimizing register bit flag to a constant 0
@W:CL169 : serdes_1_to_n_data_s2_se.vhd(210) | Pruning Register flag  
Post processing for work.p2l_des.rtl
@W:CL169 : p2l_des_s6.vhd(136) | Pruning Register p2l_data_bitslip(1 downto 0)  
@N:CD630 : serdes_1_to_n_clk_pll_s2_diff.vhd(69) | Synthesizing work.serdes_1_to_n_clk_pll_s2_diff.arch_serdes_1_to_n_clk_pll_s2_diff 
@N:CD630 : unisim.vhd(6077) | Synthesizing unisim.ibufds.syn_black_box 
Post processing for unisim.ibufds.syn_black_box
@N:CD630 : unisim.vhd(583) | Synthesizing unisim.bufio2.syn_black_box 
Post processing for unisim.bufio2.syn_black_box
@N:CD630 : unisim.vhd(599) | Synthesizing unisim.bufio2fb.syn_black_box 
Post processing for unisim.bufio2fb.syn_black_box
@N:CD630 : unisim.vhd(16190) | Synthesizing unisim.pll_adv.syn_black_box 
Post processing for unisim.pll_adv.syn_black_box
@N:CD630 : unisim.vhd(636) | Synthesizing unisim.bufpll.syn_black_box 
Post processing for unisim.bufpll.syn_black_box
@W:CD638 : serdes_1_to_n_clk_pll_s2_diff.vhd(102) | Signal busys is undriven 
@N:CD630 : unisim.vhd(428) | Synthesizing unisim.bufg.syn_black_box 
Post processing for unisim.bufg.syn_black_box
Post processing for work.serdes_1_to_n_clk_pll_s2_diff.arch_serdes_1_to_n_clk_pll_s2_diff
@A: : serdes_1_to_n_clk_pll_s2_diff.vhd(155) | Feedback mux created for signal count[2:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area
@W:CL190 : serdes_1_to_n_clk_pll_s2_diff.vhd(155) | Optimizing register bit bslip to a constant 0
@W:CL169 : serdes_1_to_n_clk_pll_s2_diff.vhd(155) | Pruning Register bslip  
Post processing for work.gn4124_core.rtl
@N:CD630 : clk_rst_managr.vhd(32) | Synthesizing work.clk_rst_managr.rtl 
@N:CD231 : clk_rst_managr.vhd(84) | Using onehot encoding for type t_pll_init_st (start="10000")
@N:CD630 : unisim.vhd(6266) | Synthesizing unisim.ibufg.syn_black_box 
Post processing for unisim.ibufg.syn_black_box
@W:CD604 : clk_rst_managr.vhd(344) | OTHERS clause is not synthesized 
@W:CD638 : clk_rst_managr.vhd(178) | Signal acam_refclk_buf is undriven 
@N:CD630 : incr_counter.vhd(16) | Synthesizing work.incr_counter.rtl 
Post processing for work.incr_counter.rtl
Post processing for work.clk_rst_managr.rtl
@W:CL240 : clk_rst_managr.vhd(51) | pll_dac_sync_o is not assigned a value (floating) - a simulation mismatch is possible 
@N:CD630 : reg_ctrl.vhd(29) | Synthesizing work.reg_ctrl.rtl 
Post processing for work.reg_ctrl.rtl
@W:CL170 : reg_ctrl.vhd(112) | Pruning bit <31> of control_register(31 downto 0) - not in use ... 
@W:CL170 : reg_ctrl.vhd(112) | Pruning bit <30> of control_register(31 downto 0) - not in use ... 
@W:CL170 : reg_ctrl.vhd(112) | Pruning bit <29> of control_register(31 downto 0) - not in use ... 
@W:CL170 : reg_ctrl.vhd(112) | Pruning bit <28> of control_register(31 downto 0) - not in use ... 
@W:CL170 : reg_ctrl.vhd(112) | Pruning bit <27> of control_register(31 downto 0) - not in use ... 
@W:CL170 : reg_ctrl.vhd(112) | Pruning bit <26> of control_register(31 downto 0) - not in use ... 
@W:CL170 : reg_ctrl.vhd(112) | Pruning bit <25> of control_register(31 downto 0) - not in use ... 
@W:CL170 : reg_ctrl.vhd(112) | Pruning bit <24> of control_register(31 downto 0) - not in use ... 
@W:CL170 : reg_ctrl.vhd(112) | Pruning bit <23> of control_register(31 downto 0) - not in use ... 
@W:CL170 : reg_ctrl.vhd(112) | Pruning bit <22> of control_register(31 downto 0) - not in use ... 
@W:CL170 : reg_ctrl.vhd(112) | Pruning bit <21> of control_register(31 downto 0) - not in use ... 
@W:CL170 : reg_ctrl.vhd(112) | Pruning bit <20> of control_register(31 downto 0) - not in use ... 
@W:CL170 : reg_ctrl.vhd(112) | Pruning bit <19> of control_register(31 downto 0) - not in use ... 
@W:CL170 : reg_ctrl.vhd(112) | Pruning bit <18> of control_register(31 downto 0) - not in use ... 
@W:CL170 : reg_ctrl.vhd(112) | Pruning bit <17> of control_register(31 downto 0) - not in use ... 
@W:CL170 : reg_ctrl.vhd(112) | Pruning bit <16> of control_register(31 downto 0) - not in use ... 
@W:CL170 : reg_ctrl.vhd(112) | Pruning bit <15> of control_register(31 downto 0) - not in use ... 
@W:CL170 : reg_ctrl.vhd(112) | Pruning bit <14> of control_register(31 downto 0) - not in use ... 
@W:CL170 : reg_ctrl.vhd(112) | Pruning bit <13> of control_register(31 downto 0) - not in use ... 
@W:CL170 : reg_ctrl.vhd(112) | Pruning bit <12> of control_register(31 downto 0) - not in use ... 
@W:CL170 : reg_ctrl.vhd(112) | Pruning bit <11> of control_register(31 downto 0) - not in use ... 
@N:CD630 : circular_buffer.vhd(30) | Synthesizing work.circular_buffer.rtl 
@N:CD231 : circular_buffer.vhd(88) | Using onehot encoding for type t_wb_pipelined_mem_interface (idle="1000")
@W:CD604 : circular_buffer.vhd(182) | OTHERS clause is not synthesized 
@N:CD630 : blk_mem_circ_buff_v6_4.vhd(43) | Synthesizing work.blk_mem_circ_buff_v6_4.blk_mem_circ_buff_v6_4_a 
@W:CD286 : blk_mem_circ_buff_v6_4.vhd(43) | Creating black box for empty architecture blk_mem_circ_buff_v6_4 
Post processing for work.blk_mem_circ_buff_v6_4.blk_mem_circ_buff_v6_4_a
Post processing for work.circular_buffer.rtl
@N:CD630 : data_formatting.vhd(28) | Synthesizing work.data_formatting.rtl 
Post processing for work.data_formatting.rtl
@N:CD630 : data_engine.vhd(33) | Synthesizing work.data_engine.rtl 
@N:CD231 : data_engine.vhd(83) | Using onehot encoding for type engine_state_ty (active="10000000000")
@W:CD604 : data_engine.vhd(301) | OTHERS clause is not synthesized 
@W:CD604 : data_engine.vhd(335) | OTHERS clause is not synthesized 
Post processing for work.data_engine.rtl
@N:CD630 : start_retrigger_control.vhd(32) | Synthesizing work.start_retrigger_control.rtl 
@W:CD638 : start_retrigger_control.vhd(103) | Signal acam_halfcounter_gone is undriven 
Post processing for work.start_retrigger_control.rtl
@N:CD630 : acam_databus_interface.vhd(28) | Synthesizing work.acam_databus_interface.rtl 
@N:CD231 : acam_databus_interface.vhd(73) | Using onehot encoding for type t_acam_interface (idle="1000000")
@W:CD604 : acam_databus_interface.vhd(185) | OTHERS clause is not synthesized 
Post processing for work.acam_databus_interface.rtl
@N:CD630 : acam_timecontrol_interface.vhd(27) | Synthesizing work.acam_timecontrol_interface.rtl 
Post processing for work.acam_timecontrol_interface.rtl
@N:CD630 : one_hz_gen.vhd(29) | Synthesizing work.one_hz_gen.rtl 
Post processing for work.one_hz_gen.rtl
Post processing for work.top_tdc.rtl
@W:CL240 : top_tdc.vhd(61) | spare_o is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL245 : top_tdc.vhd(857) | Bit 0 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 1 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 2 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 3 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 4 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 5 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 6 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 7 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 8 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 9 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 10 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 11 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 12 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 13 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 14 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 15 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 16 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 17 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 18 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 19 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 20 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 21 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 22 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 23 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 24 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 25 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 26 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 27 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 28 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 29 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 30 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 31 of input irq_code_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 0 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 1 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 2 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 3 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 4 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 5 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 6 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 7 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 8 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 9 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 10 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 11 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 12 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 13 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 14 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 15 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 16 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 17 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 18 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 19 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 20 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 21 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 22 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 23 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 24 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 25 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 26 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 27 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 28 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 29 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 30 of input core_status_i of instance reg_control_block is floating
@W:CL245 : top_tdc.vhd(857) | Bit 31 of input core_status_i of instance reg_control_block is floating
@N:CL177 : top_tdc.vhd(119) | Sharing sequential element spec_aux4_o.
@N:CL177 : top_tdc.vhd(117) | Sharing sequential element spec_aux2_o.
@N:CL201 : acam_databus_interface.vhd(75) | Trying to extract state machine for register acam_data_st
Extracted state machine for register acam_data_st
State machine has 7 reachable states with original encodings of:
   0000001
   0000010
   0000100
   0001000
   0010000
   0100000
   1000000
@W:CL246 : acam_databus_interface.vhd(57) | Input port bits 31 to 4 of adr_i(31 downto 0) are unused 
@W:CL246 : acam_databus_interface.vhd(59) | Input port bits 31 to 28 of dat_i(31 downto 0) are unused 
@W:CL159 : start_retrigger_control.vhd(37) | Input acam_rise_intflag_p_i is unused
@N:CL201 : data_engine.vhd(85) | Trying to extract state machine for register engine_st
Extracted state machine for register engine_st
State machine has 11 reachable states with original encodings of:
   00000000001
   00000000010
   00000000100
   00000001000
   00000010000
   00000100000
   00001000000
   00010000000
   00100000000
   01000000000
   10000000000
@W:CL247 : data_formatting.vhd(46) | Input port bit 30 of acam_timestamp1_i(31 downto 0) is unused 
@W:CL247 : data_formatting.vhd(46) | Input port bit 28 of acam_timestamp1_i(31 downto 0) is unused 
@W:CL247 : data_formatting.vhd(48) | Input port bit 31 of acam_timestamp2_i(31 downto 0) is unused 
@W:CL247 : data_formatting.vhd(48) | Input port bit 29 of acam_timestamp2_i(31 downto 0) is unused 
@W:CL246 : data_formatting.vhd(54) | Input port bits 31 to 18 of current_roll_over_i(31 downto 0) are unused 
@W:CL246 : data_formatting.vhd(56) | Input port bits 31 to 26 of retrig_nb_offset_i(31 downto 0) are unused 
@W:CL159 : data_formatting.vhd(37) | Input dat_i is unused
@N:CL201 : circular_buffer.vhd(90) | Trying to extract state machine for register wb_pipelined_st
Extracted state machine for register wb_pipelined_st
State machine has 4 reachable states with original encodings of:
   0001
   0010
   0100
   1000
@W:CL246 : circular_buffer.vhd(40) | Input port bits 31 to 8 of class_adr_i(31 downto 0) are unused 
@W:CL246 : circular_buffer.vhd(53) | Input port bits 31 to 10 of pipe_adr_i(31 downto 0) are unused 
@W:CL246 : reg_ctrl.vhd(39) | Input port bits 31 to 8 of reg_adr_i(31 downto 0) are unused 
@W:CL159 : reg_ctrl.vhd(63) | Input acam_status_i is unused
@N:CL201 : clk_rst_managr.vhd(172) | Trying to extract state machine for register pll_init_st
Extracted state machine for register pll_init_st
State machine has 5 reachable states with original encodings of:
   00001
   00010
   00100
   01000
   10000
@W:CL159 : clk_rst_managr.vhd(39) | Input pll_ld_i is unused
@W:CL159 : clk_rst_managr.vhd(40) | Input pll_refmon_i is unused
@W:CL159 : clk_rst_managr.vhd(41) | Input pll_sdo_i is unused
@W:CL159 : clk_rst_managr.vhd(42) | Input pll_status_i is unused
@N:CL201 : serdes_1_to_n_clk_pll_s2_diff.vhd(155) | Trying to extract state machine for register state
Extracted state machine for register state
State machine has 9 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1001
@W:CL159 : serdes_1_to_n_clk_pll_s2_diff.vhd(81) | Input pattern1 is unused
@W:CL159 : serdes_1_to_n_clk_pll_s2_diff.vhd(82) | Input pattern2 is unused
@N:CL201 : serdes_1_to_n_data_s2_se.vhd(141) | Trying to extract state machine for register state
Extracted state machine for register state
State machine has 2 reachable states with original encodings of:
   0000
   0001
@W:CL189 : serdes_1_to_n_data_s2_se.vhd(141) | Register bit rst_data is always 0, optimizing ...
@W:CL190 : serdes_1_to_n_data_s2_se.vhd(210) | Optimizing register bit ce_data_inta to a constant 0
@W:CL169 : serdes_1_to_n_data_s2_se.vhd(210) | Pruning Register pdcounter(4 downto 0)  
@W:CL169 : serdes_1_to_n_data_s2_se.vhd(210) | Pruning Register ce_data_inta  
@W:CL260 : serdes_1_to_n_data_s2_se.vhd(210) | Pruning Register bit 15 of ce_data(15 downto 0)  
@W:CL260 : serdes_1_to_n_data_s2_se.vhd(210) | Pruning Register bit 14 of ce_data(15 downto 0)  
@W:CL260 : serdes_1_to_n_data_s2_se.vhd(210) | Pruning Register bit 13 of ce_data(15 downto 0)  
@W:CL260 : serdes_1_to_n_data_s2_se.vhd(210) | Pruning Register bit 12 of ce_data(15 downto 0)  
@W:CL260 : serdes_1_to_n_data_s2_se.vhd(210) | Pruning Register bit 11 of ce_data(15 downto 0)  
@W:CL260 : serdes_1_to_n_data_s2_se.vhd(210) | Pruning Register bit 10 of ce_data(15 downto 0)  
@W:CL260 : serdes_1_to_n_data_s2_se.vhd(210) | Pruning Register bit 9 of ce_data(15 downto 0)  
@W:CL260 : serdes_1_to_n_data_s2_se.vhd(210) | Pruning Register bit 8 of ce_data(15 downto 0)  
@W:CL260 : serdes_1_to_n_data_s2_se.vhd(210) | Pruning Register bit 7 of ce_data(15 downto 0)  
@W:CL260 : serdes_1_to_n_data_s2_se.vhd(210) | Pruning Register bit 6 of ce_data(15 downto 0)  
@W:CL260 : serdes_1_to_n_data_s2_se.vhd(210) | Pruning Register bit 5 of ce_data(15 downto 0)  
@W:CL260 : serdes_1_to_n_data_s2_se.vhd(210) | Pruning Register bit 4 of ce_data(15 downto 0)  
@W:CL260 : serdes_1_to_n_data_s2_se.vhd(210) | Pruning Register bit 3 of ce_data(15 downto 0)  
@W:CL260 : serdes_1_to_n_data_s2_se.vhd(210) | Pruning Register bit 2 of ce_data(15 downto 0)  
@W:CL260 : serdes_1_to_n_data_s2_se.vhd(210) | Pruning Register bit 1 of ce_data(15 downto 0)  
@N:CL201 : serdes_1_to_n_data_s2_se.vhd(141) | Trying to extract state machine for register state
Extracted state machine for register state
State machine has 2 reachable states with original encodings of:
   0000
   0001
@W:CL169 : serdes_1_to_n_data_s2_se.vhd(210) | Pruning Register pdcounter(4 downto 0)  
@W:CL169 : serdes_1_to_n_data_s2_se.vhd(210) | Pruning Register ce_data_inta  
@N:CL201 : wbmaster32.vhd(344) | Trying to extract state machine for register wishbone_current_state
Extracted state machine for register wishbone_current_state
State machine has 4 reachable states with original encodings of:
   0001
   0010
   0100
   1000
@N:CL201 : wbmaster32.vhd(248) | Trying to extract state machine for register l2p_read_cpl_current_state
Extracted state machine for register l2p_read_cpl_current_state
State machine has 3 reachable states with original encodings of:
   001
   010
   100
@W:CL260 : wbmaster32.vhd(344) | Pruning Register bit 3 of wb_sel_t(3 downto 0)  
@W:CL260 : wbmaster32.vhd(344) | Pruning Register bit 2 of wb_sel_t(3 downto 0)  
@W:CL260 : wbmaster32.vhd(344) | Pruning Register bit 1 of wb_sel_t(3 downto 0)  
@W:CL247 : wbmaster32.vhd(61) | Input port bit 1 of pd_wbm_addr_i(31 downto 0) is unused 
@W:CL159 : wbmaster32.vhd(54) | Input pd_wbm_hdr_length_i is unused
@W:CL159 : wbmaster32.vhd(66) | Input pd_wbm_data_last_i is unused
@W:CL159 : wbmaster32.vhd(68) | Input pd_wbm_be_i is unused
@W:CL190 : dma_controller_wb_slave.vhd(177) | Optimizing register bit ack_sreg(7) to a constant 0
@W:CL260 : dma_controller_wb_slave.vhd(177) | Pruning Register bit 7 of ack_sreg(7 downto 0)  
@W:CL189 : dma_controller_wb_slave.vhd(177) | Register bit ack_sreg(6) is always 0, optimizing ...
@W:CL260 : dma_controller_wb_slave.vhd(177) | Pruning Register bit 6 of ack_sreg(6 downto 0)  
@W:CL159 : dma_controller_wb_slave.vhd(25) | Input wb_sel_i is unused
@N:CL201 : dma_controller.vhd(327) | Trying to extract state machine for register dma_ctrl_current_state
Extracted state machine for register dma_ctrl_current_state
State machine has 7 reachable states with original encodings of:
   0000001
   0000010
   0000100
   0001000
   0010000
   0100000
   1000000
@W:CL260 : l2p_dma_master.vhd(544) | Pruning Register bit 3 of l2p_dma_sel_o(3 downto 0)  
@W:CL260 : l2p_dma_master.vhd(544) | Pruning Register bit 2 of l2p_dma_sel_o(3 downto 0)  
@W:CL260 : l2p_dma_master.vhd(544) | Pruning Register bit 1 of l2p_dma_sel_o(3 downto 0)  
@N:CL177 : l2p_dma_master.vhd(544) | Sharing sequential element l2p_dma_stb_t.
@N:CL201 : l2p_dma_master.vhd(312) | Trying to extract state machine for register l2p_dma_current_state
Extracted state machine for register l2p_dma_current_state
State machine has 8 reachable states with original encodings of:
   00000001
   00000010
   00000100
   00001000
   00010000
   00100000
   01000000
   10000000
@W:CL246 : l2p_dma_master.vhd(47) | Input port bits 1 to 0 of dma_ctrl_target_addr_i(31 downto 0) are unused 
@W:CL246 : l2p_dma_master.vhd(50) | Input port bits 1 to 0 of dma_ctrl_len_i(31 downto 0) are unused 
@W:CL159 : l2p_dma_master.vhd(54) | Input dma_ctrl_byte_swap_i is unused
@W:CL260 : p2l_dma_master.vhd(527) | Pruning Register bit 3 of p2l_dma_sel_o(3 downto 0)  
@W:CL260 : p2l_dma_master.vhd(527) | Pruning Register bit 2 of p2l_dma_sel_o(3 downto 0)  
@W:CL260 : p2l_dma_master.vhd(527) | Pruning Register bit 1 of p2l_dma_sel_o(3 downto 0)  
@N:CL177 : p2l_dma_master.vhd(527) | Sharing sequential element p2l_dma_stb_t.
@N:CL201 : p2l_dma_master.vhd(272) | Trying to extract state machine for register p2l_dma_current_state
Extracted state machine for register p2l_dma_current_state
State machine has 5 reachable states with original encodings of:
   00001
   00010
   00100
   01000
   10000
@W:CL246 : p2l_dma_master.vhd(48) | Input port bits 1 to 0 of dma_ctrl_carrier_addr_i(31 downto 0) are unused 
@W:CL246 : p2l_dma_master.vhd(51) | Input port bits 1 to 0 of dma_ctrl_len_i(31 downto 0) are unused 
@W:CL159 : p2l_dma_master.vhd(56) | Input dma_ctrl_byte_swap_i is unused
@W:CL159 : p2l_dma_master.vhd(63) | Input pd_pdm_hdr_start_i is unused
@W:CL159 : p2l_dma_master.vhd(64) | Input pd_pdm_hdr_length_i is unused
@W:CL159 : p2l_dma_master.vhd(65) | Input pd_pdm_hdr_cid_i is unused
@W:CL159 : p2l_dma_master.vhd(73) | Input pd_pdm_be_i is unused
@W:CL159 : p2l_dma_master.vhd(92) | Input p2l_dma_dat_i is unused
@N:CL135 : gn4124_core_s6.vhd(746) | Found seqShift p_rd_d, depth=3, width=2
@N:CL135 : gn4124_core_s6.vhd(746) | Found seqShift l_wr, depth=3, width=2
@N:CL135 : gn4124_core_s6.vhd(746) | Found seqShift l2p, depth=3, width=1
@N:CL135 : gn4124_core_s6.vhd(746) | Found seqShift l2p_edb, depth=3, width=1
@W:CL159 : gn4124_core_s6.vhd(72) | Input p_wr_req_i is unused
@W:CL159 : gn4124_core_s6.vhd(75) | Input vc_rdy_i is unused
@W:CL159 : gn4124_core_s6.vhd(91) | Input tx_error_i is unused
@W:CL159 : top_tdc.vhd(99) | Input tdc_in_fpga_5_i is unused
@END
Process took 0h:00m:05s realtime, 0h:00m:05s cputime
# Fri Nov  4 11:35:09 2011

###########################################################]
Synopsys Xilinx Technology Mapper, Version map510rc, Build 068R, Built Feb 22 2010 15:14:03
Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved
Product Version D-2010.03
Reading constraint file: /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/tdc_syn_constraints.sdc
Adding property syn_input_delay1, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=tdc_clk125:r" to view:work.top_tdc(rtl)
Adding property syn_output_delay2, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=tdc_clk125:r" to view:work.top_tdc(rtl)
Adding property syn_multicycle_path1034, value "3 cycles from p:data_bus_io[27:0]" to view:work.top_tdc(rtl)
Adding property syn_multicycle_path1035, value "3 cycles to p:data_bus_io[27:0]" to view:work.top_tdc(rtl)
Adding property syn_multicycle_path1036, value "3 cycles to p:address_o[3:0]" to view:work.top_tdc(rtl)
Adding property syn_multicycle_path1037, value "2 cycles through n:csr_adr[18:0]" to view:work.top_tdc(rtl)
Adding property syn_multicycle_path1038, value "2 cycles to p:start_from_fpga_o" to view:work.top_tdc(rtl)
Adding property syn_false_path1039, value "from p:spec_aux0_i" to view:work.top_tdc(rtl)
Adding property syn_false_path1040, value "from p:spec_aux1_i" to view:work.top_tdc(rtl)
Adding property syn_false_path1041, value "to p:spec_aux2_o" to view:work.top_tdc(rtl)
Adding property syn_false_path1042, value "to p:spec_aux3_o" to view:work.top_tdc(rtl)
Adding property syn_false_path1043, value "to p:spec_aux4_o" to view:work.top_tdc(rtl)
Adding property syn_false_path1044, value "to p:spec_aux5_o" to view:work.top_tdc(rtl)
Adding property syn_false_path1045, value "to p:spec_led_green_o" to view:work.top_tdc(rtl)
Adding property syn_false_path1046, value "to p:spec_led_red_o" to view:work.top_tdc(rtl)
Adding property syn_false_path1047, value "to p:tdc_led_status_o" to view:work.top_tdc(rtl)
Adding property syn_false_path1048, value "to p:tdc_led_trig1_o" to view:work.top_tdc(rtl)
Adding property syn_false_path1049, value "to p:tdc_led_trig2_o" to view:work.top_tdc(rtl)
Adding property syn_false_path1050, value "to p:tdc_led_trig3_o" to view:work.top_tdc(rtl)
Adding property syn_false_path1051, value "to p:tdc_led_trig4_o" to view:work.top_tdc(rtl)
Adding property syn_false_path1052, value "to p:tdc_led_trig5_o" to view:work.top_tdc(rtl)
Adding property syn_false_path1053, value "to p:irq_p_o" to view:work.top_tdc(rtl)
Adding property syn_useioff, value 1 to view:work.top_tdc(rtl)
Adding property syn_noarrayports, value 1 to view:work.top_tdc(rtl)
Adding property syn_netlist_hierarchy, value 0 to view:work.top_tdc(rtl)
@N:MF249 :  | Running in 64-bit mode. 
@N:MF257 :  | Gated clock conversion enabled  
Adding property syn_pad_type, value "LVCMOS18", to instance spec_aux2_o
Adding property syn_pad_type, value "LVCMOS18", to instance spec_aux3_o
Adding property syn_pad_type, value "LVCMOS18", to instance spec_aux4_o
Adding property syn_pad_type, value "LVCMOS18", to instance spec_aux5_o
Adding property syn_pad_type, value "LVCMOS_25", to instance spare_o
Adding property syn_pad_type, value "LVCMOS_25", to instance mute_inputs_o
Adding property syn_pad_type, value "LVCMOS_25", to instance term_en_1_o
Adding property syn_pad_type, value "LVCMOS_25", to instance term_en_2_o
Adding property syn_pad_type, value "LVCMOS_25", to instance term_en_3_o
Adding property syn_pad_type, value "LVCMOS_25", to instance term_en_4_o
Adding property syn_pad_type, value "LVCMOS_25", to instance term_en_5_o
Adding property syn_pad_type, value "LVCMOS_25", to instance spec_led_green_o
Adding property syn_pad_type, value "LVCMOS_25", to instance tdc_led_status_o
Adding property syn_pad_type, value "LVCMOS_25", to instance tdc_led_trig1_o
Adding property syn_pad_type, value "LVCMOS_25", to instance tdc_led_trig2_o
Adding property syn_pad_type, value "LVCMOS_25", to instance tdc_led_trig3_o
Adding property syn_pad_type, value "LVCMOS_25", to instance tdc_led_trig4_o
Adding property syn_pad_type, value "LVCMOS_25", to instance tdc_led_trig5_o
Adding property syn_pad_type, value "LVCMOS_25", to instance spec_led_red_o
Adding property syn_loc, value "N20", to port rst_n_a_i
Adding property syn_pad_type, value "LVCMOS18", to port rst_n_a_i
Adding property syn_input_delay3, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=gnum_clk200:r", to port p2l_clk_p_i
Adding property syn_pad_type, value "DIFF_SSTL_18_Class_II", to port p2l_clk_p_i
Adding property syn_loc, value "M20", to port p2l_clk_p_i
Adding property syn_input_delay4, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=gnum_clk200:r", to port p2l_clk_n_i
Adding property syn_pad_type, value "DIFF_SSTL_18_Class_II", to port p2l_clk_n_i
Adding property syn_loc, value "M19", to port p2l_clk_n_i
Adding property syn_pad_type, value "SSTL_18_Class_I", to port p2l_data_i[15:0]
Adding property syn_input_delay6, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=gnum_clk200:r", to port p2l_dframe_i
Adding property syn_pad_type, value "SSTL_18_Class_I", to port p2l_dframe_i
Adding property syn_loc, value "J22", to port p2l_dframe_i
Adding property syn_input_delay7, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=gnum_clk200:r", to port p2l_valid_i
Adding property syn_pad_type, value "SSTL_18_Class_I", to port p2l_valid_i
Adding property syn_loc, value "L19", to port p2l_valid_i
Adding property syn_output_delay10, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=gnum_clk200:r", to port p2l_rdy_o
Adding property syn_pad_type, value "SSTL_18_Class_I", to port p2l_rdy_o
Adding property syn_loc, value "J16", to port p2l_rdy_o
Adding property syn_pad_type, value "SSTL_18_Class_I", to port p_wr_req_i[1:0]
Adding property syn_pad_type, value "SSTL_18_Class_I", to port p_wr_rdy_o[1:0]
Adding property syn_output_delay12, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=gnum_clk200:r", to port rx_error_o
Adding property syn_pad_type, value "SSTL_18_Class_I", to port rx_error_o
Adding property syn_loc, value "J17", to port rx_error_o
Adding property syn_pad_type, value "SSTL_18_Class_I", to port vc_rdy_i[1:0]
Adding property syn_output_delay13, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=gnum_clk200:r", to port l2p_clk_p_o
Adding property syn_pad_type, value "DIFF_SSTL_18_Class_II", to port l2p_clk_p_o
Adding property syn_loc, value "K21", to port l2p_clk_p_o
Adding property syn_output_delay14, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=gnum_clk200:r", to port l2p_clk_n_o
Adding property syn_pad_type, value "DIFF_SSTL_18_Class_II", to port l2p_clk_n_o
Adding property syn_loc, value "K22", to port l2p_clk_n_o
Adding property syn_pad_type, value "SSTL_18_Class_I", to port l2p_data_o[15:0]
Adding property syn_output_delay16, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=gnum_clk200:r", to port l2p_dframe_o
Adding property syn_pad_type, value "SSTL_18_Class_I", to port l2p_dframe_o
Adding property syn_loc, value "U22", to port l2p_dframe_o
Adding property syn_output_delay17, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=gnum_clk200:r", to port l2p_valid_o
Adding property syn_pad_type, value "SSTL_18_Class_I", to port l2p_valid_o
Adding property syn_loc, value "T18", to port l2p_valid_o
Adding property syn_output_delay18, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=gnum_clk200:r", to port l2p_edb_o
Adding property syn_pad_type, value "SSTL_18_Class_I", to port l2p_edb_o
Adding property syn_loc, value "U20", to port l2p_edb_o
Adding property syn_input_delay20, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=gnum_clk200:r", to port l2p_rdy_i
Adding property syn_pad_type, value "SSTL_18_Class_I", to port l2p_rdy_i
Adding property syn_loc, value "U19", to port l2p_rdy_i
Adding property syn_pad_type, value "SSTL_18_Class_I", to port l_wr_rdy_i[1:0]
Adding property syn_pad_type, value "SSTL_18_Class_I", to port p_rd_d_rdy_i[1:0]
Adding property syn_input_delay23, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=gnum_clk200:r", to port tx_error_i
Adding property syn_pad_type, value "SSTL_18_Class_I", to port tx_error_i
Adding property syn_loc, value "M17", to port tx_error_i
Adding property syn_loc, value "U16", to port irq_p_o
Adding property syn_pad_type, value "LVCMOS_25", to port irq_p_o
Adding property syn_output_delay19, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=gnum_clk200:r", to port spare_o
Adding property syn_pad_type, value "LVCMOS_25", to port spare_o
Adding property syn_loc, value "AB19", to port spare_o
Adding property syn_loc, value "E16", to port acam_refclk_i
Adding property syn_pad_type, value "LVCMOS_25", to port acam_refclk_i
Adding property syn_input_delay27, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=spec_clk20:r", to port pll_ld_i
Adding property syn_pad_type, value "LVCMOS_25", to port pll_ld_i
Adding property syn_loc, value "C18", to port pll_ld_i
Adding property syn_input_delay28, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=spec_clk20:r", to port pll_refmon_i
Adding property syn_pad_type, value "LVCMOS_25", to port pll_refmon_i
Adding property syn_loc, value "D17", to port pll_refmon_i
Adding property syn_input_delay29, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=spec_clk20:r", to port pll_sdo_i
Adding property syn_pad_type, value "LVCMOS_25", to port pll_sdo_i
Adding property syn_loc, value "AB18", to port pll_sdo_i
Adding property syn_input_delay30, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=spec_clk20:r", to port pll_status_i
Adding property syn_pad_type, value "LVCMOS_25", to port pll_status_i
Adding property syn_loc, value "Y18", to port pll_status_i
Adding property syn_loc, value "L20", to port tdc_clk_p_i
Adding property syn_pad_type, value "DIFF_SSTL_18_Class_II", to port tdc_clk_p_i
Adding property syn_loc, value "L22", to port tdc_clk_n_i
Adding property syn_pad_type, value "DIFF_SSTL_18_Class_II", to port tdc_clk_n_i
Adding property syn_output_delay25, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=spec_clk20:r", to port pll_cs_o
Adding property syn_pad_type, value "LVCMOS_25", to port pll_cs_o
Adding property syn_loc, value "Y17", to port pll_cs_o
Adding property syn_loc, value "AB16", to port pll_dac_sync_o
Adding property syn_pad_type, value "LVCMOS_25", to port pll_dac_sync_o
Adding property syn_output_delay24, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=spec_clk20:r", to port pll_sdi_o
Adding property syn_pad_type, value "LVCMOS_25", to port pll_sdi_o
Adding property syn_loc, value "AA18", to port pll_sdi_o
Adding property syn_output_delay26, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=spec_clk20:r", to port pll_sclk_o
Adding property syn_pad_type, value "LVCMOS_25", to port pll_sclk_o
Adding property syn_loc, value "AB17", to port pll_sclk_o
Adding property syn_loc, value "V11", to port err_flag_i
Adding property syn_pad_type, value "LVCMOS_25", to port err_flag_i
Adding property syn_loc, value "W11", to port int_flag_i
Adding property syn_pad_type, value "LVCMOS_25", to port int_flag_i
Adding property syn_loc, value "T15", to port start_dis_o
Adding property syn_pad_type, value "LVCMOS_25", to port start_dis_o
Adding property syn_loc, value "W17", to port start_from_fpga_o
Adding property syn_pad_type, value "LVCMOS_25", to port start_from_fpga_o
Adding property syn_loc, value "U15", to port stop_dis_o
Adding property syn_pad_type, value "LVCMOS_25", to port stop_dis_o
Adding property syn_pad_type, value "LVCMOS_25", to port data_bus_io[27:0]
Adding property syn_loc, value "W12", to port ef1_i
Adding property syn_pad_type, value "LVCMOS_25", to port ef1_i
Adding property syn_loc, value "R11", to port ef2_i
Adding property syn_pad_type, value "LVCMOS_25", to port ef2_i
Adding property syn_loc, value "Y12", to port lf1_i
Adding property syn_pad_type, value "LVCMOS_25", to port lf1_i
Adding property syn_loc, value "T11", to port lf2_i
Adding property syn_pad_type, value "LVCMOS_25", to port lf2_i
Adding property syn_pad_type, value "LVCMOS_25", to port address_o[3:0]
Adding property syn_loc, value "T14", to port cs_n_o
Adding property syn_pad_type, value "LVCMOS_25", to port cs_n_o
Adding property syn_loc, value "V13", to port oe_n_o
Adding property syn_pad_type, value "LVCMOS_25", to port oe_n_o
Adding property syn_loc, value "AB13", to port rd_n_o
Adding property syn_pad_type, value "LVCMOS_25", to port rd_n_o
Adding property syn_loc, value "Y13", to port wr_n_o
Adding property syn_pad_type, value "LVCMOS_25", to port wr_n_o
Adding property syn_loc, value "AA14", to port tdc_in_fpga_5_i
Adding property syn_pad_type, value "LVCMOS_25", to port tdc_in_fpga_5_i
Adding property syn_loc, value "C19", to port mute_inputs_o
Adding property syn_pad_type, value "LVCMOS_25", to port mute_inputs_o
Adding property syn_loc, value "W13", to port tdc_led_status_o
Adding property syn_pad_type, value "LVCMOS_25", to port tdc_led_status_o
Adding property syn_loc, value "W14", to port tdc_led_trig1_o
Adding property syn_pad_type, value "LVCMOS_25", to port tdc_led_trig1_o
Adding property syn_loc, value "Y14", to port tdc_led_trig2_o
Adding property syn_pad_type, value "LVCMOS_25", to port tdc_led_trig2_o
Adding property syn_loc, value "Y16", to port tdc_led_trig3_o
Adding property syn_pad_type, value "LVCMOS_25", to port tdc_led_trig3_o
Adding property syn_loc, value "W15", to port tdc_led_trig4_o
Adding property syn_pad_type, value "LVCMOS_25", to port tdc_led_trig4_o
Adding property syn_loc, value "V17", to port tdc_led_trig5_o
Adding property syn_pad_type, value "LVCMOS_25", to port tdc_led_trig5_o
Adding property syn_loc, value "W18", to port term_en_1_o
Adding property syn_pad_type, value "LVCMOS_25", to port term_en_1_o
Adding property syn_loc, value "B20", to port term_en_2_o
Adding property syn_pad_type, value "LVCMOS_25", to port term_en_2_o
Adding property syn_loc, value "A20", to port term_en_3_o
Adding property syn_pad_type, value "LVCMOS_25", to port term_en_3_o
Adding property syn_loc, value "H10", to port term_en_4_o
Adding property syn_pad_type, value "LVCMOS_25", to port term_en_4_o
Adding property syn_loc, value "E6", to port term_en_5_o
Adding property syn_pad_type, value "LVCMOS_25", to port term_en_5_o
Adding property syn_loc, value "C22", to port spec_aux0_i
Adding property syn_pad_type, value "LVCMOS18", to port spec_aux0_i
Adding property syn_loc, value "D21", to port spec_aux1_i
Adding property syn_pad_type, value "LVCMOS18", to port spec_aux1_i
Adding property syn_loc, value "G19", to port spec_aux2_o
Adding property syn_pad_type, value "LVCMOS18", to port spec_aux2_o
Adding property syn_loc, value "F20", to port spec_aux3_o
Adding property syn_pad_type, value "LVCMOS18", to port spec_aux3_o
Adding property syn_loc, value "F18", to port spec_aux4_o
Adding property syn_pad_type, value "LVCMOS18", to port spec_aux4_o
Adding property syn_loc, value "C20", to port spec_aux5_o
Adding property syn_pad_type, value "LVCMOS18", to port spec_aux5_o
Adding property syn_loc, value "E5", to port spec_led_green_o
Adding property syn_pad_type, value "LVCMOS_25", to port spec_led_green_o
Adding property syn_loc, value "D5", to port spec_led_red_o
Adding property syn_pad_type, value "LVCMOS_25", to port spec_led_red_o
Adding property syn_loc, value "H12", to port spec_clk_i
Adding property syn_pad_type, value "LVCMOS_25", to port spec_clk_i
Reading Xilinx I/O pad type table from file [/afs/cern.ch/project/parc/elec/synplify/D-2010.03/lib/xilinx/x_io_tbl.txt] 
Reading Xilinx Rocket I/O parameter type table from file [/afs/cern.ch/project/parc/elec/synplify/D-2010.03/lib/xilinx/gttype.txt] 
@N: :  | Running in logic synthesis mode without enhanced optimization 
@W:BN132 : data_formatting.vhd(111) | Removing sequential instance mem_stb,  because it is equivalent to instance mem_we
@W:BN132 : data_formatting.vhd(109) | Removing sequential instance mem_cyc,  because it is equivalent to instance mem_we
@W:BN132 : clk_rst_managr.vhd(192) | Removing sequential instance silly_altern,  because it is equivalent to instance pll_sclk
@W:BN132 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cal_data_master,  because it is equivalent to instance cal_data_sint
@W:BN132 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cal_data_master,  because it is equivalent to instance cal_data_sint

Automatic dissolve at startup in view:work.dma_controller(behaviour) of dma_controller_wb_slave_0(dma_controller_wb_slave)
@N:BN116 : dma_controller_wb_slave.vhd(177) | Removing sequential instance dma_controller_wb_slave_0.dma_stat_int_write[31:0] of view:PrimLib.dffre(prim) because there are no references to its outputs 
@N:BN116 : dma_controller_wb_slave.vhd(474) | Removing sequential instance dma_controller_wb_slave_0.dma_stat_o[31:0] of view:PrimLib.dffre(prim) because there are no references to its outputs 
@N:BN116 : dma_controller_wb_slave.vhd(474) | Removing sequential instance dma_controller_wb_slave_0.dma_stat_load_o of view:PrimLib.dffr(prim) because there are no references to its outputs 
Automatic dissolve at startup in view:work.l2p_ser(rtl) of cmp_valid_out(serdes_n_to_1_s2_se_2_1)
Automatic dissolve at startup in view:work.l2p_ser(rtl) of cmp_dframe_out(serdes_n_to_1_s2_se_2_1)
Automatic dissolve at startup in view:work.l2p_ser(rtl) of cmp_data_out(serdes_n_to_1_s2_se_2_16)
Automatic dissolve at startup in view:work.l2p_ser(rtl) of cmp_clk_out(serdes_n_to_1_s2_diff)
Automatic dissolve at startup in view:work.gn4124_core(rtl) of cmp_l2p_ser(l2p_ser)
Automatic dissolve at startup in view:work.gn4124_core(rtl) of cmp_l2p_arbiter(l2p_arbiter)
Automatic dissolve at startup in view:work.gn4124_core(rtl) of cmp_p2l_decode32(p2l_decode32)
@N:BN116 : p2l_decode32.vhd(187) | Removing sequential instance cmp_p2l_decode32.p2l_hdr_stat[1:0] of view:PrimLib.dffre(prim) because there are no references to its outputs 
@N:BN116 : p2l_decode32.vhd(187) | Removing sequential instance cmp_p2l_decode32.p2l_hdr_last of view:PrimLib.dffre(prim) because there are no references to its outputs 
Automatic dissolve at startup in view:work.top_tdc(rtl) of reg_control_block(reg_ctrl)
Automatic dissolve at startup in view:work.top_tdc(rtl) of data_formatting_block(data_formatting)
Automatic dissolve at startup in view:work.top_tdc(rtl) of data_engine_block(data_engine)
Automatic dissolve at startup in view:work.top_tdc(rtl) of one_second_block(one_hz_gen)

Available hyper_sources - for debug and ip models
	None Found

Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 137MB peak: 141MB)

Encoding state machine work.top_tdc(rtl)-data_engine_block.engine_st[0:10]
original code -> new code
   00000000001 -> 00000000001
   00000000010 -> 00000000010
   00000000100 -> 00000000100
   00000001000 -> 00000001000
   00000010000 -> 00000010000
   00000100000 -> 00000100000
   00001000000 -> 00001000000
   00010000000 -> 00010000000
   00100000000 -> 00100000000
   01000000000 -> 01000000000
   10000000000 -> 10000000000
@N: : one_hz_gen.vhd(85) | Found counter in view:work.top_tdc(rtl) inst one_second_block.local_utc[31:0]
@N: : data_engine.vhd(111) | Found counter in view:work.top_tdc(rtl) inst data_engine_block.config_adr_counter[7:0]
@N: : free_counter.vhd(35) | Found counter in view:work.free_counter(rtl) inst value[31:0]
@N: : countdown_counter.vhd(37) | Found counter in view:work.countdown_counter(rtl) inst value[31:0]
@N:FX404 : countdown_counter.vhd(43) | Found addmux in view:work.countdown_counter(rtl) inst decount\.value_6[31:0] from decount\.value_5[31:0] 
@N: : incr_counter.vhd(36) | Found counter in view:work.incr_counter_retrig_nb_counter(rtl) inst value[31:0]
Encoding state machine work.acam_databus_interface(rtl)-acam_data_st[0:6]
original code -> new code
   0000001 -> 0000001
   0000010 -> 0000010
   0000100 -> 0000100
   0001000 -> 0001000
   0010000 -> 0010000
   0100000 -> 0100000
   1000000 -> 1000000
@N: : free_counter.vhd(35) | Found counter in view:work.free_counter_retrig_period_counter(rtl) inst value[31:0]
@N: : incr_counter.vhd(36) | Found counter in view:work.incr_counter_retrig_nb_counter_retrig_nb_counter(rtl) inst value[31:0]
@N: : incr_counter.vhd(36) | Found counter in view:work.incr_counter(rtl) inst value[31:0]
Encoding state machine work.circular_buffer(rtl)-wb_pipelined_st[0:3]
original code -> new code
   0001 -> 00
   0010 -> 01
   0100 -> 10
   1000 -> 11
Encoding state machine work.clk_rst_managr(rtl)-pll_init_st[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
@N:BN116 : clk_rst_managr.vhd(339) | Removing sequential instance pll_init_st[0] of view:PrimLib.dff(prim) because there are no references to its outputs 
@N: : incr_counter.vhd(36) | Found counter in view:work.incr_counter_general_poreset(rtl) inst value[31:0]
@N:FX404 : p2l_decode32.vhd(249) | Found addmux in view:work.gn4124_core(rtl) inst cmp_p2l_decode32.p_addr_decode\.p2l_addr_4[31:0] from cmp_p2l_decode32.un8_p2l_addr[29:0],cmp_p2l_decode32.un8_p2l_addr_un1,cmp_p2l_decode32.un8_p2l_addr_un0 
Encoding state machine work.serdes_1_to_n_clk_pll_s2_diff(arch_serdes_1_to_n_clk_pll_s2_diff)-state[0:8]
original code -> new code
   0000 -> 000000001
   0001 -> 000000010
   0010 -> 000000100
   0011 -> 000001000
   0100 -> 000010000
   0101 -> 000100000
   0110 -> 001000000
   0111 -> 010000000
   1001 -> 100000000
@N:BN116 :  | Removing sequential instance state[0] of view:PrimLib.dffr(prim) because there are no references to its outputs  
@N:BN116 :  | Removing sequential instance state[1] of view:PrimLib.dffr(prim) because there are no references to its outputs  
@N:BN116 :  | Removing sequential instance state[2] of view:PrimLib.dffr(prim) because there are no references to its outputs  
@N:BN116 :  | Removing sequential instance state[3] of view:PrimLib.dffr(prim) because there are no references to its outputs  
@N:BN116 : serdes_1_to_n_clk_pll_s2_diff.vhd(155) | Removing sequential instance count[2:0] of view:PrimLib.sdffr(prim) because there are no references to its outputs 
Encoding state machine work.serdes_1_to_n_data_s2_se_false_2_16(arch_serdes_1_to_n_data_s2_se)-state[0:1]
original code -> new code
   0000 -> 0
   0001 -> 1
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance mux[15] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance mux[14] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance mux[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance mux[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance mux[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance mux[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance mux[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance mux[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance mux[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance mux[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance mux[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance mux[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance mux[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance mux[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance mux[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
Encoding state machine work.serdes_1_to_n_data_s2_se_false_2_1(arch_serdes_1_to_n_data_s2_se)-state[0:1]
original code -> new code
   0000 -> 0
   0001 -> 1
Encoding state machine work.wbmaster32(behaviour)-wishbone_current_state[0:3]
original code -> new code
   0001 -> 00
   0010 -> 01
   0100 -> 10
   1000 -> 11
Encoding state machine work.wbmaster32(behaviour)-l2p_read_cpl_current_state[0:2]
original code -> new code
   001 -> 00
   010 -> 01
   100 -> 10
Encoding state machine work.dma_controller(behaviour)-dma_ctrl_current_state[0:6]
original code -> new code
   0000001 -> 0000001
   0000010 -> 0000010
   0000100 -> 0000100
   0001000 -> 0001000
   0010000 -> 0010000
   0100000 -> 0100000
   1000000 -> 1000000
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[30],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[29],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[28],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[27],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[26],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[25],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[24],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[23],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[22],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[21],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[20],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[19],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[18],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[17],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[16],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[15],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[14],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[13],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[12],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[11],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[10],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[9],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[8],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[7],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[6],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[5],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[4],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@W:BN132 : dma_controller_wb_slave.vhd(474) | Removing instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[3],  because it is equivalent to instance gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read[31]
@N:BN116 : dma_controller_wb_slave.vhd(474) | Removing sequential instance dma_controller_wb_slave_0.dma_stat_int_read[31] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@A:BN291 : dma_controller_wb_slave.vhd(474) | Boundary register dma_controller_wb_slave_0.dma_stat_int_read[31] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
Encoding state machine work.l2p_dma_master(behaviour)-l2p_dma_current_state[0:7]
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
@N: : l2p_dma_master.vhd(173) | Found counter in view:work.l2p_dma_master(behaviour) inst target_addr_cnt[29:0]
@N: : l2p_dma_master.vhd(173) | Found counter in view:work.l2p_dma_master(behaviour) inst dma_length_cnt[29:0]
@N: : l2p_dma_master.vhd(215) | Found counter in view:work.l2p_dma_master(behaviour) inst l2p_data_cnt[10:0]
@N: : l2p_dma_master.vhd(591) | Found counter in view:work.l2p_dma_master(behaviour) inst wb_ack_cnt[31:0]
@N: : l2p_dma_master.vhd(579) | Found counter in view:work.l2p_dma_master(behaviour) inst wb_read_cnt[31:0]
@N:FX404 : l2p_dma_master.vhd(226) | Found addmux in view:work.l2p_dma_master(behaviour) inst p_pkt_gen\.l2p_address_l_4[31:0] from un1_l2p_address_l[32:1] 
@N:MF179 :  | Found 32 bit by 32 bit '==' comparator, 'p_wb_master\.un2_wb_ack_cnt' 
Encoding state machine work.p2l_dma_master(behaviour)-p2l_dma_current_state[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
@N: : p2l_dma_master.vhd(458) | Found counter in view:work.p2l_dma_master(behaviour) inst target_addr_cnt[29:0]
@N: : p2l_dma_master.vhd(396) | Found counter in view:work.p2l_dma_master(behaviour) inst p2l_data_cnt[10:0]
@N: : p2l_dma_master.vhd(576) | Found counter in view:work.p2l_dma_master(behaviour) inst wb_ack_cnt[31:0]
@N: : p2l_dma_master.vhd(564) | Found counter in view:work.p2l_dma_master(behaviour) inst wb_write_cnt[31:0]
@N:MF179 :  | Found 32 bit by 32 bit '==' comparator, 'p_wb_master\.un2_wb_ack_cnt' 
@N: : free_counter.vhd(35) | Found counter in view:work.free_counter_spec_led_period_counter(rtl) inst value[31:0]
@N: : countdown_counter.vhd(37) | Found counter in view:work.countdown_counter_spec_led_blink_counter(rtl) inst value[31:0]
@N: : countdown_counter.vhd(37) | Found counter in view:work.countdown_counter_tdc_led_blink_counter(rtl) inst value[31:0]
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_valid_in.counter[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_valid_in.counter[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_valid_in.counter[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_valid_in.counter[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_valid_in.counter[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_valid_in.counter[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_valid_in.counter[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_valid_in.counter[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_valid_in.counter[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_valid_in.cal_data_sint of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_valid_in.enable of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_valid_in.state[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_dframe_in.counter[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_dframe_in.counter[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_dframe_in.counter[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_dframe_in.counter[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_dframe_in.counter[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_dframe_in.counter[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_dframe_in.counter[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_dframe_in.counter[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_dframe_in.counter[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_dframe_in.cal_data_sint of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_dframe_in.enable of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_dframe_in.state[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_data_in.counter[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_data_in.counter[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_data_in.counter[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_data_in.counter[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_data_in.counter[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_data_in.counter[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_data_in.counter[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_data_in.counter[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_data_in.counter[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_data_in.mux[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_data_in.cal_data_sint of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_data_in.enable of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : serdes_1_to_n_data_s2_se.vhd(141) | Removing sequential instance cmp_p2l_des.cmp_data_in.state[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@W:BN132 : acam_timecontrol_interface.vhd(96) | Removing instance acam_timing_block.refclk_r[3],  because it is equivalent to instance one_second_block.s_acam_refclk[3]
@W:BN132 : one_hz_gen.vhd(92) | Removing instance one_second_block.s_acam_refclk[2],  because it is equivalent to instance acam_timing_block.refclk_r[2]
@W:BN132 : acam_timecontrol_interface.vhd(96) | Removing instance acam_timing_block.refclk_r[1],  because it is equivalent to instance one_second_block.s_acam_refclk[1]
@W:BN132 : one_hz_gen.vhd(92) | Removing instance one_second_block.s_acam_refclk[0],  because it is equivalent to instance acam_timing_block.refclk_r[0]
@N:BN116 : start_retrigger_control.vhd(94) | Removing sequential instance start_retrigger_block.retrig_nb_offset[31] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs 
@A:BN291 : start_retrigger_control.vhd(94) | Boundary register start_retrigger_block.retrig_nb_offset[31] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : start_retrigger_control.vhd(94) | Removing sequential instance start_retrigger_block.retrig_nb_offset[30] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs 
@A:BN291 : start_retrigger_control.vhd(94) | Boundary register start_retrigger_block.retrig_nb_offset[30] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : start_retrigger_control.vhd(94) | Removing sequential instance start_retrigger_block.retrig_nb_offset[29] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs 
@A:BN291 : start_retrigger_control.vhd(94) | Boundary register start_retrigger_block.retrig_nb_offset[29] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : start_retrigger_control.vhd(94) | Removing sequential instance start_retrigger_block.retrig_nb_offset[28] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs 
@A:BN291 : start_retrigger_control.vhd(94) | Boundary register start_retrigger_block.retrig_nb_offset[28] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : start_retrigger_control.vhd(94) | Removing sequential instance start_retrigger_block.retrig_nb_offset[27] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs 
@A:BN291 : start_retrigger_control.vhd(94) | Boundary register start_retrigger_block.retrig_nb_offset[27] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : start_retrigger_control.vhd(94) | Removing sequential instance start_retrigger_block.retrig_nb_offset[26] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs 
@A:BN291 : start_retrigger_control.vhd(94) | Boundary register start_retrigger_block.retrig_nb_offset[26] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : start_retrigger_control.vhd(152) | Removing sequential instance start_retrigger_block.roll_over_counter.count_done of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@N:BN116 : start_retrigger_control.vhd(138) | Removing sequential instance start_retrigger_block.retrig_nb_counter.count_done of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@N:BN116 : acam_timecontrol_interface.vhd(99) | Removing sequential instance acam_timing_block.err_flag_r[2] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@A:BN291 : acam_timecontrol_interface.vhd(99) | Boundary register acam_timing_block.err_flag_r[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : acam_timecontrol_interface.vhd(99) | Removing sequential instance acam_timing_block.err_flag_r[1] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@A:BN291 : acam_timecontrol_interface.vhd(99) | Boundary register acam_timing_block.err_flag_r[1] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : acam_timecontrol_interface.vhd(99) | Removing sequential instance acam_timing_block.err_flag_r[0] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@A:BN291 : acam_timecontrol_interface.vhd(99) | Boundary register acam_timing_block.err_flag_r[0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@N:BN116 : acam_timecontrol_interface.vhd(167) | Removing sequential instance acam_timing_block.window_active_counter.count_done of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
Finished factoring (Time elapsed 0h:00m:09s; Memory used current: 189MB peak: 190MB)

@N:BN116 : p2l_decode32.vhd(187) | Removing sequential instance gnum_interface_block.cmp_p2l_decode32.p2l_hdr_length[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : p2l_decode32.vhd(187) | Removing sequential instance gnum_interface_block.cmp_p2l_decode32.p2l_hdr_length[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : p2l_decode32.vhd(187) | Removing sequential instance gnum_interface_block.cmp_p2l_decode32.p2l_hdr_length[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : p2l_decode32.vhd(187) | Removing sequential instance gnum_interface_block.cmp_p2l_decode32.p2l_hdr_length[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : p2l_decode32.vhd(187) | Removing sequential instance gnum_interface_block.cmp_p2l_decode32.p2l_hdr_length[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : p2l_decode32.vhd(187) | Removing sequential instance gnum_interface_block.cmp_p2l_decode32.p2l_hdr_length[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : p2l_decode32.vhd(187) | Removing sequential instance gnum_interface_block.cmp_p2l_decode32.p2l_hdr_length[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : p2l_decode32.vhd(187) | Removing sequential instance gnum_interface_block.cmp_p2l_decode32.p2l_hdr_length[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : p2l_decode32.vhd(187) | Removing sequential instance gnum_interface_block.cmp_p2l_decode32.p2l_hdr_length[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : p2l_decode32.vhd(187) | Removing sequential instance gnum_interface_block.cmp_p2l_decode32.p2l_hdr_length[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : p2l_decode32.vhd(187) | Removing sequential instance gnum_interface_block.cmp_p2l_decode32.p2l_hdr_fbe[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : p2l_decode32.vhd(187) | Removing sequential instance gnum_interface_block.cmp_p2l_decode32.p2l_hdr_fbe[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : p2l_decode32.vhd(187) | Removing sequential instance gnum_interface_block.cmp_p2l_decode32.p2l_hdr_fbe[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : p2l_decode32.vhd(187) | Removing sequential instance gnum_interface_block.cmp_p2l_decode32.p2l_hdr_fbe[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : p2l_decode32.vhd(187) | Removing sequential instance gnum_interface_block.cmp_p2l_decode32.p2l_hdr_lbe[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : p2l_decode32.vhd(187) | Removing sequential instance gnum_interface_block.cmp_p2l_decode32.p2l_hdr_lbe[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : p2l_decode32.vhd(187) | Removing sequential instance gnum_interface_block.cmp_p2l_decode32.p2l_hdr_lbe[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : p2l_decode32.vhd(187) | Removing sequential instance gnum_interface_block.cmp_p2l_decode32.p2l_hdr_lbe[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : p2l_decode32.vhd(306) | Removing sequential instance gnum_interface_block.cmp_p2l_decode32.p2l_be[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : p2l_decode32.vhd(306) | Removing sequential instance gnum_interface_block.cmp_p2l_decode32.p2l_be[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : p2l_decode32.vhd(306) | Removing sequential instance gnum_interface_block.cmp_p2l_decode32.p2l_be[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : p2l_decode32.vhd(306) | Removing sequential instance gnum_interface_block.cmp_p2l_decode32.p2l_be[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : dma_controller.vhd(327) | Removing sequential instance gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : dma_controller.vhd(327) | Removing sequential instance gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : dma_controller.vhd(327) | Removing sequential instance gnum_interface_block.cmp_dma_controller.dma_ctrl_len_o[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : dma_controller.vhd(327) | Removing sequential instance gnum_interface_block.cmp_dma_controller.dma_ctrl_len_o[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N:BN116 : wbmaster32.vhd(344) | Removing sequential instance gnum_interface_block.cmp_wbmaster32.wb_sel_t[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@A:BN291 : wbmaster32.vhd(344) | Boundary register gnum_interface_block.cmp_wbmaster32.wb_sel_t[0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 


#################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[

======================================================================================
                                Instance:Pin        Generated Clock Optimization Status
======================================================================================
                          tdc_led_status:C              Not Done
                            spec_led_red:C              Not Done
gnum_interface_block.cmp_p2l_decode32.p2l_addr_start:C              Not Done


##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################]

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:09s; Memory used current: 179MB peak: 191MB)

@N:FX430 :  | Found 3 global buffers instantiated by user  
Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:12s; Memory used current: 169MB peak: 191MB)

@N:FX276 : clk_rst_managr.vhd(390) | Startup value clks_rsts_mgment.un7_word_being_sent_0_0.INIT_00 = 000000000000000000000000000000000000000000000000FD1FF51EFECFFECE
@N:FX276 : clk_rst_managr.vhd(390) | Startup value clks_rsts_mgment.un7_word_being_sent_0_0.INIT_04 = ECE9FCE8E0E7FCE6FCEDF0ECD8EBFCEAF0FCFCFB0CEFF8EEFACD9CFFFCFEBCFD
@N:FX276 : clk_rst_managr.vhd(390) | Startup value clks_rsts_mgment.un7_word_being_sent_0_0.INIT_05 = F859FC58FC57F856FC5DF85CFC5BFC5AFCE1C4E0F85FFC5EFCE5FCE4F4E3FCE2
@N:FX276 : clk_rst_managr.vhd(390) | Startup value clks_rsts_mgment.un7_word_being_sent_0_0.INIT_06 = FD6FFD6EFD6DFD6CD5BF95BEF1BDF5BCD40DD40CD40BD40AFC55FC54D40FD40E
@N:FX276 : clk_rst_managr.vhd(390) | Startup value clks_rsts_mgment.un7_word_being_sent_0_0.INIT_07 = B95F7D5EFD5DFD5CFD63FD627561FD60FD677566FD65B964FD6BFD6AFD69FD68
@N:FX276 : clk_rst_managr.vhd(390) | Startup value clks_rsts_mgment.un7_word_being_sent_0_0.INITP_00 = FFFFFF7DDFAAFFFFFFFFFFFFFFFF3BFF000000000000000000000000000000FF
@N:FX211 :  | Packed ROM clks_rsts_mgment.un7_word_being_sent_0[17:0] (7 input, 18 output) to Block SelectRAM  
@N:FX404 : p2l_dma_master.vhd(248) | Found addmux in view:work.top_tdc(rtl) inst gnum_interface_block.cmp_p2l_dma_master.p_read_req\.l2p_len_cnt_6_0[29:10] from gnum_interface_block.cmp_p2l_dma_master.l2p_len_cnt_4[29:10] 
@A:BN291 : free_counter.vhd(35) | Boundary register spec_led_period_counter.value[31:0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A:BN291 : countdown_counter.vhd(37) | Boundary register spec_led_blink_counter.value[31:0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A:BN291 : incr_counter.vhd(36) | Boundary register clks_rsts_mgment.general_poreset.value[31:0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. 
Starting Early Timing Optimization (Time elapsed 0h:00m:16s; Memory used current: 173MB peak: 191MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:21s; Memory used current: 173MB peak: 191MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:21s; Memory used current: 171MB peak: 191MB)

@N:BN116 : p2l_decode32.vhd(220) | Removing sequential instance gnum_interface_block.cmp_p2l_decode32.p2l_addr[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
Finished preparing to map (Time elapsed 0h:00m:25s; Memory used current: 174MB peak: 191MB)

Finished technology mapping (Time elapsed 0h:00m:28s; Memory used current: 174MB peak: 191MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:29s		    -3.07ns		3453 /      4172
   2		0h:00m:29s		    -3.07ns		3450 /      4172
   3		0h:00m:30s		    -3.07ns		3450 /      4172
------------------------------------------------------------

Timing driven replication report
@N:FX271 : l2p_dma_master.vhd(180) | Instance "gnum_interface_block.cmp_l2p_dma_master.l2p_dma_current_state[7]" with 117 loads has been replicated 3 time(s) to improve timing 
Added 3 Registers via timing driven replication
Added 3 LUTs via timing driven replication

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:38s		    -3.07ns		3452 /      4175
Timing driven replication report
No replication required.

   2		0h:00m:39s		    -3.07ns		3452 /      4175
   3		0h:00m:39s		    -3.07ns		3454 /      4175
   4		0h:00m:40s		    -3.07ns		3455 /      4175
   5		0h:00m:40s		    -3.07ns		3455 /      4175
   6		0h:00m:40s		    -3.07ns		3455 /      4175
------------------------------------------------------------

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:41s		    -3.07ns		3455 /      4175
Timing driven replication report
No replication required.

   2		0h:00m:42s		    -3.07ns		3455 /      4175
   3		0h:00m:42s		    -3.07ns		3455 /      4175
   4		0h:00m:43s		    -3.07ns		3455 /      4175
------------------------------------------------------------

Net buffering Report for view:work.top_tdc(rtl):
No nets needed buffering.

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:44s; Memory used current: 176MB peak: 191MB)

@N:FX623 :  | Packing into LUT62 
Finished restoring hierarchy (Time elapsed 0h:00m:45s; Memory used current: 178MB peak: 191MB)

@W:BN102 :  | Cannot find object p2l_data_i to apply define_input_delay  
@W:BN102 :  | Cannot find object p_wr_req_i to apply define_input_delay  
@W:BN102 :  | Cannot find object vc_rdy_i to apply define_input_delay  
@W:BN103 :  | Cannot find object p_wr_rdy_o to apply define_output_delay  
@W:BN103 :  | Cannot find object l2p_data_o to apply define_output_delay  
@W:BN102 :  | Cannot find object l_wr_rdy_i to apply define_input_delay  
@W:BN102 :  | Cannot find object p_rd_d_rdy_i to apply define_input_delay  
Writing Analyst data base /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/syn_tdc.srm
Finished Writing Netlist Databases (Time elapsed 0h:00m:49s; Memory used current: 170MB peak: 191MB)

Writing EDIF Netlist and constraint files
D-2010.03
Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:50s; Memory used current: 177MB peak: 191MB)

Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:51s; Memory used current: 171MB peak: 191MB)

@N:MF276 :  | Gated clock conversion enabled, but no gated clocks found in design  
Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:51s; Memory used current: 171MB peak: 191MB)

Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:51s; Memory used current: 171MB peak: 191MB)

@N:MF333 :  | Generated clock conversion enabled, but no generated clocks found in design  
Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:51s; Memory used current: 171MB peak: 191MB)

Found clock tdc_clk125 with period 8.00ns 
Found clock spec_clk20 with period 50.00ns 
Found clock gnum_clk200 with period 5.00ns 
@W:MT420 :  | Found inferred clock serdes_1_to_n_clk_pll_s2_diff|buf_pll_fb_clk_inferred_clock with period 5.00ns. A user-defined clock should be declared on object "n:gnum_interface_block.cmp_clk_in.buf_pll_fb_clk" 

@W:MT420 :  | Found inferred clock serdes_1_to_n_clk_pll_s2_diff|buf_P_clk_inferred_clock with period 5.00ns. A user-defined clock should be declared on object "n:gnum_interface_block.cmp_clk_in.buf_P_clk" 

All Input Ports in the design have input constraint of 2.00ns w.r.t. clock tdc_clk125:r 
All Output Ports in the design have output constraint of 2.00ns w.r.t. clock tdc_clk125:r 
Port p2l_clk_p_i - has input  constraint of 2.00ns w.r.t. clock gnum_clk200:r 
Port p2l_clk_n_i - has input  constraint of 2.00ns w.r.t. clock gnum_clk200:r 
Port p2l_dframe_i - has input  constraint of 2.00ns w.r.t. clock gnum_clk200:r 
Port p2l_valid_i - has input  constraint of 2.00ns w.r.t. clock gnum_clk200:r 
Port p2l_rdy_o - has output constraint of 2.00ns w.r.t. clock gnum_clk200:r 
Port rx_error_o - has output constraint of 2.00ns w.r.t. clock gnum_clk200:r 
Port l2p_clk_p_o - has output constraint of 2.00ns w.r.t. clock gnum_clk200:r 
Port l2p_clk_n_o - has output constraint of 2.00ns w.r.t. clock gnum_clk200:r 
Port l2p_dframe_o - has output constraint of 2.00ns w.r.t. clock gnum_clk200:r 
Port l2p_valid_o - has output constraint of 2.00ns w.r.t. clock gnum_clk200:r 
Port l2p_edb_o - has output constraint of 2.00ns w.r.t. clock gnum_clk200:r 
Port l2p_rdy_i - has input  constraint of 2.00ns w.r.t. clock gnum_clk200:r 
Port tx_error_i - has input  constraint of 2.00ns w.r.t. clock gnum_clk200:r 
Port spare_o - has output constraint of 2.00ns w.r.t. clock gnum_clk200:r 
Port pll_ld_i - has input  constraint of 2.00ns w.r.t. clock spec_clk20:r 
Port pll_refmon_i - has input  constraint of 2.00ns w.r.t. clock spec_clk20:r 
Port pll_sdo_i - has input  constraint of 2.00ns w.r.t. clock spec_clk20:r 
Port pll_status_i - has input  constraint of 2.00ns w.r.t. clock spec_clk20:r 
Port pll_cs_o - has output constraint of 2.00ns w.r.t. clock spec_clk20:r 
Port pll_sdi_o - has output constraint of 2.00ns w.r.t. clock spec_clk20:r 
Port pll_sclk_o - has output constraint of 2.00ns w.r.t. clock spec_clk20:r 
@W:MT246 : circular_buffer.vhd(189) | Blackbox blk_mem_circ_buff_v6_4 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT246 : serdes_1_to_n_clk_pll_s2_diff.vhd(220) | Blackbox IODELAY2 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT246 : serdes_1_to_n_clk_pll_s2_diff.vhd(277) | Blackbox BUFIO2 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT246 : serdes_1_to_n_clk_pll_s2_diff.vhd(286) | Blackbox BUFIO2FB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT246 : serdes_1_to_n_clk_pll_s2_diff.vhd(292) | Blackbox ISERDES2 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT246 : serdes_1_to_n_clk_pll_s2_diff.vhd(408) | Blackbox BUFPLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT246 : wbmaster32.vhd(302) | Blackbox fifo_64x512 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT246 : wbmaster32.vhd(323) | Blackbox fifo_32x512 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT246 : serdes_n_to_1_s2_diff.vhd(199) | Blackbox OSERDES2 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 


##### START OF TIMING REPORT #####[
# Timing Report written on Fri Nov  4 11:36:03 2011
#


Top view:               top_tdc
Requested Frequency:    20.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/tdc_syn_constraints.sdc
                       
@N:MT320 :  | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. 


Performance Summary 
*******************


Worst slack in design: -4.688

                   Requested     Estimated     Requested     Estimated                Clock        Clock              
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group              
----------------------------------------------------------------------------------------------------------------------
gnum_clk200        200.0 MHz     158.6 MHz     5.000         6.306         -1.306     declared     default_clkgroup__3
spec_clk20         20.0 MHz      58.1 MHz      50.000        17.200        32.800     declared     default_clkgroup__2
tdc_clk125         125.0 MHz     135.9 MHz     8.000         7.360         0.640      declared     default_clkgroup__1
System             200.0 MHz     474.1 MHz     5.000         2.109         2.891      system       default_clkgroup3  
======================================================================================================================





Clock Relationships
*******************

Clocks                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-----------------------------------------------------------------------------------------------------------------
Starting     Ending       |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-----------------------------------------------------------------------------------------------------------------
tdc_clk125   tdc_clk125   |  8.000       0.640   |  No paths    -      |  No paths    -      |  No paths    -    
tdc_clk125   spec_clk20   |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
tdc_clk125   gnum_clk200  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
spec_clk20   tdc_clk125   |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
spec_clk20   spec_clk20   |  50.000      32.800  |  No paths    -      |  No paths    -      |  No paths    -    
gnum_clk200  tdc_clk125   |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
gnum_clk200  gnum_clk200  |  5.000       -1.306  |  No paths    -      |  No paths    -      |  No paths    -    
=================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************



Input Ports: 

Port                Starting                 User           Arrival     Required           
Name                Reference                Constraint     Time        Time         Slack 
                    Clock                                                                  
-------------------------------------------------------------------------------------------
acam_refclk_i       tdc_clk125 (rising)      2.000          2.000       7.290        5.290 
data_bus_io[0]      tdc_clk125 (rising)      2.000          2.000       25.756       23.756
data_bus_io[1]      tdc_clk125 (rising)      2.000          2.000       25.756       23.756
data_bus_io[2]      tdc_clk125 (rising)      2.000          2.000       25.756       23.756
data_bus_io[3]      tdc_clk125 (rising)      2.000          2.000       25.756       23.756
data_bus_io[4]      tdc_clk125 (rising)      2.000          2.000       25.756       23.756
data_bus_io[5]      tdc_clk125 (rising)      2.000          2.000       25.756       23.756
data_bus_io[6]      tdc_clk125 (rising)      2.000          2.000       25.756       23.756
data_bus_io[7]      tdc_clk125 (rising)      2.000          2.000       25.756       23.756
data_bus_io[8]      tdc_clk125 (rising)      2.000          2.000       25.756       23.756
data_bus_io[9]      tdc_clk125 (rising)      2.000          2.000       25.756       23.756
data_bus_io[10]     tdc_clk125 (rising)      2.000          2.000       25.756       23.756
data_bus_io[11]     tdc_clk125 (rising)      2.000          2.000       25.756       23.756
data_bus_io[12]     tdc_clk125 (rising)      2.000          2.000       25.756       23.756
data_bus_io[13]     tdc_clk125 (rising)      2.000          2.000       25.756       23.756
data_bus_io[14]     tdc_clk125 (rising)      2.000          2.000       25.756       23.756
data_bus_io[15]     tdc_clk125 (rising)      2.000          2.000       25.756       23.756
data_bus_io[16]     tdc_clk125 (rising)      2.000          2.000       25.756       23.756
data_bus_io[17]     tdc_clk125 (rising)      2.000          2.000       25.756       23.756
data_bus_io[18]     tdc_clk125 (rising)      2.000          2.000       25.756       23.756
data_bus_io[19]     tdc_clk125 (rising)      2.000          2.000       25.756       23.756
data_bus_io[20]     tdc_clk125 (rising)      2.000          2.000       25.756       23.756
data_bus_io[21]     tdc_clk125 (rising)      2.000          2.000       25.756       23.756
data_bus_io[22]     tdc_clk125 (rising)      2.000          2.000       25.756       23.756
data_bus_io[23]     tdc_clk125 (rising)      2.000          2.000       25.756       23.756
data_bus_io[24]     tdc_clk125 (rising)      2.000          2.000       25.756       23.756
data_bus_io[25]     tdc_clk125 (rising)      2.000          2.000       25.756       23.756
data_bus_io[26]     tdc_clk125 (rising)      2.000          2.000       25.756       23.756
data_bus_io[27]     tdc_clk125 (rising)      2.000          2.000       25.756       23.756
ef1_i               tdc_clk125 (rising)      2.000          2.000       7.290        5.290 
ef2_i               tdc_clk125 (rising)      2.000          2.000       7.290        5.290 
err_flag_i          tdc_clk125 (rising)      2.000          NA          NA           NA    
int_flag_i          tdc_clk125 (rising)      2.000          2.000       7.290        5.290 
l2p_rdy_i           gnum_clk200 (rising)     2.000          2.000       2.805        0.805 
l_wr_rdy_i[0]       tdc_clk125 (rising)      2.000          NA          NA           NA    
l_wr_rdy_i[1]       tdc_clk125 (rising)      2.000          NA          NA           NA    
lf1_i               tdc_clk125 (rising)      2.000          2.000       7.290        5.290 
lf2_i               tdc_clk125 (rising)      2.000          2.000       7.290        5.290 
p2l_clk_n_i         gnum_clk200 (rising)     2.000          2.000       5.539        3.539 
p2l_clk_p_i         gnum_clk200 (rising)     2.000          2.000       5.539        3.539 
p2l_data_i[0]       tdc_clk125 (rising)      2.000          2.000       10.072       8.072 
p2l_data_i[1]       tdc_clk125 (rising)      2.000          2.000       10.072       8.072 
p2l_data_i[2]       tdc_clk125 (rising)      2.000          2.000       10.072       8.072 
p2l_data_i[3]       tdc_clk125 (rising)      2.000          2.000       10.072       8.072 
p2l_data_i[4]       tdc_clk125 (rising)      2.000          2.000       10.072       8.072 
p2l_data_i[5]       tdc_clk125 (rising)      2.000          2.000       10.072       8.072 
p2l_data_i[6]       tdc_clk125 (rising)      2.000          2.000       10.072       8.072 
p2l_data_i[7]       tdc_clk125 (rising)      2.000          2.000       10.072       8.072 
p2l_data_i[8]       tdc_clk125 (rising)      2.000          2.000       10.072       8.072 
p2l_data_i[9]       tdc_clk125 (rising)      2.000          2.000       10.072       8.072 
p2l_data_i[10]      tdc_clk125 (rising)      2.000          2.000       10.072       8.072 
p2l_data_i[11]      tdc_clk125 (rising)      2.000          2.000       10.072       8.072 
p2l_data_i[12]      tdc_clk125 (rising)      2.000          2.000       10.072       8.072 
p2l_data_i[13]      tdc_clk125 (rising)      2.000          2.000       10.072       8.072 
p2l_data_i[14]      tdc_clk125 (rising)      2.000          2.000       10.072       8.072 
p2l_data_i[15]      tdc_clk125 (rising)      2.000          2.000       10.072       8.072 
p2l_dframe_i        gnum_clk200 (rising)     2.000          2.000       5.587        3.587 
p2l_valid_i         gnum_clk200 (rising)     2.000          2.000       5.587        3.587 
p_rd_d_rdy_i[0]     tdc_clk125 (rising)      2.000          NA          NA           NA    
p_rd_d_rdy_i[1]     tdc_clk125 (rising)      2.000          NA          NA           NA    
p_wr_req_i[0]       tdc_clk125 (rising)      2.000          NA          NA           NA    
p_wr_req_i[1]       tdc_clk125 (rising)      2.000          NA          NA           NA    
pll_ld_i            spec_clk20 (rising)      2.000          NA          NA           NA    
pll_refmon_i        spec_clk20 (rising)      2.000          NA          NA           NA    
pll_sdo_i           spec_clk20 (rising)      2.000          NA          NA           NA    
pll_status_i        spec_clk20 (rising)      2.000          NA          NA           NA    
rst_n_a_i           tdc_clk125 (rising)      2.000          2.000       8.573        6.573 
spec_aux0_i         tdc_clk125 (rising)      2.000          NA          NA           NA    
spec_aux1_i         tdc_clk125 (rising)      2.000          NA          NA           NA    
spec_clk_i          NA                       NA             NA          NA           NA    
tdc_clk_n_i         tdc_clk125 (rising)      2.000          NA          NA           NA    
tdc_clk_p_i         NA                       NA             NA          NA           NA    
tdc_in_fpga_5_i     tdc_clk125 (rising)      2.000          NA          NA           NA    
tx_error_i          gnum_clk200 (rising)     2.000          NA          NA           NA    
vc_rdy_i[0]         tdc_clk125 (rising)      2.000          NA          NA           NA    
vc_rdy_i[1]         tdc_clk125 (rising)      2.000          NA          NA           NA    
===========================================================================================


Output Ports: 

Port                  Starting                 User                          Arrival     Required           
Name                  Reference                Constraint                    Time        Time         Slack 
                      Clock                                                                                 
------------------------------------------------------------------------------------------------------------
address_o[0]          tdc_clk125 (rising)      2.000(tdc_clk125 rising)      10.664      22.000       11.336
address_o[1]          tdc_clk125 (rising)      2.000(tdc_clk125 rising)      10.520      22.000       11.480
address_o[2]          tdc_clk125 (rising)      2.000(tdc_clk125 rising)      10.742      22.000       11.258
address_o[3]          tdc_clk125 (rising)      2.000(tdc_clk125 rising)      11.527      22.000       10.473
cs_n_o                tdc_clk125 (rising)      2.000(tdc_clk125 rising)      4.823       6.000        1.177 
data_bus_io[0]        tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.486      22.000       6.514 
data_bus_io[1]        tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.284      22.000       6.716 
data_bus_io[2]        tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.486      22.000       6.514 
data_bus_io[3]        tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.486      22.000       6.514 
data_bus_io[4]        tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.486      22.000       6.514 
data_bus_io[5]        tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.486      22.000       6.514 
data_bus_io[6]        tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.486      22.000       6.514 
data_bus_io[7]        tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.486      22.000       6.514 
data_bus_io[8]        tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.486      22.000       6.514 
data_bus_io[9]        tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.486      22.000       6.514 
data_bus_io[10]       tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.486      22.000       6.514 
data_bus_io[11]       tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.486      22.000       6.514 
data_bus_io[12]       tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.486      22.000       6.514 
data_bus_io[13]       tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.486      22.000       6.514 
data_bus_io[14]       tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.486      22.000       6.514 
data_bus_io[15]       tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.486      22.000       6.514 
data_bus_io[16]       tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.486      22.000       6.514 
data_bus_io[17]       tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.486      22.000       6.514 
data_bus_io[18]       tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.486      22.000       6.514 
data_bus_io[19]       tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.486      22.000       6.514 
data_bus_io[20]       tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.486      22.000       6.514 
data_bus_io[21]       tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.486      22.000       6.514 
data_bus_io[22]       tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.417      22.000       6.583 
data_bus_io[23]       tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.417      22.000       6.583 
data_bus_io[24]       tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.486      22.000       6.514 
data_bus_io[25]       tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.486      22.000       6.514 
data_bus_io[26]       tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.486      22.000       6.514 
data_bus_io[27]       tdc_clk125 (rising)      2.000(tdc_clk125 rising)      15.486      22.000       6.514 
irq_p_o               gnum_clk200 (rising)     2.000(tdc_clk125 rising)      8.262       NA           NA    
l2p_clk_p_o           System (rising)          2.000(gnum_clk200 rising)     3.958       0.377        -3.582
l2p_data_o[0]         System (rising)          2.000(tdc_clk125 rising)      3.958       1.892        -2.067
l2p_data_o[1]         System (rising)          2.000(tdc_clk125 rising)      3.958       1.892        -2.067
l2p_data_o[2]         System (rising)          2.000(tdc_clk125 rising)      3.958       1.892        -2.067
l2p_data_o[3]         System (rising)          2.000(tdc_clk125 rising)      3.958       1.892        -2.067
l2p_data_o[4]         System (rising)          2.000(tdc_clk125 rising)      3.958       1.892        -2.067
l2p_data_o[5]         System (rising)          2.000(tdc_clk125 rising)      3.958       1.892        -2.067
l2p_data_o[6]         System (rising)          2.000(tdc_clk125 rising)      3.958       1.892        -2.067
l2p_data_o[7]         System (rising)          2.000(tdc_clk125 rising)      3.958       1.892        -2.067
l2p_data_o[8]         System (rising)          2.000(tdc_clk125 rising)      3.958       1.892        -2.067
l2p_data_o[9]         System (rising)          2.000(tdc_clk125 rising)      3.958       1.892        -2.067
l2p_data_o[10]        System (rising)          2.000(tdc_clk125 rising)      3.958       1.892        -2.067
l2p_data_o[11]        System (rising)          2.000(tdc_clk125 rising)      3.958       1.892        -2.067
l2p_data_o[12]        System (rising)          2.000(tdc_clk125 rising)      3.958       1.892        -2.067
l2p_data_o[13]        System (rising)          2.000(tdc_clk125 rising)      3.958       1.892        -2.067
l2p_data_o[14]        System (rising)          2.000(tdc_clk125 rising)      3.958       1.892        -2.067
l2p_data_o[15]        System (rising)          2.000(tdc_clk125 rising)      3.958       1.892        -2.067
l2p_dframe_o          System (rising)          2.000(gnum_clk200 rising)     3.958       0.377        -3.582
l2p_edb_o             gnum_clk200 (rising)     2.000(gnum_clk200 rising)     3.337       3.000        -0.337
l2p_valid_o           System (rising)          2.000(gnum_clk200 rising)     3.958       0.377        -3.582
mute_inputs_o         tdc_clk125 (rising)      2.000(tdc_clk125 rising)      4.823       6.000        1.177 
p2l_rdy_o             System (rising)          2.000(gnum_clk200 rising)     5.064       0.377        -4.688
p_wr_rdy_o[0]         System (rising)          2.000(tdc_clk125 rising)      4.917       1.892        -3.025
p_wr_rdy_o[1]         System (rising)          2.000(tdc_clk125 rising)      4.917       1.892        -3.025
pll_cs_o              spec_clk20 (rising)      2.000(spec_clk20 rising)      9.920       48.000       38.080
pll_sclk_o            spec_clk20 (rising)      2.000(spec_clk20 rising)      4.823       48.000       43.177
pll_sdi_o             spec_clk20 (rising)      2.000(spec_clk20 rising)      15.200      48.000       32.800
rd_n_o                tdc_clk125 (rising)      2.000(tdc_clk125 rising)      4.823       6.000        1.177 
rx_error_o            gnum_clk200 (rising)     2.000(gnum_clk200 rising)     3.337       3.000        -0.337
spec_aux2_o           spec_clk20 (rising)      2.000(tdc_clk125 rising)      4.823       NA           NA    
spec_aux3_o           spec_clk20 (rising)      2.000(tdc_clk125 rising)      4.823       NA           NA    
spec_aux4_o           tdc_clk125 (rising)      2.000(tdc_clk125 rising)      4.823       NA           NA    
spec_aux5_o           tdc_clk125 (rising)      2.000(tdc_clk125 rising)      4.823       NA           NA    
spec_led_green_o      tdc_clk125 (rising)      2.000(tdc_clk125 rising)      4.823       NA           NA    
spec_led_red_o        tdc_clk125 (rising)      2.000(tdc_clk125 rising)      4.823       NA           NA    
start_from_fpga_o     tdc_clk125 (rising)      2.000(tdc_clk125 rising)      4.823       14.000       9.177 
tdc_led_status_o      tdc_clk125 (rising)      2.000(tdc_clk125 rising)      4.823       NA           NA    
tdc_led_trig1_o       tdc_clk125 (rising)      2.000(tdc_clk125 rising)      4.823       NA           NA    
tdc_led_trig2_o       tdc_clk125 (rising)      2.000(tdc_clk125 rising)      4.823       NA           NA    
tdc_led_trig3_o       tdc_clk125 (rising)      2.000(tdc_clk125 rising)      4.823       NA           NA    
tdc_led_trig4_o       tdc_clk125 (rising)      2.000(tdc_clk125 rising)      4.823       NA           NA    
tdc_led_trig5_o       tdc_clk125 (rising)      2.000(tdc_clk125 rising)      4.823       NA           NA    
term_en_1_o           tdc_clk125 (rising)      2.000(tdc_clk125 rising)      4.823       6.000        1.177 
term_en_2_o           tdc_clk125 (rising)      2.000(tdc_clk125 rising)      4.823       6.000        1.177 
term_en_3_o           tdc_clk125 (rising)      2.000(tdc_clk125 rising)      4.823       6.000        1.177 
term_en_4_o           tdc_clk125 (rising)      2.000(tdc_clk125 rising)      4.823       6.000        1.177 
term_en_5_o           tdc_clk125 (rising)      2.000(tdc_clk125 rising)      4.823       6.000        1.177 
wr_n_o                tdc_clk125 (rising)      2.000(tdc_clk125 rising)      4.823       6.000        1.177 
============================================================================================================



====================================
Detailed Report for Clock: gnum_clk200
====================================



Starting Points with Worst Slack
********************************

                                                            Starting                                                                                     Arrival           
Instance                                                    Reference       Type     Pin     Net                                                         Time        Slack 
                                                            Clock                                                                                                          
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
gnum_interface_block.cmp_dma_controller.dma_len_reg[20]     gnum_clk200     FDCE     Q       gnum_interface_block.cmp_dma_controller.dma_len_reg[20]     3.154       -1.306
gnum_interface_block.cmp_dma_controller.dma_len_reg[21]     gnum_clk200     FDCE     Q       gnum_interface_block.cmp_dma_controller.dma_len_reg[21]     3.154       -1.306
gnum_interface_block.cmp_dma_controller.dma_len_reg[24]     gnum_clk200     FDCE     Q       gnum_interface_block.cmp_dma_controller.dma_len_reg[24]     3.154       -1.306
gnum_interface_block.cmp_dma_controller.dma_len_reg[25]     gnum_clk200     FDCE     Q       gnum_interface_block.cmp_dma_controller.dma_len_reg[25]     3.154       -1.306
gnum_interface_block.cmp_dma_controller.dma_len_reg[26]     gnum_clk200     FDCE     Q       gnum_interface_block.cmp_dma_controller.dma_len_reg[26]     3.154       -1.306
gnum_interface_block.cmp_dma_controller.dma_len_reg[27]     gnum_clk200     FDCE     Q       gnum_interface_block.cmp_dma_controller.dma_len_reg[27]     3.154       -1.306
gnum_interface_block.cmp_dma_controller.dma_len_reg[22]     gnum_clk200     FDCE     Q       gnum_interface_block.cmp_dma_controller.dma_len_reg[22]     3.154       -1.288
gnum_interface_block.cmp_dma_controller.dma_len_reg[23]     gnum_clk200     FDCE     Q       gnum_interface_block.cmp_dma_controller.dma_len_reg[23]     3.154       -1.288
gnum_interface_block.cmp_dma_controller.dma_len_reg[10]     gnum_clk200     FDCE     Q       gnum_interface_block.cmp_dma_controller.dma_len_reg[10]     3.154       -1.149
gnum_interface_block.cmp_dma_controller.dma_len_reg[11]     gnum_clk200     FDCE     Q       gnum_interface_block.cmp_dma_controller.dma_len_reg[11]     3.154       -1.149
===========================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                      Starting                                      Required           
Instance                                                              Reference       Type     Pin     Net          Time         Slack 
                                                                      Clock                                                            
---------------------------------------------------------------------------------------------------------------------------------------
gnum_interface_block.cmp_dma_controller.dma_ctrl_host_addr_h_o[0]     gnum_clk200     FDCE     CE      N_5274_i     7.359        -1.306
gnum_interface_block.cmp_dma_controller.dma_ctrl_host_addr_h_o[1]     gnum_clk200     FDCE     CE      N_5274_i     7.359        -1.306
gnum_interface_block.cmp_dma_controller.dma_ctrl_host_addr_h_o[2]     gnum_clk200     FDCE     CE      N_5274_i     7.359        -1.306
gnum_interface_block.cmp_dma_controller.dma_ctrl_host_addr_h_o[3]     gnum_clk200     FDCE     CE      N_5274_i     7.359        -1.306
gnum_interface_block.cmp_dma_controller.dma_ctrl_host_addr_h_o[4]     gnum_clk200     FDCE     CE      N_5274_i     7.359        -1.306
gnum_interface_block.cmp_dma_controller.dma_ctrl_host_addr_h_o[5]     gnum_clk200     FDCE     CE      N_5274_i     7.359        -1.306
gnum_interface_block.cmp_dma_controller.dma_ctrl_host_addr_h_o[6]     gnum_clk200     FDCE     CE      N_5274_i     7.359        -1.306
gnum_interface_block.cmp_dma_controller.dma_ctrl_host_addr_h_o[7]     gnum_clk200     FDCE     CE      N_5274_i     7.359        -1.306
gnum_interface_block.cmp_dma_controller.dma_ctrl_host_addr_h_o[8]     gnum_clk200     FDCE     CE      N_5274_i     7.359        -1.306
gnum_interface_block.cmp_dma_controller.dma_ctrl_host_addr_h_o[9]     gnum_clk200     FDCE     CE      N_5274_i     7.359        -1.306
=======================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      5.000
    - Setup time:                            0.268
    + Clock delay at ending point:           2.627
    = Required time:                         7.359

    - Propagation time:                      6.038
    - Clock delay at starting point:         2.627
    = Slack (non-critical) :                 -1.306

    Number of logic level(s):                3
    Starting point:                          gnum_interface_block.cmp_dma_controller.dma_len_reg[20] / Q
    Ending point:                            gnum_interface_block.cmp_dma_controller.dma_ctrl_host_addr_h_o[0] / CE
    The start point is clocked by            gnum_clk200 [rising] on pin C
    The end   point is clocked by            gnum_clk200 [rising] on pin C

Instance / Net                                                                                              Pin      Pin               Arrival     No. of    
Name                                                                                             Type       Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------------------
gnum_interface_block.cmp_dma_controller.dma_len_reg[20]                                          FDCE       Q        Out     0.526     3.154       -         
gnum_interface_block.cmp_dma_controller.dma_len_reg[20]                                          Net        -        -       0.985     -           5         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_0_1           LUT2_L     I0       In      -         4.139       -         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_0_1           LUT2_L     LO       Out     0.220     4.358       -         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_0_1           Net        -        -       0.945     -           1         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_5             LUT6       I5       In      -         5.303       -         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_5             LUT6       O        Out     0.422     5.725       -         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_5             Net        -        -       0.935     -           4         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_26_0_RNIJ00I     LUT6       I5       In      -         6.660       -         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_26_0_RNIJ00I     LUT6       O        Out     0.110     6.770       -         
N_5274_i                                                                                         Net        -        -       1.895     -           94        
gnum_interface_block.cmp_dma_controller.dma_ctrl_host_addr_h_o[0]                                FDCE       CE       In      -         8.665       -         
=============================================================================================================================================================
Total path delay (propagation time + setup) of 6.306 is 1.546(24.5%) logic and 4.760(75.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Start clock path:

Instance / Net                                                       Pin      Pin               Arrival     No. of    
Name                                                        Type     Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------
gnum_interface_block.cmp_clk_in.rx_pllout_x1                Net      -        -       0.862     -           1         
gnum_interface_block.cmp_clk_in.bufg_135                    BUFG     I        In      -         0.862       -         
gnum_interface_block.cmp_clk_in.bufg_135                    BUFG     O        Out     0.225     1.087       -         
gnum_interface_block.sys_clk                                Net      -        -       1.540     -           46        
gnum_interface_block.cmp_dma_controller.dma_len_reg[20]     FDCE     C        In      -         2.627       -         
======================================================================================================================


End clock path:

Instance / Net                                                                 Pin      Pin               Arrival     No. of    
Name                                                                  Type     Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------
gnum_interface_block.cmp_clk_in.rx_pllout_x1                          Net      -        -       0.862     -           1         
gnum_interface_block.cmp_clk_in.bufg_135                              BUFG     I        In      -         0.862       -         
gnum_interface_block.cmp_clk_in.bufg_135                              BUFG     O        Out     0.225     1.087       -         
gnum_interface_block.sys_clk                                          Net      -        -       1.540     -           46        
gnum_interface_block.cmp_dma_controller.dma_ctrl_host_addr_h_o[0]     FDCE     C        In      -         2.627       -         
================================================================================================================================


Path information for path number 2: 
      Requested Period:                      5.000
    - Setup time:                            0.268
    + Clock delay at ending point:           2.627
    = Required time:                         7.359

    - Propagation time:                      6.038
    - Clock delay at starting point:         2.627
    = Slack (non-critical) :                 -1.306

    Number of logic level(s):                3
    Starting point:                          gnum_interface_block.cmp_dma_controller.dma_len_reg[21] / Q
    Ending point:                            gnum_interface_block.cmp_dma_controller.dma_ctrl_host_addr_h_o[0] / CE
    The start point is clocked by            gnum_clk200 [rising] on pin C
    The end   point is clocked by            gnum_clk200 [rising] on pin C

Instance / Net                                                                                              Pin      Pin               Arrival     No. of    
Name                                                                                             Type       Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------------------
gnum_interface_block.cmp_dma_controller.dma_len_reg[21]                                          FDCE       Q        Out     0.526     3.154       -         
gnum_interface_block.cmp_dma_controller.dma_len_reg[21]                                          Net        -        -       0.985     -           5         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_0_1           LUT2_L     I1       In      -         4.139       -         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_0_1           LUT2_L     LO       Out     0.220     4.358       -         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_0_1           Net        -        -       0.945     -           1         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_5             LUT6       I5       In      -         5.303       -         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_5             LUT6       O        Out     0.422     5.725       -         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_5             Net        -        -       0.935     -           4         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_26_0_RNIJ00I     LUT6       I5       In      -         6.660       -         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_26_0_RNIJ00I     LUT6       O        Out     0.110     6.770       -         
N_5274_i                                                                                         Net        -        -       1.895     -           94        
gnum_interface_block.cmp_dma_controller.dma_ctrl_host_addr_h_o[0]                                FDCE       CE       In      -         8.665       -         
=============================================================================================================================================================
Total path delay (propagation time + setup) of 6.306 is 1.546(24.5%) logic and 4.760(75.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Start clock path:

Instance / Net                                                       Pin      Pin               Arrival     No. of    
Name                                                        Type     Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------
gnum_interface_block.cmp_clk_in.rx_pllout_x1                Net      -        -       0.862     -           1         
gnum_interface_block.cmp_clk_in.bufg_135                    BUFG     I        In      -         0.862       -         
gnum_interface_block.cmp_clk_in.bufg_135                    BUFG     O        Out     0.225     1.087       -         
gnum_interface_block.sys_clk                                Net      -        -       1.540     -           46        
gnum_interface_block.cmp_dma_controller.dma_len_reg[21]     FDCE     C        In      -         2.627       -         
======================================================================================================================


End clock path:

Instance / Net                                                                 Pin      Pin               Arrival     No. of    
Name                                                                  Type     Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------
gnum_interface_block.cmp_clk_in.rx_pllout_x1                          Net      -        -       0.862     -           1         
gnum_interface_block.cmp_clk_in.bufg_135                              BUFG     I        In      -         0.862       -         
gnum_interface_block.cmp_clk_in.bufg_135                              BUFG     O        Out     0.225     1.087       -         
gnum_interface_block.sys_clk                                          Net      -        -       1.540     -           46        
gnum_interface_block.cmp_dma_controller.dma_ctrl_host_addr_h_o[0]     FDCE     C        In      -         2.627       -         
================================================================================================================================


Path information for path number 3: 
      Requested Period:                      5.000
    - Setup time:                            0.268
    + Clock delay at ending point:           2.627
    = Required time:                         7.359

    - Propagation time:                      6.038
    - Clock delay at starting point:         2.627
    = Slack (non-critical) :                 -1.306

    Number of logic level(s):                3
    Starting point:                          gnum_interface_block.cmp_dma_controller.dma_len_reg[20] / Q
    Ending point:                            gnum_interface_block.cmp_dma_controller.dma_ctrl_len_o[3] / CE
    The start point is clocked by            gnum_clk200 [rising] on pin C
    The end   point is clocked by            gnum_clk200 [rising] on pin C

Instance / Net                                                                                              Pin      Pin               Arrival     No. of    
Name                                                                                             Type       Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------------------
gnum_interface_block.cmp_dma_controller.dma_len_reg[20]                                          FDCE       Q        Out     0.526     3.154       -         
gnum_interface_block.cmp_dma_controller.dma_len_reg[20]                                          Net        -        -       0.985     -           5         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_0_1           LUT2_L     I0       In      -         4.139       -         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_0_1           LUT2_L     LO       Out     0.220     4.358       -         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_0_1           Net        -        -       0.945     -           1         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_5             LUT6       I5       In      -         5.303       -         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_5             LUT6       O        Out     0.422     5.725       -         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_5             Net        -        -       0.935     -           4         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_26_0_RNIJ00I     LUT6       I5       In      -         6.660       -         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_26_0_RNIJ00I     LUT6       O        Out     0.110     6.770       -         
N_5274_i                                                                                         Net        -        -       1.895     -           94        
gnum_interface_block.cmp_dma_controller.dma_ctrl_len_o[3]                                        FDCE       CE       In      -         8.665       -         
=============================================================================================================================================================
Total path delay (propagation time + setup) of 6.306 is 1.546(24.5%) logic and 4.760(75.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Start clock path:

Instance / Net                                                       Pin      Pin               Arrival     No. of    
Name                                                        Type     Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------
gnum_interface_block.cmp_clk_in.rx_pllout_x1                Net      -        -       0.862     -           1         
gnum_interface_block.cmp_clk_in.bufg_135                    BUFG     I        In      -         0.862       -         
gnum_interface_block.cmp_clk_in.bufg_135                    BUFG     O        Out     0.225     1.087       -         
gnum_interface_block.sys_clk                                Net      -        -       1.540     -           46        
gnum_interface_block.cmp_dma_controller.dma_len_reg[20]     FDCE     C        In      -         2.627       -         
======================================================================================================================


End clock path:

Instance / Net                                                         Pin      Pin               Arrival     No. of    
Name                                                          Type     Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------
gnum_interface_block.cmp_clk_in.rx_pllout_x1                  Net      -        -       0.862     -           1         
gnum_interface_block.cmp_clk_in.bufg_135                      BUFG     I        In      -         0.862       -         
gnum_interface_block.cmp_clk_in.bufg_135                      BUFG     O        Out     0.225     1.087       -         
gnum_interface_block.sys_clk                                  Net      -        -       1.540     -           46        
gnum_interface_block.cmp_dma_controller.dma_ctrl_len_o[3]     FDCE     C        In      -         2.627       -         
========================================================================================================================


Path information for path number 4: 
      Requested Period:                      5.000
    - Setup time:                            0.268
    + Clock delay at ending point:           2.627
    = Required time:                         7.359

    - Propagation time:                      6.038
    - Clock delay at starting point:         2.627
    = Slack (non-critical) :                 -1.306

    Number of logic level(s):                3
    Starting point:                          gnum_interface_block.cmp_dma_controller.dma_len_reg[20] / Q
    Ending point:                            gnum_interface_block.cmp_dma_controller.dma_ctrl_len_o[4] / CE
    The start point is clocked by            gnum_clk200 [rising] on pin C
    The end   point is clocked by            gnum_clk200 [rising] on pin C

Instance / Net                                                                                              Pin      Pin               Arrival     No. of    
Name                                                                                             Type       Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------------------
gnum_interface_block.cmp_dma_controller.dma_len_reg[20]                                          FDCE       Q        Out     0.526     3.154       -         
gnum_interface_block.cmp_dma_controller.dma_len_reg[20]                                          Net        -        -       0.985     -           5         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_0_1           LUT2_L     I0       In      -         4.139       -         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_0_1           LUT2_L     LO       Out     0.220     4.358       -         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_0_1           Net        -        -       0.945     -           1         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_5             LUT6       I5       In      -         5.303       -         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_5             LUT6       O        Out     0.422     5.725       -         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_5             Net        -        -       0.935     -           4         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_26_0_RNIJ00I     LUT6       I5       In      -         6.660       -         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_26_0_RNIJ00I     LUT6       O        Out     0.110     6.770       -         
N_5274_i                                                                                         Net        -        -       1.895     -           94        
gnum_interface_block.cmp_dma_controller.dma_ctrl_len_o[4]                                        FDCE       CE       In      -         8.665       -         
=============================================================================================================================================================
Total path delay (propagation time + setup) of 6.306 is 1.546(24.5%) logic and 4.760(75.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Start clock path:

Instance / Net                                                       Pin      Pin               Arrival     No. of    
Name                                                        Type     Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------
gnum_interface_block.cmp_clk_in.rx_pllout_x1                Net      -        -       0.862     -           1         
gnum_interface_block.cmp_clk_in.bufg_135                    BUFG     I        In      -         0.862       -         
gnum_interface_block.cmp_clk_in.bufg_135                    BUFG     O        Out     0.225     1.087       -         
gnum_interface_block.sys_clk                                Net      -        -       1.540     -           46        
gnum_interface_block.cmp_dma_controller.dma_len_reg[20]     FDCE     C        In      -         2.627       -         
======================================================================================================================


End clock path:

Instance / Net                                                         Pin      Pin               Arrival     No. of    
Name                                                          Type     Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------
gnum_interface_block.cmp_clk_in.rx_pllout_x1                  Net      -        -       0.862     -           1         
gnum_interface_block.cmp_clk_in.bufg_135                      BUFG     I        In      -         0.862       -         
gnum_interface_block.cmp_clk_in.bufg_135                      BUFG     O        Out     0.225     1.087       -         
gnum_interface_block.sys_clk                                  Net      -        -       1.540     -           46        
gnum_interface_block.cmp_dma_controller.dma_ctrl_len_o[4]     FDCE     C        In      -         2.627       -         
========================================================================================================================


Path information for path number 5: 
      Requested Period:                      5.000
    - Setup time:                            0.268
    + Clock delay at ending point:           2.627
    = Required time:                         7.359

    - Propagation time:                      6.038
    - Clock delay at starting point:         2.627
    = Slack (non-critical) :                 -1.306

    Number of logic level(s):                3
    Starting point:                          gnum_interface_block.cmp_dma_controller.dma_len_reg[20] / Q
    Ending point:                            gnum_interface_block.cmp_dma_controller.dma_ctrl_len_o[5] / CE
    The start point is clocked by            gnum_clk200 [rising] on pin C
    The end   point is clocked by            gnum_clk200 [rising] on pin C

Instance / Net                                                                                              Pin      Pin               Arrival     No. of    
Name                                                                                             Type       Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------------------
gnum_interface_block.cmp_dma_controller.dma_len_reg[20]                                          FDCE       Q        Out     0.526     3.154       -         
gnum_interface_block.cmp_dma_controller.dma_len_reg[20]                                          Net        -        -       0.985     -           5         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_0_1           LUT2_L     I0       In      -         4.139       -         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_0_1           LUT2_L     LO       Out     0.220     4.358       -         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_0_1           Net        -        -       0.945     -           1         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_5             LUT6       I5       In      -         5.303       -         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_5             LUT6       O        Out     0.422     5.725       -         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_27_5             Net        -        -       0.935     -           4         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_26_0_RNIJ00I     LUT6       I5       In      -         6.660       -         
gnum_interface_block.cmp_dma_controller.dma_ctrl_carrier_addr_o_1_sqmuxa_i_0_a2_26_0_RNIJ00I     LUT6       O        Out     0.110     6.770       -         
N_5274_i                                                                                         Net        -        -       1.895     -           94        
gnum_interface_block.cmp_dma_controller.dma_ctrl_len_o[5]                                        FDCE       CE       In      -         8.665       -         
=============================================================================================================================================================
Total path delay (propagation time + setup) of 6.306 is 1.546(24.5%) logic and 4.760(75.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Start clock path:

Instance / Net                                                       Pin      Pin               Arrival     No. of    
Name                                                        Type     Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------
gnum_interface_block.cmp_clk_in.rx_pllout_x1                Net      -        -       0.862     -           1         
gnum_interface_block.cmp_clk_in.bufg_135                    BUFG     I        In      -         0.862       -         
gnum_interface_block.cmp_clk_in.bufg_135                    BUFG     O        Out     0.225     1.087       -         
gnum_interface_block.sys_clk                                Net      -        -       1.540     -           46        
gnum_interface_block.cmp_dma_controller.dma_len_reg[20]     FDCE     C        In      -         2.627       -         
======================================================================================================================


End clock path:

Instance / Net                                                         Pin      Pin               Arrival     No. of    
Name                                                          Type     Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------
gnum_interface_block.cmp_clk_in.rx_pllout_x1                  Net      -        -       0.862     -           1         
gnum_interface_block.cmp_clk_in.bufg_135                      BUFG     I        In      -         0.862       -         
gnum_interface_block.cmp_clk_in.bufg_135                      BUFG     O        Out     0.225     1.087       -         
gnum_interface_block.sys_clk                                  Net      -        -       1.540     -           46        
gnum_interface_block.cmp_dma_controller.dma_ctrl_len_o[5]     FDCE     C        In      -         2.627       -         
========================================================================================================================




====================================
Detailed Report for Clock: spec_clk20
====================================



Starting Points with Worst Slack
********************************

                                             Starting                                                                                  Arrival           
Instance                                     Reference      Type          Pin           Net                                            Time        Slack 
                                             Clock                                                                                                       
---------------------------------------------------------------------------------------------------------------------------------------------------------
clks_rsts_mgment.un7_word_being_sent_0_0     spec_clk20     RAMB8BWER     DOADO[3]      clks_rsts_mgment.un4_word_being_sent_i[9]      6.431       32.800
clks_rsts_mgment.un7_word_being_sent_0_0     spec_clk20     RAMB8BWER     DOADO[4]      clks_rsts_mgment.un4_word_being_sent_i[10]     6.431       32.800
clks_rsts_mgment.un7_word_being_sent_0_0     spec_clk20     RAMB8BWER     DOADO[13]     clks_rsts_mgment.un7_word_being_sent_i[3]      6.431       32.800
clks_rsts_mgment.un7_word_being_sent_0_0     spec_clk20     RAMB8BWER     DOADO[14]     clks_rsts_mgment.un7_word_being_sent_i[4]      6.431       32.800
clks_rsts_mgment.un7_word_being_sent_0_0     spec_clk20     RAMB8BWER     DOADO[0]      clks_rsts_mgment.un4_word_being_sent_i[6]      6.431       32.934
clks_rsts_mgment.un7_word_being_sent_0_0     spec_clk20     RAMB8BWER     DOADO[1]      clks_rsts_mgment.un4_word_being_sent_i[7]      6.431       32.934
clks_rsts_mgment.un7_word_being_sent_0_0     spec_clk20     RAMB8BWER     DOADO[2]      clks_rsts_mgment.un4_word_being_sent_i[8]      6.431       32.934
clks_rsts_mgment.un7_word_being_sent_0_0     spec_clk20     RAMB8BWER     DOADO[5]      clks_rsts_mgment.un4_word_being_sent_i[11]     6.431       32.934
clks_rsts_mgment.un7_word_being_sent_0_0     spec_clk20     RAMB8BWER     DOADO[6]      clks_rsts_mgment.un4_word_being_sent_i[12]     6.431       32.934
clks_rsts_mgment.un7_word_being_sent_0_0     spec_clk20     RAMB8BWER     DOADO[7]      clks_rsts_mgment.un4_word_being_sent_i[13]     6.431       32.934
=========================================================================================================================================================


Ending Points with Worst Slack
******************************

                                    Starting                                                            Required           
Instance                            Reference      Type     Pin            Net                          Time         Slack 
                                    Clock                                                                                  
---------------------------------------------------------------------------------------------------------------------------
pll_sdi_o                           spec_clk20     Port     pll_sdi_o      pll_sdi_o                    48.000       32.800
pll_cs_o                            spec_clk20     Port     pll_cs_o       pll_cs_o                     48.000       38.080
pll_sclk_o                          spec_clk20     Port     pll_sclk_o     pll_sclk_o                   48.000       43.177
clks_rsts_mgment.byte_index[5]      spec_clk20     FD       D              clks_rsts_mgment.N_183       54.108       45.360
clks_rsts_mgment.byte_index[4]      spec_clk20     FD       D              clks_rsts_mgment.N_182       54.108       45.377
clks_rsts_mgment.byte_index[3]      spec_clk20     FD       D              clks_rsts_mgment.N_181       54.108       45.393
clks_rsts_mgment.byte_index[2]      spec_clk20     FD       D              clks_rsts_mgment.N_180       54.108       45.410
clks_rsts_mgment.pll_init_st[3]     spec_clk20     FD       D              clks_rsts_mgment.N_82s       54.212       46.189
clks_rsts_mgment.byte_index[6]      spec_clk20     FD       D              clks_rsts_mgment.N_224_i     54.212       46.413
clks_rsts_mgment.byte_index[1]      spec_clk20     FD       D              clks_rsts_mgment.N_225_i     54.212       46.577
===========================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      50.000
    - User constraint on ending point:       2.000
    = Required time:                         48.000

    - Propagation time:                      11.088
    - Clock delay at starting point:         4.112
    = Slack (non-critical) :                 32.800

    Number of logic level(s):                4
    Starting point:                          clks_rsts_mgment.un7_word_being_sent_0_0 / DOADO[3]
    Ending point:                            pll_sdi_o / pll_sdi_o
    The start point is clocked by            spec_clk20 [rising] on pin CLKAWRCLK
    The end   point is clocked by            spec_clk20 [rising]

Instance / Net                                                     Pin           Pin               Arrival     No. of    
Name                                                 Type          Name          Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------
clks_rsts_mgment.un7_word_being_sent_0_0             RAMB8BWER     DOADO[3]      Out     2.318     6.431       -         
clks_rsts_mgment.un4_word_being_sent_i[9]            Net           -             -       1.991     -           1         
clks_rsts_mgment.un7_word_being_sent_0_0_RNI23L9     LUT6          I2            In      -         8.422       -         
clks_rsts_mgment.un7_word_being_sent_0_0_RNI23L9     LUT6          O             Out     0.439     8.861       -         
N_81                                                 Net           -             -       0.910     -           2         
pll_sdi_o_obuf_RNO_1                                 LUT6          I5            In      -         9.772       -         
pll_sdi_o_obuf_RNO_1                                 LUT6          O             Out     0.305     10.077      -         
N_25_0                                               Net           -             -       0.945     -           1         
pll_sdi_o_obuf_RNO                                   LUT6          I4            In      -         11.022      -         
pll_sdi_o_obuf_RNO                                   LUT6          O             Out     0.220     11.242      -         
N_35_0                                               Net           -             -       0.862     -           1         
pll_sdi_o_obuf                                       OBUF          I             In      -         12.104      -         
pll_sdi_o_obuf                                       OBUF          O             Out     3.096     15.200      -         
pll_sdi_o                                            Net           -             -       0.000     -           1         
pll_sdi_o                                            Port          pll_sdi_o     Out     -         15.200      -         
=========================================================================================================================
Total path delay (propagation time + setup) of 11.088 is 6.379(57.5%) logic and 4.709(42.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Start clock path:

Instance / Net                                              Pin            Pin               Arrival     No. of    
Name                                         Type           Name           Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------
Start Clock :                                spec_clk20                                                            
------------                                                                                                       
spec_clk_i                                   Port           spec_clk_i     In      -         0.000       -         
spec_clk_i                                   Net            -              -       0.000     -           1         
clks_rsts_mgment.spec_clk_ibuf               IBUFG          I              In      -         0.000       -         
clks_rsts_mgment.spec_clk_ibuf               IBUFG          O              Out     1.174     1.174       -         
clks_rsts_mgment.spec_clk_buf                Net            -              -       1.174     -           1         
clks_rsts_mgment.spec_clk_gbuf               BUFG           I              In      -         2.348       -         
clks_rsts_mgment.spec_clk_gbuf               BUFG           O              Out     0.225     2.573       -         
spec_clk                                     Net            -              -       1.540     -           0         
clks_rsts_mgment.un7_word_being_sent_0_0     RAMB8BWER      CLKAWRCLK      In      -         4.112       -         
===================================================================================================================


Path information for path number 2: 
      Requested Period:                      50.000
    - User constraint on ending point:       2.000
    = Required time:                         48.000

    - Propagation time:                      11.088
    - Clock delay at starting point:         4.112
    = Slack (non-critical) :                 32.800

    Number of logic level(s):                4
    Starting point:                          clks_rsts_mgment.un7_word_being_sent_0_0 / DOADO[4]
    Ending point:                            pll_sdi_o / pll_sdi_o
    The start point is clocked by            spec_clk20 [rising] on pin CLKAWRCLK
    The end   point is clocked by            spec_clk20 [rising]

Instance / Net                                                     Pin           Pin               Arrival     No. of    
Name                                                 Type          Name          Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------
clks_rsts_mgment.un7_word_being_sent_0_0             RAMB8BWER     DOADO[4]      Out     2.318     6.431       -         
clks_rsts_mgment.un4_word_being_sent_i[10]           Net           -             -       1.991     -           1         
clks_rsts_mgment.un7_word_being_sent_0_0_RNI23L9     LUT6          I3            In      -         8.422       -         
clks_rsts_mgment.un7_word_being_sent_0_0_RNI23L9     LUT6          O             Out     0.439     8.861       -         
N_81                                                 Net           -             -       0.910     -           2         
pll_sdi_o_obuf_RNO_1                                 LUT6          I5            In      -         9.772       -         
pll_sdi_o_obuf_RNO_1                                 LUT6          O             Out     0.305     10.077      -         
N_25_0                                               Net           -             -       0.945     -           1         
pll_sdi_o_obuf_RNO                                   LUT6          I4            In      -         11.022      -         
pll_sdi_o_obuf_RNO                                   LUT6          O             Out     0.220     11.242      -         
N_35_0                                               Net           -             -       0.862     -           1         
pll_sdi_o_obuf                                       OBUF          I             In      -         12.104      -         
pll_sdi_o_obuf                                       OBUF          O             Out     3.096     15.200      -         
pll_sdi_o                                            Net           -             -       0.000     -           1         
pll_sdi_o                                            Port          pll_sdi_o     Out     -         15.200      -         
=========================================================================================================================
Total path delay (propagation time + setup) of 11.088 is 6.379(57.5%) logic and 4.709(42.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Start clock path:

Instance / Net                                              Pin            Pin               Arrival     No. of    
Name                                         Type           Name           Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------
Start Clock :                                spec_clk20                                                            
------------                                                                                                       
spec_clk_i                                   Port           spec_clk_i     In      -         0.000       -         
spec_clk_i                                   Net            -              -       0.000     -           1         
clks_rsts_mgment.spec_clk_ibuf               IBUFG          I              In      -         0.000       -         
clks_rsts_mgment.spec_clk_ibuf               IBUFG          O              Out     1.174     1.174       -         
clks_rsts_mgment.spec_clk_buf                Net            -              -       1.174     -           1         
clks_rsts_mgment.spec_clk_gbuf               BUFG           I              In      -         2.348       -         
clks_rsts_mgment.spec_clk_gbuf               BUFG           O              Out     0.225     2.573       -         
spec_clk                                     Net            -              -       1.540     -           0         
clks_rsts_mgment.un7_word_being_sent_0_0     RAMB8BWER      CLKAWRCLK      In      -         4.112       -         
===================================================================================================================


Path information for path number 3: 
      Requested Period:                      50.000
    - User constraint on ending point:       2.000
    = Required time:                         48.000

    - Propagation time:                      11.088
    - Clock delay at starting point:         4.112
    = Slack (non-critical) :                 32.800

    Number of logic level(s):                4
    Starting point:                          clks_rsts_mgment.un7_word_being_sent_0_0 / DOADO[13]
    Ending point:                            pll_sdi_o / pll_sdi_o
    The start point is clocked by            spec_clk20 [rising] on pin CLKAWRCLK
    The end   point is clocked by            spec_clk20 [rising]

Instance / Net                                                     Pin           Pin               Arrival     No. of    
Name                                                 Type          Name          Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------
clks_rsts_mgment.un7_word_being_sent_0_0             RAMB8BWER     DOADO[13]     Out     2.318     6.431       -         
clks_rsts_mgment.un7_word_being_sent_i[3]            Net           -             -       1.991     -           1         
clks_rsts_mgment.un7_word_being_sent_0_0_RNI23L9     LUT6          I4            In      -         8.422       -         
clks_rsts_mgment.un7_word_being_sent_0_0_RNI23L9     LUT6          O             Out     0.439     8.861       -         
N_81                                                 Net           -             -       0.910     -           2         
pll_sdi_o_obuf_RNO_1                                 LUT6          I5            In      -         9.772       -         
pll_sdi_o_obuf_RNO_1                                 LUT6          O             Out     0.305     10.077      -         
N_25_0                                               Net           -             -       0.945     -           1         
pll_sdi_o_obuf_RNO                                   LUT6          I4            In      -         11.022      -         
pll_sdi_o_obuf_RNO                                   LUT6          O             Out     0.220     11.242      -         
N_35_0                                               Net           -             -       0.862     -           1         
pll_sdi_o_obuf                                       OBUF          I             In      -         12.104      -         
pll_sdi_o_obuf                                       OBUF          O             Out     3.096     15.200      -         
pll_sdi_o                                            Net           -             -       0.000     -           1         
pll_sdi_o                                            Port          pll_sdi_o     Out     -         15.200      -         
=========================================================================================================================
Total path delay (propagation time + setup) of 11.088 is 6.379(57.5%) logic and 4.709(42.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Start clock path:

Instance / Net                                              Pin            Pin               Arrival     No. of    
Name                                         Type           Name           Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------
Start Clock :                                spec_clk20                                                            
------------                                                                                                       
spec_clk_i                                   Port           spec_clk_i     In      -         0.000       -         
spec_clk_i                                   Net            -              -       0.000     -           1         
clks_rsts_mgment.spec_clk_ibuf               IBUFG          I              In      -         0.000       -         
clks_rsts_mgment.spec_clk_ibuf               IBUFG          O              Out     1.174     1.174       -         
clks_rsts_mgment.spec_clk_buf                Net            -              -       1.174     -           1         
clks_rsts_mgment.spec_clk_gbuf               BUFG           I              In      -         2.348       -         
clks_rsts_mgment.spec_clk_gbuf               BUFG           O              Out     0.225     2.573       -         
spec_clk                                     Net            -              -       1.540     -           0         
clks_rsts_mgment.un7_word_being_sent_0_0     RAMB8BWER      CLKAWRCLK      In      -         4.112       -         
===================================================================================================================


Path information for path number 4: 
      Requested Period:                      50.000
    - User constraint on ending point:       2.000
    = Required time:                         48.000

    - Propagation time:                      11.088
    - Clock delay at starting point:         4.112
    = Slack (non-critical) :                 32.800

    Number of logic level(s):                4
    Starting point:                          clks_rsts_mgment.un7_word_being_sent_0_0 / DOADO[14]
    Ending point:                            pll_sdi_o / pll_sdi_o
    The start point is clocked by            spec_clk20 [rising] on pin CLKAWRCLK
    The end   point is clocked by            spec_clk20 [rising]

Instance / Net                                                     Pin           Pin               Arrival     No. of    
Name                                                 Type          Name          Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------
clks_rsts_mgment.un7_word_being_sent_0_0             RAMB8BWER     DOADO[14]     Out     2.318     6.431       -         
clks_rsts_mgment.un7_word_being_sent_i[4]            Net           -             -       1.991     -           1         
clks_rsts_mgment.un7_word_being_sent_0_0_RNI23L9     LUT6          I5            In      -         8.422       -         
clks_rsts_mgment.un7_word_being_sent_0_0_RNI23L9     LUT6          O             Out     0.439     8.861       -         
N_81                                                 Net           -             -       0.910     -           2         
pll_sdi_o_obuf_RNO_1                                 LUT6          I5            In      -         9.772       -         
pll_sdi_o_obuf_RNO_1                                 LUT6          O             Out     0.305     10.077      -         
N_25_0                                               Net           -             -       0.945     -           1         
pll_sdi_o_obuf_RNO                                   LUT6          I4            In      -         11.022      -         
pll_sdi_o_obuf_RNO                                   LUT6          O             Out     0.220     11.242      -         
N_35_0                                               Net           -             -       0.862     -           1         
pll_sdi_o_obuf                                       OBUF          I             In      -         12.104      -         
pll_sdi_o_obuf                                       OBUF          O             Out     3.096     15.200      -         
pll_sdi_o                                            Net           -             -       0.000     -           1         
pll_sdi_o                                            Port          pll_sdi_o     Out     -         15.200      -         
=========================================================================================================================
Total path delay (propagation time + setup) of 11.088 is 6.379(57.5%) logic and 4.709(42.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Start clock path:

Instance / Net                                              Pin            Pin               Arrival     No. of    
Name                                         Type           Name           Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------
Start Clock :                                spec_clk20                                                            
------------                                                                                                       
spec_clk_i                                   Port           spec_clk_i     In      -         0.000       -         
spec_clk_i                                   Net            -              -       0.000     -           1         
clks_rsts_mgment.spec_clk_ibuf               IBUFG          I              In      -         0.000       -         
clks_rsts_mgment.spec_clk_ibuf               IBUFG          O              Out     1.174     1.174       -         
clks_rsts_mgment.spec_clk_buf                Net            -              -       1.174     -           1         
clks_rsts_mgment.spec_clk_gbuf               BUFG           I              In      -         2.348       -         
clks_rsts_mgment.spec_clk_gbuf               BUFG           O              Out     0.225     2.573       -         
spec_clk                                     Net            -              -       1.540     -           0         
clks_rsts_mgment.un7_word_being_sent_0_0     RAMB8BWER      CLKAWRCLK      In      -         4.112       -         
===================================================================================================================


Path information for path number 5: 
      Requested Period:                      50.000
    - User constraint on ending point:       2.000
    = Required time:                         48.000

    - Propagation time:                      11.088
    - Clock delay at starting point:         4.112
    = Slack (non-critical) :                 32.800

    Number of logic level(s):                4
    Starting point:                          clks_rsts_mgment.un7_word_being_sent_0_0 / DOADO[3]
    Ending point:                            pll_sdi_o / pll_sdi_o
    The start point is clocked by            spec_clk20 [rising] on pin CLKAWRCLK
    The end   point is clocked by            spec_clk20 [rising]

Instance / Net                                                     Pin           Pin               Arrival     No. of    
Name                                                 Type          Name          Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------
clks_rsts_mgment.un7_word_being_sent_0_0             RAMB8BWER     DOADO[3]      Out     2.318     6.431       -         
clks_rsts_mgment.un4_word_being_sent_i[9]            Net           -             -       1.991     -           1         
clks_rsts_mgment.un7_word_being_sent_0_0_RNI23L9     LUT6          I2            In      -         8.422       -         
clks_rsts_mgment.un7_word_being_sent_0_0_RNI23L9     LUT6          O             Out     0.439     8.861       -         
N_81                                                 Net           -             -       0.910     -           2         
pll_sdi_o_obuf_RNO_2                                 LUT6          I5            In      -         9.772       -         
pll_sdi_o_obuf_RNO_2                                 LUT6          O             Out     0.305     10.077      -         
N_28_0                                               Net           -             -       0.945     -           1         
pll_sdi_o_obuf_RNO                                   LUT6          I5            In      -         11.022      -         
pll_sdi_o_obuf_RNO                                   LUT6          O             Out     0.220     11.242      -         
N_35_0                                               Net           -             -       0.862     -           1         
pll_sdi_o_obuf                                       OBUF          I             In      -         12.104      -         
pll_sdi_o_obuf                                       OBUF          O             Out     3.096     15.200      -         
pll_sdi_o                                            Net           -             -       0.000     -           1         
pll_sdi_o                                            Port          pll_sdi_o     Out     -         15.200      -         
=========================================================================================================================
Total path delay (propagation time + setup) of 11.088 is 6.379(57.5%) logic and 4.709(42.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Start clock path:

Instance / Net                                              Pin            Pin               Arrival     No. of    
Name                                         Type           Name           Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------
Start Clock :                                spec_clk20                                                            
------------                                                                                                       
spec_clk_i                                   Port           spec_clk_i     In      -         0.000       -         
spec_clk_i                                   Net            -              -       0.000     -           1         
clks_rsts_mgment.spec_clk_ibuf               IBUFG          I              In      -         0.000       -         
clks_rsts_mgment.spec_clk_ibuf               IBUFG          O              Out     1.174     1.174       -         
clks_rsts_mgment.spec_clk_buf                Net            -              -       1.174     -           1         
clks_rsts_mgment.spec_clk_gbuf               BUFG           I              In      -         2.348       -         
clks_rsts_mgment.spec_clk_gbuf               BUFG           O              Out     0.225     2.573       -         
spec_clk                                     Net            -              -       1.540     -           0         
clks_rsts_mgment.un7_word_being_sent_0_0     RAMB8BWER      CLKAWRCLK      In      -         4.112       -         
===================================================================================================================




====================================
Detailed Report for Clock: tdc_clk125
====================================



Starting Points with Worst Slack
********************************

                                         Starting                                           Arrival          
Instance                                 Reference      Type     Pin     Net                Time        Slack
                                         Clock                                                               
-------------------------------------------------------------------------------------------------------------
data_formatting_block.wr_pointer[2]      tdc_clk125     FDR      Q       wr_pointer[6]      4.639       0.640
data_formatting_block.wr_pointer[3]      tdc_clk125     FDR      Q       wr_pointer[7]      4.639       0.640
data_formatting_block.wr_pointer[4]      tdc_clk125     FDR      Q       wr_pointer[8]      4.639       0.640
data_formatting_block.wr_pointer[5]      tdc_clk125     FDR      Q       wr_pointer[9]      4.639       0.640
data_formatting_block.wr_pointer[6]      tdc_clk125     FDR      Q       wr_pointer[10]     4.639       0.640
data_formatting_block.wr_pointer[7]      tdc_clk125     FDR      Q       wr_pointer[11]     4.639       0.640
data_formatting_block.wr_pointer[9]      tdc_clk125     FDR      Q       wr_pointer[13]     4.639       0.655
data_formatting_block.wr_pointer[19]     tdc_clk125     FDR      Q       wr_pointer[23]     4.639       0.655
data_formatting_block.wr_pointer[20]     tdc_clk125     FDR      Q       wr_pointer[24]     4.639       0.655
data_formatting_block.wr_pointer[23]     tdc_clk125     FDR      Q       wr_pointer[27]     4.639       0.655
=============================================================================================================


Ending Points with Worst Slack
******************************

                                                      Starting                                                                                Required          
Instance                                              Reference      Type     Pin     Net                                                     Time         Slack
                                                      Clock                                                                                                     
----------------------------------------------------------------------------------------------------------------------------------------------------------------
data_formatting_block.wr_pointer[31]                  tdc_clk125     FDR      D       N_6528                                                  11.692       0.640
data_formatting_block.wr_pointer[30]                  tdc_clk125     FDR      D       N_6527                                                  11.692       0.673
data_formatting_block.wr_pointer[29]                  tdc_clk125     FDR      D       N_6526                                                  11.692       0.706
data_formatting_block.wr_pointer[28]                  tdc_clk125     FDR      D       N_6525                                                  11.692       0.739
data_formatting_block.wr_pointer[27]                  tdc_clk125     FDR      D       N_6524                                                  11.692       0.772
data_formatting_block.wr_pointer[26]                  tdc_clk125     FDR      D       N_6523                                                  11.692       0.804
start_retrigger_block.retrig_nb_counter.value[31]     tdc_clk125     FDRE     D       start_retrigger_block.retrig_nb_counter.value_s[31]     11.692       0.810
data_formatting_block.wr_pointer[25]                  tdc_clk125     FDR      D       N_6522                                                  11.692       0.837
start_retrigger_block.retrig_nb_counter.value[30]     tdc_clk125     FDRE     D       start_retrigger_block.retrig_nb_counter.value_s[30]     11.692       0.843
data_formatting_block.wr_pointer[24]                  tdc_clk125     FDR      D       N_6521                                                  11.692       0.870
================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      8.000
    - Setup time:                            0.420
    + Clock delay at ending point:           4.112
    = Required time:                         11.692

    - Propagation time:                      6.939
    - Clock delay at starting point:         4.112
    = Slack (non-critical) :                 0.640

    Number of logic level(s):                35
    Starting point:                          data_formatting_block.wr_pointer[2] / Q
    Ending point:                            data_formatting_block.wr_pointer[31] / D
    The start point is clocked by            tdc_clk125 [rising] on pin C
    The end   point is clocked by            tdc_clk125 [rising] on pin C

Instance / Net                                                                Pin      Pin               Arrival     No. of    
Name                                                              Type        Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------
data_formatting_block.wr_pointer[2]                               FDR         Q        Out     0.526     4.639       -         
wr_pointer[6]                                                     Net         -        -       0.985     -           4         
data_formatting_block.pointer_update\.un37_mem_cyc_4_0            LUT2        I0       In      -         5.624       -         
data_formatting_block.pointer_update\.un37_mem_cyc_4_0            LUT2        O        Out     0.220     5.843       -         
data_formatting_block.pointer_update\.un37_mem_cyc_4_0            Net         -        -       0.910     -           2         
data_formatting_block.pointer_update\.un37_mem_cyc_3_0_RNIT54P    LUT6_L      I3       In      -         6.753       -         
data_formatting_block.pointer_update\.un37_mem_cyc_3_0_RNIT54P    LUT6_L      LO       Out     0.754     7.507       -         
N_36168                                                           Net         -        -       0.945     -           1         
circular_buffer_block.class_ack_RNI8MTE1                          LUT6        I5       In      -         8.452       -         
circular_buffer_block.class_ack_RNI8MTE1                          LUT6        O        Out     0.110     8.562       -         
data_formatting_block.wr_pointer_1_sqmuxa                         Net         -        -       0.910     -           2         
data_formatting_block.un1_wr_pointer_cry_0                        MUXCY_L     CI       In      -         9.472       -         
data_formatting_block.un1_wr_pointer_cry_0                        MUXCY_L     LO       Out     0.388     9.860       -         
data_formatting_block.un1_wr_pointer_cry_0                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_1                        MUXCY_L     CI       In      -         9.860       -         
data_formatting_block.un1_wr_pointer_cry_1                        MUXCY_L     LO       Out     0.033     9.893       -         
data_formatting_block.un1_wr_pointer_cry_1                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_2                        MUXCY_L     CI       In      -         9.893       -         
data_formatting_block.un1_wr_pointer_cry_2                        MUXCY_L     LO       Out     0.033     9.925       -         
data_formatting_block.un1_wr_pointer_cry_2                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_3                        MUXCY_L     CI       In      -         9.925       -         
data_formatting_block.un1_wr_pointer_cry_3                        MUXCY_L     LO       Out     0.033     9.958       -         
data_formatting_block.un1_wr_pointer_cry_3                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_4                        MUXCY_L     CI       In      -         9.958       -         
data_formatting_block.un1_wr_pointer_cry_4                        MUXCY_L     LO       Out     0.033     9.991       -         
data_formatting_block.un1_wr_pointer_cry_4                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_5                        MUXCY_L     CI       In      -         9.991       -         
data_formatting_block.un1_wr_pointer_cry_5                        MUXCY_L     LO       Out     0.033     10.024      -         
data_formatting_block.un1_wr_pointer_cry_5                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_6                        MUXCY_L     CI       In      -         10.024      -         
data_formatting_block.un1_wr_pointer_cry_6                        MUXCY_L     LO       Out     0.033     10.057      -         
data_formatting_block.un1_wr_pointer_cry_6                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_7                        MUXCY_L     CI       In      -         10.057      -         
data_formatting_block.un1_wr_pointer_cry_7                        MUXCY_L     LO       Out     0.033     10.089      -         
data_formatting_block.un1_wr_pointer_cry_7                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_8                        MUXCY_L     CI       In      -         10.089      -         
data_formatting_block.un1_wr_pointer_cry_8                        MUXCY_L     LO       Out     0.033     10.122      -         
data_formatting_block.un1_wr_pointer_cry_8                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_9                        MUXCY_L     CI       In      -         10.122      -         
data_formatting_block.un1_wr_pointer_cry_9                        MUXCY_L     LO       Out     0.033     10.155      -         
data_formatting_block.un1_wr_pointer_cry_9                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_10                       MUXCY_L     CI       In      -         10.155      -         
data_formatting_block.un1_wr_pointer_cry_10                       MUXCY_L     LO       Out     0.033     10.188      -         
data_formatting_block.un1_wr_pointer_cry_10                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_11                       MUXCY_L     CI       In      -         10.188      -         
data_formatting_block.un1_wr_pointer_cry_11                       MUXCY_L     LO       Out     0.033     10.221      -         
data_formatting_block.un1_wr_pointer_cry_11                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_12                       MUXCY_L     CI       In      -         10.221      -         
data_formatting_block.un1_wr_pointer_cry_12                       MUXCY_L     LO       Out     0.033     10.253      -         
data_formatting_block.un1_wr_pointer_cry_12                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_13                       MUXCY_L     CI       In      -         10.253      -         
data_formatting_block.un1_wr_pointer_cry_13                       MUXCY_L     LO       Out     0.033     10.286      -         
data_formatting_block.un1_wr_pointer_cry_13                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_14                       MUXCY_L     CI       In      -         10.286      -         
data_formatting_block.un1_wr_pointer_cry_14                       MUXCY_L     LO       Out     0.033     10.319      -         
data_formatting_block.un1_wr_pointer_cry_14                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_15                       MUXCY_L     CI       In      -         10.319      -         
data_formatting_block.un1_wr_pointer_cry_15                       MUXCY_L     LO       Out     0.033     10.352      -         
data_formatting_block.un1_wr_pointer_cry_15                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_16                       MUXCY_L     CI       In      -         10.352      -         
data_formatting_block.un1_wr_pointer_cry_16                       MUXCY_L     LO       Out     0.033     10.385      -         
data_formatting_block.un1_wr_pointer_cry_16                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_17                       MUXCY_L     CI       In      -         10.385      -         
data_formatting_block.un1_wr_pointer_cry_17                       MUXCY_L     LO       Out     0.033     10.417      -         
data_formatting_block.un1_wr_pointer_cry_17                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_18                       MUXCY_L     CI       In      -         10.417      -         
data_formatting_block.un1_wr_pointer_cry_18                       MUXCY_L     LO       Out     0.033     10.450      -         
data_formatting_block.un1_wr_pointer_cry_18                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_19                       MUXCY_L     CI       In      -         10.450      -         
data_formatting_block.un1_wr_pointer_cry_19                       MUXCY_L     LO       Out     0.033     10.483      -         
data_formatting_block.un1_wr_pointer_cry_19                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_20                       MUXCY_L     CI       In      -         10.483      -         
data_formatting_block.un1_wr_pointer_cry_20                       MUXCY_L     LO       Out     0.033     10.516      -         
data_formatting_block.un1_wr_pointer_cry_20                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_21                       MUXCY_L     CI       In      -         10.516      -         
data_formatting_block.un1_wr_pointer_cry_21                       MUXCY_L     LO       Out     0.033     10.549      -         
data_formatting_block.un1_wr_pointer_cry_21                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_22                       MUXCY_L     CI       In      -         10.549      -         
data_formatting_block.un1_wr_pointer_cry_22                       MUXCY_L     LO       Out     0.033     10.581      -         
data_formatting_block.un1_wr_pointer_cry_22                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_23                       MUXCY_L     CI       In      -         10.581      -         
data_formatting_block.un1_wr_pointer_cry_23                       MUXCY_L     LO       Out     0.033     10.614      -         
data_formatting_block.un1_wr_pointer_cry_23                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_24                       MUXCY_L     CI       In      -         10.614      -         
data_formatting_block.un1_wr_pointer_cry_24                       MUXCY_L     LO       Out     0.033     10.647      -         
data_formatting_block.un1_wr_pointer_cry_24                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_25                       MUXCY_L     CI       In      -         10.647      -         
data_formatting_block.un1_wr_pointer_cry_25                       MUXCY_L     LO       Out     0.033     10.680      -         
data_formatting_block.un1_wr_pointer_cry_25                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_26                       MUXCY_L     CI       In      -         10.680      -         
data_formatting_block.un1_wr_pointer_cry_26                       MUXCY_L     LO       Out     0.033     10.713      -         
data_formatting_block.un1_wr_pointer_cry_26                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_27                       MUXCY_L     CI       In      -         10.713      -         
data_formatting_block.un1_wr_pointer_cry_27                       MUXCY_L     LO       Out     0.033     10.745      -         
data_formatting_block.un1_wr_pointer_cry_27                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_28                       MUXCY_L     CI       In      -         10.745      -         
data_formatting_block.un1_wr_pointer_cry_28                       MUXCY_L     LO       Out     0.033     10.778      -         
data_formatting_block.un1_wr_pointer_cry_28                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_29                       MUXCY_L     CI       In      -         10.778      -         
data_formatting_block.un1_wr_pointer_cry_29                       MUXCY_L     LO       Out     0.033     10.811      -         
data_formatting_block.un1_wr_pointer_cry_29                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_30                       MUXCY_L     CI       In      -         10.811      -         
data_formatting_block.un1_wr_pointer_cry_30                       MUXCY_L     LO       Out     0.033     10.844      -         
data_formatting_block.un1_wr_pointer_cry_30                       Net         -        -       0.000     -           1         
data_formatting_block.un1_wr_pointer_s_31                         XORCY       CI       In      -         10.844      -         
data_formatting_block.un1_wr_pointer_s_31                         XORCY       O        Out     0.208     11.052      -         
N_6528                                                            Net         -        -       0.000     -           1         
data_formatting_block.wr_pointer[31]                              FDR         D        In      -         11.052      -         
===============================================================================================================================
Total path delay (propagation time + setup) of 7.360 is 3.609(49.0%) logic and 3.750(51.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Start clock path:

Instance / Net                                         Pin             Pin               Arrival     No. of    
Name                                    Type           Name            Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------
Start Clock :                           tdc_clk125                                                             
------------                                                                                                   
tdc_clk_p_i                             Port           tdc_clk_p_i     In      -         0.000       -         
tdc_clk_p_i                             Net            -               -       0.000     -           1         
clks_rsts_mgment.tdc_clk125_ibuf        IBUFDS         I               In      -         0.000       -         
clks_rsts_mgment.tdc_clk125_ibuf        IBUFDS         O               Out     1.174     1.174       -         
clks_rsts_mgment.tdc_clk_buf            Net            -               -       1.174     -           1         
clks_rsts_mgment.tdc_clk125_gbuf        BUFG           I               In      -         2.348       -         
clks_rsts_mgment.tdc_clk125_gbuf        BUFG           O               Out     0.225     2.573       -         
clk                                     Net            -               -       1.540     -           7         
data_formatting_block.wr_pointer[2]     FDR            C               In      -         4.112       -         
===============================================================================================================


End clock path:

Instance / Net                                          Pin             Pin               Arrival     No. of    
Name                                     Type           Name            Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------
Start Clock :                            tdc_clk125                                                             
------------                                                                                                    
tdc_clk_p_i                              Port           tdc_clk_p_i     In      -         0.000       -         
tdc_clk_p_i                              Net            -               -       0.000     -           1         
clks_rsts_mgment.tdc_clk125_ibuf         IBUFDS         I               In      -         0.000       -         
clks_rsts_mgment.tdc_clk125_ibuf         IBUFDS         O               Out     1.174     1.174       -         
clks_rsts_mgment.tdc_clk_buf             Net            -               -       1.174     -           1         
clks_rsts_mgment.tdc_clk125_gbuf         BUFG           I               In      -         2.348       -         
clks_rsts_mgment.tdc_clk125_gbuf         BUFG           O               Out     0.225     2.573       -         
clk                                      Net            -               -       1.540     -           7         
data_formatting_block.wr_pointer[31]     FDR            C               In      -         4.112       -         
================================================================================================================


Path information for path number 2: 
      Requested Period:                      8.000
    - Setup time:                            0.420
    + Clock delay at ending point:           4.112
    = Required time:                         11.692

    - Propagation time:                      6.939
    - Clock delay at starting point:         4.112
    = Slack (non-critical) :                 0.640

    Number of logic level(s):                35
    Starting point:                          data_formatting_block.wr_pointer[3] / Q
    Ending point:                            data_formatting_block.wr_pointer[31] / D
    The start point is clocked by            tdc_clk125 [rising] on pin C
    The end   point is clocked by            tdc_clk125 [rising] on pin C

Instance / Net                                                                Pin      Pin               Arrival     No. of    
Name                                                              Type        Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------
data_formatting_block.wr_pointer[3]                               FDR         Q        Out     0.526     4.639       -         
wr_pointer[7]                                                     Net         -        -       0.985     -           4         
data_formatting_block.pointer_update\.un37_mem_cyc_4_0            LUT2        I1       In      -         5.624       -         
data_formatting_block.pointer_update\.un37_mem_cyc_4_0            LUT2        O        Out     0.220     5.843       -         
data_formatting_block.pointer_update\.un37_mem_cyc_4_0            Net         -        -       0.910     -           2         
data_formatting_block.pointer_update\.un37_mem_cyc_3_0_RNIT54P    LUT6_L      I3       In      -         6.753       -         
data_formatting_block.pointer_update\.un37_mem_cyc_3_0_RNIT54P    LUT6_L      LO       Out     0.754     7.507       -         
N_36168                                                           Net         -        -       0.945     -           1         
circular_buffer_block.class_ack_RNI8MTE1                          LUT6        I5       In      -         8.452       -         
circular_buffer_block.class_ack_RNI8MTE1                          LUT6        O        Out     0.110     8.562       -         
data_formatting_block.wr_pointer_1_sqmuxa                         Net         -        -       0.910     -           2         
data_formatting_block.un1_wr_pointer_cry_0                        MUXCY_L     CI       In      -         9.472       -         
data_formatting_block.un1_wr_pointer_cry_0                        MUXCY_L     LO       Out     0.388     9.860       -         
data_formatting_block.un1_wr_pointer_cry_0                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_1                        MUXCY_L     CI       In      -         9.860       -         
data_formatting_block.un1_wr_pointer_cry_1                        MUXCY_L     LO       Out     0.033     9.893       -         
data_formatting_block.un1_wr_pointer_cry_1                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_2                        MUXCY_L     CI       In      -         9.893       -         
data_formatting_block.un1_wr_pointer_cry_2                        MUXCY_L     LO       Out     0.033     9.925       -         
data_formatting_block.un1_wr_pointer_cry_2                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_3                        MUXCY_L     CI       In      -         9.925       -         
data_formatting_block.un1_wr_pointer_cry_3                        MUXCY_L     LO       Out     0.033     9.958       -         
data_formatting_block.un1_wr_pointer_cry_3                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_4                        MUXCY_L     CI       In      -         9.958       -         
data_formatting_block.un1_wr_pointer_cry_4                        MUXCY_L     LO       Out     0.033     9.991       -         
data_formatting_block.un1_wr_pointer_cry_4                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_5                        MUXCY_L     CI       In      -         9.991       -         
data_formatting_block.un1_wr_pointer_cry_5                        MUXCY_L     LO       Out     0.033     10.024      -         
data_formatting_block.un1_wr_pointer_cry_5                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_6                        MUXCY_L     CI       In      -         10.024      -         
data_formatting_block.un1_wr_pointer_cry_6                        MUXCY_L     LO       Out     0.033     10.057      -         
data_formatting_block.un1_wr_pointer_cry_6                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_7                        MUXCY_L     CI       In      -         10.057      -         
data_formatting_block.un1_wr_pointer_cry_7                        MUXCY_L     LO       Out     0.033     10.089      -         
data_formatting_block.un1_wr_pointer_cry_7                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_8                        MUXCY_L     CI       In      -         10.089      -         
data_formatting_block.un1_wr_pointer_cry_8                        MUXCY_L     LO       Out     0.033     10.122      -         
data_formatting_block.un1_wr_pointer_cry_8                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_9                        MUXCY_L     CI       In      -         10.122      -         
data_formatting_block.un1_wr_pointer_cry_9                        MUXCY_L     LO       Out     0.033     10.155      -         
data_formatting_block.un1_wr_pointer_cry_9                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_10                       MUXCY_L     CI       In      -         10.155      -         
data_formatting_block.un1_wr_pointer_cry_10                       MUXCY_L     LO       Out     0.033     10.188      -         
data_formatting_block.un1_wr_pointer_cry_10                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_11                       MUXCY_L     CI       In      -         10.188      -         
data_formatting_block.un1_wr_pointer_cry_11                       MUXCY_L     LO       Out     0.033     10.221      -         
data_formatting_block.un1_wr_pointer_cry_11                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_12                       MUXCY_L     CI       In      -         10.221      -         
data_formatting_block.un1_wr_pointer_cry_12                       MUXCY_L     LO       Out     0.033     10.253      -         
data_formatting_block.un1_wr_pointer_cry_12                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_13                       MUXCY_L     CI       In      -         10.253      -         
data_formatting_block.un1_wr_pointer_cry_13                       MUXCY_L     LO       Out     0.033     10.286      -         
data_formatting_block.un1_wr_pointer_cry_13                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_14                       MUXCY_L     CI       In      -         10.286      -         
data_formatting_block.un1_wr_pointer_cry_14                       MUXCY_L     LO       Out     0.033     10.319      -         
data_formatting_block.un1_wr_pointer_cry_14                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_15                       MUXCY_L     CI       In      -         10.319      -         
data_formatting_block.un1_wr_pointer_cry_15                       MUXCY_L     LO       Out     0.033     10.352      -         
data_formatting_block.un1_wr_pointer_cry_15                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_16                       MUXCY_L     CI       In      -         10.352      -         
data_formatting_block.un1_wr_pointer_cry_16                       MUXCY_L     LO       Out     0.033     10.385      -         
data_formatting_block.un1_wr_pointer_cry_16                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_17                       MUXCY_L     CI       In      -         10.385      -         
data_formatting_block.un1_wr_pointer_cry_17                       MUXCY_L     LO       Out     0.033     10.417      -         
data_formatting_block.un1_wr_pointer_cry_17                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_18                       MUXCY_L     CI       In      -         10.417      -         
data_formatting_block.un1_wr_pointer_cry_18                       MUXCY_L     LO       Out     0.033     10.450      -         
data_formatting_block.un1_wr_pointer_cry_18                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_19                       MUXCY_L     CI       In      -         10.450      -         
data_formatting_block.un1_wr_pointer_cry_19                       MUXCY_L     LO       Out     0.033     10.483      -         
data_formatting_block.un1_wr_pointer_cry_19                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_20                       MUXCY_L     CI       In      -         10.483      -         
data_formatting_block.un1_wr_pointer_cry_20                       MUXCY_L     LO       Out     0.033     10.516      -         
data_formatting_block.un1_wr_pointer_cry_20                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_21                       MUXCY_L     CI       In      -         10.516      -         
data_formatting_block.un1_wr_pointer_cry_21                       MUXCY_L     LO       Out     0.033     10.549      -         
data_formatting_block.un1_wr_pointer_cry_21                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_22                       MUXCY_L     CI       In      -         10.549      -         
data_formatting_block.un1_wr_pointer_cry_22                       MUXCY_L     LO       Out     0.033     10.581      -         
data_formatting_block.un1_wr_pointer_cry_22                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_23                       MUXCY_L     CI       In      -         10.581      -         
data_formatting_block.un1_wr_pointer_cry_23                       MUXCY_L     LO       Out     0.033     10.614      -         
data_formatting_block.un1_wr_pointer_cry_23                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_24                       MUXCY_L     CI       In      -         10.614      -         
data_formatting_block.un1_wr_pointer_cry_24                       MUXCY_L     LO       Out     0.033     10.647      -         
data_formatting_block.un1_wr_pointer_cry_24                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_25                       MUXCY_L     CI       In      -         10.647      -         
data_formatting_block.un1_wr_pointer_cry_25                       MUXCY_L     LO       Out     0.033     10.680      -         
data_formatting_block.un1_wr_pointer_cry_25                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_26                       MUXCY_L     CI       In      -         10.680      -         
data_formatting_block.un1_wr_pointer_cry_26                       MUXCY_L     LO       Out     0.033     10.713      -         
data_formatting_block.un1_wr_pointer_cry_26                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_27                       MUXCY_L     CI       In      -         10.713      -         
data_formatting_block.un1_wr_pointer_cry_27                       MUXCY_L     LO       Out     0.033     10.745      -         
data_formatting_block.un1_wr_pointer_cry_27                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_28                       MUXCY_L     CI       In      -         10.745      -         
data_formatting_block.un1_wr_pointer_cry_28                       MUXCY_L     LO       Out     0.033     10.778      -         
data_formatting_block.un1_wr_pointer_cry_28                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_29                       MUXCY_L     CI       In      -         10.778      -         
data_formatting_block.un1_wr_pointer_cry_29                       MUXCY_L     LO       Out     0.033     10.811      -         
data_formatting_block.un1_wr_pointer_cry_29                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_30                       MUXCY_L     CI       In      -         10.811      -         
data_formatting_block.un1_wr_pointer_cry_30                       MUXCY_L     LO       Out     0.033     10.844      -         
data_formatting_block.un1_wr_pointer_cry_30                       Net         -        -       0.000     -           1         
data_formatting_block.un1_wr_pointer_s_31                         XORCY       CI       In      -         10.844      -         
data_formatting_block.un1_wr_pointer_s_31                         XORCY       O        Out     0.208     11.052      -         
N_6528                                                            Net         -        -       0.000     -           1         
data_formatting_block.wr_pointer[31]                              FDR         D        In      -         11.052      -         
===============================================================================================================================
Total path delay (propagation time + setup) of 7.360 is 3.609(49.0%) logic and 3.750(51.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Start clock path:

Instance / Net                                         Pin             Pin               Arrival     No. of    
Name                                    Type           Name            Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------
Start Clock :                           tdc_clk125                                                             
------------                                                                                                   
tdc_clk_p_i                             Port           tdc_clk_p_i     In      -         0.000       -         
tdc_clk_p_i                             Net            -               -       0.000     -           1         
clks_rsts_mgment.tdc_clk125_ibuf        IBUFDS         I               In      -         0.000       -         
clks_rsts_mgment.tdc_clk125_ibuf        IBUFDS         O               Out     1.174     1.174       -         
clks_rsts_mgment.tdc_clk_buf            Net            -               -       1.174     -           1         
clks_rsts_mgment.tdc_clk125_gbuf        BUFG           I               In      -         2.348       -         
clks_rsts_mgment.tdc_clk125_gbuf        BUFG           O               Out     0.225     2.573       -         
clk                                     Net            -               -       1.540     -           7         
data_formatting_block.wr_pointer[3]     FDR            C               In      -         4.112       -         
===============================================================================================================


End clock path:

Instance / Net                                          Pin             Pin               Arrival     No. of    
Name                                     Type           Name            Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------
Start Clock :                            tdc_clk125                                                             
------------                                                                                                    
tdc_clk_p_i                              Port           tdc_clk_p_i     In      -         0.000       -         
tdc_clk_p_i                              Net            -               -       0.000     -           1         
clks_rsts_mgment.tdc_clk125_ibuf         IBUFDS         I               In      -         0.000       -         
clks_rsts_mgment.tdc_clk125_ibuf         IBUFDS         O               Out     1.174     1.174       -         
clks_rsts_mgment.tdc_clk_buf             Net            -               -       1.174     -           1         
clks_rsts_mgment.tdc_clk125_gbuf         BUFG           I               In      -         2.348       -         
clks_rsts_mgment.tdc_clk125_gbuf         BUFG           O               Out     0.225     2.573       -         
clk                                      Net            -               -       1.540     -           7         
data_formatting_block.wr_pointer[31]     FDR            C               In      -         4.112       -         
================================================================================================================


Path information for path number 3: 
      Requested Period:                      8.000
    - Setup time:                            0.420
    + Clock delay at ending point:           4.112
    = Required time:                         11.692

    - Propagation time:                      6.939
    - Clock delay at starting point:         4.112
    = Slack (non-critical) :                 0.640

    Number of logic level(s):                35
    Starting point:                          data_formatting_block.wr_pointer[4] / Q
    Ending point:                            data_formatting_block.wr_pointer[31] / D
    The start point is clocked by            tdc_clk125 [rising] on pin C
    The end   point is clocked by            tdc_clk125 [rising] on pin C

Instance / Net                                                                Pin      Pin               Arrival     No. of    
Name                                                              Type        Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------
data_formatting_block.wr_pointer[4]                               FDR         Q        Out     0.526     4.639       -         
wr_pointer[8]                                                     Net         -        -       0.985     -           4         
data_formatting_block.pointer_update\.un37_mem_cyc_4_1            LUT2        I0       In      -         5.624       -         
data_formatting_block.pointer_update\.un37_mem_cyc_4_1            LUT2        O        Out     0.220     5.843       -         
data_formatting_block.pointer_update\.un37_mem_cyc_4_1            Net         -        -       0.910     -           2         
data_formatting_block.pointer_update\.un37_mem_cyc_3_0_RNIT54P    LUT6_L      I4       In      -         6.753       -         
data_formatting_block.pointer_update\.un37_mem_cyc_3_0_RNIT54P    LUT6_L      LO       Out     0.754     7.507       -         
N_36168                                                           Net         -        -       0.945     -           1         
circular_buffer_block.class_ack_RNI8MTE1                          LUT6        I5       In      -         8.452       -         
circular_buffer_block.class_ack_RNI8MTE1                          LUT6        O        Out     0.110     8.562       -         
data_formatting_block.wr_pointer_1_sqmuxa                         Net         -        -       0.910     -           2         
data_formatting_block.un1_wr_pointer_cry_0                        MUXCY_L     CI       In      -         9.472       -         
data_formatting_block.un1_wr_pointer_cry_0                        MUXCY_L     LO       Out     0.388     9.860       -         
data_formatting_block.un1_wr_pointer_cry_0                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_1                        MUXCY_L     CI       In      -         9.860       -         
data_formatting_block.un1_wr_pointer_cry_1                        MUXCY_L     LO       Out     0.033     9.893       -         
data_formatting_block.un1_wr_pointer_cry_1                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_2                        MUXCY_L     CI       In      -         9.893       -         
data_formatting_block.un1_wr_pointer_cry_2                        MUXCY_L     LO       Out     0.033     9.925       -         
data_formatting_block.un1_wr_pointer_cry_2                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_3                        MUXCY_L     CI       In      -         9.925       -         
data_formatting_block.un1_wr_pointer_cry_3                        MUXCY_L     LO       Out     0.033     9.958       -         
data_formatting_block.un1_wr_pointer_cry_3                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_4                        MUXCY_L     CI       In      -         9.958       -         
data_formatting_block.un1_wr_pointer_cry_4                        MUXCY_L     LO       Out     0.033     9.991       -         
data_formatting_block.un1_wr_pointer_cry_4                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_5                        MUXCY_L     CI       In      -         9.991       -         
data_formatting_block.un1_wr_pointer_cry_5                        MUXCY_L     LO       Out     0.033     10.024      -         
data_formatting_block.un1_wr_pointer_cry_5                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_6                        MUXCY_L     CI       In      -         10.024      -         
data_formatting_block.un1_wr_pointer_cry_6                        MUXCY_L     LO       Out     0.033     10.057      -         
data_formatting_block.un1_wr_pointer_cry_6                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_7                        MUXCY_L     CI       In      -         10.057      -         
data_formatting_block.un1_wr_pointer_cry_7                        MUXCY_L     LO       Out     0.033     10.089      -         
data_formatting_block.un1_wr_pointer_cry_7                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_8                        MUXCY_L     CI       In      -         10.089      -         
data_formatting_block.un1_wr_pointer_cry_8                        MUXCY_L     LO       Out     0.033     10.122      -         
data_formatting_block.un1_wr_pointer_cry_8                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_9                        MUXCY_L     CI       In      -         10.122      -         
data_formatting_block.un1_wr_pointer_cry_9                        MUXCY_L     LO       Out     0.033     10.155      -         
data_formatting_block.un1_wr_pointer_cry_9                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_10                       MUXCY_L     CI       In      -         10.155      -         
data_formatting_block.un1_wr_pointer_cry_10                       MUXCY_L     LO       Out     0.033     10.188      -         
data_formatting_block.un1_wr_pointer_cry_10                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_11                       MUXCY_L     CI       In      -         10.188      -         
data_formatting_block.un1_wr_pointer_cry_11                       MUXCY_L     LO       Out     0.033     10.221      -         
data_formatting_block.un1_wr_pointer_cry_11                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_12                       MUXCY_L     CI       In      -         10.221      -         
data_formatting_block.un1_wr_pointer_cry_12                       MUXCY_L     LO       Out     0.033     10.253      -         
data_formatting_block.un1_wr_pointer_cry_12                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_13                       MUXCY_L     CI       In      -         10.253      -         
data_formatting_block.un1_wr_pointer_cry_13                       MUXCY_L     LO       Out     0.033     10.286      -         
data_formatting_block.un1_wr_pointer_cry_13                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_14                       MUXCY_L     CI       In      -         10.286      -         
data_formatting_block.un1_wr_pointer_cry_14                       MUXCY_L     LO       Out     0.033     10.319      -         
data_formatting_block.un1_wr_pointer_cry_14                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_15                       MUXCY_L     CI       In      -         10.319      -         
data_formatting_block.un1_wr_pointer_cry_15                       MUXCY_L     LO       Out     0.033     10.352      -         
data_formatting_block.un1_wr_pointer_cry_15                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_16                       MUXCY_L     CI       In      -         10.352      -         
data_formatting_block.un1_wr_pointer_cry_16                       MUXCY_L     LO       Out     0.033     10.385      -         
data_formatting_block.un1_wr_pointer_cry_16                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_17                       MUXCY_L     CI       In      -         10.385      -         
data_formatting_block.un1_wr_pointer_cry_17                       MUXCY_L     LO       Out     0.033     10.417      -         
data_formatting_block.un1_wr_pointer_cry_17                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_18                       MUXCY_L     CI       In      -         10.417      -         
data_formatting_block.un1_wr_pointer_cry_18                       MUXCY_L     LO       Out     0.033     10.450      -         
data_formatting_block.un1_wr_pointer_cry_18                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_19                       MUXCY_L     CI       In      -         10.450      -         
data_formatting_block.un1_wr_pointer_cry_19                       MUXCY_L     LO       Out     0.033     10.483      -         
data_formatting_block.un1_wr_pointer_cry_19                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_20                       MUXCY_L     CI       In      -         10.483      -         
data_formatting_block.un1_wr_pointer_cry_20                       MUXCY_L     LO       Out     0.033     10.516      -         
data_formatting_block.un1_wr_pointer_cry_20                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_21                       MUXCY_L     CI       In      -         10.516      -         
data_formatting_block.un1_wr_pointer_cry_21                       MUXCY_L     LO       Out     0.033     10.549      -         
data_formatting_block.un1_wr_pointer_cry_21                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_22                       MUXCY_L     CI       In      -         10.549      -         
data_formatting_block.un1_wr_pointer_cry_22                       MUXCY_L     LO       Out     0.033     10.581      -         
data_formatting_block.un1_wr_pointer_cry_22                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_23                       MUXCY_L     CI       In      -         10.581      -         
data_formatting_block.un1_wr_pointer_cry_23                       MUXCY_L     LO       Out     0.033     10.614      -         
data_formatting_block.un1_wr_pointer_cry_23                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_24                       MUXCY_L     CI       In      -         10.614      -         
data_formatting_block.un1_wr_pointer_cry_24                       MUXCY_L     LO       Out     0.033     10.647      -         
data_formatting_block.un1_wr_pointer_cry_24                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_25                       MUXCY_L     CI       In      -         10.647      -         
data_formatting_block.un1_wr_pointer_cry_25                       MUXCY_L     LO       Out     0.033     10.680      -         
data_formatting_block.un1_wr_pointer_cry_25                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_26                       MUXCY_L     CI       In      -         10.680      -         
data_formatting_block.un1_wr_pointer_cry_26                       MUXCY_L     LO       Out     0.033     10.713      -         
data_formatting_block.un1_wr_pointer_cry_26                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_27                       MUXCY_L     CI       In      -         10.713      -         
data_formatting_block.un1_wr_pointer_cry_27                       MUXCY_L     LO       Out     0.033     10.745      -         
data_formatting_block.un1_wr_pointer_cry_27                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_28                       MUXCY_L     CI       In      -         10.745      -         
data_formatting_block.un1_wr_pointer_cry_28                       MUXCY_L     LO       Out     0.033     10.778      -         
data_formatting_block.un1_wr_pointer_cry_28                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_29                       MUXCY_L     CI       In      -         10.778      -         
data_formatting_block.un1_wr_pointer_cry_29                       MUXCY_L     LO       Out     0.033     10.811      -         
data_formatting_block.un1_wr_pointer_cry_29                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_30                       MUXCY_L     CI       In      -         10.811      -         
data_formatting_block.un1_wr_pointer_cry_30                       MUXCY_L     LO       Out     0.033     10.844      -         
data_formatting_block.un1_wr_pointer_cry_30                       Net         -        -       0.000     -           1         
data_formatting_block.un1_wr_pointer_s_31                         XORCY       CI       In      -         10.844      -         
data_formatting_block.un1_wr_pointer_s_31                         XORCY       O        Out     0.208     11.052      -         
N_6528                                                            Net         -        -       0.000     -           1         
data_formatting_block.wr_pointer[31]                              FDR         D        In      -         11.052      -         
===============================================================================================================================
Total path delay (propagation time + setup) of 7.360 is 3.609(49.0%) logic and 3.750(51.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Start clock path:

Instance / Net                                         Pin             Pin               Arrival     No. of    
Name                                    Type           Name            Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------
Start Clock :                           tdc_clk125                                                             
------------                                                                                                   
tdc_clk_p_i                             Port           tdc_clk_p_i     In      -         0.000       -         
tdc_clk_p_i                             Net            -               -       0.000     -           1         
clks_rsts_mgment.tdc_clk125_ibuf        IBUFDS         I               In      -         0.000       -         
clks_rsts_mgment.tdc_clk125_ibuf        IBUFDS         O               Out     1.174     1.174       -         
clks_rsts_mgment.tdc_clk_buf            Net            -               -       1.174     -           1         
clks_rsts_mgment.tdc_clk125_gbuf        BUFG           I               In      -         2.348       -         
clks_rsts_mgment.tdc_clk125_gbuf        BUFG           O               Out     0.225     2.573       -         
clk                                     Net            -               -       1.540     -           7         
data_formatting_block.wr_pointer[4]     FDR            C               In      -         4.112       -         
===============================================================================================================


End clock path:

Instance / Net                                          Pin             Pin               Arrival     No. of    
Name                                     Type           Name            Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------
Start Clock :                            tdc_clk125                                                             
------------                                                                                                    
tdc_clk_p_i                              Port           tdc_clk_p_i     In      -         0.000       -         
tdc_clk_p_i                              Net            -               -       0.000     -           1         
clks_rsts_mgment.tdc_clk125_ibuf         IBUFDS         I               In      -         0.000       -         
clks_rsts_mgment.tdc_clk125_ibuf         IBUFDS         O               Out     1.174     1.174       -         
clks_rsts_mgment.tdc_clk_buf             Net            -               -       1.174     -           1         
clks_rsts_mgment.tdc_clk125_gbuf         BUFG           I               In      -         2.348       -         
clks_rsts_mgment.tdc_clk125_gbuf         BUFG           O               Out     0.225     2.573       -         
clk                                      Net            -               -       1.540     -           7         
data_formatting_block.wr_pointer[31]     FDR            C               In      -         4.112       -         
================================================================================================================


Path information for path number 4: 
      Requested Period:                      8.000
    - Setup time:                            0.420
    + Clock delay at ending point:           4.112
    = Required time:                         11.692

    - Propagation time:                      6.939
    - Clock delay at starting point:         4.112
    = Slack (non-critical) :                 0.640

    Number of logic level(s):                35
    Starting point:                          data_formatting_block.wr_pointer[5] / Q
    Ending point:                            data_formatting_block.wr_pointer[31] / D
    The start point is clocked by            tdc_clk125 [rising] on pin C
    The end   point is clocked by            tdc_clk125 [rising] on pin C

Instance / Net                                                                Pin      Pin               Arrival     No. of    
Name                                                              Type        Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------
data_formatting_block.wr_pointer[5]                               FDR         Q        Out     0.526     4.639       -         
wr_pointer[9]                                                     Net         -        -       0.985     -           4         
data_formatting_block.pointer_update\.un37_mem_cyc_4_1            LUT2        I1       In      -         5.624       -         
data_formatting_block.pointer_update\.un37_mem_cyc_4_1            LUT2        O        Out     0.220     5.843       -         
data_formatting_block.pointer_update\.un37_mem_cyc_4_1            Net         -        -       0.910     -           2         
data_formatting_block.pointer_update\.un37_mem_cyc_3_0_RNIT54P    LUT6_L      I4       In      -         6.753       -         
data_formatting_block.pointer_update\.un37_mem_cyc_3_0_RNIT54P    LUT6_L      LO       Out     0.754     7.507       -         
N_36168                                                           Net         -        -       0.945     -           1         
circular_buffer_block.class_ack_RNI8MTE1                          LUT6        I5       In      -         8.452       -         
circular_buffer_block.class_ack_RNI8MTE1                          LUT6        O        Out     0.110     8.562       -         
data_formatting_block.wr_pointer_1_sqmuxa                         Net         -        -       0.910     -           2         
data_formatting_block.un1_wr_pointer_cry_0                        MUXCY_L     CI       In      -         9.472       -         
data_formatting_block.un1_wr_pointer_cry_0                        MUXCY_L     LO       Out     0.388     9.860       -         
data_formatting_block.un1_wr_pointer_cry_0                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_1                        MUXCY_L     CI       In      -         9.860       -         
data_formatting_block.un1_wr_pointer_cry_1                        MUXCY_L     LO       Out     0.033     9.893       -         
data_formatting_block.un1_wr_pointer_cry_1                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_2                        MUXCY_L     CI       In      -         9.893       -         
data_formatting_block.un1_wr_pointer_cry_2                        MUXCY_L     LO       Out     0.033     9.925       -         
data_formatting_block.un1_wr_pointer_cry_2                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_3                        MUXCY_L     CI       In      -         9.925       -         
data_formatting_block.un1_wr_pointer_cry_3                        MUXCY_L     LO       Out     0.033     9.958       -         
data_formatting_block.un1_wr_pointer_cry_3                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_4                        MUXCY_L     CI       In      -         9.958       -         
data_formatting_block.un1_wr_pointer_cry_4                        MUXCY_L     LO       Out     0.033     9.991       -         
data_formatting_block.un1_wr_pointer_cry_4                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_5                        MUXCY_L     CI       In      -         9.991       -         
data_formatting_block.un1_wr_pointer_cry_5                        MUXCY_L     LO       Out     0.033     10.024      -         
data_formatting_block.un1_wr_pointer_cry_5                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_6                        MUXCY_L     CI       In      -         10.024      -         
data_formatting_block.un1_wr_pointer_cry_6                        MUXCY_L     LO       Out     0.033     10.057      -         
data_formatting_block.un1_wr_pointer_cry_6                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_7                        MUXCY_L     CI       In      -         10.057      -         
data_formatting_block.un1_wr_pointer_cry_7                        MUXCY_L     LO       Out     0.033     10.089      -         
data_formatting_block.un1_wr_pointer_cry_7                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_8                        MUXCY_L     CI       In      -         10.089      -         
data_formatting_block.un1_wr_pointer_cry_8                        MUXCY_L     LO       Out     0.033     10.122      -         
data_formatting_block.un1_wr_pointer_cry_8                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_9                        MUXCY_L     CI       In      -         10.122      -         
data_formatting_block.un1_wr_pointer_cry_9                        MUXCY_L     LO       Out     0.033     10.155      -         
data_formatting_block.un1_wr_pointer_cry_9                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_10                       MUXCY_L     CI       In      -         10.155      -         
data_formatting_block.un1_wr_pointer_cry_10                       MUXCY_L     LO       Out     0.033     10.188      -         
data_formatting_block.un1_wr_pointer_cry_10                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_11                       MUXCY_L     CI       In      -         10.188      -         
data_formatting_block.un1_wr_pointer_cry_11                       MUXCY_L     LO       Out     0.033     10.221      -         
data_formatting_block.un1_wr_pointer_cry_11                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_12                       MUXCY_L     CI       In      -         10.221      -         
data_formatting_block.un1_wr_pointer_cry_12                       MUXCY_L     LO       Out     0.033     10.253      -         
data_formatting_block.un1_wr_pointer_cry_12                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_13                       MUXCY_L     CI       In      -         10.253      -         
data_formatting_block.un1_wr_pointer_cry_13                       MUXCY_L     LO       Out     0.033     10.286      -         
data_formatting_block.un1_wr_pointer_cry_13                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_14                       MUXCY_L     CI       In      -         10.286      -         
data_formatting_block.un1_wr_pointer_cry_14                       MUXCY_L     LO       Out     0.033     10.319      -         
data_formatting_block.un1_wr_pointer_cry_14                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_15                       MUXCY_L     CI       In      -         10.319      -         
data_formatting_block.un1_wr_pointer_cry_15                       MUXCY_L     LO       Out     0.033     10.352      -         
data_formatting_block.un1_wr_pointer_cry_15                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_16                       MUXCY_L     CI       In      -         10.352      -         
data_formatting_block.un1_wr_pointer_cry_16                       MUXCY_L     LO       Out     0.033     10.385      -         
data_formatting_block.un1_wr_pointer_cry_16                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_17                       MUXCY_L     CI       In      -         10.385      -         
data_formatting_block.un1_wr_pointer_cry_17                       MUXCY_L     LO       Out     0.033     10.417      -         
data_formatting_block.un1_wr_pointer_cry_17                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_18                       MUXCY_L     CI       In      -         10.417      -         
data_formatting_block.un1_wr_pointer_cry_18                       MUXCY_L     LO       Out     0.033     10.450      -         
data_formatting_block.un1_wr_pointer_cry_18                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_19                       MUXCY_L     CI       In      -         10.450      -         
data_formatting_block.un1_wr_pointer_cry_19                       MUXCY_L     LO       Out     0.033     10.483      -         
data_formatting_block.un1_wr_pointer_cry_19                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_20                       MUXCY_L     CI       In      -         10.483      -         
data_formatting_block.un1_wr_pointer_cry_20                       MUXCY_L     LO       Out     0.033     10.516      -         
data_formatting_block.un1_wr_pointer_cry_20                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_21                       MUXCY_L     CI       In      -         10.516      -         
data_formatting_block.un1_wr_pointer_cry_21                       MUXCY_L     LO       Out     0.033     10.549      -         
data_formatting_block.un1_wr_pointer_cry_21                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_22                       MUXCY_L     CI       In      -         10.549      -         
data_formatting_block.un1_wr_pointer_cry_22                       MUXCY_L     LO       Out     0.033     10.581      -         
data_formatting_block.un1_wr_pointer_cry_22                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_23                       MUXCY_L     CI       In      -         10.581      -         
data_formatting_block.un1_wr_pointer_cry_23                       MUXCY_L     LO       Out     0.033     10.614      -         
data_formatting_block.un1_wr_pointer_cry_23                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_24                       MUXCY_L     CI       In      -         10.614      -         
data_formatting_block.un1_wr_pointer_cry_24                       MUXCY_L     LO       Out     0.033     10.647      -         
data_formatting_block.un1_wr_pointer_cry_24                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_25                       MUXCY_L     CI       In      -         10.647      -         
data_formatting_block.un1_wr_pointer_cry_25                       MUXCY_L     LO       Out     0.033     10.680      -         
data_formatting_block.un1_wr_pointer_cry_25                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_26                       MUXCY_L     CI       In      -         10.680      -         
data_formatting_block.un1_wr_pointer_cry_26                       MUXCY_L     LO       Out     0.033     10.713      -         
data_formatting_block.un1_wr_pointer_cry_26                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_27                       MUXCY_L     CI       In      -         10.713      -         
data_formatting_block.un1_wr_pointer_cry_27                       MUXCY_L     LO       Out     0.033     10.745      -         
data_formatting_block.un1_wr_pointer_cry_27                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_28                       MUXCY_L     CI       In      -         10.745      -         
data_formatting_block.un1_wr_pointer_cry_28                       MUXCY_L     LO       Out     0.033     10.778      -         
data_formatting_block.un1_wr_pointer_cry_28                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_29                       MUXCY_L     CI       In      -         10.778      -         
data_formatting_block.un1_wr_pointer_cry_29                       MUXCY_L     LO       Out     0.033     10.811      -         
data_formatting_block.un1_wr_pointer_cry_29                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_30                       MUXCY_L     CI       In      -         10.811      -         
data_formatting_block.un1_wr_pointer_cry_30                       MUXCY_L     LO       Out     0.033     10.844      -         
data_formatting_block.un1_wr_pointer_cry_30                       Net         -        -       0.000     -           1         
data_formatting_block.un1_wr_pointer_s_31                         XORCY       CI       In      -         10.844      -         
data_formatting_block.un1_wr_pointer_s_31                         XORCY       O        Out     0.208     11.052      -         
N_6528                                                            Net         -        -       0.000     -           1         
data_formatting_block.wr_pointer[31]                              FDR         D        In      -         11.052      -         
===============================================================================================================================
Total path delay (propagation time + setup) of 7.360 is 3.609(49.0%) logic and 3.750(51.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Start clock path:

Instance / Net                                         Pin             Pin               Arrival     No. of    
Name                                    Type           Name            Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------
Start Clock :                           tdc_clk125                                                             
------------                                                                                                   
tdc_clk_p_i                             Port           tdc_clk_p_i     In      -         0.000       -         
tdc_clk_p_i                             Net            -               -       0.000     -           1         
clks_rsts_mgment.tdc_clk125_ibuf        IBUFDS         I               In      -         0.000       -         
clks_rsts_mgment.tdc_clk125_ibuf        IBUFDS         O               Out     1.174     1.174       -         
clks_rsts_mgment.tdc_clk_buf            Net            -               -       1.174     -           1         
clks_rsts_mgment.tdc_clk125_gbuf        BUFG           I               In      -         2.348       -         
clks_rsts_mgment.tdc_clk125_gbuf        BUFG           O               Out     0.225     2.573       -         
clk                                     Net            -               -       1.540     -           7         
data_formatting_block.wr_pointer[5]     FDR            C               In      -         4.112       -         
===============================================================================================================


End clock path:

Instance / Net                                          Pin             Pin               Arrival     No. of    
Name                                     Type           Name            Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------
Start Clock :                            tdc_clk125                                                             
------------                                                                                                    
tdc_clk_p_i                              Port           tdc_clk_p_i     In      -         0.000       -         
tdc_clk_p_i                              Net            -               -       0.000     -           1         
clks_rsts_mgment.tdc_clk125_ibuf         IBUFDS         I               In      -         0.000       -         
clks_rsts_mgment.tdc_clk125_ibuf         IBUFDS         O               Out     1.174     1.174       -         
clks_rsts_mgment.tdc_clk_buf             Net            -               -       1.174     -           1         
clks_rsts_mgment.tdc_clk125_gbuf         BUFG           I               In      -         2.348       -         
clks_rsts_mgment.tdc_clk125_gbuf         BUFG           O               Out     0.225     2.573       -         
clk                                      Net            -               -       1.540     -           7         
data_formatting_block.wr_pointer[31]     FDR            C               In      -         4.112       -         
================================================================================================================


Path information for path number 5: 
      Requested Period:                      8.000
    - Setup time:                            0.420
    + Clock delay at ending point:           4.112
    = Required time:                         11.692

    - Propagation time:                      6.939
    - Clock delay at starting point:         4.112
    = Slack (non-critical) :                 0.640

    Number of logic level(s):                35
    Starting point:                          data_formatting_block.wr_pointer[6] / Q
    Ending point:                            data_formatting_block.wr_pointer[31] / D
    The start point is clocked by            tdc_clk125 [rising] on pin C
    The end   point is clocked by            tdc_clk125 [rising] on pin C

Instance / Net                                                                Pin      Pin               Arrival     No. of    
Name                                                              Type        Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------
data_formatting_block.wr_pointer[6]                               FDR         Q        Out     0.526     4.639       -         
wr_pointer[10]                                                    Net         -        -       0.985     -           4         
data_formatting_block.pointer_update\.un37_mem_cyc_4_2            LUT2        I0       In      -         5.624       -         
data_formatting_block.pointer_update\.un37_mem_cyc_4_2            LUT2        O        Out     0.220     5.843       -         
data_formatting_block.pointer_update\.un37_mem_cyc_4_2            Net         -        -       0.910     -           2         
data_formatting_block.pointer_update\.un37_mem_cyc_3_0_RNIT54P    LUT6_L      I5       In      -         6.753       -         
data_formatting_block.pointer_update\.un37_mem_cyc_3_0_RNIT54P    LUT6_L      LO       Out     0.754     7.507       -         
N_36168                                                           Net         -        -       0.945     -           1         
circular_buffer_block.class_ack_RNI8MTE1                          LUT6        I5       In      -         8.452       -         
circular_buffer_block.class_ack_RNI8MTE1                          LUT6        O        Out     0.110     8.562       -         
data_formatting_block.wr_pointer_1_sqmuxa                         Net         -        -       0.910     -           2         
data_formatting_block.un1_wr_pointer_cry_0                        MUXCY_L     CI       In      -         9.472       -         
data_formatting_block.un1_wr_pointer_cry_0                        MUXCY_L     LO       Out     0.388     9.860       -         
data_formatting_block.un1_wr_pointer_cry_0                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_1                        MUXCY_L     CI       In      -         9.860       -         
data_formatting_block.un1_wr_pointer_cry_1                        MUXCY_L     LO       Out     0.033     9.893       -         
data_formatting_block.un1_wr_pointer_cry_1                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_2                        MUXCY_L     CI       In      -         9.893       -         
data_formatting_block.un1_wr_pointer_cry_2                        MUXCY_L     LO       Out     0.033     9.925       -         
data_formatting_block.un1_wr_pointer_cry_2                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_3                        MUXCY_L     CI       In      -         9.925       -         
data_formatting_block.un1_wr_pointer_cry_3                        MUXCY_L     LO       Out     0.033     9.958       -         
data_formatting_block.un1_wr_pointer_cry_3                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_4                        MUXCY_L     CI       In      -         9.958       -         
data_formatting_block.un1_wr_pointer_cry_4                        MUXCY_L     LO       Out     0.033     9.991       -         
data_formatting_block.un1_wr_pointer_cry_4                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_5                        MUXCY_L     CI       In      -         9.991       -         
data_formatting_block.un1_wr_pointer_cry_5                        MUXCY_L     LO       Out     0.033     10.024      -         
data_formatting_block.un1_wr_pointer_cry_5                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_6                        MUXCY_L     CI       In      -         10.024      -         
data_formatting_block.un1_wr_pointer_cry_6                        MUXCY_L     LO       Out     0.033     10.057      -         
data_formatting_block.un1_wr_pointer_cry_6                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_7                        MUXCY_L     CI       In      -         10.057      -         
data_formatting_block.un1_wr_pointer_cry_7                        MUXCY_L     LO       Out     0.033     10.089      -         
data_formatting_block.un1_wr_pointer_cry_7                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_8                        MUXCY_L     CI       In      -         10.089      -         
data_formatting_block.un1_wr_pointer_cry_8                        MUXCY_L     LO       Out     0.033     10.122      -         
data_formatting_block.un1_wr_pointer_cry_8                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_9                        MUXCY_L     CI       In      -         10.122      -         
data_formatting_block.un1_wr_pointer_cry_9                        MUXCY_L     LO       Out     0.033     10.155      -         
data_formatting_block.un1_wr_pointer_cry_9                        Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_10                       MUXCY_L     CI       In      -         10.155      -         
data_formatting_block.un1_wr_pointer_cry_10                       MUXCY_L     LO       Out     0.033     10.188      -         
data_formatting_block.un1_wr_pointer_cry_10                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_11                       MUXCY_L     CI       In      -         10.188      -         
data_formatting_block.un1_wr_pointer_cry_11                       MUXCY_L     LO       Out     0.033     10.221      -         
data_formatting_block.un1_wr_pointer_cry_11                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_12                       MUXCY_L     CI       In      -         10.221      -         
data_formatting_block.un1_wr_pointer_cry_12                       MUXCY_L     LO       Out     0.033     10.253      -         
data_formatting_block.un1_wr_pointer_cry_12                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_13                       MUXCY_L     CI       In      -         10.253      -         
data_formatting_block.un1_wr_pointer_cry_13                       MUXCY_L     LO       Out     0.033     10.286      -         
data_formatting_block.un1_wr_pointer_cry_13                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_14                       MUXCY_L     CI       In      -         10.286      -         
data_formatting_block.un1_wr_pointer_cry_14                       MUXCY_L     LO       Out     0.033     10.319      -         
data_formatting_block.un1_wr_pointer_cry_14                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_15                       MUXCY_L     CI       In      -         10.319      -         
data_formatting_block.un1_wr_pointer_cry_15                       MUXCY_L     LO       Out     0.033     10.352      -         
data_formatting_block.un1_wr_pointer_cry_15                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_16                       MUXCY_L     CI       In      -         10.352      -         
data_formatting_block.un1_wr_pointer_cry_16                       MUXCY_L     LO       Out     0.033     10.385      -         
data_formatting_block.un1_wr_pointer_cry_16                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_17                       MUXCY_L     CI       In      -         10.385      -         
data_formatting_block.un1_wr_pointer_cry_17                       MUXCY_L     LO       Out     0.033     10.417      -         
data_formatting_block.un1_wr_pointer_cry_17                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_18                       MUXCY_L     CI       In      -         10.417      -         
data_formatting_block.un1_wr_pointer_cry_18                       MUXCY_L     LO       Out     0.033     10.450      -         
data_formatting_block.un1_wr_pointer_cry_18                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_19                       MUXCY_L     CI       In      -         10.450      -         
data_formatting_block.un1_wr_pointer_cry_19                       MUXCY_L     LO       Out     0.033     10.483      -         
data_formatting_block.un1_wr_pointer_cry_19                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_20                       MUXCY_L     CI       In      -         10.483      -         
data_formatting_block.un1_wr_pointer_cry_20                       MUXCY_L     LO       Out     0.033     10.516      -         
data_formatting_block.un1_wr_pointer_cry_20                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_21                       MUXCY_L     CI       In      -         10.516      -         
data_formatting_block.un1_wr_pointer_cry_21                       MUXCY_L     LO       Out     0.033     10.549      -         
data_formatting_block.un1_wr_pointer_cry_21                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_22                       MUXCY_L     CI       In      -         10.549      -         
data_formatting_block.un1_wr_pointer_cry_22                       MUXCY_L     LO       Out     0.033     10.581      -         
data_formatting_block.un1_wr_pointer_cry_22                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_23                       MUXCY_L     CI       In      -         10.581      -         
data_formatting_block.un1_wr_pointer_cry_23                       MUXCY_L     LO       Out     0.033     10.614      -         
data_formatting_block.un1_wr_pointer_cry_23                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_24                       MUXCY_L     CI       In      -         10.614      -         
data_formatting_block.un1_wr_pointer_cry_24                       MUXCY_L     LO       Out     0.033     10.647      -         
data_formatting_block.un1_wr_pointer_cry_24                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_25                       MUXCY_L     CI       In      -         10.647      -         
data_formatting_block.un1_wr_pointer_cry_25                       MUXCY_L     LO       Out     0.033     10.680      -         
data_formatting_block.un1_wr_pointer_cry_25                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_26                       MUXCY_L     CI       In      -         10.680      -         
data_formatting_block.un1_wr_pointer_cry_26                       MUXCY_L     LO       Out     0.033     10.713      -         
data_formatting_block.un1_wr_pointer_cry_26                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_27                       MUXCY_L     CI       In      -         10.713      -         
data_formatting_block.un1_wr_pointer_cry_27                       MUXCY_L     LO       Out     0.033     10.745      -         
data_formatting_block.un1_wr_pointer_cry_27                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_28                       MUXCY_L     CI       In      -         10.745      -         
data_formatting_block.un1_wr_pointer_cry_28                       MUXCY_L     LO       Out     0.033     10.778      -         
data_formatting_block.un1_wr_pointer_cry_28                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_29                       MUXCY_L     CI       In      -         10.778      -         
data_formatting_block.un1_wr_pointer_cry_29                       MUXCY_L     LO       Out     0.033     10.811      -         
data_formatting_block.un1_wr_pointer_cry_29                       Net         -        -       0.000     -           2         
data_formatting_block.un1_wr_pointer_cry_30                       MUXCY_L     CI       In      -         10.811      -         
data_formatting_block.un1_wr_pointer_cry_30                       MUXCY_L     LO       Out     0.033     10.844      -         
data_formatting_block.un1_wr_pointer_cry_30                       Net         -        -       0.000     -           1         
data_formatting_block.un1_wr_pointer_s_31                         XORCY       CI       In      -         10.844      -         
data_formatting_block.un1_wr_pointer_s_31                         XORCY       O        Out     0.208     11.052      -         
N_6528                                                            Net         -        -       0.000     -           1         
data_formatting_block.wr_pointer[31]                              FDR         D        In      -         11.052      -         
===============================================================================================================================
Total path delay (propagation time + setup) of 7.360 is 3.609(49.0%) logic and 3.750(51.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Start clock path:

Instance / Net                                         Pin             Pin               Arrival     No. of    
Name                                    Type           Name            Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------
Start Clock :                           tdc_clk125                                                             
------------                                                                                                   
tdc_clk_p_i                             Port           tdc_clk_p_i     In      -         0.000       -         
tdc_clk_p_i                             Net            -               -       0.000     -           1         
clks_rsts_mgment.tdc_clk125_ibuf        IBUFDS         I               In      -         0.000       -         
clks_rsts_mgment.tdc_clk125_ibuf        IBUFDS         O               Out     1.174     1.174       -         
clks_rsts_mgment.tdc_clk_buf            Net            -               -       1.174     -           1         
clks_rsts_mgment.tdc_clk125_gbuf        BUFG           I               In      -         2.348       -         
clks_rsts_mgment.tdc_clk125_gbuf        BUFG           O               Out     0.225     2.573       -         
clk                                     Net            -               -       1.540     -           7         
data_formatting_block.wr_pointer[6]     FDR            C               In      -         4.112       -         
===============================================================================================================


End clock path:

Instance / Net                                          Pin             Pin               Arrival     No. of    
Name                                     Type           Name            Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------
Start Clock :                            tdc_clk125                                                             
------------                                                                                                    
tdc_clk_p_i                              Port           tdc_clk_p_i     In      -         0.000       -         
tdc_clk_p_i                              Net            -               -       0.000     -           1         
clks_rsts_mgment.tdc_clk125_ibuf         IBUFDS         I               In      -         0.000       -         
clks_rsts_mgment.tdc_clk125_ibuf         IBUFDS         O               Out     1.174     1.174       -         
clks_rsts_mgment.tdc_clk_buf             Net            -               -       1.174     -           1         
clks_rsts_mgment.tdc_clk125_gbuf         BUFG           I               In      -         2.348       -         
clks_rsts_mgment.tdc_clk125_gbuf         BUFG           O               Out     0.225     2.573       -         
clk                                      Net            -               -       1.540     -           7         
data_formatting_block.wr_pointer[31]     FDR            C               In      -         4.112       -         
================================================================================================================




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                                                            Starting                                                                                                       Arrival           
Instance                                                                    Reference     Type            Pin           Net                                                                Time        Slack 
                                                                            Clock                                                                                                                            
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
gnum_interface_block.cmp_wbmaster32.cmp_fifo_to_wb                          System        fifo_64x512     prog_full     gnum_interface_block.cmp_wbmaster32.to_wb_fifo_full                0.000       -4.688
gnum_interface_block.cmp_p2l_dma_master.cmp_to_wb_fifo                      System        fifo_64x512     prog_full     gnum_interface_block.cmp_p2l_dma_master.to_wb_fifo_full            0.000       -4.664
gnum_interface_block.cmp_l2p_ser.cmp_clk_out.loop0\.0\.loop3\.oserdes_m     System        OSERDES2        OQ            gnum_interface_block.cmp_l2p_ser.cmp_clk_out.tx_data_out[0]        0.000       -3.582
gnum_interface_block.cmp_l2p_ser.cmp_dframe_out.loop0\.0\.loop3\.oserdes_m  System        OSERDES2        OQ            gnum_interface_block.cmp_l2p_ser.cmp_dframe_out.tx_data_out[0]     0.000       -3.582
gnum_interface_block.cmp_l2p_ser.cmp_valid_out.loop0\.0\.loop3\.oserdes_m   System        OSERDES2        OQ            gnum_interface_block.cmp_l2p_ser.cmp_valid_out.tx_data_out[0]      0.000       -3.582
gnum_interface_block.cmp_l2p_ser.cmp_data_out.loop0\.0\.loop3\.oserdes_m    System        OSERDES2        OQ            gnum_interface_block.cmp_l2p_ser.cmp_data_out.tx_data_out[0]       0.000       -2.067
gnum_interface_block.cmp_l2p_ser.cmp_data_out.loop0\.1\.loop3\.oserdes_m    System        OSERDES2        OQ            gnum_interface_block.cmp_l2p_ser.cmp_data_out.tx_data_out[1]       0.000       -2.067
gnum_interface_block.cmp_l2p_ser.cmp_data_out.loop0\.2\.loop3\.oserdes_m    System        OSERDES2        OQ            gnum_interface_block.cmp_l2p_ser.cmp_data_out.tx_data_out[2]       0.000       -2.067
gnum_interface_block.cmp_l2p_ser.cmp_data_out.loop0\.3\.loop3\.oserdes_m    System        OSERDES2        OQ            gnum_interface_block.cmp_l2p_ser.cmp_data_out.tx_data_out[3]       0.000       -2.067
gnum_interface_block.cmp_l2p_ser.cmp_data_out.loop0\.4\.loop3\.oserdes_m    System        OSERDES2        OQ            gnum_interface_block.cmp_l2p_ser.cmp_data_out.tx_data_out[4]       0.000       -2.067
=============================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                     Starting                                                   Required           
Instance             Reference     Type     Pin               Net               Time         Slack 
                     Clock                                                                         
---------------------------------------------------------------------------------------------------
p2l_rdy_o            System        Port     p2l_rdy_o         p2l_rdy_o         0.377        -4.688
l2p_clk_p_o          System        Port     l2p_clk_p_o       l2p_clk_p_o       0.377        -3.582
l2p_dframe_o         System        Port     l2p_dframe_o      l2p_dframe_o      0.377        -3.582
l2p_valid_o          System        Port     l2p_valid_o       l2p_valid_o       0.377        -3.582
p_wr_rdy_o[1:0]      System        Port     p_wr_rdy_o[0]     p_wr_rdy_o[0]     1.892        -3.025
p_wr_rdy_o[1:0]      System        Port     p_wr_rdy_o[1]     p_wr_rdy_o[1]     1.892        -3.025
l2p_data_o[15:0]     System        Port     l2p_data_o[0]     l2p_data_o[0]     1.892        -2.067
l2p_data_o[15:0]     System        Port     l2p_data_o[1]     l2p_data_o[1]     1.892        -2.067
l2p_data_o[15:0]     System        Port     l2p_data_o[2]     l2p_data_o[2]     1.892        -2.067
l2p_data_o[15:0]     System        Port     l2p_data_o[3]     l2p_data_o[3]     1.892        -2.067
===================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      5.000
    - User constraint on ending point:       2.000
    = Required time:                         3.000

    - Propagation time:                      5.064
    - Estimated clock delay at start point:  2.623
    = Slack (non-critical) :                 -4.688

    Number of logic level(s):                2
    Starting point:                          gnum_interface_block.cmp_wbmaster32.cmp_fifo_to_wb / prog_full
    Ending point:                            p2l_rdy_o / p2l_rdy_o
    The start point is clocked by            System [rising]
    The end   point is clocked by            gnum_clk200 [rising]

Instance / Net                                                          Pin           Pin               Arrival     No. of    
Name                                                    Type            Name          Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------
gnum_interface_block.cmp_wbmaster32.cmp_fifo_to_wb      fifo_64x512     prog_full     Out     0.000     0.000       -         
gnum_interface_block.cmp_wbmaster32.to_wb_fifo_full     Net             -             -       0.910     -           2         
gnum_interface_block.p2l_rdy_o                          LUT2            I1            In      -         0.910       -         
gnum_interface_block.p2l_rdy_o                          LUT2            O             Out     0.196     1.106       -         
p2l_rdy_o_c                                             Net             -             -       0.862     -           1         
p2l_rdy_o_obuf                                          OBUF            I             In      -         1.968       -         
p2l_rdy_o_obuf                                          OBUF            O             Out     3.096     5.064       -         
p2l_rdy_o                                               Net             -             -       0.000     -           1         
p2l_rdy_o                                               Port            p2l_rdy_o     Out     -         5.064       -         
==============================================================================================================================
Total path delay (propagation time + setup) of 5.064 is 3.292(65.0%) logic and 1.773(35.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

@W: :  | No start clock found for start point gnum_interface_block.cmp_wbmaster32.cmp_fifo_to_wb / prog_full (rising). Should not occur.  

Path information for path number 2: 
      Requested Period:                      5.000
    - User constraint on ending point:       2.000
    = Required time:                         3.000

    - Propagation time:                      5.040
    - Estimated clock delay at start point:  2.623
    = Slack (non-critical) :                 -4.664

    Number of logic level(s):                2
    Starting point:                          gnum_interface_block.cmp_p2l_dma_master.cmp_to_wb_fifo / prog_full
    Ending point:                            p2l_rdy_o / p2l_rdy_o
    The start point is clocked by            System [rising]
    The end   point is clocked by            gnum_clk200 [rising]

Instance / Net                                                              Pin           Pin               Arrival     No. of    
Name                                                        Type            Name          Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------
gnum_interface_block.cmp_p2l_dma_master.cmp_to_wb_fifo      fifo_64x512     prog_full     Out     0.000     0.000       -         
gnum_interface_block.cmp_p2l_dma_master.to_wb_fifo_full     Net             -             -       0.862     -           1         
gnum_interface_block.p2l_rdy_o                              LUT2            I0            In      -         0.862       -         
gnum_interface_block.p2l_rdy_o                              LUT2            O             Out     0.220     1.082       -         
p2l_rdy_o_c                                                 Net             -             -       0.862     -           1         
p2l_rdy_o_obuf                                              OBUF            I             In      -         1.944       -         
p2l_rdy_o_obuf                                              OBUF            O             Out     3.096     5.040       -         
p2l_rdy_o                                                   Net             -             -       0.000     -           1         
p2l_rdy_o                                                   Port            p2l_rdy_o     Out     -         5.040       -         
==================================================================================================================================
Total path delay (propagation time + setup) of 5.040 is 3.316(65.8%) logic and 1.725(34.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

@W: :  | No start clock found for start point gnum_interface_block.cmp_p2l_dma_master.cmp_to_wb_fifo / prog_full (rising). Should not occur.  

Path information for path number 3: 
      Requested Period:                      5.000
    - User constraint on ending point:       2.000
    = Required time:                         3.000

    - Propagation time:                      3.958
    - Estimated clock delay at start point:  2.623
    = Slack (non-critical) :                 -3.582

    Number of logic level(s):                1
    Starting point:                          gnum_interface_block.cmp_l2p_ser.cmp_clk_out.loop0\.0\.loop3\.oserdes_m / OQ
    Ending point:                            l2p_clk_p_o / l2p_clk_p_o
    The start point is clocked by            System [rising]
    The end   point is clocked by            gnum_clk200 [rising]

Instance / Net                                                                        Pin             Pin               Arrival     No. of    
Name                                                                     Type         Name            Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------------------
gnum_interface_block.cmp_l2p_ser.cmp_clk_out.loop0\.0\.loop3\.oserdes_m  OSERDES2     OQ              Out     0.000     0.000       -         
gnum_interface_block.cmp_l2p_ser.cmp_clk_out.tx_data_out[0]              Net          -               -       0.862     -           1         
gnum_interface_block.cmp_l2p_ser.cmp_clk_out.loop0\.0\.io_clk_out        OBUFDS       I               In      -         0.862       -         
gnum_interface_block.cmp_l2p_ser.cmp_clk_out.loop0\.0\.io_clk_out        OBUFDS       O               Out     3.096     3.958       -         
l2p_clk_p_o                                                              Net          -               -       0.000     -           1         
l2p_clk_p_o                                                              Port         l2p_clk_p_o     Out     -         3.958       -         
==============================================================================================================================================
Total path delay (propagation time + setup) of 3.958 is 3.096(78.2%) logic and 0.862(21.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

@W: :  | No start clock found for start point gnum_interface_block.cmp_l2p_ser.cmp_clk_out.loop0®0®loop3®oserdes_m / OQ (rising). Should not occur.  

Path information for path number 4: 
      Requested Period:                      5.000
    - User constraint on ending point:       2.000
    = Required time:                         3.000

    - Propagation time:                      3.958
    - Estimated clock delay at start point:  2.623
    = Slack (non-critical) :                 -3.582

    Number of logic level(s):                1
    Starting point:                          gnum_interface_block.cmp_l2p_ser.cmp_dframe_out.loop0\.0\.loop3\.oserdes_m / OQ
    Ending point:                            l2p_dframe_o / l2p_dframe_o
    The start point is clocked by            System [rising]
    The end   point is clocked by            gnum_clk200 [rising]

Instance / Net                                                                           Pin              Pin               Arrival     No. of    
Name                                                                        Type         Name             Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------
gnum_interface_block.cmp_l2p_ser.cmp_dframe_out.loop0\.0\.loop3\.oserdes_m  OSERDES2     OQ               Out     0.000     0.000       -         
gnum_interface_block.cmp_l2p_ser.cmp_dframe_out.tx_data_out[0]              Net          -                -       0.862     -           1         
gnum_interface_block.cmp_l2p_ser.cmp_dframe_out.loop0\.0\.io_clk_out        OBUF         I                In      -         0.862       -         
gnum_interface_block.cmp_l2p_ser.cmp_dframe_out.loop0\.0\.io_clk_out        OBUF         O                Out     3.096     3.958       -         
l2p_dframe_o                                                                Net          -                -       0.000     -           1         
l2p_dframe_o                                                                Port         l2p_dframe_o     Out     -         3.958       -         
==================================================================================================================================================
Total path delay (propagation time + setup) of 3.958 is 3.096(78.2%) logic and 0.862(21.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

@W: :  | No start clock found for start point gnum_interface_block.cmp_l2p_ser.cmp_dframe_out.loop0®0®loop3®oserdes_m / OQ (rising). Should not occur.  

Path information for path number 5: 
      Requested Period:                      5.000
    - User constraint on ending point:       2.000
    = Required time:                         3.000

    - Propagation time:                      3.958
    - Estimated clock delay at start point:  2.623
    = Slack (non-critical) :                 -3.582

    Number of logic level(s):                1
    Starting point:                          gnum_interface_block.cmp_l2p_ser.cmp_valid_out.loop0\.0\.loop3\.oserdes_m / OQ
    Ending point:                            l2p_valid_o / l2p_valid_o
    The start point is clocked by            System [rising]
    The end   point is clocked by            gnum_clk200 [rising]

Instance / Net                                                                          Pin             Pin               Arrival     No. of    
Name                                                                       Type         Name            Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------------------
gnum_interface_block.cmp_l2p_ser.cmp_valid_out.loop0\.0\.loop3\.oserdes_m  OSERDES2     OQ              Out     0.000     0.000       -         
gnum_interface_block.cmp_l2p_ser.cmp_valid_out.tx_data_out[0]              Net          -               -       0.862     -           1         
gnum_interface_block.cmp_l2p_ser.cmp_valid_out.loop0\.0\.io_clk_out        OBUF         I               In      -         0.862       -         
gnum_interface_block.cmp_l2p_ser.cmp_valid_out.loop0\.0\.io_clk_out        OBUF         O               Out     3.096     3.958       -         
l2p_valid_o                                                                Net          -               -       0.000     -           1         
l2p_valid_o                                                                Port         l2p_valid_o     Out     -         3.958       -         
================================================================================================================================================
Total path delay (propagation time + setup) of 3.958 is 3.096(78.2%) logic and 0.862(21.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

@W: :  | No start clock found for start point gnum_interface_block.cmp_l2p_ser.cmp_valid_out.loop0®0®loop3®oserdes_m / OQ (rising). Should not occur.  


##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report for top_tdc 

Mapping to part: xc6slx45tfgg484-3
Cell usage:
BUFIO2          1 use
BUFIO2FB        1 use
BUFPLL          1 use
DSP48A1         3 uses
FD              32 uses
FDC             350 uses
FDCE            2340 uses
FDE             70 uses
FDP             8 uses
FDR             200 uses
FDRE            1156 uses
FDS             19 uses
GND             1 use
IODELAY2        2 uses
ISERDES2        20 uses
LD              22 uses
MUXCY           3 uses
MUXCY_L         890 uses
MUXF7           8 uses
MUXF8           4 uses
OSERDES2        19 uses
PLL_ADV         1 use
RAMB8BWER       1 use
VCC             1 use
XORCY           876 uses
blk_mem_circ_buff_v6_4  1 use
fifo_32x512     3 uses
fifo_64x512     2 uses
LUT1            592 uses
LUT2            511 uses
LUT3            836 uses
LUT4            293 uses
LUT5            385 uses
LUT6            781 uses
LUT6_2            9 uses

I/O ports: 136
I/O primitives: 123
IBUF           33 uses
IBUFDS         2 uses
IBUFG          1 use
IOBUF          28 uses
OBUF           58 uses
OBUFDS         1 use

BUFG           3 uses

I/O Register bits:                  36
Register bits not including I/Os:   4139 (6%)
Latch bits not including I/Os:      22 (0%)

RAM/ROM usage summary
Block Rams : 1 of 116 (0%)


DSP48s: 3 of 58 (5%)

Global Clock Buffers: 3 of 16 (18%)


 Number of unique control sets:              156
 C(clk), CLR(GND), PRE(GND), CE(VCC)		: 2
 C(spec_clk), CLR(GND), PRE(GND), CE(VCC)		: 12
 C(clk), CLR(pll_sclk_o_c_i), PRE(GND), CE(VCC)		: 1
 C(gnum_interface_block.sys_clk), CLR(un1_gnum_interface_block_i), PRE(GND), CE(VCC)		: 19
 C(gnum_interface_block.sys_clk), CLR(GND), PRE(un1_gnum_interface_block_i), CE(VCC)		: 2
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(VCC)		: 263
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_wbmaster32.from_wb_fifo_din_0_sqmuxa)		: 32
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(VCC)		: 59
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(N_5217_i)		: 1
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.N_163_i)		: 33
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.N_4_i)		: 2
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(N_5890)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_wbmaster32.N_329_i)		: 32
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_wbmaster32.wishbone_current_state_46_d)		: 52
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.p2l_hdr_start)		: 2
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(N_5274_i)		: 94
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.N_96_i)		: 30
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(N_5119_i)		: 1
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_nextl_reg_1_sqmuxa_i)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_nexth_reg_1_sqmuxa_i)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_len_reg_1_sqmuxa_i)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_hstartl_reg_1_sqmuxa_i)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_hstarth_reg_1_sqmuxa_i)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_cstart_reg_1_sqmuxa_i)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_attrib_reg_1_sqmuxa_i)		: 32
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.N_71_i)		: 32
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(N_5304_i)		: 1
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(N_5294_i)		: 2
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(N_5299_i)		: 1
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(N_5293_i)		: 2
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(N_5302_i)		: 1
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(N_5292_i)		: 2
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(N_5300_i)		: 1
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(N_5290_i)		: 2
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(N_5306_i)		: 1
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(N_5296_i)		: 2
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(N_5305_i)		: 1
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(N_5295_i)		: 2
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(N_5307_i)		: 1
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(N_5298_i)		: 2
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(N_5303_i)		: 1
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(N_5297_i)		: 2
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(N_5291_i)		: 2
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_nextl_int_write_1_sqmuxa)		: 32
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_nexth_int_write_1_sqmuxa)		: 32
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_len_int_write_1_sqmuxa)		: 32
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_hstartl_int_write_1_sqmuxa)		: 32
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_hstarth_int_write_1_sqmuxa)		: 32
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_ctrl_int_write_0_sqmuxa)		: 32
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_cstart_int_write_1_sqmuxa)		: 32
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_attrib_int_write_1_sqmuxa)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_attrib_int_read_0_sqmuxa)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_attrib_int_read_1_sqmuxa)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_nexth_int_read_0_sqmuxa)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_nexth_int_read_1_sqmuxa)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_nextl_int_read_0_sqmuxa)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_nextl_int_read_1_sqmuxa)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_len_int_read_0_sqmuxa)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_len_int_read_1_sqmuxa)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_hstarth_int_read_0_sqmuxa)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_hstarth_int_read_1_sqmuxa)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_hstartl_int_read_0_sqmuxa)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_hstartl_int_read_1_sqmuxa)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_cstart_int_read_0_sqmuxa)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_cstart_int_read_1_sqmuxa)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_stat_int_read_1_sqmuxa)		: 3
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_ctrl_int_read_0_sqmuxa)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_controller_wb_slave_0.dma_ctrl_int_read_1_sqmuxa)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_dma_controller.dma_ctrl_load)		: 31
 C(gnum_interface_block.sys_clk), CLR(GND), PRE(gnum_interface_block.rst_reg_i), CE(VCC)		: 6
 C(gnum_interface_block.sys_clk), CLR(GND), PRE(GND), CE(gnum_interface_block.cmp_l2p_dma_master.addr_fifo_din_1_sqmuxa)		: 30
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_l2p_dma_master.N_1363_i)		: 1
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.N_315_i)		: 1
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_l2p_dma_master.N_1378_i_i)		: 7
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.N_747_i)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.dma_ctrl_start_l2p_i)		: 1
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(N_5192_i)		: 1
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_l2p_dma_master.dma_length_cnt_0_sqmuxa)		: 39
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_l2p_dma_master.addr_fifo_valid)		: 64
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.N_4_0_i)		: 30
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_p2l_dma_master.N_1356_i)		: 1
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(N_5157_i)		: 1
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_p2l_dma_master.N_106_i)		: 1
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_p2l_dma_master.p2l_dma_current_state[3])		: 11
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_p2l_dma_master.N_65_i)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_p2l_dma_master.l2p_address_h_0_sqmuxa)		: 66
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_p2l_dma_master.N_39_i)		: 1
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_p2l_dma_master.next_item_next_l_o_1_sqmuxa)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_p2l_dma_master.next_item_next_h_o_1_sqmuxa)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_p2l_dma_master.next_item_len_o_1_sqmuxa)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_p2l_dma_master.next_item_host_addr_l_o_1_sqmuxa)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_p2l_dma_master.next_item_host_addr_h_o_1_sqmuxa)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_p2l_dma_master.next_item_carrier_addr_o_0_sqmuxa)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_p2l_dma_master.next_item_attrib_o_1_sqmuxa)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_p2l_dma_master.N_138)		: 62
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_p2l_dma_master.to_wb_fifo_valid)		: 94
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_p2l_dma_master.N_1350_i)		: 30
 C(gnum_interface_block.sys_clk), CLR(rst_n_a_i_c_i), PRE(GND), CE(VCC)		: 1
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.N_507_i)		: 1
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.N_511_i)		: 4
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_p2l_decode32.p2l_packet_start)		: 2
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.des_pd_valid)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.N_510_i)		: 30
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(N_11000)		: 1
 C(spec_clk), R(rst_n_a_i_c_i), S(GND), CE(VCC)		: 4
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(VCC)		: 165
 C(clk), R(N_5896), S(GND), CE(VCC)		: 1
 C(clk), CLR(GND), PRE(GND), CE(N_2608_i)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_l2p_dma_master.N_1361_i)		: 60
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(N_5109_i)		: 11
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_p2l_dma_master.N_1342_i)		: 11
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_l2p_dma_master.data_fifo_wr)		: 32
 C(gnum_interface_block.sys_clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_p2l_dma_master.N_39_i_i)		: 30
 C(clk), CLR(gnum_interface_block.rst_reg_i), PRE(GND), CE(gnum_interface_block.cmp_p2l_dma_master.p_wb_ack_cnt\.un1_p2l_dma_ack_i)		: 32
 C(clk), CLR(GND), PRE(GND), CE(N_1799_i)		: 8
 C(clk), R(GND), S(start_retrigger_block.retrig_period_counter.un1_value_1_i), CE(VCC)		: 6
 C(clk), R(start_retrigger_block.retrig_period_counter.un1_value_1_i), S(GND), CE(VCC)		: 26
 C(clk), R(GND), S(clks_rsts_mgment.inv_reset_i), CE(VCC)		: 2
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_5177_i)		: 32
 C(clk), R(one_hz_p), S(GND), CE(N_73_i)		: 32
 C(clk), R(N_2), S(GND), CE(N_2510_i)		: 32
 C(clk), R(N_5173_i), S(GND), CE(N_5174_i)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1814)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1817)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1818)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1819)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1812)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1813)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1820)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1815)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1810)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1811)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1816)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1803)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1802)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1804)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_185_1)		: 31
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1731)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1732)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1736)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1740)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1730)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1735)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1734)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1739)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1733)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1737)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1738)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1742)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1741)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1743)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1744)		: 32
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_1806)		: 10
 C(spec_clk), R(GND), S(rst_n_a_i_c_i), CE(VCC)		: 4
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(one_hz_p)		: 58
 C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(N_2608_i)		: 1

Total load per clock:
   tdc_clk125: 1
   spec_clk20: 27
   serdes_1_to_n_clk_pll_s2_diff|buf_pll_fb_clk_inferred_clock: 1
   serdes_1_to_n_clk_pll_s2_diff|buf_P_clk_inferred_clock: 1
   gnum_clk200: 2092

Mapping Summary:
Total  LUTs: 3407 (11%)

Mapper successful!
Process took 0h:00m:52s realtime, 0h:00m:52s cputime
# Fri Nov  4 11:36:04 2011

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