
rem Clean up the results directory
rmdir /S /Q results
mkdir results

rem Synthesize the VHDL Wrapper Files


echo 'Synthesizing example design with Synplify'
synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx


rem Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
copy ..\..\blk_mem_circ_buff_v6_4.ngc results\


rem  Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
copy ..\example_design\blk_mem_circ_buff_v6_4_top.ucf results\

cd results

echo 'Running ngdbuild'
ngdbuild -p xc6slx45t-fgg484-2 blk_mem_circ_buff_v6_4_top

echo 'Running map'
map blk_mem_circ_buff_v6_4_top -o mapped.ncd -pr i

echo 'Running par'
par mapped.ncd routed.ncd

echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed

echo 'Running design through bitgen'
bitgen -w routed

echo 'Running netgen to create gate level VHDL model'
netgen -ofmt vhdl -sim -tm blk_mem_circ_buff_v6_4_top -pcf mapped.pcf -w routed.ncd routed.vhd
