top_tdc Project Status
Project File:	svec-tdc-fmc.xise	Parser Errors:	No Errors
Module Name:	top_tdc	Implementation State:	New
Target Device:	xc6slx150t-3fgg900	Errors:
Product Version:	ISE 13.4	Warnings:
Design Goal:	Balanced	Routing Results:
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:		Final Timing Score:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report
Translation Report
Map Report
Place and Route Report
Power Report
Post-PAR Static Timing Report	Current	Wed Oct 2 16:35:12 2013
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated

Date Generated: 10/02/2013 - 19:12:58