top_tdc Project Status
Project File: | svec-tdc-fmc.xise | Parser Errors: | No Errors
Module Name: | top_tdc | Implementation State: | Programming File Generated

Target Device:

xc6slx150t-3fgg900

- Errors:

Product Version:

ISE 13.4

- Warnings:

Design Goal:</dif>

Balanced

- Routing Results:

All Signals Completely Routed

Design Strategy:</dif>

Xilinx Default (unlocked)

- Timing Constraints:

All Constraints Met

Environment:</dif>

System Settings

- Final Timing Score:

0 (Timing Report)

Device Utilization Summary | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Registers | 6,526 | 184,304 | 3% |
Number used as Flip Flops | 6,480 |  |  |
Number used as Latches | 0 |  |  |
Number used as Latch-thrus | 0 |  |  |
Number used as AND/OR logics | 46 |  |  |
Number of Slice LUTs | 9,248 | 92,152 | 10% |
Number used as logic | 8,960 | 92,152 | 9% |
Number using O6 output only | 5,957 |  |  |
Number using O5 output only | 409 |  |  |
Number using O5 and O6 | 2,594 |  |  |
Number used as ROM | 0 |  |  |
Number used as Memory | 37 | 21,680 | 1% |
Number used as Dual Port RAM | 0 |  |  |
Number used as Single Port RAM | 0 |  |  |
Number used as Shift Register | 37 |  |  |
Number using O6 output only | 11 |  |  |
Number using O5 output only | 0 |  |  |
Number using O5 and O6 | 26 |  |  |
Number used exclusively as route-thrus | 251 |  |  |
Number with same-slice register load | 176 |  |  |
Number with same-slice carry load | 75 |  |  |
Number with other load | 0 |  |  |
Number of occupied Slices | 3,647 | 23,038 | 15% |
Nummber of MUXCYs used | 2,420 | 46,076 | 5% |
Number of LUT Flip Flop pairs used | 10,494 |  |  |
Number with an unused Flip Flop | 4,755 | 10,494 | 45% |
Number with an unused LUT | 1,246 | 10,494 | 11% |
Number of fully used LUT-FF pairs | 4,493 | 10,494 | 42% |
Number of unique control sets | 208 |  |  |
Number of slice register sites lost to control set restrictions | 369 | 184,304 | 1% |
Number of bonded IOBs | 253 | 540 | 46% |
Number of LOCed IOBs | 253 | 253 | 100% |
IOB Flip Flops | 209 |  |  |
Number of RAMB16BWERs | 14 | 268 | 5% |
Number of RAMB8BWERs | 7 | 536 | 1% |
Number of BUFIO2/BUFIO2_2CLKs | 0 | 32 | 0% |
Number of BUFIO2FB/BUFIO2FB_2CLKs | 0 | 32 | 0% |
Number of BUFG/BUFGMUXs | 4 | 16 | 25% |
Number used as BUFGs | 4 |  |  |
Number used as BUFGMUX | 0 |  |  |
Number of DCM/DCM_CLKGENs | 0 | 12 | 0% |
Number of ILOGIC2/ISERDES2s | 138 | 586 | 23% |
Number used as ILOGIC2s | 138 |  |  |
Number used as ISERDES2s | 0 |  |  |
Number of IODELAY2/IODRP2/IODRP2_MCBs | 0 | 586 | 0% |
Number of OLOGIC2/OSERDES2s | 71 | 586 | 12% |
Number used as OLOGIC2s | 71 |  |  |
Number used as OSERDES2s | 0 |  |  |
Number of BSCANs | 0 | 4 | 0% |
Number of BUFHs | 0 | 384 | 0% |
Number of BUFPLLs | 0 | 8 | 0% |
Number of BUFPLL_MCBs | 0 | 4 | 0% |
Number of DSP48A1s | 0 | 180 | 0% |
Number of GTPA1_DUALs | 0 | 4 | 0% |
Number of ICAPs | 0 | 1 | 0% |
Number of MCBs | 0 | 4 | 0% |
Number of PCIE_A1s | 0 | 1 | 0% |
Number of PCILOGICSEs | 0 | 2 | 0% |
Number of PLL_ADVs | 1 | 6 | 16% |
Number of PMVs | 0 | 1 | 0% |
Number of STARTUPs | 0 | 1 | 0% |
Number of SUSPEND_SYNCs | 0 | 1 | 0% |
Average Fanout of Non-Clock Nets | 3.94 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | Thu Nov 28 15:35:36 2013 | 0 | 3314 Warnings (3303 new) | 131 Infos (131 new)
Translation Report | Current | Thu Nov 28 15:35:53 2013 |  |  |
Map Report | Current | Thu Nov 28 15:39:22 2013 | 0 | 1 Warning (0 new) | 279 Infos (0 new)
Place and Route Report | Current | Thu Nov 28 15:41:21 2013 | 0 | 6 Warnings (0 new) | 2 Infos (0 new)
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | Thu Nov 28 15:41:43 2013 | 0 | 0 | 4 Infos (0 new)
Bitgen Report | Current | Thu Nov 28 15:42:40 2013 | 0 | 0 | 1 Info (0 new)

Secondary Reports | [-]
Report Name | Status | Generated
WebTalk Report | Current | Thu Nov 28 15:42:40 2013
WebTalk Log File | Current | Thu Nov 28 15:42:48 2013

Date Generated: 01/27/2014 - 11:38:41