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-- Title          : Wishbone slave core for GN4124 core DMA controller 
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-- File           : async_regs.vhd
-- Author         : auto-generated by wbgen2 from async_regs.wb
-- Created        : Wed Oct  6 15:30:35 2010
-- Standard       : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE async_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity dma_controller_wb_slave is
  port (
    rst_n_i                                  : in     std_logic;
    wb_clk_i                                 : in     std_logic;
    wb_addr_i                                : in     std_logic_vector(3 downto 0);
    wb_data_i                                : in     std_logic_vector(31 downto 0);
    wb_data_o                                : out    std_logic_vector(31 downto 0);
    wb_cyc_i                                 : in     std_logic;
    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
    wb_stb_i                                 : in     std_logic;
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    clk_i                                    : in     std_logic;
-- Ports for asynchronous (clock: clk_i) std_logic_vector field: 'DMA engine control' in reg: 'DMACTRLR'
    dma_ctrl_o                               : out    std_logic_vector(31 downto 0);
    dma_ctrl_i                               : in     std_logic_vector(31 downto 0);
    dma_ctrl_load_o                          : out    std_logic;
-- Ports for asynchronous (clock: clk_i) std_logic_vector field: 'DMA engine status' in reg: 'DMASTATR'
    dma_stat_o                               : out    std_logic_vector(31 downto 0);
    dma_stat_i                               : in     std_logic_vector(31 downto 0);
    dma_stat_load_o                          : out    std_logic;
-- Ports for asynchronous (clock: clk_i) std_logic_vector field: 'DMA start address in the carrier' in reg: 'DMACSTARTR'
    dma_cstart_o                             : out    std_logic_vector(31 downto 0);
    dma_cstart_i                             : in     std_logic_vector(31 downto 0);
    dma_cstart_load_o                        : out    std_logic;
-- Ports for asynchronous (clock: clk_i) std_logic_vector field: 'DMA start address (low) in the host' in reg: 'DMAHSTARTLR'
    dma_hstartl_o                            : out    std_logic_vector(31 downto 0);
    dma_hstartl_i                            : in     std_logic_vector(31 downto 0);
    dma_hstartl_load_o                       : out    std_logic;
-- Ports for asynchronous (clock: clk_i) std_logic_vector field: 'DMA start address (high) in the host' in reg: 'DMAHSTARTHR'
    dma_hstarth_o                            : out    std_logic_vector(31 downto 0);
    dma_hstarth_i                            : in     std_logic_vector(31 downto 0);
    dma_hstarth_load_o                       : out    std_logic;
-- Ports for asynchronous (clock: clk_i) std_logic_vector field: 'DMA read length in bytes' in reg: 'DMALENR'
    dma_len_o                                : out    std_logic_vector(31 downto 0);
    dma_len_i                                : in     std_logic_vector(31 downto 0);
    dma_len_load_o                           : out    std_logic;
-- Ports for asynchronous (clock: clk_i) std_logic_vector field: 'Pointer (low) to next item in list' in reg: 'DMANEXTLR'
    dma_nextl_o                              : out    std_logic_vector(31 downto 0);
    dma_nextl_i                              : in     std_logic_vector(31 downto 0);
    dma_nextl_load_o                         : out    std_logic;
-- Ports for asynchronous (clock: clk_i) std_logic_vector field: 'Pointer (high) to next item in list' in reg: 'DMANEXTHR'
    dma_nexth_o                              : out    std_logic_vector(31 downto 0);
    dma_nexth_i                              : in     std_logic_vector(31 downto 0);
    dma_nexth_load_o                         : out    std_logic;
-- Ports for asynchronous (clock: clk_i) std_logic_vector field: 'DMA chain control' in reg: 'DMAATTRIBR'
    dma_attrib_o                             : out    std_logic_vector(31 downto 0);
    dma_attrib_i                             : in     std_logic_vector(31 downto 0);
    dma_attrib_load_o                        : out    std_logic
  );
end dma_controller_wb_slave;

architecture syn of dma_controller_wb_slave is

signal dma_ctrl_int_read                        : std_logic_vector(31 downto 0);
signal dma_ctrl_int_write                       : std_logic_vector(31 downto 0);
signal dma_ctrl_lw                              : std_logic      ;
signal dma_ctrl_lw_delay                        : std_logic      ;
signal dma_ctrl_lw_read_in_progress             : std_logic      ;
signal dma_ctrl_lw_s0                           : std_logic      ;
signal dma_ctrl_lw_s1                           : std_logic      ;
signal dma_ctrl_lw_s2                           : std_logic      ;
signal dma_ctrl_rwsel                           : std_logic      ;
signal dma_stat_int_read                        : std_logic_vector(31 downto 0);
signal dma_stat_int_write                       : std_logic_vector(31 downto 0);
signal dma_stat_lw                              : std_logic      ;
signal dma_stat_lw_delay                        : std_logic      ;
signal dma_stat_lw_read_in_progress             : std_logic      ;
signal dma_stat_lw_s0                           : std_logic      ;
signal dma_stat_lw_s1                           : std_logic      ;
signal dma_stat_lw_s2                           : std_logic      ;
signal dma_stat_rwsel                           : std_logic      ;
signal dma_cstart_int_read                      : std_logic_vector(31 downto 0);
signal dma_cstart_int_write                     : std_logic_vector(31 downto 0);
signal dma_cstart_lw                            : std_logic      ;
signal dma_cstart_lw_delay                      : std_logic      ;
signal dma_cstart_lw_read_in_progress           : std_logic      ;
signal dma_cstart_lw_s0                         : std_logic      ;
signal dma_cstart_lw_s1                         : std_logic      ;
signal dma_cstart_lw_s2                         : std_logic      ;
signal dma_cstart_rwsel                         : std_logic      ;
signal dma_hstartl_int_read                     : std_logic_vector(31 downto 0);
signal dma_hstartl_int_write                    : std_logic_vector(31 downto 0);
signal dma_hstartl_lw                           : std_logic      ;
signal dma_hstartl_lw_delay                     : std_logic      ;
signal dma_hstartl_lw_read_in_progress          : std_logic      ;
signal dma_hstartl_lw_s0                        : std_logic      ;
signal dma_hstartl_lw_s1                        : std_logic      ;
signal dma_hstartl_lw_s2                        : std_logic      ;
signal dma_hstartl_rwsel                        : std_logic      ;
signal dma_hstarth_int_read                     : std_logic_vector(31 downto 0);
signal dma_hstarth_int_write                    : std_logic_vector(31 downto 0);
signal dma_hstarth_lw                           : std_logic      ;
signal dma_hstarth_lw_delay                     : std_logic      ;
signal dma_hstarth_lw_read_in_progress          : std_logic      ;
signal dma_hstarth_lw_s0                        : std_logic      ;
signal dma_hstarth_lw_s1                        : std_logic      ;
signal dma_hstarth_lw_s2                        : std_logic      ;
signal dma_hstarth_rwsel                        : std_logic      ;
signal dma_len_int_read                         : std_logic_vector(31 downto 0);
signal dma_len_int_write                        : std_logic_vector(31 downto 0);
signal dma_len_lw                               : std_logic      ;
signal dma_len_lw_delay                         : std_logic      ;
signal dma_len_lw_read_in_progress              : std_logic      ;
signal dma_len_lw_s0                            : std_logic      ;
signal dma_len_lw_s1                            : std_logic      ;
signal dma_len_lw_s2                            : std_logic      ;
signal dma_len_rwsel                            : std_logic      ;
signal dma_nextl_int_read                       : std_logic_vector(31 downto 0);
signal dma_nextl_int_write                      : std_logic_vector(31 downto 0);
signal dma_nextl_lw                             : std_logic      ;
signal dma_nextl_lw_delay                       : std_logic      ;
signal dma_nextl_lw_read_in_progress            : std_logic      ;
signal dma_nextl_lw_s0                          : std_logic      ;
signal dma_nextl_lw_s1                          : std_logic      ;
signal dma_nextl_lw_s2                          : std_logic      ;
signal dma_nextl_rwsel                          : std_logic      ;
signal dma_nexth_int_read                       : std_logic_vector(31 downto 0);
signal dma_nexth_int_write                      : std_logic_vector(31 downto 0);
signal dma_nexth_lw                             : std_logic      ;
signal dma_nexth_lw_delay                       : std_logic      ;
signal dma_nexth_lw_read_in_progress            : std_logic      ;
signal dma_nexth_lw_s0                          : std_logic      ;
signal dma_nexth_lw_s1                          : std_logic      ;
signal dma_nexth_lw_s2                          : std_logic      ;
signal dma_nexth_rwsel                          : std_logic      ;
signal dma_attrib_int_read                      : std_logic_vector(31 downto 0);
signal dma_attrib_int_write                     : std_logic_vector(31 downto 0);
signal dma_attrib_lw                            : std_logic      ;
signal dma_attrib_lw_delay                      : std_logic      ;
signal dma_attrib_lw_read_in_progress           : std_logic      ;
signal dma_attrib_lw_s0                         : std_logic      ;
signal dma_attrib_lw_s1                         : std_logic      ;
signal dma_attrib_lw_s2                         : std_logic      ;
signal dma_attrib_rwsel                         : std_logic      ;
signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
signal rwaddr_reg                               : std_logic_vector(3 downto 0);
signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal bus_clock_int                            : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
  wrdata_reg <= wb_data_i;
  bwsel_reg <= wb_sel_i;
  bus_clock_int <= wb_clk_i;
  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
  allones <= (others => '1');
  allzeros <= (others => '0');
-- 
-- Main register bank access process.
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      ack_sreg <= "0000000000";
      ack_in_progress <= '0';
      rddata_reg <= "00000000000000000000000000000000";
      dma_ctrl_lw <= '0';
      dma_ctrl_lw_delay <= '0';
      dma_ctrl_lw_read_in_progress <= '0';
      dma_ctrl_rwsel <= '0';
      dma_ctrl_int_write <= "00000000000000000000000000000000";
      dma_stat_lw <= '0';
      dma_stat_lw_delay <= '0';
      dma_stat_lw_read_in_progress <= '0';
      dma_stat_rwsel <= '0';
      dma_stat_int_write <= "00000000000000000000000000000000";
      dma_cstart_lw <= '0';
      dma_cstart_lw_delay <= '0';
      dma_cstart_lw_read_in_progress <= '0';
      dma_cstart_rwsel <= '0';
      dma_cstart_int_write <= "00000000000000000000000000000000";
      dma_hstartl_lw <= '0';
      dma_hstartl_lw_delay <= '0';
      dma_hstartl_lw_read_in_progress <= '0';
      dma_hstartl_rwsel <= '0';
      dma_hstartl_int_write <= "00000000000000000000000000000000";
      dma_hstarth_lw <= '0';
      dma_hstarth_lw_delay <= '0';
      dma_hstarth_lw_read_in_progress <= '0';
      dma_hstarth_rwsel <= '0';
      dma_hstarth_int_write <= "00000000000000000000000000000000";
      dma_len_lw <= '0';
      dma_len_lw_delay <= '0';
      dma_len_lw_read_in_progress <= '0';
      dma_len_rwsel <= '0';
      dma_len_int_write <= "00000000000000000000000000000000";
      dma_nextl_lw <= '0';
      dma_nextl_lw_delay <= '0';
      dma_nextl_lw_read_in_progress <= '0';
      dma_nextl_rwsel <= '0';
      dma_nextl_int_write <= "00000000000000000000000000000000";
      dma_nexth_lw <= '0';
      dma_nexth_lw_delay <= '0';
      dma_nexth_lw_read_in_progress <= '0';
      dma_nexth_rwsel <= '0';
      dma_nexth_int_write <= "00000000000000000000000000000000";
      dma_attrib_lw <= '0';
      dma_attrib_lw_delay <= '0';
      dma_attrib_lw_read_in_progress <= '0';
      dma_attrib_rwsel <= '0';
      dma_attrib_int_write <= "00000000000000000000000000000000";
    elsif rising_edge(wb_clk_i) then
-- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ack_sreg(9) <= '0';
      if (ack_in_progress = '1') then
        if (ack_sreg(0) = '1') then
          ack_in_progress <= '0';
        else
          dma_ctrl_lw <= dma_ctrl_lw_delay;
          dma_ctrl_lw_delay <= '0';
          if ((ack_sreg(1) = '1') and (dma_ctrl_lw_read_in_progress = '1')) then
            dma_ctrl_lw_read_in_progress <= '0';
            rddata_reg(31 downto 0) <= dma_ctrl_int_read;
          end if;
          dma_stat_lw <= dma_stat_lw_delay;
          dma_stat_lw_delay <= '0';
          if ((ack_sreg(1) = '1') and (dma_stat_lw_read_in_progress = '1')) then
            dma_stat_lw_read_in_progress <= '0';
            rddata_reg(31 downto 0) <= dma_stat_int_read;
          end if;
          dma_cstart_lw <= dma_cstart_lw_delay;
          dma_cstart_lw_delay <= '0';
          if ((ack_sreg(1) = '1') and (dma_cstart_lw_read_in_progress = '1')) then
            dma_cstart_lw_read_in_progress <= '0';
            rddata_reg(31 downto 0) <= dma_cstart_int_read;
          end if;
          dma_hstartl_lw <= dma_hstartl_lw_delay;
          dma_hstartl_lw_delay <= '0';
          if ((ack_sreg(1) = '1') and (dma_hstartl_lw_read_in_progress = '1')) then
            dma_hstartl_lw_read_in_progress <= '0';
            rddata_reg(31 downto 0) <= dma_hstartl_int_read;
          end if;
          dma_hstarth_lw <= dma_hstarth_lw_delay;
          dma_hstarth_lw_delay <= '0';
          if ((ack_sreg(1) = '1') and (dma_hstarth_lw_read_in_progress = '1')) then
            dma_hstarth_lw_read_in_progress <= '0';
            rddata_reg(31 downto 0) <= dma_hstarth_int_read;
          end if;
          dma_len_lw <= dma_len_lw_delay;
          dma_len_lw_delay <= '0';
          if ((ack_sreg(1) = '1') and (dma_len_lw_read_in_progress = '1')) then
            dma_len_lw_read_in_progress <= '0';
            rddata_reg(31 downto 0) <= dma_len_int_read;
          end if;
          dma_nextl_lw <= dma_nextl_lw_delay;
          dma_nextl_lw_delay <= '0';
          if ((ack_sreg(1) = '1') and (dma_nextl_lw_read_in_progress = '1')) then
            dma_nextl_lw_read_in_progress <= '0';
            rddata_reg(31 downto 0) <= dma_nextl_int_read;
          end if;
          dma_nexth_lw <= dma_nexth_lw_delay;
          dma_nexth_lw_delay <= '0';
          if ((ack_sreg(1) = '1') and (dma_nexth_lw_read_in_progress = '1')) then
            dma_nexth_lw_read_in_progress <= '0';
            rddata_reg(31 downto 0) <= dma_nexth_int_read;
          end if;
          dma_attrib_lw <= dma_attrib_lw_delay;
          dma_attrib_lw_delay <= '0';
          if ((ack_sreg(1) = '1') and (dma_attrib_lw_read_in_progress = '1')) then
            dma_attrib_lw_read_in_progress <= '0';
            rddata_reg(31 downto 0) <= dma_attrib_int_read;
          end if;
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
          case rwaddr_reg(3 downto 0) is
          when "0000" => 
            if (wb_we_i = '1') then
              dma_ctrl_int_write <= wrdata_reg(31 downto 0);
              dma_ctrl_lw <= '1';
              dma_ctrl_lw_delay <= '1';
              dma_ctrl_lw_read_in_progress <= '0';
              dma_ctrl_rwsel <= '1';
            else
              dma_ctrl_lw <= '1';
              dma_ctrl_lw_delay <= '1';
              dma_ctrl_lw_read_in_progress <= '1';
              dma_ctrl_rwsel <= '0';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0001" => 
            if (wb_we_i = '1') then
              dma_stat_int_write <= wrdata_reg(31 downto 0);
              dma_stat_lw <= '1';
              dma_stat_lw_delay <= '1';
              dma_stat_lw_read_in_progress <= '0';
              dma_stat_rwsel <= '1';
            else
              dma_stat_lw <= '1';
              dma_stat_lw_delay <= '1';
              dma_stat_lw_read_in_progress <= '1';
              dma_stat_rwsel <= '0';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0010" => 
            if (wb_we_i = '1') then
              dma_cstart_int_write <= wrdata_reg(31 downto 0);
              dma_cstart_lw <= '1';
              dma_cstart_lw_delay <= '1';
              dma_cstart_lw_read_in_progress <= '0';
              dma_cstart_rwsel <= '1';
            else
              dma_cstart_lw <= '1';
              dma_cstart_lw_delay <= '1';
              dma_cstart_lw_read_in_progress <= '1';
              dma_cstart_rwsel <= '0';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0011" => 
            if (wb_we_i = '1') then
              dma_hstartl_int_write <= wrdata_reg(31 downto 0);
              dma_hstartl_lw <= '1';
              dma_hstartl_lw_delay <= '1';
              dma_hstartl_lw_read_in_progress <= '0';
              dma_hstartl_rwsel <= '1';
            else
              dma_hstartl_lw <= '1';
              dma_hstartl_lw_delay <= '1';
              dma_hstartl_lw_read_in_progress <= '1';
              dma_hstartl_rwsel <= '0';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0100" => 
            if (wb_we_i = '1') then
              dma_hstarth_int_write <= wrdata_reg(31 downto 0);
              dma_hstarth_lw <= '1';
              dma_hstarth_lw_delay <= '1';
              dma_hstarth_lw_read_in_progress <= '0';
              dma_hstarth_rwsel <= '1';
            else
              dma_hstarth_lw <= '1';
              dma_hstarth_lw_delay <= '1';
              dma_hstarth_lw_read_in_progress <= '1';
              dma_hstarth_rwsel <= '0';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0101" => 
            if (wb_we_i = '1') then
              dma_len_int_write <= wrdata_reg(31 downto 0);
              dma_len_lw <= '1';
              dma_len_lw_delay <= '1';
              dma_len_lw_read_in_progress <= '0';
              dma_len_rwsel <= '1';
            else
              dma_len_lw <= '1';
              dma_len_lw_delay <= '1';
              dma_len_lw_read_in_progress <= '1';
              dma_len_rwsel <= '0';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0110" => 
            if (wb_we_i = '1') then
              dma_nextl_int_write <= wrdata_reg(31 downto 0);
              dma_nextl_lw <= '1';
              dma_nextl_lw_delay <= '1';
              dma_nextl_lw_read_in_progress <= '0';
              dma_nextl_rwsel <= '1';
            else
              dma_nextl_lw <= '1';
              dma_nextl_lw_delay <= '1';
              dma_nextl_lw_read_in_progress <= '1';
              dma_nextl_rwsel <= '0';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0111" => 
            if (wb_we_i = '1') then
              dma_nexth_int_write <= wrdata_reg(31 downto 0);
              dma_nexth_lw <= '1';
              dma_nexth_lw_delay <= '1';
              dma_nexth_lw_read_in_progress <= '0';
              dma_nexth_rwsel <= '1';
            else
              dma_nexth_lw <= '1';
              dma_nexth_lw_delay <= '1';
              dma_nexth_lw_read_in_progress <= '1';
              dma_nexth_rwsel <= '0';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "1000" => 
            if (wb_we_i = '1') then
              dma_attrib_int_write <= wrdata_reg(31 downto 0);
              dma_attrib_lw <= '1';
              dma_attrib_lw_delay <= '1';
              dma_attrib_lw_read_in_progress <= '0';
              dma_attrib_rwsel <= '1';
            else
              dma_attrib_lw <= '1';
              dma_attrib_lw_delay <= '1';
              dma_attrib_lw_read_in_progress <= '1';
              dma_attrib_rwsel <= '0';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when others =>
-- prevent the slave from hanging the bus on invalid address
            ack_in_progress <= '1';
            ack_sreg(0) <= '1';
          end case;
        end if;
      end if;
    end if;
  end process;
  
  
-- Drive the data output bus
  wb_data_o <= rddata_reg;
-- DMA engine control
-- asynchronous std_logic_vector register : DMA engine control (type RW/WO, clk_i <-> wb_clk_i)
  process (clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dma_ctrl_lw_s0 <= '0';
      dma_ctrl_lw_s1 <= '0';
      dma_ctrl_lw_s2 <= '0';
      dma_ctrl_o <= "00000000000000000000000000000000";
      dma_ctrl_load_o <= '0';
      dma_ctrl_int_read <= "00000000000000000000000000000000";
    elsif rising_edge(clk_i) then
      dma_ctrl_lw_s0 <= dma_ctrl_lw;
      dma_ctrl_lw_s1 <= dma_ctrl_lw_s0;
      dma_ctrl_lw_s2 <= dma_ctrl_lw_s1;
      if ((dma_ctrl_lw_s2 = '0') and (dma_ctrl_lw_s1 = '1')) then
        if (dma_ctrl_rwsel = '1') then
          dma_ctrl_o <= dma_ctrl_int_write;
          dma_ctrl_load_o <= '1';
        else
          dma_ctrl_load_o <= '0';
          dma_ctrl_int_read <= dma_ctrl_i;
        end if;
      else
        dma_ctrl_load_o <= '0';
      end if;
    end if;
  end process;
  
  
-- DMA engine status
-- asynchronous std_logic_vector register : DMA engine status (type RW/WO, clk_i <-> wb_clk_i)
  process (clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dma_stat_lw_s0 <= '0';
      dma_stat_lw_s1 <= '0';
      dma_stat_lw_s2 <= '0';
      dma_stat_o <= "00000000000000000000000000000000";
      dma_stat_load_o <= '0';
      dma_stat_int_read <= "00000000000000000000000000000000";
    elsif rising_edge(clk_i) then
      dma_stat_lw_s0 <= dma_stat_lw;
      dma_stat_lw_s1 <= dma_stat_lw_s0;
      dma_stat_lw_s2 <= dma_stat_lw_s1;
      if ((dma_stat_lw_s2 = '0') and (dma_stat_lw_s1 = '1')) then
        if (dma_stat_rwsel = '1') then
          dma_stat_o <= dma_stat_int_write;
          dma_stat_load_o <= '1';
        else
          dma_stat_load_o <= '0';
          dma_stat_int_read <= dma_stat_i;
        end if;
      else
        dma_stat_load_o <= '0';
      end if;
    end if;
  end process;
  
  
-- DMA start address in the carrier
-- asynchronous std_logic_vector register : DMA start address in the carrier (type RW/WO, clk_i <-> wb_clk_i)
  process (clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dma_cstart_lw_s0 <= '0';
      dma_cstart_lw_s1 <= '0';
      dma_cstart_lw_s2 <= '0';
      dma_cstart_o <= "00000000000000000000000000000000";
      dma_cstart_load_o <= '0';
      dma_cstart_int_read <= "00000000000000000000000000000000";
    elsif rising_edge(clk_i) then
      dma_cstart_lw_s0 <= dma_cstart_lw;
      dma_cstart_lw_s1 <= dma_cstart_lw_s0;
      dma_cstart_lw_s2 <= dma_cstart_lw_s1;
      if ((dma_cstart_lw_s2 = '0') and (dma_cstart_lw_s1 = '1')) then
        if (dma_cstart_rwsel = '1') then
          dma_cstart_o <= dma_cstart_int_write;
          dma_cstart_load_o <= '1';
        else
          dma_cstart_load_o <= '0';
          dma_cstart_int_read <= dma_cstart_i;
        end if;
      else
        dma_cstart_load_o <= '0';
      end if;
    end if;
  end process;
  
  
-- DMA start address (low) in the host
-- asynchronous std_logic_vector register : DMA start address (low) in the host (type RW/WO, clk_i <-> wb_clk_i)
  process (clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dma_hstartl_lw_s0 <= '0';
      dma_hstartl_lw_s1 <= '0';
      dma_hstartl_lw_s2 <= '0';
      dma_hstartl_o <= "00000000000000000000000000000000";
      dma_hstartl_load_o <= '0';
      dma_hstartl_int_read <= "00000000000000000000000000000000";
    elsif rising_edge(clk_i) then
      dma_hstartl_lw_s0 <= dma_hstartl_lw;
      dma_hstartl_lw_s1 <= dma_hstartl_lw_s0;
      dma_hstartl_lw_s2 <= dma_hstartl_lw_s1;
      if ((dma_hstartl_lw_s2 = '0') and (dma_hstartl_lw_s1 = '1')) then
        if (dma_hstartl_rwsel = '1') then
          dma_hstartl_o <= dma_hstartl_int_write;
          dma_hstartl_load_o <= '1';
        else
          dma_hstartl_load_o <= '0';
          dma_hstartl_int_read <= dma_hstartl_i;
        end if;
      else
        dma_hstartl_load_o <= '0';
      end if;
    end if;
  end process;
  
  
-- DMA start address (high) in the host
-- asynchronous std_logic_vector register : DMA start address (high) in the host (type RW/WO, clk_i <-> wb_clk_i)
  process (clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dma_hstarth_lw_s0 <= '0';
      dma_hstarth_lw_s1 <= '0';
      dma_hstarth_lw_s2 <= '0';
      dma_hstarth_o <= "00000000000000000000000000000000";
      dma_hstarth_load_o <= '0';
      dma_hstarth_int_read <= "00000000000000000000000000000000";
    elsif rising_edge(clk_i) then
      dma_hstarth_lw_s0 <= dma_hstarth_lw;
      dma_hstarth_lw_s1 <= dma_hstarth_lw_s0;
      dma_hstarth_lw_s2 <= dma_hstarth_lw_s1;
      if ((dma_hstarth_lw_s2 = '0') and (dma_hstarth_lw_s1 = '1')) then
        if (dma_hstarth_rwsel = '1') then
          dma_hstarth_o <= dma_hstarth_int_write;
          dma_hstarth_load_o <= '1';
        else
          dma_hstarth_load_o <= '0';
          dma_hstarth_int_read <= dma_hstarth_i;
        end if;
      else
        dma_hstarth_load_o <= '0';
      end if;
    end if;
  end process;
  
  
-- DMA read length in bytes
-- asynchronous std_logic_vector register : DMA read length in bytes (type RW/WO, clk_i <-> wb_clk_i)
  process (clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dma_len_lw_s0 <= '0';
      dma_len_lw_s1 <= '0';
      dma_len_lw_s2 <= '0';
      dma_len_o <= "00000000000000000000000000000000";
      dma_len_load_o <= '0';
      dma_len_int_read <= "00000000000000000000000000000000";
    elsif rising_edge(clk_i) then
      dma_len_lw_s0 <= dma_len_lw;
      dma_len_lw_s1 <= dma_len_lw_s0;
      dma_len_lw_s2 <= dma_len_lw_s1;
      if ((dma_len_lw_s2 = '0') and (dma_len_lw_s1 = '1')) then
        if (dma_len_rwsel = '1') then
          dma_len_o <= dma_len_int_write;
          dma_len_load_o <= '1';
        else
          dma_len_load_o <= '0';
          dma_len_int_read <= dma_len_i;
        end if;
      else
        dma_len_load_o <= '0';
      end if;
    end if;
  end process;
  
  
-- Pointer (low) to next item in list
-- asynchronous std_logic_vector register : Pointer (low) to next item in list (type RW/WO, clk_i <-> wb_clk_i)
  process (clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dma_nextl_lw_s0 <= '0';
      dma_nextl_lw_s1 <= '0';
      dma_nextl_lw_s2 <= '0';
      dma_nextl_o <= "00000000000000000000000000000000";
      dma_nextl_load_o <= '0';
      dma_nextl_int_read <= "00000000000000000000000000000000";
    elsif rising_edge(clk_i) then
      dma_nextl_lw_s0 <= dma_nextl_lw;
      dma_nextl_lw_s1 <= dma_nextl_lw_s0;
      dma_nextl_lw_s2 <= dma_nextl_lw_s1;
      if ((dma_nextl_lw_s2 = '0') and (dma_nextl_lw_s1 = '1')) then
        if (dma_nextl_rwsel = '1') then
          dma_nextl_o <= dma_nextl_int_write;
          dma_nextl_load_o <= '1';
        else
          dma_nextl_load_o <= '0';
          dma_nextl_int_read <= dma_nextl_i;
        end if;
      else
        dma_nextl_load_o <= '0';
      end if;
    end if;
  end process;
  
  
-- Pointer (high) to next item in list
-- asynchronous std_logic_vector register : Pointer (high) to next item in list (type RW/WO, clk_i <-> wb_clk_i)
  process (clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dma_nexth_lw_s0 <= '0';
      dma_nexth_lw_s1 <= '0';
      dma_nexth_lw_s2 <= '0';
      dma_nexth_o <= "00000000000000000000000000000000";
      dma_nexth_load_o <= '0';
      dma_nexth_int_read <= "00000000000000000000000000000000";
    elsif rising_edge(clk_i) then
      dma_nexth_lw_s0 <= dma_nexth_lw;
      dma_nexth_lw_s1 <= dma_nexth_lw_s0;
      dma_nexth_lw_s2 <= dma_nexth_lw_s1;
      if ((dma_nexth_lw_s2 = '0') and (dma_nexth_lw_s1 = '1')) then
        if (dma_nexth_rwsel = '1') then
          dma_nexth_o <= dma_nexth_int_write;
          dma_nexth_load_o <= '1';
        else
          dma_nexth_load_o <= '0';
          dma_nexth_int_read <= dma_nexth_i;
        end if;
      else
        dma_nexth_load_o <= '0';
      end if;
    end if;
  end process;
  
  
-- DMA chain control
-- asynchronous std_logic_vector register : DMA chain control (type RW/WO, clk_i <-> wb_clk_i)
  process (clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dma_attrib_lw_s0 <= '0';
      dma_attrib_lw_s1 <= '0';
      dma_attrib_lw_s2 <= '0';
      dma_attrib_o <= "00000000000000000000000000000000";
      dma_attrib_load_o <= '0';
      dma_attrib_int_read <= "00000000000000000000000000000000";
    elsif rising_edge(clk_i) then
      dma_attrib_lw_s0 <= dma_attrib_lw;
      dma_attrib_lw_s1 <= dma_attrib_lw_s0;
      dma_attrib_lw_s2 <= dma_attrib_lw_s1;
      if ((dma_attrib_lw_s2 = '0') and (dma_attrib_lw_s1 = '1')) then
        if (dma_attrib_rwsel = '1') then
          dma_attrib_o <= dma_attrib_int_write;
          dma_attrib_load_o <= '1';
        else
          dma_attrib_load_o <= '0';
          dma_attrib_int_read <= dma_attrib_i;
        end if;
      else
        dma_attrib_load_o <= '0';
      end if;
    end if;
  end process;
  
  
  rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
  wb_ack_o <= ack_sreg(0);
end syn;
