------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /   Vendor: Xilinx
-- \   \   \/    Version: 1.0
--  \   \        Filename: clock_generator_ddr_s2_diff.vhd
--  /   /        Date Last Modified:  November 5 2009
-- /___/   /\    Date Created: August 1 2008
-- \   \  /  \
--  \___\/\___\
--
--Device:       Spartan 6
--Purpose:      BUFIO2 Based DDR clock generator. Takes in a differential clock
--              and instantiates two sets of 2 BUFIO2s, one for each half bank
--
--Reference:
--
--Revision History:
--    Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
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------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

library unisim;
use unisim.vcomponents.all;

entity clock_generator_ddr_s2_diff is
  generic (
    S         : integer := 2;            -- Parameter to set the serdes factor
    DIFF_TERM : boolean := false) ;      -- Enable or disable internal differential termination
  port (
    clkin_p, clkin_n : in  std_logic;    -- differential clock input
    ioclkap          : out std_logic;    -- A P ioclock from BUFIO2
    ioclkan          : out std_logic;    -- A N ioclock from BUFIO2
    serdesstrobea    : out std_logic;    -- A serdes strobe from BUFIO2
    ioclkbp          : out std_logic;    -- B P ioclock from BUFIO2 - leave open if not required
    ioclkbn          : out std_logic;    -- B N ioclock from BUFIO2 - leave open if not required
    serdesstrobeb    : out std_logic;    -- B serdes strobe from BUFIO2 - leave open if not required
    gclk             : out std_logic) ;  -- global clock output from BUFIO2
end clock_generator_ddr_s2_diff;

architecture arch_clock_generator_ddr_s2_diff of clock_generator_ddr_s2_diff is

  signal clkint       : std_logic;      --
  signal gclk_int     : std_logic;      --
  signal freqgen_in_p : std_logic;      --
  signal tx_bufio2_x1 : std_logic;      --

begin

  gclk <= gclk_int;

  iob_freqgen_in : IBUFGDS generic map(
    DIFF_TERM => DIFF_TERM)
    port map (
      I  => clkin_p,
      IB => clkin_n,
      O  => freqgen_in_p);

  bufio2_inst1 : BUFIO2 generic map(
    DIVIDE        => S,                 -- The DIVCLK divider divide-by value; default 1
    I_INVERT      => false,             --
    DIVIDE_BYPASS => false,             --
    USE_DOUBLER   => true)              --
    port map (
      I            => freqgen_in_p,     -- Input source clock 0 degrees
      IOCLK        => ioclkap,          -- Output Clock for IO
      DIVCLK       => tx_bufio2_x1,     -- Output Divided Clock
      SERDESSTROBE => serdesstrobea) ;  -- Output SERDES strobe (Clock Enable)

  bufio2_inst2 : BUFIO2 generic map(
    I_INVERT      => true,              --
    DIVIDE_BYPASS => false,             --
    USE_DOUBLER   => false)             --
    port map (
      I            => freqgen_in_p,     -- N_clk input from IDELAY
      IOCLK        => ioclkan,          -- Output Clock
      DIVCLK       => open,             -- Output Divided Clock
      SERDESSTROBE => open) ;           -- Output SERDES strobe (Clock Enable)

  bufio2_inst3 : BUFIO2 generic map(
    DIVIDE        => S,                 -- The DIVCLK divider divide-by value; default 1
    I_INVERT      => false,             --
    DIVIDE_BYPASS => false,             --
    USE_DOUBLER   => true)              --
    port map (
      I            => freqgen_in_p,     -- Input source clock 0 degrees
      IOCLK        => ioclkbp,          -- Output Clock for IO
      DIVCLK       => open,             -- Output Divided Clock
      SERDESSTROBE => serdesstrobeb) ;  -- Output SERDES strobe (Clock Enable)

  bufio2_inst4 : BUFIO2 generic map(
    I_INVERT      => true,              --
    DIVIDE_BYPASS => false,             --
    USE_DOUBLER   => false)             --
    port map (
      I            => freqgen_in_p,     -- N_clk input from IDELAY
      IOCLK        => ioclkbn,          -- Output Clock
      DIVCLK       => open,             -- Output Divided Clock
      SERDESSTROBE => open) ;           -- Output SERDES strobe (Clock Enable)

  bufg_tx : BUFG port map (I => tx_bufio2_x1, O => gclk_int);

end arch_clock_generator_ddr_s2_diff;
