`

    #Build: Synplify Pro D-2010.03, Build 093R, Feb 19 2010
    #install: /afs/cern.ch/project/parc/elec/synplify/D-2010.03
    #OS: Linux
    #Hostname: lxparc47.cern.ch

    #Implementation: test_tdc_pll

    #Fri Jul 15 19:30:52 2011

    $ Start of Compile
    #Fri Jul 15 19:30:52 2011

    Synopsys VHDL Compiler, version comp500rc, Build 027R, built Feb 19 2010
    Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved

    @N:CD720 : std.vhd(123) | Setting time resolution to ns
    @N: : top_test_pll.vhd(29) | Top entity is set to top_tdc.
    VHDL syntax check successful!
    @N:CD630 : top_test_pll.vhd(29) | Synthesizing work.top_tdc.rtl
    @W:CD638 : top_test_pll.vhd(179) | Signal pulse_delay is undriven
    @W:CD638 : top_test_pll.vhd(180) | Signal clock_period is undriven
    @W:CD638 : top_test_pll.vhd(190) | Signal tdc_led_trig1 is undriven
    @W:CD638 : top_test_pll.vhd(191) | Signal tdc_led_trig2 is undriven
    @W:CD638 : top_test_pll.vhd(192) | Signal tdc_led_trig3 is undriven
    @W:CD638 : top_test_pll.vhd(193) | Signal tdc_led_trig4 is undriven
    @W:CD638 : top_test_pll.vhd(194) | Signal tdc_led_trig5 is undriven
    @W:CD638 : top_test_pll.vhd(196) | Signal acam_errflag_p is undriven
    @W:CD638 : top_test_pll.vhd(197) | Signal acam_intflag_p is undriven
    @W:CD638 : top_test_pll.vhd(198) | Signal acam_start01 is undriven
    @W:CD638 : top_test_pll.vhd(199) | Signal acam_timestamp is undriven
    @W:CD638 : top_test_pll.vhd(200) | Signal acam_timestamp_valid is undriven
    @W:CD638 : top_test_pll.vhd(201) | Signal full_timestamp is undriven
    @W:CD638 : top_test_pll.vhd(202) | Signal full_timestamp_valid is undriven
    @W:CD638 : top_test_pll.vhd(203) | Signal one_hz_p is undriven
    @W:CD638 : top_test_pll.vhd(205) | Signal start_nb_offset is undriven
    @W:CD638 : top_test_pll.vhd(206) | Signal start_timer_reg is undriven
    @W:CD638 : top_test_pll.vhd(207) | Signal utc_current_time is undriven
    @W:CD638 : top_test_pll.vhd(209) | Signal acm_adr is undriven
    @W:CD638 : top_test_pll.vhd(210) | Signal acm_cyc is undriven
    @W:CD638 : top_test_pll.vhd(211) | Signal acm_stb is undriven
    @W:CD638 : top_test_pll.vhd(212) | Signal acm_we is undriven
    @W:CD638 : top_test_pll.vhd(213) | Signal acm_ack is undriven
    @W:CD638 : top_test_pll.vhd(214) | Signal acm_dat_r is undriven
    @W:CD638 : top_test_pll.vhd(215) | Signal acm_dat_w is undriven
    @W:CD638 : top_test_pll.vhd(217) | Signal dma_irq is undriven
    @W:CD638 : top_test_pll.vhd(218) | Signal irq_p is undriven
    @W:CD638 : top_test_pll.vhd(220) | Signal csr_clk is undriven
    @W:CD638 : top_test_pll.vhd(221) | Signal csr_adr is undriven
    @W:CD638 : top_test_pll.vhd(222) | Signal csr_dat_r is undriven
    @W:CD638 : top_test_pll.vhd(223) | Signal csr_sel is undriven
    @W:CD638 : top_test_pll.vhd(224) | Signal csr_stb is undriven
    @W:CD638 : top_test_pll.vhd(225) | Signal csr_we is undriven
    @W:CD638 : top_test_pll.vhd(226) | Signal csr_cyc is undriven
    @W:CD638 : top_test_pll.vhd(227) | Signal csr_dat_w is undriven
    @W:CD638 : top_test_pll.vhd(228) | Signal csr_ack is undriven
    @W:CD638 : top_test_pll.vhd(230) | Signal dma_clk is undriven
    @W:CD638 : top_test_pll.vhd(231) | Signal dma_adr is undriven
    @W:CD638 : top_test_pll.vhd(232) | Signal dma_dat_i is undriven
    @W:CD638 : top_test_pll.vhd(233) | Signal dma_sel is undriven
    @W:CD638 : top_test_pll.vhd(234) | Signal dma_stb is undriven
    @W:CD638 : top_test_pll.vhd(235) | Signal dma_we is undriven
    @W:CD638 : top_test_pll.vhd(236) | Signal dma_cyc is undriven
    @W:CD638 : top_test_pll.vhd(237) | Signal dma_dat_o is undriven
    @W:CD638 : top_test_pll.vhd(238) | Signal dma_ack is undriven
    @W:CD638 : top_test_pll.vhd(239) | Signal dma_stall is undriven
    @N:CD630 : free_counter.vhd(15) | Synthesizing work.free_counter.rtl
    Post processing for work.free_counter.rtl
    @N:CD630 : clk_rst_managr.vhd(32) | Synthesizing work.clk_rst_managr.rtl
    @N:CD231 : clk_rst_managr.vhd(83) | Using onehot encoding for type t_pll_init_st (start="10000")
    @N:CD630 : unisim.vhd(6077) | Synthesizing unisim.ibufds.syn_black_box
    Post processing for unisim.ibufds.syn_black_box
    @N:CD630 : unisim.vhd(6266) | Synthesizing unisim.ibufg.syn_black_box
    Post processing for unisim.ibufg.syn_black_box
    @W:CD604 : clk_rst_managr.vhd(335) | OTHERS clause is not synthesized
    @W:CD638 : clk_rst_managr.vhd(173) | Signal acam_refclk_buf is undriven
    @N:CD630 : incr_counter.vhd(16) | Synthesizing work.incr_counter.rtl
    Post processing for work.incr_counter.rtl
    @N:CD630 : unisim.vhd(428) | Synthesizing unisim.bufg.syn_black_box
    Post processing for unisim.bufg.syn_black_box
    Post processing for work.clk_rst_managr.rtl
    @W:CL240 : clk_rst_managr.vhd(50) | pll_dac_sync_o is not assigned a value (floating) - a simulation mismatch is possible
    Post processing for work.top_tdc.rtl
    @W:CL240 : top_test_pll.vhd(95) | wr_n_o is not assigned a value (floating) - a simulation mismatch is possible
    @W:CL240 : top_test_pll.vhd(94) | rd_n_o is not assigned a value (floating) - a simulation mismatch is possible
    @W:CL240 : top_test_pll.vhd(93) | oe_n_o is not assigned a value (floating) - a simulation mismatch is possible
    @W:CL240 : top_test_pll.vhd(92) | cs_n_o is not assigned a value (floating) - a simulation mismatch is possible
    @W:CL240 : top_test_pll.vhd(91) | address_o is not assigned a value (floating) - a simulation mismatch is possible
    @W:CL240 : top_test_pll.vhd(82) | stop_dis_o is not assigned a value (floating) - a simulation mismatch is possible
    @W:CL240 : top_test_pll.vhd(81) | start_from_fpga_o is not assigned a value (floating) - a simulation mismatch is possible
    @W:CL240 : top_test_pll.vhd(80) | start_dis_o is not assigned a value (floating) - a simulation mismatch is possible
    @W:CL240 : top_test_pll.vhd(60) | spare_o is not assigned a value (floating) - a simulation mismatch is possible
    @W:CL240 : top_test_pll.vhd(59) | irq_p_o is not assigned a value (floating) - a simulation mismatch is possible
    @W:CL240 : top_test_pll.vhd(54) | l2p_edb_o is not assigned a value (floating) - a simulation mismatch is possible
    @W:CL240 : top_test_pll.vhd(53) | l2p_valid_o is not assigned a value (floating) - a simulation mismatch is possible
    @W:CL240 : top_test_pll.vhd(52) | l2p_dframe_o is not assigned a value (floating) - a simulation mismatch is possible
    @W:CL240 : top_test_pll.vhd(51) | l2p_data_o is not assigned a value (floating) - a simulation mismatch is possible
    @W:CL240 : top_test_pll.vhd(50) | l2p_clk_n_o is not assigned a value (floating) - a simulation mismatch is possible
    @W:CL240 : top_test_pll.vhd(49) | l2p_clk_p_o is not assigned a value (floating) - a simulation mismatch is possible
    @W:CL240 : top_test_pll.vhd(46) | rx_error_o is not assigned a value (floating) - a simulation mismatch is possible
    @W:CL240 : top_test_pll.vhd(45) | p_wr_rdy_o is not assigned a value (floating) - a simulation mismatch is possible
    @W:CL240 : top_test_pll.vhd(43) | p2l_rdy_o is not assigned a value (floating) - a simulation mismatch is possible
    @N:CL201 : clk_rst_managr.vhd(167) | Trying to extract state machine for register pll_init_st
    Extracted state machine for register pll_init_st
    State machine has 5 reachable states with original encodings of:
       00001
       00010
       00100
       01000
       10000
    @W:CL159 : clk_rst_managr.vhd(38) | Input pll_ld_i is unused
    @W:CL159 : clk_rst_managr.vhd(39) | Input pll_refmon_i is unused
    @W:CL159 : clk_rst_managr.vhd(40) | Input pll_sdo_i is unused
    @W:CL159 : clk_rst_managr.vhd(41) | Input pll_status_i is unused
    @W:CL159 : top_test_pll.vhd(38) | Input p2l_clk_p_i is unused
    @W:CL159 : top_test_pll.vhd(39) | Input p2l_clk_n_i is unused
    @W:CL159 : top_test_pll.vhd(40) | Input p2l_data_i is unused
    @W:CL159 : top_test_pll.vhd(41) | Input p2l_dframe_i is unused
    @W:CL159 : top_test_pll.vhd(42) | Input p2l_valid_i is unused
    @W:CL159 : top_test_pll.vhd(44) | Input p_wr_req_i is unused
    @W:CL159 : top_test_pll.vhd(47) | Input vc_rdy_i is unused
    @W:CL159 : top_test_pll.vhd(55) | Input l2p_rdy_i is unused
    @W:CL159 : top_test_pll.vhd(56) | Input l_wr_rdy_i is unused
    @W:CL159 : top_test_pll.vhd(57) | Input p_rd_d_rdy_i is unused
    @W:CL159 : top_test_pll.vhd(58) | Input tx_error_i is unused
    @W:CL159 : top_test_pll.vhd(77) | Input err_flag_i is unused
    @W:CL159 : top_test_pll.vhd(78) | Input int_flag_i is unused
    @W:CL158 : top_test_pll.vhd(85) | Inout data_bus_io is unused
    @W:CL159 : top_test_pll.vhd(86) | Input ef1_i is unused
    @W:CL159 : top_test_pll.vhd(87) | Input ef2_i is unused
    @W:CL159 : top_test_pll.vhd(88) | Input lf1_i is unused
    @W:CL159 : top_test_pll.vhd(89) | Input lf2_i is unused
    @END
    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Fri Jul 15 19:30:53 2011

    ###########################################################]
    Synopsys Xilinx Technology Mapper, Version map510rc, Build 068R, Built Feb 22 2010 15:14:03
    Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved
    Product Version D-2010.03
    Reading constraint file: /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/tdc_syn_constraints.sdc
    Adding property syn_input_delay1, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=tdc_clk125:r" to view:work.top_tdc(rtl)
    Adding property syn_output_delay2, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=tdc_clk125:r" to view:work.top_tdc(rtl)
    Adding property syn_useioff, value 1 to view:work.top_tdc(rtl)
    Adding property syn_noarrayports, value 1 to view:work.top_tdc(rtl)
    Adding property syn_netlist_hierarchy, value 0 to view:work.top_tdc(rtl)
    @N:MF249 :  | Running in 64-bit mode.
    @N:MF257 :  | Gated clock conversion enabled
    Adding property syn_pad_type, value "LVCMOS_25", to instance spec_led_green_o
    Adding property syn_pad_type, value "LVCMOS_25", to instance pll_cs_o
    Adding property syn_pad_type, value "LVCMOS18", to instance spec_aux4_o
    Adding property syn_pad_type, value "LVCMOS_25", to instance pll_sdi_o
    Adding property syn_pad_type, value "LVCMOS18", to instance spec_aux3_o
    Adding property syn_pad_type, value "LVCMOS_25", to instance pll_sclk_o
    Adding property syn_pad_type, value "LVCMOS18", to instance spec_aux2_o
    Adding property syn_pad_type, value "LVCMOS_25", to instance tdc_led_trig1_o
    Adding property syn_pad_type, value "LVCMOS_25", to instance tdc_led_trig2_o
    Adding property syn_pad_type, value "LVCMOS_25", to instance tdc_led_trig3_o
    Adding property syn_pad_type, value "LVCMOS_25", to instance tdc_led_trig4_o
    Adding property syn_pad_type, value "LVCMOS_25", to instance tdc_led_trig5_o
    Adding property syn_pad_type, value "LVCMOS_25", to instance term_en_1_o
    Adding property syn_pad_type, value "LVCMOS_25", to instance term_en_2_o
    Adding property syn_pad_type, value "LVCMOS_25", to instance term_en_3_o
    Adding property syn_pad_type, value "LVCMOS_25", to instance term_en_4_o
    Adding property syn_pad_type, value "LVCMOS_25", to instance term_en_5_o
    Adding property syn_pad_type, value "LVCMOS_25", to instance cs_n_o
    Adding property syn_pad_type, value "LVCMOS_25", to instance irq_p_o
    Adding property syn_pad_type, value "SSTL_18_Class_II", to instance l2p_clk_n_o
    Adding property syn_pad_type, value "SSTL_18_Class_II", to instance l2p_clk_p_o
    Adding property syn_pad_type, value "SSTL_18_Class_I", to instance l2p_dframe_o
    Adding property syn_pad_type, value "SSTL_18_Class_I", to instance l2p_edb_o
    Adding property syn_pad_type, value "SSTL_18_Class_I", to instance l2p_valid_o
    Adding property syn_pad_type, value "LVCMOS_25", to instance oe_n_o
    Adding property syn_pad_type, value "SSTL_18_Class_I", to instance p2l_rdy_o
    Adding property syn_pad_type, value "LVCMOS_25", to instance rd_n_o
    Adding property syn_pad_type, value "SSTL_18_Class_I", to instance rx_error_o
    Adding property syn_pad_type, value "LVCMOS_25", to instance spare_o
    Adding property syn_pad_type, value "LVCMOS_25", to instance start_dis_o
    Adding property syn_pad_type, value "LVCMOS_25", to instance start_from_fpga_o
    Adding property syn_pad_type, value "LVCMOS_25", to instance stop_dis_o
    Adding property syn_pad_type, value "LVCMOS_25", to instance wr_n_o
    Adding property syn_pad_type, value "LVCMOS18", to instance spec_aux5_o
    Adding property syn_loc, value "N20", to port rst_n_a_i
    Adding property syn_pad_type, value "LVCMOS18", to port rst_n_a_i
    Adding property syn_loc, value "M20", to port p2l_clk_p_i
    Adding property syn_pad_type, value "DIFF_SSTL_18_Class_II", to port p2l_clk_p_i
    Adding property syn_loc, value "M19", to port p2l_clk_n_i
    Adding property syn_pad_type, value "DIFF_SSTL_18_Class_II", to port p2l_clk_n_i
    Adding property syn_pad_type, value "SSTL_18_Class_I", to port p2l_data_i[15:0]
    Adding property syn_loc, value "J22", to port p2l_dframe_i
    Adding property syn_pad_type, value "SSTL_18_Class_I", to port p2l_dframe_i
    Adding property syn_loc, value "L19", to port p2l_valid_i
    Adding property syn_pad_type, value "SSTL_18_Class_I", to port p2l_valid_i
    Adding property syn_loc, value "J16", to port p2l_rdy_o
    Adding property syn_pad_type, value "SSTL_18_Class_I", to port p2l_rdy_o
    Adding property syn_pad_type, value "SSTL_18_Class_I", to port p_wr_req_i[1:0]
    Adding property syn_pad_type, value "SSTL_18_Class_I", to port p_wr_rdy_o[1:0]
    Adding property syn_loc, value "J17", to port rx_error_o
    Adding property syn_pad_type, value "SSTL_18_Class_I", to port rx_error_o
    Adding property syn_pad_type, value "SSTL_18_Class_I", to port vc_rdy_i[1:0]
    Adding property syn_loc, value "K21", to port l2p_clk_p_o
    Adding property syn_pad_type, value "SSTL_18_Class_II", to port l2p_clk_p_o
    Adding property syn_loc, value "K22", to port l2p_clk_n_o
    Adding property syn_pad_type, value "SSTL_18_Class_II", to port l2p_clk_n_o
    Adding property syn_pad_type, value "SSTL_18_Class_I", to port l2p_data_o[15:0]
    Adding property syn_loc, value "U22", to port l2p_dframe_o
    Adding property syn_pad_type, value "SSTL_18_Class_I", to port l2p_dframe_o
    Adding property syn_loc, value "T18", to port l2p_valid_o
    Adding property syn_pad_type, value "SSTL_18_Class_I", to port l2p_valid_o
    Adding property syn_loc, value "U20", to port l2p_edb_o
    Adding property syn_pad_type, value "SSTL_18_Class_I", to port l2p_edb_o
    Adding property syn_loc, value "U19", to port l2p_rdy_i
    Adding property syn_pad_type, value "SSTL_18_Class_I", to port l2p_rdy_i
    Adding property syn_pad_type, value "SSTL_18_Class_I", to port l_wr_rdy_i[1:0]
    Adding property syn_pad_type, value "SSTL_18_Class_I", to port p_rd_d_rdy_i[1:0]
    Adding property syn_loc, value "M17", to port tx_error_i
    Adding property syn_pad_type, value "SSTL_18_Class_I", to port tx_error_i
    Adding property syn_loc, value "U16", to port irq_p_o
    Adding property syn_pad_type, value "LVCMOS_25", to port irq_p_o
    Adding property syn_loc, value "AB19", to port spare_o
    Adding property syn_pad_type, value "LVCMOS_25", to port spare_o
    Adding property syn_loc, value "E16", to port acam_refclk_i
    Adding property syn_pad_type, value "LVCMOS_25", to port acam_refclk_i
    Adding property syn_input_delay8, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=spec_clk20:r", to port pll_ld_i
    Adding property syn_pad_type, value "LVCMOS_25", to port pll_ld_i
    Adding property syn_loc, value "C18", to port pll_ld_i
    Adding property syn_input_delay9, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=spec_clk20:r", to port pll_refmon_i
    Adding property syn_pad_type, value "LVCMOS_25", to port pll_refmon_i
    Adding property syn_loc, value "D17", to port pll_refmon_i
    Adding property syn_input_delay10, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=spec_clk20:r", to port pll_sdo_i
    Adding property syn_pad_type, value "LVCMOS_25", to port pll_sdo_i
    Adding property syn_loc, value "AB18", to port pll_sdo_i
    Adding property syn_input_delay11, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=spec_clk20:r", to port pll_status_i
    Adding property syn_pad_type, value "LVCMOS_25", to port pll_status_i
    Adding property syn_loc, value "Y18", to port pll_status_i
    Adding property syn_loc, value "L20", to port tdc_clk_p_i
    Adding property syn_pad_type, value "DIFF_SSTL_18_Class_II", to port tdc_clk_p_i
    Adding property syn_loc, value "L22", to port tdc_clk_n_i
    Adding property syn_pad_type, value "DIFF_SSTL_18_Class_II", to port tdc_clk_n_i
    Adding property syn_output_delay6, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=spec_clk20:r", to port pll_cs_o
    Adding property syn_pad_type, value "LVCMOS_25", to port pll_cs_o
    Adding property syn_loc, value "Y17", to port pll_cs_o
    Adding property syn_loc, value "AB16", to port pll_dac_sync_o
    Adding property syn_pad_type, value "LVCMOS_25", to port pll_dac_sync_o
    Adding property syn_output_delay5, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=spec_clk20:r", to port pll_sdi_o
    Adding property syn_pad_type, value "LVCMOS_25", to port pll_sdi_o
    Adding property syn_loc, value "AA18", to port pll_sdi_o
    Adding property syn_output_delay7, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=spec_clk20:r", to port pll_sclk_o
    Adding property syn_pad_type, value "LVCMOS_25", to port pll_sclk_o
    Adding property syn_loc, value "AB17", to port pll_sclk_o
    Adding property syn_loc, value "V11", to port err_flag_i
    Adding property syn_pad_type, value "LVCMOS_25", to port err_flag_i
    Adding property syn_loc, value "W11", to port int_flag_i
    Adding property syn_pad_type, value "LVCMOS_25", to port int_flag_i
    Adding property syn_loc, value "T15", to port start_dis_o
    Adding property syn_pad_type, value "LVCMOS_25", to port start_dis_o
    Adding property syn_pad_type, value "LVCMOS_25", to port start_from_fpga_o
    Adding property syn_loc, value "U15", to port stop_dis_o
    Adding property syn_pad_type, value "LVCMOS_25", to port stop_dis_o
    Adding property syn_pad_type, value "LVCMOS_25", to port data_bus_io[27:0]
    Adding property syn_loc, value "W12", to port ef1_i
    Adding property syn_pad_type, value "LVCMOS_25", to port ef1_i
    Adding property syn_loc, value "R11", to port ef2_i
    Adding property syn_pad_type, value "LVCMOS_25", to port ef2_i
    Adding property syn_loc, value "Y12", to port lf1_i
    Adding property syn_pad_type, value "LVCMOS_25", to port lf1_i
    Adding property syn_loc, value "T11", to port lf2_i
    Adding property syn_pad_type, value "LVCMOS_25", to port lf2_i
    Adding property syn_pad_type, value "LVCMOS_25", to port address_o[3:0]
    Adding property syn_loc, value "T14", to port cs_n_o
    Adding property syn_pad_type, value "LVCMOS_25", to port cs_n_o
    Adding property syn_loc, value "V13", to port oe_n_o
    Adding property syn_pad_type, value "LVCMOS_25", to port oe_n_o
    Adding property syn_loc, value "AB13", to port rd_n_o
    Adding property syn_pad_type, value "LVCMOS_25", to port rd_n_o
    Adding property syn_loc, value "Y13", to port wr_n_o
    Adding property syn_pad_type, value "LVCMOS_25", to port wr_n_o
    Adding property syn_loc, value "C19", to port mute_inputs_o
    Adding property syn_pad_type, value "LVCMOS_25", to port mute_inputs_o
    Adding property syn_loc, value "W13", to port tdc_led_status_o
    Adding property syn_pad_type, value "LVCMOS_25", to port tdc_led_status_o
    Adding property syn_loc, value "W14", to port tdc_led_trig1_o
    Adding property syn_pad_type, value "LVCMOS_25", to port tdc_led_trig1_o
    Adding property syn_loc, value "Y14", to port tdc_led_trig2_o
    Adding property syn_pad_type, value "LVCMOS_25", to port tdc_led_trig2_o
    Adding property syn_loc, value "Y16", to port tdc_led_trig3_o
    Adding property syn_pad_type, value "LVCMOS_25", to port tdc_led_trig3_o
    Adding property syn_loc, value "W15", to port tdc_led_trig4_o
    Adding property syn_pad_type, value "LVCMOS_25", to port tdc_led_trig4_o
    Adding property syn_loc, value "V17", to port tdc_led_trig5_o
    Adding property syn_pad_type, value "LVCMOS_25", to port tdc_led_trig5_o
    Adding property syn_loc, value "W18", to port term_en_1_o
    Adding property syn_pad_type, value "LVCMOS_25", to port term_en_1_o
    Adding property syn_loc, value "B20", to port term_en_2_o
    Adding property syn_pad_type, value "LVCMOS_25", to port term_en_2_o
    Adding property syn_loc, value "A20", to port term_en_3_o
    Adding property syn_pad_type, value "LVCMOS_25", to port term_en_3_o
    Adding property syn_loc, value "H10", to port term_en_4_o
    Adding property syn_pad_type, value "LVCMOS_25", to port term_en_4_o
    Adding property syn_loc, value "E6", to port term_en_5_o
    Adding property syn_pad_type, value "LVCMOS_25", to port term_en_5_o
    Adding property syn_loc, value "C22", to port spec_aux0_i
    Adding property syn_pad_type, value "LVCMOS18", to port spec_aux0_i
    Adding property syn_loc, value "D21", to port spec_aux1_i
    Adding property syn_pad_type, value "LVCMOS18", to port spec_aux1_i
    Adding property syn_loc, value "G19", to port spec_aux2_o
    Adding property syn_pad_type, value "LVCMOS18", to port spec_aux2_o
    Adding property syn_loc, value "F20", to port spec_aux3_o
    Adding property syn_pad_type, value "LVCMOS18", to port spec_aux3_o
    Adding property syn_loc, value "F18", to port spec_aux4_o
    Adding property syn_pad_type, value "LVCMOS18", to port spec_aux4_o
    Adding property syn_loc, value "C20", to port spec_aux5_o
    Adding property syn_pad_type, value "LVCMOS18", to port spec_aux5_o
    Adding property syn_output_delay3, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=spec_clk20:r", to port spec_led_green_o
    Adding property syn_pad_type, value "LVCMOS_25", to port spec_led_green_o
    Adding property syn_loc, value "E5", to port spec_led_green_o
    Adding property syn_output_delay4, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=spec_clk20:r", to port spec_led_red_o
    Adding property syn_pad_type, value "LVCMOS_25", to port spec_led_red_o
    Adding property syn_loc, value "D5", to port spec_led_red_o
    Adding property syn_loc, value "H12", to port spec_clk_i
    Adding property syn_pad_type, value "LVCMOS_25", to port spec_clk_i
    Adding property syn_keep, value "true", to net spec_clk
    Reading Xilinx I/O pad type table from file [/afs/cern.ch/project/parc/elec/synplify/D-2010.03/lib/xilinx/x_io_tbl.txt]
    Reading Xilinx Rocket I/O parameter type table from file [/afs/cern.ch/project/parc/elec/synplify/D-2010.03/lib/xilinx/gttype.txt]
    @N: :  | Running in logic synthesis mode without enhanced optimization
    @W:BN132 : clk_rst_managr.vhd(187) | Removing sequential instance silly_altern,  because it is equivalent to instance pll_sclk

    Available hyper_sources - for debug and ip models
    	None Found

    Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 123MB peak: 125MB)

    Encoding state machine work.clk_rst_managr(rtl)-pll_init_st[0:4]
    original code -> new code
       00001 -> 00001
       00010 -> 00010
       00100 -> 00100
       01000 -> 01000
       10000 -> 10000
    @N:BN116 : clk_rst_managr.vhd(330) | Removing sequential instance pll_init_st[0] of view:PrimLib.dff(prim) because there are no references to its outputs
    @N: : incr_counter.vhd(36) | Found counter in view:work.incr_counter(rtl) inst value[31:0]
    @N: : free_counter.vhd(35) | Found counter in view:work.free_counter_tdc_led_counter(rtl) inst value[31:0]
    @N: : free_counter.vhd(35) | Found counter in view:work.free_counter_spec_led_red_counter(rtl) inst value[31:0]
    Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 125MB)

    #################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[

    ======================================================================================
                                    Instance:Pin        Generated Clock Optimization Status
    ======================================================================================
                             tdc_led_trig2_o:C              Not Done
                             tdc_led_trig1_o:C              Not Done
           clks_rsts_mgment.pll_init_st_i[4]:C              Not Done
                  clks_rsts_mgment.gral_incr:C              Not Done

    ##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################]

    Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 125MB)

    @N:FX430 :  | Found 2 global buffers instantiated by user
    Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 125MB)

    @N:FX276 : clk_rst_managr.vhd(381) | Startup value clks_rsts_mgment.un7_word_being_sent_0_0.INIT_00 = 00000000000000000000000000000000000000000000000001E009E102300231
    @N:FX276 : clk_rst_managr.vhd(381) | Startup value clks_rsts_mgment.un7_word_being_sent_0_0.INIT_04 = 101600171C18001900120C13241400150C030004F01004110632600000014002
    @N:FX276 : clk_rst_managr.vhd(381) | Startup value clks_rsts_mgment.un7_word_being_sent_0_0.INIT_05 = 04A600A700A804A900A204A300A400A5001E381F04A000A1001A001B081C001D
    @N:FX276 : clk_rst_managr.vhd(381) | Startup value clks_rsts_mgment.un7_word_being_sent_0_0.INIT_06 = 0190019101920193294069410D42094328F228F328F428F500AA00AB28F028F1
    @N:FX276 : clk_rst_managr.vhd(381) | Startup value clks_rsts_mgment.un7_word_being_sent_0_0.INIT_07 = 45A081A101A201A3019C019D899E019F01988999019A459B0194019501960197
    @N:FX276 : clk_rst_managr.vhd(381) | Startup value clks_rsts_mgment.un7_word_being_sent_0_0.INITP_00 = 0000008220550000000000000000C40000000000000000000000000000000000
    @N:FX211 :  | Packed ROM clks_rsts_mgment.un7_word_being_sent_0[17:0] (7 input, 18 output) to Block SelectRAM
    @A:BN291 : free_counter.vhd(35) | Boundary register spec_led_red_counter.value[31:0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
    Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 126MB peak: 127MB)

    Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 126MB peak: 127MB)

    Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 126MB peak: 127MB)

    Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 126MB peak: 127MB)

    Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 126MB peak: 127MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:01s		    -3.67ns		 188 /        92
       2		0h:00m:01s		    -3.67ns		 188 /        92
    ------------------------------------------------------------

    Timing driven replication report
    @N:FX271 :  | Instance "N_132_i" with 44 loads has been replicated 1 time(s) to improve timing
    Added 0 Registers via timing driven replication
    Added 1 LUTs via timing driven replication

    Timing driven replication report
    No replication required.

    Timing driven replication report
    No replication required.

    Timing driven replication report
    No replication required.

    Timing driven replication report
    No replication required.

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:01s		    -3.14ns		 182 /        92
    Timing driven replication report
    No replication required.

       2		0h:00m:01s		    -3.14ns		 182 /        92
       3		0h:00m:01s		    -3.14ns		 182 /        92
       4		0h:00m:01s		    -3.14ns		 183 /        92
       5		0h:00m:01s		    -3.14ns		 183 /        92
       6		0h:00m:01s		    -3.14ns		 183 /        92
       7		0h:00m:01s		    -3.14ns		 183 /        92
       8		0h:00m:01s		    -3.14ns		 183 /        92
    ------------------------------------------------------------

    Timing driven replication report
    No replication required.

    Timing driven replication report
    No replication required.

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:01s		    -3.14ns		 184 /        92
    Timing driven replication report
    No replication required.

       2		0h:00m:01s		    -3.14ns		 184 /        92
       3		0h:00m:01s		    -3.14ns		 184 /        92
       4		0h:00m:01s		    -3.14ns		 184 /        92
    ------------------------------------------------------------

    Net buffering Report for view:work.top_tdc(rtl):
    No nets needed buffering.

    Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:02s; Memory used current: 127MB peak: 128MB)

    @N:FX623 :  | Packing into LUT62
    Finished restoring hierarchy (Time elapsed 0h:00m:02s; Memory used current: 127MB peak: 128MB)

    Writing Analyst data base /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syn_tdc.srm
    Finished Writing Netlist Databases (Time elapsed 0h:00m:02s; Memory used current: 126MB peak: 128MB)

    Writing EDIF Netlist and constraint files
    D-2010.03
    Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:02s; Memory used current: 127MB peak: 129MB)

    Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:03s; Memory used current: 126MB peak: 129MB)

    @N:MF276 :  | Gated clock conversion enabled, but no gated clocks found in design
    Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:03s; Memory used current: 126MB peak: 129MB)

    Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:03s; Memory used current: 126MB peak: 129MB)

    @N:MF333 :  | Generated clock conversion enabled, but no generated clocks found in design
    Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:03s; Memory used current: 126MB peak: 129MB)

    @W:MT420 :  | Found inferred clock top_tdc|spec_clk_i with period 5.00ns. A user-defined clock should be declared on object "p:spec_clk_i"

    Found clock spec_clk20 with period 50.00ns
    Found clock tdc_clk125 with period 8.00ns
    All Input Ports in the design have input constraint of 2.00ns w.r.t. clock tdc_clk125:r
    All Output Ports in the design have output constraint of 2.00ns w.r.t. clock tdc_clk125:r
    Port pll_ld_i - has input  constraint of 2.00ns w.r.t. clock spec_clk20:r
    Port pll_refmon_i - has input  constraint of 2.00ns w.r.t. clock spec_clk20:r
    Port pll_sdo_i - has input  constraint of 2.00ns w.r.t. clock spec_clk20:r
    Port pll_status_i - has input  constraint of 2.00ns w.r.t. clock spec_clk20:r
    Port pll_cs_o - has output constraint of 2.00ns w.r.t. clock spec_clk20:r
    Port pll_sdi_o - has output constraint of 2.00ns w.r.t. clock spec_clk20:r
    Port pll_sclk_o - has output constraint of 2.00ns w.r.t. clock spec_clk20:r
    Port spec_led_green_o - has output constraint of 2.00ns w.r.t. clock spec_clk20:r
    Port spec_led_red_o - has output constraint of 2.00ns w.r.t. clock spec_clk20:r

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Fri Jul 15 19:30:57 2011
    #

    Top view:               top_tdc
    Requested Frequency:    20.0 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):    /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/tdc_syn_constraints.sdc

    @N:MT320 :  | This timing report estimates place and route data. Please look at the place and route timing report for final timing..

    Performance Summary
    *******************

    Worst slack in design: -2.997

                           Requested     Estimated     Requested     Estimated                Clock        Clock
    Starting Clock         Frequency     Frequency     Period        Period        Slack      Type         Group
    --------------------------------------------------------------------------------------------------------------------------
    spec_clk20             20.0 MHz      104.2 MHz     50.000        9.592         40.408     declared     default_clkgroup__2
    tdc_clk125             125.0 MHz     90.9 MHz      8.000         10.997        -2.997     declared     default_clkgroup__1
    top_tdc|spec_clk_i     200.0 MHz     167.5 MHz     5.000         5.971         -0.971     inferred     Inferred_clkgroup_0
    ==========================================================================================================================

    Clock Relationships
    *******************

    Clocks                                  |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    -------------------------------------------------------------------------------------------------------------------------------
    Starting            Ending              |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
    -------------------------------------------------------------------------------------------------------------------------------
    tdc_clk125          tdc_clk125          |  8.000       -2.997  |  No paths    -      |  No paths    -      |  No paths    -
    tdc_clk125          spec_clk20          |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -
    tdc_clk125          top_tdc|spec_clk_i  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -
    spec_clk20          tdc_clk125          |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -
    spec_clk20          spec_clk20          |  50.000      40.408  |  No paths    -      |  No paths    -      |  No paths    -
    top_tdc|spec_clk_i  tdc_clk125          |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -
    top_tdc|spec_clk_i  spec_clk20          |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -
    top_tdc|spec_clk_i  top_tdc|spec_clk_i  |  5.000       -0.971  |  No paths    -      |  No paths    -      |  No paths    -
    ===============================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    Input Ports:

    Port                Starting                User           Arrival     Required
    Name                Reference               Constraint     Time        Time         Slack
                        Clock
    ------------------------------------------------------------------------------------------
    acam_refclk_i       tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[0]      tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[1]      tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[2]      tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[3]      tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[4]      tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[5]      tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[6]      tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[7]      tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[8]      tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[9]      tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[10]     tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[11]     tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[12]     tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[13]     tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[14]     tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[15]     tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[16]     tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[17]     tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[18]     tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[19]     tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[20]     tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[21]     tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[22]     tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[23]     tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[24]     tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[25]     tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[26]     tdc_clk125 (rising)     2.000          NA          NA           NA
    data_bus_io[27]     tdc_clk125 (rising)     2.000          NA          NA           NA
    ef1_i               tdc_clk125 (rising)     2.000          NA          NA           NA
    ef2_i               tdc_clk125 (rising)     2.000          NA          NA           NA
    err_flag_i          tdc_clk125 (rising)     2.000          NA          NA           NA
    int_flag_i          tdc_clk125 (rising)     2.000          NA          NA           NA
    l2p_rdy_i           tdc_clk125 (rising)     2.000          NA          NA           NA
    l_wr_rdy_i[0]       tdc_clk125 (rising)     2.000          NA          NA           NA
    l_wr_rdy_i[1]       tdc_clk125 (rising)     2.000          NA          NA           NA
    lf1_i               tdc_clk125 (rising)     2.000          NA          NA           NA
    lf2_i               tdc_clk125 (rising)     2.000          NA          NA           NA
    p2l_clk_n_i         tdc_clk125 (rising)     2.000          NA          NA           NA
    p2l_clk_p_i         tdc_clk125 (rising)     2.000          NA          NA           NA
    p2l_data_i[0]       tdc_clk125 (rising)     2.000          NA          NA           NA
    p2l_data_i[1]       tdc_clk125 (rising)     2.000          NA          NA           NA
    p2l_data_i[2]       tdc_clk125 (rising)     2.000          NA          NA           NA
    p2l_data_i[3]       tdc_clk125 (rising)     2.000          NA          NA           NA
    p2l_data_i[4]       tdc_clk125 (rising)     2.000          NA          NA           NA
    p2l_data_i[5]       tdc_clk125 (rising)     2.000          NA          NA           NA
    p2l_data_i[6]       tdc_clk125 (rising)     2.000          NA          NA           NA
    p2l_data_i[7]       tdc_clk125 (rising)     2.000          NA          NA           NA
    p2l_data_i[8]       tdc_clk125 (rising)     2.000          NA          NA           NA
    p2l_data_i[9]       tdc_clk125 (rising)     2.000          NA          NA           NA
    p2l_data_i[10]      tdc_clk125 (rising)     2.000          NA          NA           NA
    p2l_data_i[11]      tdc_clk125 (rising)     2.000          NA          NA           NA
    p2l_data_i[12]      tdc_clk125 (rising)     2.000          NA          NA           NA
    p2l_data_i[13]      tdc_clk125 (rising)     2.000          NA          NA           NA
    p2l_data_i[14]      tdc_clk125 (rising)     2.000          NA          NA           NA
    p2l_data_i[15]      tdc_clk125 (rising)     2.000          NA          NA           NA
    p2l_dframe_i        tdc_clk125 (rising)     2.000          NA          NA           NA
    p2l_valid_i         tdc_clk125 (rising)     2.000          NA          NA           NA
    p_rd_d_rdy_i[0]     tdc_clk125 (rising)     2.000          NA          NA           NA
    p_rd_d_rdy_i[1]     tdc_clk125 (rising)     2.000          NA          NA           NA
    p_wr_req_i[0]       tdc_clk125 (rising)     2.000          NA          NA           NA
    p_wr_req_i[1]       tdc_clk125 (rising)     2.000          NA          NA           NA
    pll_ld_i            spec_clk20 (rising)     2.000          2.000       42.408       40.408
    pll_refmon_i        spec_clk20 (rising)     2.000          NA          NA           NA
    pll_sdo_i           spec_clk20 (rising)     2.000          NA          NA           NA
    pll_status_i        spec_clk20 (rising)     2.000          NA          NA           NA
    rst_n_a_i           tdc_clk125 (rising)     2.000          2.000       -0.997       -2.997
    spec_aux0_i         tdc_clk125 (rising)     2.000          2.000       -0.581       -2.581
    spec_aux1_i         tdc_clk125 (rising)     2.000          2.000       -0.997       -2.997
    spec_clk_i          NA                      NA             NA          NA           NA
    tdc_clk_n_i         tdc_clk125 (rising)     2.000          NA          NA           NA
    tdc_clk_p_i         tdc_clk125 (rising)     2.000          NA          NA           NA
    tx_error_i          tdc_clk125 (rising)     2.000          NA          NA           NA
    vc_rdy_i[0]         tdc_clk125 (rising)     2.000          NA          NA           NA
    vc_rdy_i[1]         tdc_clk125 (rising)     2.000          NA          NA           NA
    ==========================================================================================

    Output Ports:

    Port                 Starting                        User                         Arrival     Required
    Name                 Reference                       Constraint                   Time        Time         Slack
                         Clock
    -----------------------------------------------------------------------------------------------------------------
    pll_cs_o             top_tdc|spec_clk_i (rising)     2.000(spec_clk20 rising)     10.827      NA           NA
    pll_sclk_o           top_tdc|spec_clk_i (rising)     2.000(spec_clk20 rising)     5.344       NA           NA
    pll_sdi_o            top_tdc|spec_clk_i (rising)     2.000(spec_clk20 rising)     16.613      NA           NA
    spec_aux2_o          top_tdc|spec_clk_i (rising)     2.000(tdc_clk125 rising)     5.344       NA           NA
    spec_aux3_o          top_tdc|spec_clk_i (rising)     2.000(tdc_clk125 rising)     16.613      NA           NA
    spec_aux4_o          top_tdc|spec_clk_i (rising)     2.000(tdc_clk125 rising)     10.827      NA           NA
    spec_aux5_o          tdc_clk125 (rising)             2.000(tdc_clk125 rising)     8.997       6.000        -2.997
    spec_led_green_o     spec_clk20 (rising)             2.000(spec_clk20 rising)     7.592       48.000       40.408
    spec_led_red_o       spec_clk20 (rising)             2.000(spec_clk20 rising)     2.500       48.000       45.500
    tdc_led_status_o     tdc_clk125 (rising)             2.000(tdc_clk125 rising)     2.500       6.000        3.500
    tdc_led_trig1_o      spec_clk20 (rising)             2.000(tdc_clk125 rising)     2.500       NA           NA
    tdc_led_trig2_o      tdc_clk125 (rising)             2.000(tdc_clk125 rising)     2.500       6.000        3.500
    tdc_led_trig3_o      tdc_clk125 (rising)             2.000(tdc_clk125 rising)     8.581       6.000        -2.581
    tdc_led_trig4_o      tdc_clk125 (rising)             2.000(tdc_clk125 rising)     8.581       6.000        -2.581
    tdc_led_trig5_o      tdc_clk125 (rising)             2.000(tdc_clk125 rising)     8.581       6.000        -2.581
    =================================================================================================================

    ====================================
    Detailed Report for Clock: spec_clk20
    ====================================

    Starting Points with Worst Slack
    ********************************

                                        Starting                                                     Arrival
    Instance                            Reference      Type     Pin          Net                     Time        Slack
                                        Clock
    -------------------------------------------------------------------------------------------------------------------
    pll_ld_i                            spec_clk20     Port     pll_ld_i     pll_ld_i                2.000       40.408
    spec_led_red_oreg                   spec_clk20     FDRE     Q            spec_led_red_oreg       1.711       45.500
    spec_led_red                        spec_clk20     FDR      Q            spec_led_red            2.296       47.916
    spec_led_red_counter.count_done     spec_clk20     FDR      Q            spec_led_count_done     2.296       48.190
    ===================================================================================================================

    Ending Points with Worst Slack
    ******************************

                          Starting                                                             Required
    Instance              Reference      Type     Pin                  Net                     Time         Slack
                          Clock
    --------------------------------------------------------------------------------------------------------------
    spec_led_green_o      spec_clk20     Port     spec_led_green_o     spec_led_green_o        48.000       40.408
    spec_led_red_o        spec_clk20     Port     spec_led_red_o       spec_led_red_o          48.000       45.500
    spec_led_red_oreg     spec_clk20     FDRE     D                    spec_led_red_i          51.147       47.916
    spec_led_red_oreg     spec_clk20     FDRE     CE                   spec_led_count_done     51.421       48.190
    spec_led_red          spec_clk20     FDR      D                    spec_led_red_0          51.821       48.346
    ==============================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      50.000
        - User constraint on ending point:       2.000
        = Required time:                         48.000

        - Propagation time:                      5.592
        - User constraint on starting point:     2.000
        = Slack (non-critical) :                 40.408

        Number of logic level(s):                2
        Starting point:                          pll_ld_i / pll_ld_i
        Ending point:                            spec_led_green_o / spec_led_green_o
        The start point is clocked by            spec_clk20 [rising]
        The end   point is clocked by            spec_clk20 [rising]

    Instance / Net                     Pin                  Pin               Arrival     No. of
    Name                      Type     Name                 Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------------
    pll_ld_i                  Port     pll_ld_i             In      0.000     2.000       -
    pll_ld_i                  Net      -                    -       0.000     -           1
    pll_ld_i_ibuf             IBUF     I                    In      -         2.000       -
    pll_ld_i_ibuf             IBUF     O                    Out     1.290     3.290       -
    pll_ld_i_c                Net      -                    -       0.862     -           1
    spec_led_green_o_obuf     OBUF     I                    In      -         4.152       -
    spec_led_green_o_obuf     OBUF     O                    Out     3.440     7.592       -
    spec_led_green_o          Net      -                    -       0.000     -           1
    spec_led_green_o          Port     spec_led_green_o     Out     -         7.592       -
    ================================================================================================
    Total path delay (propagation time + setup) of 5.592 is 4.730(84.6%) logic and 0.862(15.4%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      50.000
        - User constraint on ending point:       2.000
        = Required time:                         48.000

        - Propagation time:                      0.789
        - Clock delay at starting point:         1.711
        = Slack (non-critical) :                 45.500

        Number of logic level(s):                1
        Starting point:                          spec_led_red_oreg / Q
        Ending point:                            spec_led_red_o / spec_led_red_o
        The start point is clocked by            spec_clk20 [rising] on pin C
        The end   point is clocked by            spec_clk20 [rising]

    Instance / Net                   Pin                Pin               Arrival     No. of
    Name                    Type     Name               Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------
    spec_led_red_oreg       FDRE     Q                  Out     0.000     1.711       -
    spec_led_red_oreg       Net      -                  -       0.000     -           1
    spec_led_red_o_obuf     OBUF     I                  In      -         1.711       -
    spec_led_red_o_obuf     OBUF     O                  Out     0.789     2.500       -
    spec_led_red_o          Net      -                  -       0.000     -           1
    spec_led_red_o          Port     spec_led_red_o     Out     -         2.500       -
    ============================================================================================
    Total path delay (propagation time + setup) of 0.789 is 0.789(100.0%) logic and 0.000(0.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Start clock path:

    Instance / Net                 Pin      Pin               Arrival     No. of
    Name                  Type     Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------
    spec_clk              Net      -        -       1.711     -           0
    spec_led_red_oreg     FDRE     C        In      -         1.711       -
    ================================================================================

    Path information for path number 3:
          Requested Period:                      50.000
        - Setup time:                            0.564
        + Clock delay at ending point:           1.711
        = Required time:                         51.147

        - Propagation time:                      1.520
        - Clock delay at starting point:         1.711
        = Slack (non-critical) :                 47.916

        Number of logic level(s):                1
        Starting point:                          spec_led_red / Q
        Ending point:                            spec_led_red_oreg / D
        The start point is clocked by            spec_clk20 [rising] on pin C
        The end   point is clocked by            spec_clk20 [rising] on pin C

    Instance / Net                 Pin      Pin               Arrival     No. of
    Name                  Type     Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------
    spec_led_red          FDR      Q        Out     0.585     2.296       -
    spec_led_red          Net      -        -       0.935     -           2
    spec_led_red_i        INV      I        In      -         3.231       -
    spec_led_red_i        INV      O        Out     0.000     3.231       -
    spec_led_red_i        Net      -        -       0.000     -           1
    spec_led_red_oreg     FDRE     D        In      -         3.231       -
    ================================================================================
    Total path delay (propagation time + setup) of 2.084 is 1.149(55.1%) logic and 0.935(44.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Start clock path:

    Instance / Net              Pin      Pin               Arrival     No. of
    Name               Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------
    spec_clk           Net      -        -       1.711     -           0
    spec_led_red       FDR      C        In      -         1.711       -
    =============================================================================

    End clock path:

    Instance / Net                 Pin      Pin               Arrival     No. of
    Name                  Type     Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------
    spec_clk              Net      -        -       1.711     -           0
    spec_led_red_oreg     FDRE     C        In      -         1.711       -
    ================================================================================

    Path information for path number 4:
          Requested Period:                      50.000
        - Setup time:                            0.290
        + Clock delay at ending point:           1.711
        = Required time:                         51.421

        - Propagation time:                      1.520
        - Clock delay at starting point:         1.711
        = Slack (non-critical) :                 48.190

        Number of logic level(s):                0
        Starting point:                          spec_led_red_counter.count_done / Q
        Ending point:                            spec_led_red_oreg / CE
        The start point is clocked by            spec_clk20 [rising] on pin C
        The end   point is clocked by            spec_clk20 [rising] on pin C

    Instance / Net                               Pin      Pin               Arrival     No. of
    Name                                Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------
    spec_led_red_counter.count_done     FDR      Q        Out     0.585     2.296       -
    spec_led_count_done                 Net      -        -       0.935     -           2
    spec_led_red_oreg                   FDRE     CE       In      -         3.231       -
    ==============================================================================================
    Total path delay (propagation time + setup) of 1.810 is 0.875(48.3%) logic and 0.935(51.7%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Start clock path:

    Instance / Net                               Pin      Pin               Arrival     No. of
    Name                                Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------
    spec_clk                            Net      -        -       1.711     -           0
    spec_led_red_counter.count_done     FDR      C        In      -         1.711       -
    ==============================================================================================

    End clock path:

    Instance / Net                 Pin      Pin               Arrival     No. of
    Name                  Type     Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------
    spec_clk              Net      -        -       1.711     -           0
    spec_led_red_oreg     FDRE     C        In      -         1.711       -
    ================================================================================

    Path information for path number 5:
          Requested Period:                      50.000
        - Setup time:                            -0.110
        + Clock delay at ending point:           1.711
        = Required time:                         51.821

        - Propagation time:                      1.764
        - Clock delay at starting point:         1.711
        = Slack (non-critical) :                 48.346

        Number of logic level(s):                1
        Starting point:                          spec_led_red / Q
        Ending point:                            spec_led_red / D
        The start point is clocked by            spec_clk20 [rising] on pin C
        The end   point is clocked by            spec_clk20 [rising] on pin C

    Instance / Net                Pin      Pin               Arrival     No. of
    Name               Type       Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------
    spec_led_red       FDR        Q        Out     0.585     2.296       -
    spec_led_red       Net        -        -       0.935     -           2
    spec_led_red_e     LUT2_L     I1       In      -         3.231       -
    spec_led_red_e     LUT2_L     LO       Out     0.244     3.475       -
    spec_led_red_0     Net        -        -       0.000     -           1
    spec_led_red       FDR        D        In      -         3.475       -
    ===============================================================================
    Total path delay (propagation time + setup) of 1.654 is 0.719(43.5%) logic and 0.935(56.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Start clock path:

    Instance / Net              Pin      Pin               Arrival     No. of
    Name               Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------
    spec_clk           Net      -        -       1.711     -           0
    spec_led_red       FDR      C        In      -         1.711       -
    =============================================================================

    End clock path:

    Instance / Net              Pin      Pin               Arrival     No. of
    Name               Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------
    spec_clk           Net      -        -       1.711     -           0
    spec_led_red       FDR      C        In      -         1.711       -
    =============================================================================

    ====================================
    Detailed Report for Clock: tdc_clk125
    ====================================

    Starting Points with Worst Slack
    ********************************

                                  Starting                                                            Arrival
    Instance                      Reference      Type     Pin             Net                         Time        Slack
                                  Clock
    --------------------------------------------------------------------------------------------------------------------
    rst_n_a_i                     tdc_clk125     Port     rst_n_a_i       rst_n_a_i                   2.000       -2.997
    spec_aux1_i                   tdc_clk125     Port     spec_aux1_i     spec_aux1_i                 2.000       -2.997
    spec_aux0_i                   tdc_clk125     Port     spec_aux0_i     spec_aux0_i                 2.000       -2.581
    tdc_led_counter.value[17]     tdc_clk125     FDR      Q               un1_tdc_led_counter[17]     2.296       1.477
    tdc_led_counter.value[18]     tdc_clk125     FDR      Q               un1_tdc_led_counter[18]     2.296       1.477
    tdc_led_counter.value[19]     tdc_clk125     FDS      Q               un1_tdc_led_counter[19]     2.296       1.477
    tdc_led_counter.value[27]     tdc_clk125     FDR      Q               un1_tdc_led_counter[27]     2.296       1.477
    tdc_led_counter.value[23]     tdc_clk125     FDS      Q               un1_tdc_led_counter[23]     2.296       1.507
    tdc_led_counter.value[25]     tdc_clk125     FDS      Q               un1_tdc_led_counter[25]     2.296       1.507
    tdc_led_counter.value[26]     tdc_clk125     FDR      Q               un1_tdc_led_counter[26]     2.296       1.507
    ====================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                 Starting                                                        Required
    Instance                     Reference      Type     Pin                 Net                 Time         Slack
                                 Clock
    ----------------------------------------------------------------------------------------------------------------
    spec_aux5_o                  tdc_clk125     Port     spec_aux5_o         spec_aux5_o         6.000        -2.997
    tdc_led_trig3_o              tdc_clk125     Port     tdc_led_trig3_o     tdc_led_trig3_o     6.000        -2.581
    tdc_led_trig4_o              tdc_clk125     Port     tdc_led_trig4_o     tdc_led_trig4_o     6.000        -2.581
    tdc_led_trig5_o              tdc_clk125     Port     tdc_led_trig5_o     tdc_led_trig5_o     6.000        -2.581
    tdc_led_counter.value[0]     tdc_clk125     FDS      S                   N_51_i              9.000        1.477
    tdc_led_counter.value[1]     tdc_clk125     FDS      S                   N_51_i              9.000        1.477
    tdc_led_counter.value[2]     tdc_clk125     FDS      S                   N_51_i              9.000        1.477
    tdc_led_counter.value[3]     tdc_clk125     FDS      S                   N_51_i              9.000        1.477
    tdc_led_counter.value[4]     tdc_clk125     FDS      S                   N_51_i              9.000        1.477
    tdc_led_counter.value[5]     tdc_clk125     FDR      R                   N_51_i              9.000        1.477
    ================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      8.000
        - User constraint on ending point:       2.000
        = Required time:                         6.000

        - Propagation time:                      6.997
        - User constraint on starting point:     2.000
        = Slack (critical) :                     -2.997

        Number of logic level(s):                3
        Starting point:                          rst_n_a_i / rst_n_a_i
        Ending point:                            spec_aux5_o / spec_aux5_o
        The start point is clocked by            tdc_clk125 [rising]
        The end   point is clocked by            tdc_clk125 [rising]

    Instance / Net                    Pin             Pin               Arrival     No. of
    Name                     Type     Name            Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------
    rst_n_a_i                Port     rst_n_a_i       In      0.000     2.000       -
    rst_n_a_i                Net      -               -       0.000     -           1
    rst_n_a_i_ibuf           IBUF     I               In      -         2.000       -
    rst_n_a_i_ibuf           IBUF     O               Out     1.290     3.290       -
    rst_n_a_i_c              Net      -               -       1.160     -           14
    spec_aux5_o_obuf_RNO     LUT2     I0              In      -         4.450       -
    spec_aux5_o_obuf_RNO     LUT2     O               Out     0.244     4.694       -
    N_132_i                  Net      -               -       0.862     -           1
    spec_aux5_o_obuf         OBUF     I               In      -         5.557       -
    spec_aux5_o_obuf         OBUF     O               Out     3.440     8.997       -
    spec_aux5_o              Net      -               -       0.000     -           1
    spec_aux5_o              Port     spec_aux5_o     Out     -         8.997       -
    ==========================================================================================
    Total path delay (propagation time + setup) of 6.997 is 4.974(71.1%) logic and 2.023(28.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      8.000
        - User constraint on ending point:       2.000
        = Required time:                         6.000

        - Propagation time:                      6.997
        - User constraint on starting point:     2.000
        = Slack (critical) :                     -2.997

        Number of logic level(s):                3
        Starting point:                          spec_aux1_i / spec_aux1_i
        Ending point:                            spec_aux5_o / spec_aux5_o
        The start point is clocked by            tdc_clk125 [rising]
        The end   point is clocked by            tdc_clk125 [rising]

    Instance / Net                    Pin             Pin               Arrival     No. of
    Name                     Type     Name            Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------
    spec_aux1_i              Port     spec_aux1_i     In      0.000     2.000       -
    spec_aux1_i              Net      -               -       0.000     -           1
    spec_aux1_i_ibuf         IBUF     I               In      -         2.000       -
    spec_aux1_i_ibuf         IBUF     O               Out     1.290     3.290       -
    spec_aux1_i_c            Net      -               -       1.160     -           14
    spec_aux5_o_obuf_RNO     LUT2     I1              In      -         4.450       -
    spec_aux5_o_obuf_RNO     LUT2     O               Out     0.244     4.694       -
    N_132_i                  Net      -               -       0.862     -           1
    spec_aux5_o_obuf         OBUF     I               In      -         5.557       -
    spec_aux5_o_obuf         OBUF     O               Out     3.440     8.997       -
    spec_aux5_o              Net      -               -       0.000     -           1
    spec_aux5_o              Port     spec_aux5_o     Out     -         8.997       -
    ==========================================================================================
    Total path delay (propagation time + setup) of 6.997 is 4.974(71.1%) logic and 2.023(28.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      8.000
        - User constraint on ending point:       2.000
        = Required time:                         6.000

        - Propagation time:                      6.581
        - User constraint on starting point:     2.000
        = Slack (non-critical) :                 -2.581

        Number of logic level(s):                3
        Starting point:                          spec_aux0_i / spec_aux0_i
        Ending point:                            tdc_led_trig3_o / tdc_led_trig3_o
        The start point is clocked by            tdc_clk125 [rising]
        The end   point is clocked by            tdc_clk125 [rising]

    Instance / Net                       Pin                 Pin               Arrival     No. of
    Name                        Type     Name                Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------
    spec_aux0_i                 Port     spec_aux0_i         In      0.000     2.000       -
    spec_aux0_i                 Net      -                   -       0.000     -           1
    spec_aux0_i_ibuf            IBUF     I                   In      -         2.000       -
    spec_aux0_i_ibuf            IBUF     O                   Out     1.290     3.290       -
    spec_aux0_i_c               Net      -                   -       0.925     -           3
    spec_aux0_i_ibuf_RNI3NV     INV      I                   In      -         4.215       -
    spec_aux0_i_ibuf_RNI3NV     INV      O                   Out     0.000     4.215       -
    spec_aux0_i_c_i             Net      -                   -       0.925     -           3
    tdc_led_trig3_o_obuf        OBUF     I                   In      -         5.141       -
    tdc_led_trig3_o_obuf        OBUF     O                   Out     3.440     8.581       -
    tdc_led_trig3_o             Net      -                   -       0.000     -           1
    tdc_led_trig3_o             Port     tdc_led_trig3_o     Out     -         8.581       -
    =================================================================================================
    Total path delay (propagation time + setup) of 6.581 is 4.730(71.9%) logic and 1.851(28.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      8.000
        - User constraint on ending point:       2.000
        = Required time:                         6.000

        - Propagation time:                      6.581
        - User constraint on starting point:     2.000
        = Slack (non-critical) :                 -2.581

        Number of logic level(s):                3
        Starting point:                          spec_aux0_i / spec_aux0_i
        Ending point:                            tdc_led_trig5_o / tdc_led_trig5_o
        The start point is clocked by            tdc_clk125 [rising]
        The end   point is clocked by            tdc_clk125 [rising]

    Instance / Net                       Pin                 Pin               Arrival     No. of
    Name                        Type     Name                Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------
    spec_aux0_i                 Port     spec_aux0_i         In      0.000     2.000       -
    spec_aux0_i                 Net      -                   -       0.000     -           1
    spec_aux0_i_ibuf            IBUF     I                   In      -         2.000       -
    spec_aux0_i_ibuf            IBUF     O                   Out     1.290     3.290       -
    spec_aux0_i_c               Net      -                   -       0.925     -           3
    spec_aux0_i_ibuf_RNI3NV     INV      I                   In      -         4.215       -
    spec_aux0_i_ibuf_RNI3NV     INV      O                   Out     0.000     4.215       -
    spec_aux0_i_c_i             Net      -                   -       0.925     -           3
    tdc_led_trig5_o_obuf        OBUF     I                   In      -         5.141       -
    tdc_led_trig5_o_obuf        OBUF     O                   Out     3.440     8.581       -
    tdc_led_trig5_o             Net      -                   -       0.000     -           1
    tdc_led_trig5_o             Port     tdc_led_trig5_o     Out     -         8.581       -
    =================================================================================================
    Total path delay (propagation time + setup) of 6.581 is 4.730(71.9%) logic and 1.851(28.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      8.000
        - User constraint on ending point:       2.000
        = Required time:                         6.000

        - Propagation time:                      6.581
        - User constraint on starting point:     2.000
        = Slack (non-critical) :                 -2.581

        Number of logic level(s):                3
        Starting point:                          spec_aux0_i / spec_aux0_i
        Ending point:                            tdc_led_trig4_o / tdc_led_trig4_o
        The start point is clocked by            tdc_clk125 [rising]
        The end   point is clocked by            tdc_clk125 [rising]

    Instance / Net                       Pin                 Pin               Arrival     No. of
    Name                        Type     Name                Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------
    spec_aux0_i                 Port     spec_aux0_i         In      0.000     2.000       -
    spec_aux0_i                 Net      -                   -       0.000     -           1
    spec_aux0_i_ibuf            IBUF     I                   In      -         2.000       -
    spec_aux0_i_ibuf            IBUF     O                   Out     1.290     3.290       -
    spec_aux0_i_c               Net      -                   -       0.925     -           3
    spec_aux0_i_ibuf_RNI3NV     INV      I                   In      -         4.215       -
    spec_aux0_i_ibuf_RNI3NV     INV      O                   Out     0.000     4.215       -
    spec_aux0_i_c_i             Net      -                   -       0.925     -           3
    tdc_led_trig4_o_obuf        OBUF     I                   In      -         5.141       -
    tdc_led_trig4_o_obuf        OBUF     O                   Out     3.440     8.581       -
    tdc_led_trig4_o             Net      -                   -       0.000     -           1
    tdc_led_trig4_o             Port     tdc_led_trig4_o     Out     -         8.581       -
    =================================================================================================
    Total path delay (propagation time + setup) of 6.581 is 4.730(71.9%) logic and 1.851(28.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: top_tdc|spec_clk_i
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                   Starting                                                                                   Arrival
    Instance                                       Reference              Type     Pin     Net                                                Time        Slack
                                                   Clock
    ------------------------------------------------------------------------------------------------------------------------------------------------------------
    clks_rsts_mgment.general_poreset.value[23]     top_tdc|spec_clk_i     FDRE     Q       clks_rsts_mgment.general_poreset.value_qxu[23]     5.140       -0.971
    clks_rsts_mgment.general_poreset.value[25]     top_tdc|spec_clk_i     FDRE     Q       clks_rsts_mgment.general_poreset.value_qxu[25]     5.140       -0.971
    clks_rsts_mgment.general_poreset.value[26]     top_tdc|spec_clk_i     FDRE     Q       clks_rsts_mgment.general_poreset.value_qxu[26]     5.140       -0.971
    clks_rsts_mgment.general_poreset.value[22]     top_tdc|spec_clk_i     FDRE     Q       clks_rsts_mgment.general_poreset.value_qxu[22]     5.140       -0.879
    clks_rsts_mgment.general_poreset.value[24]     top_tdc|spec_clk_i     FDRE     Q       clks_rsts_mgment.general_poreset.value_qxu[24]     5.140       -0.879
    clks_rsts_mgment.general_poreset.value[7]      top_tdc|spec_clk_i     FDRE     Q       clks_rsts_mgment.general_poreset.value_qxu[7]      5.140       -0.871
    clks_rsts_mgment.general_poreset.value[8]      top_tdc|spec_clk_i     FDRE     Q       clks_rsts_mgment.general_poreset.value_qxu[8]      5.140       -0.871
    clks_rsts_mgment.general_poreset.value[13]     top_tdc|spec_clk_i     FDRE     Q       clks_rsts_mgment.general_poreset.value_qxu[13]     5.140       -0.831
    clks_rsts_mgment.general_poreset.value[14]     top_tdc|spec_clk_i     FDRE     Q       clks_rsts_mgment.general_poreset.value_qxu[14]     5.140       -0.831
    clks_rsts_mgment.general_poreset.value[1]      top_tdc|spec_clk_i     FDRE     Q       clks_rsts_mgment.general_poreset.value_qxu[1]      5.140       -0.791
    ============================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                  Starting                                           Required
    Instance                                      Reference              Type     Pin     Net        Time         Slack
                                                  Clock
    --------------------------------------------------------------------------------------------------------------------
    clks_rsts_mgment.general_poreset.value[0]     top_tdc|spec_clk_i     FDRE     CE      N_10_i     9.257        -0.971
    clks_rsts_mgment.general_poreset.value[1]     top_tdc|spec_clk_i     FDRE     CE      N_10_i     9.257        -0.971
    clks_rsts_mgment.general_poreset.value[2]     top_tdc|spec_clk_i     FDRE     CE      N_10_i     9.257        -0.971
    clks_rsts_mgment.general_poreset.value[3]     top_tdc|spec_clk_i     FDRE     CE      N_10_i     9.257        -0.971
    clks_rsts_mgment.general_poreset.value[4]     top_tdc|spec_clk_i     FDRE     CE      N_10_i     9.257        -0.971
    clks_rsts_mgment.general_poreset.value[5]     top_tdc|spec_clk_i     FDRE     CE      N_10_i     9.257        -0.971
    clks_rsts_mgment.general_poreset.value[6]     top_tdc|spec_clk_i     FDRE     CE      N_10_i     9.257        -0.971
    clks_rsts_mgment.general_poreset.value[7]     top_tdc|spec_clk_i     FDRE     CE      N_10_i     9.257        -0.971
    clks_rsts_mgment.general_poreset.value[8]     top_tdc|spec_clk_i     FDRE     CE      N_10_i     9.257        -0.971
    clks_rsts_mgment.general_poreset.value[9]     top_tdc|spec_clk_i     FDRE     CE      N_10_i     9.257        -0.971
    ====================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      5.000
        - Setup time:                            0.298
        + Clock delay at ending point:           4.555
        = Required time:                         9.257

        - Propagation time:                      5.673
        - Clock delay at starting point:         4.555
        = Slack (non-critical) :                 -0.971

        Number of logic level(s):                3
        Starting point:                          clks_rsts_mgment.general_poreset.value[23] / Q
        Ending point:                            clks_rsts_mgment.general_poreset.value[0] / CE
        The start point is clocked by            top_tdc|spec_clk_i [rising] on pin C
        The end   point is clocked by            top_tdc|spec_clk_i [rising] on pin C

    Instance / Net                                                    Pin      Pin               Arrival     No. of
    Name                                                   Type       Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------
    clks_rsts_mgment.general_poreset.value[23]             FDRE       Q        Out     0.585     5.140       -
    clks_rsts_mgment.general_poreset.value_qxu[23]         Net        -        -       0.935     -           2
    clks_rsts_mgment.general_poreset.value_RNIBN28[23]     LUT3       I0       In      -         6.075       -
    clks_rsts_mgment.general_poreset.value_RNIBN28[23]     LUT3       O        Out     0.427     6.502       -
    m11_0_a2_2                                             Net        -        -       0.910     -           2
    clks_rsts_mgment.general_poreset.value_RNIUV8Q[20]     LUT6_L     I5       In      -         7.412       -
    clks_rsts_mgment.general_poreset.value_RNIUV8Q[20]     LUT6_L     LO       Out     0.195     7.608       -
    N_2251                                                 Net        -        -       1.050     -           1
    clks_rsts_mgment.gral_incr_RNIIVJI3                    LUT6       I5       In      -         8.658       -
    clks_rsts_mgment.gral_incr_RNIIVJI3                    LUT6       O        Out     0.287     8.945       -
    N_10_i                                                 Net        -        -       1.283     -           32
    clks_rsts_mgment.general_poreset.value[0]              FDRE       CE       In      -         10.228      -
    ===================================================================================================================
    Total path delay (propagation time + setup) of 5.971 is 1.793(30.0%) logic and 4.178(70.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Start clock path:

    Instance / Net                                                        Pin            Pin               Arrival     No. of
    Name                                           Type                   Name           Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------
    Start Clock :                                  top_tdc|spec_clk_i
    ------------
    spec_clk_i                                     Port                   spec_clk_i     In      -         0.000       -
    spec_clk_i                                     Net                    -              -       0.000     -           1
    clks_rsts_mgment.spec_clk_ibuf                 IBUFG                  I              In      -         0.000       -
    clks_rsts_mgment.spec_clk_ibuf                 IBUFG                  O              Out     1.290     1.290       -
    clks_rsts_mgment.spec_clk_buf                  Net                    -              -       1.304     -           1
    clks_rsts_mgment.spec_clk_gbuf                 BUFG                   I              In      -         2.594       -
    clks_rsts_mgment.spec_clk_gbuf                 BUFG                   O              Out     0.250     2.844       -
    spec_clk_i_0                                   Net                    -              -       1.711     -           0
    clks_rsts_mgment.general_poreset.value[23]     FDRE                   C              In      -         4.555       -
    =============================================================================================================================

    End clock path:

    Instance / Net                                                       Pin            Pin               Arrival     No. of
    Name                                          Type                   Name           Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------------------------------
    Start Clock :                                 top_tdc|spec_clk_i
    ------------
    spec_clk_i                                    Port                   spec_clk_i     In      -         0.000       -
    spec_clk_i                                    Net                    -              -       0.000     -           1
    clks_rsts_mgment.spec_clk_ibuf                IBUFG                  I              In      -         0.000       -
    clks_rsts_mgment.spec_clk_ibuf                IBUFG                  O              Out     1.290     1.290       -
    clks_rsts_mgment.spec_clk_buf                 Net                    -              -       1.304     -           1
    clks_rsts_mgment.spec_clk_gbuf                BUFG                   I              In      -         2.594       -
    clks_rsts_mgment.spec_clk_gbuf                BUFG                   O              Out     0.250     2.844       -
    spec_clk_i_0                                  Net                    -              -       1.711     -           0
    clks_rsts_mgment.general_poreset.value[0]     FDRE                   C              In      -         4.555       -
    ============================================================================================================================

    Path information for path number 2:
          Requested Period:                      5.000
        - Setup time:                            0.298
        + Clock delay at ending point:           4.555
        = Required time:                         9.257

        - Propagation time:                      5.673
        - Clock delay at starting point:         4.555
        = Slack (non-critical) :                 -0.971

        Number of logic level(s):                3
        Starting point:                          clks_rsts_mgment.general_poreset.value[25] / Q
        Ending point:                            clks_rsts_mgment.general_poreset.value[0] / CE
        The start point is clocked by            top_tdc|spec_clk_i [rising] on pin C
        The end   point is clocked by            top_tdc|spec_clk_i [rising] on pin C

    Instance / Net                                                    Pin      Pin               Arrival     No. of
    Name                                                   Type       Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------
    clks_rsts_mgment.general_poreset.value[25]             FDRE       Q        Out     0.585     5.140       -
    clks_rsts_mgment.general_poreset.value_qxu[25]         Net        -        -       0.935     -           2
    clks_rsts_mgment.general_poreset.value_RNIBN28[23]     LUT3       I1       In      -         6.075       -
    clks_rsts_mgment.general_poreset.value_RNIBN28[23]     LUT3       O        Out     0.427     6.502       -
    m11_0_a2_2                                             Net        -        -       0.910     -           2
    clks_rsts_mgment.general_poreset.value_RNIUV8Q[20]     LUT6_L     I5       In      -         7.412       -
    clks_rsts_mgment.general_poreset.value_RNIUV8Q[20]     LUT6_L     LO       Out     0.195     7.608       -
    N_2251                                                 Net        -        -       1.050     -           1
    clks_rsts_mgment.gral_incr_RNIIVJI3                    LUT6       I5       In      -         8.658       -
    clks_rsts_mgment.gral_incr_RNIIVJI3                    LUT6       O        Out     0.287     8.945       -
    N_10_i                                                 Net        -        -       1.283     -           32
    clks_rsts_mgment.general_poreset.value[0]              FDRE       CE       In      -         10.228      -
    ===================================================================================================================
    Total path delay (propagation time + setup) of 5.971 is 1.793(30.0%) logic and 4.178(70.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Start clock path:

    Instance / Net                                                        Pin            Pin               Arrival     No. of
    Name                                           Type                   Name           Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------
    Start Clock :                                  top_tdc|spec_clk_i
    ------------
    spec_clk_i                                     Port                   spec_clk_i     In      -         0.000       -
    spec_clk_i                                     Net                    -              -       0.000     -           1
    clks_rsts_mgment.spec_clk_ibuf                 IBUFG                  I              In      -         0.000       -
    clks_rsts_mgment.spec_clk_ibuf                 IBUFG                  O              Out     1.290     1.290       -
    clks_rsts_mgment.spec_clk_buf                  Net                    -              -       1.304     -           1
    clks_rsts_mgment.spec_clk_gbuf                 BUFG                   I              In      -         2.594       -
    clks_rsts_mgment.spec_clk_gbuf                 BUFG                   O              Out     0.250     2.844       -
    spec_clk_i_0                                   Net                    -              -       1.711     -           0
    clks_rsts_mgment.general_poreset.value[25]     FDRE                   C              In      -         4.555       -
    =============================================================================================================================

    End clock path:

    Instance / Net                                                       Pin            Pin               Arrival     No. of
    Name                                          Type                   Name           Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------------------------------
    Start Clock :                                 top_tdc|spec_clk_i
    ------------
    spec_clk_i                                    Port                   spec_clk_i     In      -         0.000       -
    spec_clk_i                                    Net                    -              -       0.000     -           1
    clks_rsts_mgment.spec_clk_ibuf                IBUFG                  I              In      -         0.000       -
    clks_rsts_mgment.spec_clk_ibuf                IBUFG                  O              Out     1.290     1.290       -
    clks_rsts_mgment.spec_clk_buf                 Net                    -              -       1.304     -           1
    clks_rsts_mgment.spec_clk_gbuf                BUFG                   I              In      -         2.594       -
    clks_rsts_mgment.spec_clk_gbuf                BUFG                   O              Out     0.250     2.844       -
    spec_clk_i_0                                  Net                    -              -       1.711     -           0
    clks_rsts_mgment.general_poreset.value[0]     FDRE                   C              In      -         4.555       -
    ============================================================================================================================

    Path information for path number 3:
          Requested Period:                      5.000
        - Setup time:                            0.298
        + Clock delay at ending point:           4.555
        = Required time:                         9.257

        - Propagation time:                      5.673
        - Clock delay at starting point:         4.555
        = Slack (non-critical) :                 -0.971

        Number of logic level(s):                3
        Starting point:                          clks_rsts_mgment.general_poreset.value[26] / Q
        Ending point:                            clks_rsts_mgment.general_poreset.value[0] / CE
        The start point is clocked by            top_tdc|spec_clk_i [rising] on pin C
        The end   point is clocked by            top_tdc|spec_clk_i [rising] on pin C

    Instance / Net                                                    Pin      Pin               Arrival     No. of
    Name                                                   Type       Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------
    clks_rsts_mgment.general_poreset.value[26]             FDRE       Q        Out     0.585     5.140       -
    clks_rsts_mgment.general_poreset.value_qxu[26]         Net        -        -       0.935     -           2
    clks_rsts_mgment.general_poreset.value_RNIBN28[23]     LUT3       I2       In      -         6.075       -
    clks_rsts_mgment.general_poreset.value_RNIBN28[23]     LUT3       O        Out     0.427     6.502       -
    m11_0_a2_2                                             Net        -        -       0.910     -           2
    clks_rsts_mgment.general_poreset.value_RNIUV8Q[20]     LUT6_L     I5       In      -         7.412       -
    clks_rsts_mgment.general_poreset.value_RNIUV8Q[20]     LUT6_L     LO       Out     0.195     7.608       -
    N_2251                                                 Net        -        -       1.050     -           1
    clks_rsts_mgment.gral_incr_RNIIVJI3                    LUT6       I5       In      -         8.658       -
    clks_rsts_mgment.gral_incr_RNIIVJI3                    LUT6       O        Out     0.287     8.945       -
    N_10_i                                                 Net        -        -       1.283     -           32
    clks_rsts_mgment.general_poreset.value[0]              FDRE       CE       In      -         10.228      -
    ===================================================================================================================
    Total path delay (propagation time + setup) of 5.971 is 1.793(30.0%) logic and 4.178(70.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Start clock path:

    Instance / Net                                                        Pin            Pin               Arrival     No. of
    Name                                           Type                   Name           Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------
    Start Clock :                                  top_tdc|spec_clk_i
    ------------
    spec_clk_i                                     Port                   spec_clk_i     In      -         0.000       -
    spec_clk_i                                     Net                    -              -       0.000     -           1
    clks_rsts_mgment.spec_clk_ibuf                 IBUFG                  I              In      -         0.000       -
    clks_rsts_mgment.spec_clk_ibuf                 IBUFG                  O              Out     1.290     1.290       -
    clks_rsts_mgment.spec_clk_buf                  Net                    -              -       1.304     -           1
    clks_rsts_mgment.spec_clk_gbuf                 BUFG                   I              In      -         2.594       -
    clks_rsts_mgment.spec_clk_gbuf                 BUFG                   O              Out     0.250     2.844       -
    spec_clk_i_0                                   Net                    -              -       1.711     -           0
    clks_rsts_mgment.general_poreset.value[26]     FDRE                   C              In      -         4.555       -
    =============================================================================================================================

    End clock path:

    Instance / Net                                                       Pin            Pin               Arrival     No. of
    Name                                          Type                   Name           Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------------------------------
    Start Clock :                                 top_tdc|spec_clk_i
    ------------
    spec_clk_i                                    Port                   spec_clk_i     In      -         0.000       -
    spec_clk_i                                    Net                    -              -       0.000     -           1
    clks_rsts_mgment.spec_clk_ibuf                IBUFG                  I              In      -         0.000       -
    clks_rsts_mgment.spec_clk_ibuf                IBUFG                  O              Out     1.290     1.290       -
    clks_rsts_mgment.spec_clk_buf                 Net                    -              -       1.304     -           1
    clks_rsts_mgment.spec_clk_gbuf                BUFG                   I              In      -         2.594       -
    clks_rsts_mgment.spec_clk_gbuf                BUFG                   O              Out     0.250     2.844       -
    spec_clk_i_0                                  Net                    -              -       1.711     -           0
    clks_rsts_mgment.general_poreset.value[0]     FDRE                   C              In      -         4.555       -
    ============================================================================================================================

    Path information for path number 4:
          Requested Period:                      5.000
        - Setup time:                            0.298
        + Clock delay at ending point:           4.555
        = Required time:                         9.257

        - Propagation time:                      5.673
        - Clock delay at starting point:         4.555
        = Slack (non-critical) :                 -0.971

        Number of logic level(s):                3
        Starting point:                          clks_rsts_mgment.general_poreset.value[23] / Q
        Ending point:                            clks_rsts_mgment.general_poreset.value[31] / CE
        The start point is clocked by            top_tdc|spec_clk_i [rising] on pin C
        The end   point is clocked by            top_tdc|spec_clk_i [rising] on pin C

    Instance / Net                                                    Pin      Pin               Arrival     No. of
    Name                                                   Type       Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------
    clks_rsts_mgment.general_poreset.value[23]             FDRE       Q        Out     0.585     5.140       -
    clks_rsts_mgment.general_poreset.value_qxu[23]         Net        -        -       0.935     -           2
    clks_rsts_mgment.general_poreset.value_RNIBN28[23]     LUT3       I0       In      -         6.075       -
    clks_rsts_mgment.general_poreset.value_RNIBN28[23]     LUT3       O        Out     0.427     6.502       -
    m11_0_a2_2                                             Net        -        -       0.910     -           2
    clks_rsts_mgment.general_poreset.value_RNIUV8Q[20]     LUT6_L     I5       In      -         7.412       -
    clks_rsts_mgment.general_poreset.value_RNIUV8Q[20]     LUT6_L     LO       Out     0.195     7.608       -
    N_2251                                                 Net        -        -       1.050     -           1
    clks_rsts_mgment.gral_incr_RNIIVJI3                    LUT6       I5       In      -         8.658       -
    clks_rsts_mgment.gral_incr_RNIIVJI3                    LUT6       O        Out     0.287     8.945       -
    N_10_i                                                 Net        -        -       1.283     -           32
    clks_rsts_mgment.general_poreset.value[31]             FDRE       CE       In      -         10.228      -
    ===================================================================================================================
    Total path delay (propagation time + setup) of 5.971 is 1.793(30.0%) logic and 4.178(70.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Start clock path:

    Instance / Net                                                        Pin            Pin               Arrival     No. of
    Name                                           Type                   Name           Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------
    Start Clock :                                  top_tdc|spec_clk_i
    ------------
    spec_clk_i                                     Port                   spec_clk_i     In      -         0.000       -
    spec_clk_i                                     Net                    -              -       0.000     -           1
    clks_rsts_mgment.spec_clk_ibuf                 IBUFG                  I              In      -         0.000       -
    clks_rsts_mgment.spec_clk_ibuf                 IBUFG                  O              Out     1.290     1.290       -
    clks_rsts_mgment.spec_clk_buf                  Net                    -              -       1.304     -           1
    clks_rsts_mgment.spec_clk_gbuf                 BUFG                   I              In      -         2.594       -
    clks_rsts_mgment.spec_clk_gbuf                 BUFG                   O              Out     0.250     2.844       -
    spec_clk_i_0                                   Net                    -              -       1.711     -           0
    clks_rsts_mgment.general_poreset.value[23]     FDRE                   C              In      -         4.555       -
    =============================================================================================================================

    End clock path:

    Instance / Net                                                        Pin            Pin               Arrival     No. of
    Name                                           Type                   Name           Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------
    Start Clock :                                  top_tdc|spec_clk_i
    ------------
    spec_clk_i                                     Port                   spec_clk_i     In      -         0.000       -
    spec_clk_i                                     Net                    -              -       0.000     -           1
    clks_rsts_mgment.spec_clk_ibuf                 IBUFG                  I              In      -         0.000       -
    clks_rsts_mgment.spec_clk_ibuf                 IBUFG                  O              Out     1.290     1.290       -
    clks_rsts_mgment.spec_clk_buf                  Net                    -              -       1.304     -           1
    clks_rsts_mgment.spec_clk_gbuf                 BUFG                   I              In      -         2.594       -
    clks_rsts_mgment.spec_clk_gbuf                 BUFG                   O              Out     0.250     2.844       -
    spec_clk_i_0                                   Net                    -              -       1.711     -           0
    clks_rsts_mgment.general_poreset.value[31]     FDRE                   C              In      -         4.555       -
    =============================================================================================================================

    Path information for path number 5:
          Requested Period:                      5.000
        - Setup time:                            0.298
        + Clock delay at ending point:           4.555
        = Required time:                         9.257

        - Propagation time:                      5.673
        - Clock delay at starting point:         4.555
        = Slack (non-critical) :                 -0.971

        Number of logic level(s):                3
        Starting point:                          clks_rsts_mgment.general_poreset.value[23] / Q
        Ending point:                            clks_rsts_mgment.general_poreset.value[30] / CE
        The start point is clocked by            top_tdc|spec_clk_i [rising] on pin C
        The end   point is clocked by            top_tdc|spec_clk_i [rising] on pin C

    Instance / Net                                                    Pin      Pin               Arrival     No. of
    Name                                                   Type       Name     Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------
    clks_rsts_mgment.general_poreset.value[23]             FDRE       Q        Out     0.585     5.140       -
    clks_rsts_mgment.general_poreset.value_qxu[23]         Net        -        -       0.935     -           2
    clks_rsts_mgment.general_poreset.value_RNIBN28[23]     LUT3       I0       In      -         6.075       -
    clks_rsts_mgment.general_poreset.value_RNIBN28[23]     LUT3       O        Out     0.427     6.502       -
    m11_0_a2_2                                             Net        -        -       0.910     -           2
    clks_rsts_mgment.general_poreset.value_RNIUV8Q[20]     LUT6_L     I5       In      -         7.412       -
    clks_rsts_mgment.general_poreset.value_RNIUV8Q[20]     LUT6_L     LO       Out     0.195     7.608       -
    N_2251                                                 Net        -        -       1.050     -           1
    clks_rsts_mgment.gral_incr_RNIIVJI3                    LUT6       I5       In      -         8.658       -
    clks_rsts_mgment.gral_incr_RNIIVJI3                    LUT6       O        Out     0.287     8.945       -
    N_10_i                                                 Net        -        -       1.283     -           32
    clks_rsts_mgment.general_poreset.value[30]             FDRE       CE       In      -         10.228      -
    ===================================================================================================================
    Total path delay (propagation time + setup) of 5.971 is 1.793(30.0%) logic and 4.178(70.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Start clock path:

    Instance / Net                                                        Pin            Pin               Arrival     No. of
    Name                                           Type                   Name           Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------
    Start Clock :                                  top_tdc|spec_clk_i
    ------------
    spec_clk_i                                     Port                   spec_clk_i     In      -         0.000       -
    spec_clk_i                                     Net                    -              -       0.000     -           1
    clks_rsts_mgment.spec_clk_ibuf                 IBUFG                  I              In      -         0.000       -
    clks_rsts_mgment.spec_clk_ibuf                 IBUFG                  O              Out     1.290     1.290       -
    clks_rsts_mgment.spec_clk_buf                  Net                    -              -       1.304     -           1
    clks_rsts_mgment.spec_clk_gbuf                 BUFG                   I              In      -         2.594       -
    clks_rsts_mgment.spec_clk_gbuf                 BUFG                   O              Out     0.250     2.844       -
    spec_clk_i_0                                   Net                    -              -       1.711     -           0
    clks_rsts_mgment.general_poreset.value[23]     FDRE                   C              In      -         4.555       -
    =============================================================================================================================

    End clock path:

    Instance / Net                                                        Pin            Pin               Arrival     No. of
    Name                                           Type                   Name           Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------
    Start Clock :                                  top_tdc|spec_clk_i
    ------------
    spec_clk_i                                     Port                   spec_clk_i     In      -         0.000       -
    spec_clk_i                                     Net                    -              -       0.000     -           1
    clks_rsts_mgment.spec_clk_ibuf                 IBUFG                  I              In      -         0.000       -
    clks_rsts_mgment.spec_clk_ibuf                 IBUFG                  O              Out     1.290     1.290       -
    clks_rsts_mgment.spec_clk_buf                  Net                    -              -       1.304     -           1
    clks_rsts_mgment.spec_clk_gbuf                 BUFG                   I              In      -         2.594       -
    clks_rsts_mgment.spec_clk_gbuf                 BUFG                   O              Out     0.250     2.844       -
    spec_clk_i_0                                   Net                    -              -       1.711     -           0
    clks_rsts_mgment.general_poreset.value[30]     FDRE                   C              In      -         4.555       -
    =============================================================================================================================

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                   Starting                                                      Arrival
    Instance                       Reference     Type     Pin     Net                            Time        Slack
                                   Clock
    --------------------------------------------------------------------------------------------------------------
    clks_rsts_mgment.gral_incr     System        FDC      Q       clks_rsts_mgment.gral_incr     0.585       1.045
    ==============================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                  Starting                                  Required
    Instance                                      Reference     Type     Pin     Net        Time         Slack
                                                  Clock
    ----------------------------------------------------------------------------------------------------------
    clks_rsts_mgment.general_poreset.value[0]     System        FDRE     CE      N_10_i     4.702        1.045
    clks_rsts_mgment.general_poreset.value[1]     System        FDRE     CE      N_10_i     4.702        1.045
    clks_rsts_mgment.general_poreset.value[2]     System        FDRE     CE      N_10_i     4.702        1.045
    clks_rsts_mgment.general_poreset.value[3]     System        FDRE     CE      N_10_i     4.702        1.045
    clks_rsts_mgment.general_poreset.value[4]     System        FDRE     CE      N_10_i     4.702        1.045
    clks_rsts_mgment.general_poreset.value[5]     System        FDRE     CE      N_10_i     4.702        1.045
    clks_rsts_mgment.general_poreset.value[6]     System        FDRE     CE      N_10_i     4.702        1.045
    clks_rsts_mgment.general_poreset.value[7]     System        FDRE     CE      N_10_i     4.702        1.045
    clks_rsts_mgment.general_poreset.value[8]     System        FDRE     CE      N_10_i     4.702        1.045
    clks_rsts_mgment.general_poreset.value[9]     System        FDRE     CE      N_10_i     4.702        1.045
    ==========================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      5.000
        - Setup time:                            0.298
        + Clock delay at ending point:           4.555
        = Required time:                         9.257

        - Propagation time:                      3.657
        - Estimated clock delay at start point:  4.555
        = Slack (non-critical) :                 1.045

        Number of logic level(s):                1
        Starting point:                          clks_rsts_mgment.gral_incr / Q
        Ending point:                            clks_rsts_mgment.general_poreset.value[0] / CE
        The start point is clocked by            System [rising] on pin C
        The end   point is clocked by            top_tdc|spec_clk_i [rising] on pin C

    Instance / Net                                         Pin      Pin               Arrival     No. of
    Name                                          Type     Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------------------
    clks_rsts_mgment.gral_incr                    FDC      Q        Out     0.585     0.585       -
    clks_rsts_mgment.gral_incr                    Net      -        -       0.935     -           2
    clks_rsts_mgment.gral_incr_RNIIVJI3           LUT6     I0       In      -         1.520       -
    clks_rsts_mgment.gral_incr_RNIIVJI3           LUT6     O        Out     0.854     2.374       -
    N_10_i                                        Net      -        -       1.283     -           32
    clks_rsts_mgment.general_poreset.value[0]     FDRE     CE       In      -         3.657       -
    ========================================================================================================
    Total path delay (propagation time + setup) of 3.955 is 1.737(43.9%) logic and 2.218(56.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Start clock path:

    Instance / Net                          Pin      Pin               Arrival     No. of
    Name                           Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------
    clk_i                          Net      -        -       0.000     -           0
    clks_rsts_mgment.gral_incr     FDC      C        In      -         0.000       -
    =========================================================================================

    End clock path:

    Instance / Net                                                       Pin            Pin               Arrival     No. of
    Name                                          Type                   Name           Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------------------------------
    Start Clock :                                 top_tdc|spec_clk_i
    ------------
    spec_clk_i                                    Port                   spec_clk_i     In      -         0.000       -
    spec_clk_i                                    Net                    -              -       0.000     -           1
    clks_rsts_mgment.spec_clk_ibuf                IBUFG                  I              In      -         0.000       -
    clks_rsts_mgment.spec_clk_ibuf                IBUFG                  O              Out     1.290     1.290       -
    clks_rsts_mgment.spec_clk_buf                 Net                    -              -       1.304     -           1
    clks_rsts_mgment.spec_clk_gbuf                BUFG                   I              In      -         2.594       -
    clks_rsts_mgment.spec_clk_gbuf                BUFG                   O              Out     0.250     2.844       -
    spec_clk_i_0                                  Net                    -              -       1.711     -           0
    clks_rsts_mgment.general_poreset.value[0]     FDRE                   C              In      -         4.555       -
    ============================================================================================================================

    Path information for path number 2:
          Requested Period:                      5.000
        - Setup time:                            0.298
        + Clock delay at ending point:           4.555
        = Required time:                         9.257

        - Propagation time:                      3.657
        - Estimated clock delay at start point:  4.555
        = Slack (non-critical) :                 1.045

        Number of logic level(s):                1
        Starting point:                          clks_rsts_mgment.gral_incr / Q
        Ending point:                            clks_rsts_mgment.general_poreset.value[31] / CE
        The start point is clocked by            System [rising] on pin C
        The end   point is clocked by            top_tdc|spec_clk_i [rising] on pin C

    Instance / Net                                          Pin      Pin               Arrival     No. of
    Name                                           Type     Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------
    clks_rsts_mgment.gral_incr                     FDC      Q        Out     0.585     0.585       -
    clks_rsts_mgment.gral_incr                     Net      -        -       0.935     -           2
    clks_rsts_mgment.gral_incr_RNIIVJI3            LUT6     I0       In      -         1.520       -
    clks_rsts_mgment.gral_incr_RNIIVJI3            LUT6     O        Out     0.854     2.374       -
    N_10_i                                         Net      -        -       1.283     -           32
    clks_rsts_mgment.general_poreset.value[31]     FDRE     CE       In      -         3.657       -
    =========================================================================================================
    Total path delay (propagation time + setup) of 3.955 is 1.737(43.9%) logic and 2.218(56.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Start clock path:

    Instance / Net                          Pin      Pin               Arrival     No. of
    Name                           Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------
    clk_i                          Net      -        -       0.000     -           0
    clks_rsts_mgment.gral_incr     FDC      C        In      -         0.000       -
    =========================================================================================

    End clock path:

    Instance / Net                                                        Pin            Pin               Arrival     No. of
    Name                                           Type                   Name           Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------
    Start Clock :                                  top_tdc|spec_clk_i
    ------------
    spec_clk_i                                     Port                   spec_clk_i     In      -         0.000       -
    spec_clk_i                                     Net                    -              -       0.000     -           1
    clks_rsts_mgment.spec_clk_ibuf                 IBUFG                  I              In      -         0.000       -
    clks_rsts_mgment.spec_clk_ibuf                 IBUFG                  O              Out     1.290     1.290       -
    clks_rsts_mgment.spec_clk_buf                  Net                    -              -       1.304     -           1
    clks_rsts_mgment.spec_clk_gbuf                 BUFG                   I              In      -         2.594       -
    clks_rsts_mgment.spec_clk_gbuf                 BUFG                   O              Out     0.250     2.844       -
    spec_clk_i_0                                   Net                    -              -       1.711     -           0
    clks_rsts_mgment.general_poreset.value[31]     FDRE                   C              In      -         4.555       -
    =============================================================================================================================

    Path information for path number 3:
          Requested Period:                      5.000
        - Setup time:                            0.298
        + Clock delay at ending point:           4.555
        = Required time:                         9.257

        - Propagation time:                      3.657
        - Estimated clock delay at start point:  4.555
        = Slack (non-critical) :                 1.045

        Number of logic level(s):                1
        Starting point:                          clks_rsts_mgment.gral_incr / Q
        Ending point:                            clks_rsts_mgment.general_poreset.value[30] / CE
        The start point is clocked by            System [rising] on pin C
        The end   point is clocked by            top_tdc|spec_clk_i [rising] on pin C

    Instance / Net                                          Pin      Pin               Arrival     No. of
    Name                                           Type     Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------
    clks_rsts_mgment.gral_incr                     FDC      Q        Out     0.585     0.585       -
    clks_rsts_mgment.gral_incr                     Net      -        -       0.935     -           2
    clks_rsts_mgment.gral_incr_RNIIVJI3            LUT6     I0       In      -         1.520       -
    clks_rsts_mgment.gral_incr_RNIIVJI3            LUT6     O        Out     0.854     2.374       -
    N_10_i                                         Net      -        -       1.283     -           32
    clks_rsts_mgment.general_poreset.value[30]     FDRE     CE       In      -         3.657       -
    =========================================================================================================
    Total path delay (propagation time + setup) of 3.955 is 1.737(43.9%) logic and 2.218(56.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Start clock path:

    Instance / Net                          Pin      Pin               Arrival     No. of
    Name                           Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------
    clk_i                          Net      -        -       0.000     -           0
    clks_rsts_mgment.gral_incr     FDC      C        In      -         0.000       -
    =========================================================================================

    End clock path:

    Instance / Net                                                        Pin            Pin               Arrival     No. of
    Name                                           Type                   Name           Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------
    Start Clock :                                  top_tdc|spec_clk_i
    ------------
    spec_clk_i                                     Port                   spec_clk_i     In      -         0.000       -
    spec_clk_i                                     Net                    -              -       0.000     -           1
    clks_rsts_mgment.spec_clk_ibuf                 IBUFG                  I              In      -         0.000       -
    clks_rsts_mgment.spec_clk_ibuf                 IBUFG                  O              Out     1.290     1.290       -
    clks_rsts_mgment.spec_clk_buf                  Net                    -              -       1.304     -           1
    clks_rsts_mgment.spec_clk_gbuf                 BUFG                   I              In      -         2.594       -
    clks_rsts_mgment.spec_clk_gbuf                 BUFG                   O              Out     0.250     2.844       -
    spec_clk_i_0                                   Net                    -              -       1.711     -           0
    clks_rsts_mgment.general_poreset.value[30]     FDRE                   C              In      -         4.555       -
    =============================================================================================================================

    Path information for path number 4:
          Requested Period:                      5.000
        - Setup time:                            0.298
        + Clock delay at ending point:           4.555
        = Required time:                         9.257

        - Propagation time:                      3.657
        - Estimated clock delay at start point:  4.555
        = Slack (non-critical) :                 1.045

        Number of logic level(s):                1
        Starting point:                          clks_rsts_mgment.gral_incr / Q
        Ending point:                            clks_rsts_mgment.general_poreset.value[29] / CE
        The start point is clocked by            System [rising] on pin C
        The end   point is clocked by            top_tdc|spec_clk_i [rising] on pin C

    Instance / Net                                          Pin      Pin               Arrival     No. of
    Name                                           Type     Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------
    clks_rsts_mgment.gral_incr                     FDC      Q        Out     0.585     0.585       -
    clks_rsts_mgment.gral_incr                     Net      -        -       0.935     -           2
    clks_rsts_mgment.gral_incr_RNIIVJI3            LUT6     I0       In      -         1.520       -
    clks_rsts_mgment.gral_incr_RNIIVJI3            LUT6     O        Out     0.854     2.374       -
    N_10_i                                         Net      -        -       1.283     -           32
    clks_rsts_mgment.general_poreset.value[29]     FDRE     CE       In      -         3.657       -
    =========================================================================================================
    Total path delay (propagation time + setup) of 3.955 is 1.737(43.9%) logic and 2.218(56.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Start clock path:

    Instance / Net                          Pin      Pin               Arrival     No. of
    Name                           Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------
    clk_i                          Net      -        -       0.000     -           0
    clks_rsts_mgment.gral_incr     FDC      C        In      -         0.000       -
    =========================================================================================

    End clock path:

    Instance / Net                                                        Pin            Pin               Arrival     No. of
    Name                                           Type                   Name           Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------
    Start Clock :                                  top_tdc|spec_clk_i
    ------------
    spec_clk_i                                     Port                   spec_clk_i     In      -         0.000       -
    spec_clk_i                                     Net                    -              -       0.000     -           1
    clks_rsts_mgment.spec_clk_ibuf                 IBUFG                  I              In      -         0.000       -
    clks_rsts_mgment.spec_clk_ibuf                 IBUFG                  O              Out     1.290     1.290       -
    clks_rsts_mgment.spec_clk_buf                  Net                    -              -       1.304     -           1
    clks_rsts_mgment.spec_clk_gbuf                 BUFG                   I              In      -         2.594       -
    clks_rsts_mgment.spec_clk_gbuf                 BUFG                   O              Out     0.250     2.844       -
    spec_clk_i_0                                   Net                    -              -       1.711     -           0
    clks_rsts_mgment.general_poreset.value[29]     FDRE                   C              In      -         4.555       -
    =============================================================================================================================

    Path information for path number 5:
          Requested Period:                      5.000
        - Setup time:                            0.298
        + Clock delay at ending point:           4.555
        = Required time:                         9.257

        - Propagation time:                      3.657
        - Estimated clock delay at start point:  4.555
        = Slack (non-critical) :                 1.045

        Number of logic level(s):                1
        Starting point:                          clks_rsts_mgment.gral_incr / Q
        Ending point:                            clks_rsts_mgment.general_poreset.value[28] / CE
        The start point is clocked by            System [rising] on pin C
        The end   point is clocked by            top_tdc|spec_clk_i [rising] on pin C

    Instance / Net                                          Pin      Pin               Arrival     No. of
    Name                                           Type     Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------
    clks_rsts_mgment.gral_incr                     FDC      Q        Out     0.585     0.585       -
    clks_rsts_mgment.gral_incr                     Net      -        -       0.935     -           2
    clks_rsts_mgment.gral_incr_RNIIVJI3            LUT6     I0       In      -         1.520       -
    clks_rsts_mgment.gral_incr_RNIIVJI3            LUT6     O        Out     0.854     2.374       -
    N_10_i                                         Net      -        -       1.283     -           32
    clks_rsts_mgment.general_poreset.value[28]     FDRE     CE       In      -         3.657       -
    =========================================================================================================
    Total path delay (propagation time + setup) of 3.955 is 1.737(43.9%) logic and 2.218(56.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Start clock path:

    Instance / Net                          Pin      Pin               Arrival     No. of
    Name                           Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------
    clk_i                          Net      -        -       0.000     -           0
    clks_rsts_mgment.gral_incr     FDC      C        In      -         0.000       -
    =========================================================================================

    End clock path:

    Instance / Net                                                        Pin            Pin               Arrival     No. of
    Name                                           Type                   Name           Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------
    Start Clock :                                  top_tdc|spec_clk_i
    ------------
    spec_clk_i                                     Port                   spec_clk_i     In      -         0.000       -
    spec_clk_i                                     Net                    -              -       0.000     -           1
    clks_rsts_mgment.spec_clk_ibuf                 IBUFG                  I              In      -         0.000       -
    clks_rsts_mgment.spec_clk_ibuf                 IBUFG                  O              Out     1.290     1.290       -
    clks_rsts_mgment.spec_clk_buf                  Net                    -              -       1.304     -           1
    clks_rsts_mgment.spec_clk_gbuf                 BUFG                   I              In      -         2.594       -
    clks_rsts_mgment.spec_clk_gbuf                 BUFG                   O              Out     0.250     2.844       -
    spec_clk_i_0                                   Net                    -              -       1.711     -           0
    clks_rsts_mgment.general_poreset.value[28]     FDRE                   C              In      -         4.555       -
    =============================================================================================================================

    ##### END OF TIMING REPORT #####]

    ---------------------------------------
    Resource Usage Report for top_tdc

    Mapping to part: xc6slx45tfgg484-2
    Cell usage:
    DSP48A1         1 use
    FD              13 uses
    FDC             1 use
    FDR             23 uses
    FDRE            34 uses
    FDS             21 uses
    GND             1 use
    MUXCY_L         70 uses
    RAMB8BWER       1 use
    VCC             1 use
    XORCY           71 uses
    LUT1            63 uses
    LUT2            18 uses
    LUT3            16 uses
    LUT4            8 uses
    LUT5            37 uses
    LUT6            35 uses
    LUT6_2            1 use

    I/O ports: 135
    I/O primitives: 66
    IBUF           4 uses
    IBUFDS         1 use
    IBUFG          1 use
    OBUF           60 uses

    BUFG           2 uses

    I/O Register bits:                  6
    Register bits not including I/Os:   86 (0%)

    RAM/ROM usage summary
    Block Rams : 1 of 116 (0%)

    DSP48s: 1 of 58 (1%)

    Global Clock Buffers: 2 of 16 (12%)

     Number of unique control sets:              9
     C(spec_clk_i_0), CLR(GND), PRE(GND), CE(VCC)		: 11
     C(clk_i), CLR(pll_sclk_i), PRE(GND), CE(VCC)		: 1
     C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(VCC)		: 2
     C(spec_clk), R(N_132_i_iso), S(GND), CE(VCC)		: 2
     C(clk), R(GND), S(N_51_i), CE(VCC)		: 17
     C(clk), R(N_51_i), S(GND), CE(VCC)		: 15
     C(spec_clk_i_0), R(N_132_i_iso), S(GND), CE(N_10_i)		: 32
     C(spec_clk_i_0), R(N_132_i_iso), S(GND), CE(VCC)		: 2
     C(spec_clk_i_0), R(GND), S(N_132_i_iso), CE(VCC)		: 4

    Total load per clock:
       top_tdc|spec_clk_i: 53
       spec_clk20: 5
       tdc_clk125: 36

    Mapping Summary:
    Total  LUTs: 178 (0%)

    Mapper successful!
    Process took 0h:00m:03s realtime, 0h:00m:03s cputime
    # Fri Jul 15 19:30:57 2011

    ###########################################################]

`