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FMC TDC 1ns 5cha - Gateware
Commit 0724de2e authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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.gitmodules
View file @ 0724de2e
......@@ -10,6 +10,6 @@
[submodule "hdl/ip_cores/gn4124-core"]
path = hdl/ip_cores/gn4124-core
url = git://ohwr.org/hdl-core-lib/gn4124-core.git
[submodule "hdl/ip_cores/etherbone-core"]
path = hdl/ip_cores/etherbone-core
url = git://ohwr.org/hdl-core-lib/etherbone-core.git
[submodule "hdl/ip_cores/ddr3-sp6-core"]
path = hdl/ip_cores/ddr3-sp6-core
url = git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git
ddr3-sp6-core @ 50317193
Subproject commit 503171933f184ae878836f28e67a78a7c81b4325
hdl/rtl/Manifest.py
View file @ 0724de2e
files = [
"tdc_core_pkg.vhd",
"acam_databus_interface.vhd",
"acam_timecontrol_interface.vhd",
"carrier_info.vhd",
"clks_rsts_manager.vhd",
"data_engine.vhd",
"data_formatting.vhd",
"decr_counter.vhd",
"fmc_tdc_core.vhd",
"fmc_tdc_mezzanine.vhd",
"free_counter.vhd",
"incr_counter.vhd",
"leds_manager.vhd",
"local_pps_gen.vhd",
"reg_ctrl.vhd",
"start_retrig_ctrl.vhd",
"tdc_eic.vhd",
"wrabbit_sync.vhd",
"fmc_tdc_direct_readout.vhd",
"fmc_tdc_direct_readout_slave.vhd",
"fmc_tdc_direct_readout_slave_pkg.vhd",
"fmc_tdc_wrapper.vhd",
"timestamp_fifo.vhd",
"timestamp_fifo_wb.vhd",
"timestamp_fifo_wbgen2_pkg.vhd"
"tdc_core_pkg.vhd",
"acam_databus_interface.vhd",
"acam_timecontrol_interface.vhd",
"carrier_info.vhd",
"clks_rsts_manager.vhd",
"data_engine.vhd",
"data_formatting.vhd",
"decr_counter.vhd",
"fmc_tdc_core.vhd",
"fmc_tdc_mezzanine.vhd",
"free_counter.vhd",
"incr_counter.vhd",
"leds_manager.vhd",
"local_pps_gen.vhd",
"reg_ctrl.vhd",
"start_retrig_ctrl.vhd",
"tdc_eic.vhd",
"wrabbit_sync.vhd",
"fmc_tdc_direct_readout.vhd",
"fmc_tdc_direct_readout_slave.vhd",
"fmc_tdc_direct_readout_slave_pkg.vhd",
"fmc_tdc_wrapper.vhd",
"timestamp_fifo.vhd",
"timestamp_fifo_wb.vhd",
"timestamp_fifo_wbgen2_pkg.vhd",
"timestamp_convert_filter.vhd",
"tdc_dma_channel.vhd",
"tdc_dma_engine.vhd",
"tdc_buffer_control_regs.vhd",
"tdc_buffer_control_regs_wbgen2_pkg.vhd",
"tdc_ts_sub.vhd",
"wbgen2_eic_nomask.vhd"
];
hdl/rtl/build_wb.sh 0 → 100755
View file @ 0724de2e
#!/bin/bash
wbgen2 -V timestamp_fifo_wb.vhd -H record_full -p timestamp_fifo_wbgen2_pkg.vhd -K timestamp_fifo_regs.vh -s defines -C timestamp_fifo_regs.h -D wbgen/timestamp_fifo_wb.html wbgen/timestamp_fifo_wb.wb
wbgen2 -V tdc_buffer_control_regs.vhd -H record_full -p tdc_buffer_control_regs_wbgen2_pkg.vhd -K tdc_buffer_control_regs.vh -s defines -C tdc_buffer_control_regs.h wbgen/tdc_buffer_control_regs.wb
#don't do this, latest wbgen is buggy
wbgen2 -V tdc_eic.vhd -s defines -C tdc_eic.h -D wbgen/tdc_eic.html wbgen/tdc_eic.wb
hdl/rtl/data_formatting.vhd
View file @ 0724de2e
......@@ -62,7 +62,7 @@
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions-- Specific library
use IEEE.NUMERIC_STD.all; -- conversion functions-- Specific library
-- Specific library
library work;
use work.tdc_core_pkg.all; -- definitions of types, constants, entities
......@@ -101,7 +101,7 @@ entity data_formatting is
-- OUTPUTS
timestamp_o : out std_logic_vector(127 downto 0);
timestamp_o : out t_raw_acam_timestamp;
timestamp_valid_o : out std_logic
);
......@@ -137,7 +137,7 @@ architecture rtl of data_formatting is
signal un_current_retrig_from_roll_over : unsigned(31 downto 0);
signal un_acam_fine_time : unsigned(31 downto 0);
signal previous_utc : std_logic_vector(31 downto 0);
signal timestamp_valid_int : std_logic;
signal timestamp_valid_int : std_logic;
--=================================================================================================
-- architecture begin
......@@ -335,14 +335,24 @@ begin
full_timestamp(127 downto 96) <= metadata;
process(clk_i)
begin
if rising_edge(clk_i) then
timestamp_o <= full_timestamp;
timestamp_valid_o <= timestamp_valid_int;
if(timestamp_valid_int = '1') then
timestamp_o.slope <= acam_slope;
timestamp_o.channel <= acam_channel;
timestamp_o.n_bins <= fine_time(16 downto 0);
timestamp_o.coarse <= coarse_time;
timestamp_o.tai <= utc;
timestamp_valid_o <= '1';
else
timestamp_valid_o <= '0';
end if;
end if;
end process;
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
......
hdl/rtl/fmc_tdc_core.vhd
View file @ 0724de2e
......@@ -17,12 +17,6 @@
-- |
-- Figure 1 shows the architecture of this core. |
-- |
-- Each timestamp is a 128-bit word with the following structure: |
-- [31:0] Fine time | each bit represents 81.03 ps |
-- [63:32] Coarse time within the current second | each bit represents 8 ns |
-- [95:64] Local UTC time | each bit represents 1 s |
-- [127:96] Metadata | rising/falling tstamp, Channel |
-- |
-- As the structure indicates, each timestamp is referred to a UTC second; the coarse|
-- and fine time indicate with 81.03 ps resolution the amount of time passed after |
-- the last UTC second. |
......@@ -156,17 +150,19 @@ use work.genram_pkg.all;
--=================================================================================================
entity fmc_tdc_core is
generic
(g_span : integer := 32; -- address span in bus interfaces
g_width : integer := 32; -- data width in bus interfaces
g_simulation : boolean := false); -- this generic is set to TRUE
(g_span : integer := 32; -- address span in bus interfaces
g_width : integer := 32; -- data width in bus interfaces
g_simulation : boolean := false;
g_with_dma_readout : boolean := false;
g_with_fifo_readout : boolean := false); -- this generic is set to TRUE
-- when instantiated in a test-bench
port
(
clk_sys_i : in std_logic;
rst_n_sys_i : in std_logic;
rst_sys_n_i : in std_logic;
clk_tdc_i : in std_logic; -- 125 MHz reference from the PLL
rst_tdc_i : in std_logic; -- global reset, synched to clk_tdc_i
clk_tdc_i : in std_logic; -- 125 MHz reference from the PLL
rst_tdc_n_i : in std_logic; -- global reset, synched to clk_tdc_i
acam_refclk_r_edge_p_i : in std_logic; -- rising edge on 31.25MHz ACAM reference clock
send_dac_word_p_o : out std_logic; -- command from GN4124/VME to reconfigure the TDC mezz DAC with dac_word_o
......@@ -200,12 +196,6 @@ entity fmc_tdc_core is
tdc_led_trig3_o : out std_logic; -- amber led on front pannel, Ch.3 termination
tdc_led_trig4_o : out std_logic; -- amber led on front pannel, Ch.4 termination
tdc_led_trig5_o : out std_logic; -- amber led on front pannel, Ch.5 termination
-- TDC input signals, also arriving to the FPGA; not used currently
tdc_in_fpga_1_i : in std_logic; -- TDC input Ch.1, not used
tdc_in_fpga_2_i : in std_logic; -- TDC input Ch.2, not used
tdc_in_fpga_3_i : in std_logic; -- TDC input Ch.3, not used
tdc_in_fpga_4_i : in std_logic; -- TDC input Ch.4, not used
tdc_in_fpga_5_i : in std_logic; -- TDC input Ch.5, not used
-- White Rabbit control and status registers
......@@ -221,8 +211,9 @@ entity fmc_tdc_core is
cfg_slave_i : in t_wishbone_slave_in;
cfg_slave_o : out t_wishbone_slave_out;
timestamp_o : out std_logic_vector(127 downto 0);
timestamp_stb_o : out std_logic;
timestamp_o : out t_tdc_timestamp_array(4 downto 0);
timestamp_valid_o : out std_logic_vector(4 downto 0);
timestamp_ready_i : in std_logic_vector(4 downto 0);
channel_enable_o : out std_logic_vector(4 downto 0);
irq_threshold_o : out std_logic_vector(9 downto 0);
......@@ -267,35 +258,45 @@ architecture rtl of fmc_tdc_core is
signal utc, wrabbit_ctrl_reg : std_logic_vector(g_width-1 downto 0);
-- LEDs
signal acam_channel : std_logic_vector(5 downto 0);
signal tdc_in_fpga_1, tdc_in_fpga_2, tdc_in_fpga_3 : std_logic_vector(1 downto 0);
signal tdc_in_fpga_4, tdc_in_fpga_5 : std_logic_vector(1 downto 0);
signal acam_tstamp_channel : std_logic_vector(2 downto 0);
signal acam_channel : std_logic_vector(5 downto 0);
signal acam_tstamp_channel : std_logic_vector(2 downto 0);
signal raw_timestamp_valid : std_logic;
signal raw_timestamp : t_raw_acam_timestamp;
signal final_timestamp_valid : std_logic_vector(4 downto 0);
signal final_timestamp_ready : std_logic_vector(4 downto 0);
signal final_timestamp : t_tdc_timestamp_array(4 downto 0);
signal rst_sys : std_logic;
signal timestamp_valid : std_logic;
signal timestamp : std_logic_vector(127 downto 0);
signal channel_enable_int : std_logic_vector(4 downto 0);
signal rst_sys, rst_tdc : std_logic;
signal core_status : std_logic_vector(31 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
rst_sys <= not rst_n_sys_i;
rst_sys <= not rst_sys_n_i;
rst_tdc <= not rst_tdc_n_i;
---------------------------------------------------------------------------------------------------
-- TDC REGISTERS CONTROLLER --
---------------------------------------------------------------------------------------------------
reg_control_block : reg_ctrl
core_status(0) <= '1' when g_with_dma_readout else '0';
core_status(1) <= '1' when g_with_fifo_readout else '0';
core_status(31 downto 2) <= (others => '0');
reg_control_block : entity work.reg_ctrl
generic map
(g_span => g_span,
g_width => g_width)
port map
(clk_tdc_i => clk_tdc_i,
rst_tdc_i => rst_tdc_i,
rst_tdc_n_i => rst_tdc_n_i,
clk_sys_i => clk_sys_i,
rst_n_sys_i => rst_n_sys_i,
rst_sys_n_i => rst_sys_n_i,
slave_i => cfg_slave_i,
......@@ -317,7 +318,7 @@ begin
acam_start01_i => acam_start01,
local_utc_i => utc,
irq_code_i => x"00000000",
core_status_i => x"00000000",
core_status_i => core_status,
wrabbit_status_reg_i => wrabbit_status_reg_i,
wrabbit_ctrl_reg_o => wrabbit_ctrl_reg,
acam_config_o => acam_config,
......@@ -348,7 +349,7 @@ begin
term_enable_regs : process (clk_tdc_i)
begin
if rising_edge (clk_tdc_i) then
if rst_tdc_i = '1' then
if rst_tdc_n_i = '0' then
enable_inputs_o <= '0';
term_en_5_o <= '0';
term_en_4_o <= '0';
......@@ -379,12 +380,12 @@ begin
clk_period_i => clk_period,
load_utc_p_i => load_utc,
pulse_delay_i => pulse_delay,
rst_i => rst_tdc_i,
rst_i => rst_tdc,
starting_utc_i => starting_utc,
local_utc_o => local_utc,
local_utc_p_o => local_utc_p);
clk_period <= f_pick(g_simulation, c_SIM_CLK_PERIOD, c_SYN_CLK_PERIOD);
clk_period <= work.tdc_core_pkg.f_pick(g_simulation, c_SIM_CLK_PERIOD, c_SYN_CLK_PERIOD);
---------------------------------------------------------------------------------------------------
-- ACAM TIMECONTROL INTERFACE --
---------------------------------------------------------------------------------------------------
......@@ -400,7 +401,7 @@ begin
activate_acq_p_i => activate_acq_p,
state_active_p_i => state_active_p,
deactivate_acq_p_i => deactivate_acq_p,
rst_i => rst_tdc_i,
rst_i => rst_tdc,
acam_errflag_f_edge_p_o => acam_errflag_f_edge_p,
acam_errflag_r_edge_p_o => acam_errflag_r_edge_p,
acam_intflag_f_edge_p_o => acam_intflag_f_edge_p);
......@@ -426,7 +427,7 @@ begin
ef2_o => acam_ef2,
ef2_meta_o => acam_ef2_meta,
clk_i => clk_tdc_i,
rst_i => rst_tdc_i,
rst_i => rst_tdc,
adr_i => acm_adr,
cyc_i => acm_cyc,
dat_i => acm_dat_w,
......@@ -446,7 +447,7 @@ begin
(acam_intflag_f_edge_p_i => acam_intflag_f_edge_p,
clk_i => clk_tdc_i,
utc_p_i => utc_p,
rst_i => rst_tdc_i,
rst_i => rst_tdc,
current_retrig_nb_o => current_retrig_nb, -- for debug
roll_over_incr_recent_o => roll_over_incr_recent,
clk_i_cycles_offset_o => clk_i_cycles_offset,
......@@ -469,7 +470,7 @@ begin
acam_stb_o => acm_stb,
acam_we_o => acm_we,
clk_i => clk_tdc_i,
rst_i => rst_tdc_i,
rst_i => rst_tdc,
acam_ef1_i => acam_ef1,
acam_ef1_meta_i => acam_ef1_meta,
acam_ef2_i => acam_ef2,
......@@ -499,10 +500,10 @@ begin
---------------------------------------------------------------------------------------------------
-- DATA FORMATTING --
---------------------------------------------------------------------------------------------------
data_formatting_block : data_formatting
data_formatting_block : entity work.data_formatting
port map
(clk_i => clk_tdc_i,
rst_i => rst_tdc_i,
rst_i => rst_tdc,
acam_tstamp1_i => acam_tstamp1,
acam_tstamp1_ok_p_i => acam_tstamp1_ok_p,
acam_tstamp2_i => acam_tstamp2,
......@@ -513,19 +514,36 @@ begin
retrig_nb_offset_i => retrig_nb_offset,
utc_p_i => utc_p,
utc_i => utc,
timestamp_o => timestamp,
timestamp_valid_o => timestamp_valid
timestamp_o => raw_timestamp,
timestamp_valid_o => raw_timestamp_valid
);
U_FilterAndConvert : entity work.timestamp_convert_filter
port map (
clk_tdc_i => clk_tdc_i,
rst_tdc_n_i => rst_tdc_n_i,
clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i,
enable_i => channel_enable_int,
ts_i => raw_timestamp,
ts_valid_i => raw_timestamp_valid,
ts_o => final_timestamp,
ts_valid_o => final_timestamp_valid,
ts_ready_i => final_timestamp_ready
);
---------------------------------------------------------------------------------------------------
-- UTC timing source --
---------------------------------------------------------------------------------------------------
utc <= wrabbit_tai_i when wrabbit_synched_i = '1' else local_utc;
utc_p <= wrabbit_tai_p_i when wrabbit_synched_i = '1' else local_utc_p;
timestamp_stb_o <= timestamp_valid;
timestamp_o <= timestamp;
timestamp_valid_o <= final_timestamp_valid;
final_timestamp_ready <= timestamp_ready_i;
timestamp_o <= final_timestamp;
---------------------------------------------------------------------------------------------------
-- TDC LEDs --
......@@ -536,11 +554,11 @@ begin
g_simulation => g_simulation)
port map
(clk_i => clk_tdc_i,
rst_i => rst_tdc_i,
rst_i => rst_tdc,
utc_p_i => local_utc_p,
acam_inputs_en_i => acam_inputs_en,
acam_channel_i => acam_channel,
tstamp_wr_p_i => timestamp_valid,
tstamp_wr_p_i => final_timestamp_valid(0),
tdc_led_status_o => tdc_led_status_o,
tdc_led_trig1_o => tdc_led_trig1_o,
tdc_led_trig2_o => tdc_led_trig2_o,
......@@ -555,8 +573,9 @@ begin
---------------------------------------------------------------------------------------------------
start_dis_o <= '0';
channel_enable_o <= acam_inputs_en(20 downto 16);
channel_enable_int <= acam_inputs_en(20 downto 16);
channel_enable_o <= channel_enable_int;
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
......
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ 0724de2e
......@@ -109,7 +109,9 @@ entity fmc_tdc_mezzanine is
(g_with_wrabbit_core : boolean := false;
g_span : integer := 32;
g_width : integer := 32;
g_simulation : boolean := false);
g_simulation : boolean := false;
g_use_dma_readout : boolean := true;
g_use_fake_timestamps_for_sim : boolean := false);
port
-- TDC core
(
......@@ -119,8 +121,8 @@ entity fmc_tdc_mezzanine is
rst_sys_n_i : in std_logic; -- reset for 62.5 MHz logic
-- TDC 125 MHz reference & Reset (FMC)
clk_tdc_i : in std_logic; -- 125 MHz clock
rst_tdc_i : in std_logic; -- reset for 125 MHz logic
clk_tdc_i : in std_logic; -- 125 MHz clock
rst_tdc_n_i : in std_logic; -- reset for 125 MHz logic
acam_refclk_r_edge_p_i : in std_logic;
send_dac_word_p_o : out std_logic;
......@@ -153,12 +155,6 @@ entity fmc_tdc_mezzanine is
tdc_led_trig3_o : out std_logic;
tdc_led_trig4_o : out std_logic;
tdc_led_trig5_o : out std_logic;
-- Input pulses arriving also to the FPGA, currently not treated
tdc_in_fpga_1_i : in std_logic;
tdc_in_fpga_2_i : in std_logic;
tdc_in_fpga_3_i : in std_logic;
tdc_in_fpga_4_i : in std_logic;
tdc_in_fpga_5_i : in std_logic;
-- White Rabbit core
wrabbit_link_up_i : in std_logic;
wrabbit_time_valid_i : in std_logic;
......@@ -176,6 +172,9 @@ entity fmc_tdc_mezzanine is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
dma_wb_o : out t_wishbone_master_out;
dma_wb_i : in t_wishbone_master_in;
wb_irq_o : out std_logic;
-- I2C EEPROM interface
......@@ -188,7 +187,12 @@ entity fmc_tdc_mezzanine is
-- 1-Wire interface
onewire_b : inout std_logic;
direct_timestamp_o : out std_logic_vector(127 downto 0);
direct_timestamp_stb_o : out std_logic
direct_timestamp_stb_o : out std_logic;
sim_timestamp_i : in t_tdc_timestamp := c_dummy_timestamp;
sim_timestamp_valid_i : in std_logic := '0';
sim_timestamp_ready_o : out std_logic
);
end fmc_tdc_mezzanine;
......@@ -198,37 +202,18 @@ end fmc_tdc_mezzanine;
--=================================================================================================
architecture rtl of fmc_tdc_mezzanine is
component timestamp_fifo is
generic (
g_channel : integer);
port (
clk_sys_i : in std_logic;
clk_tdc_i : in std_logic;
rst_n_sys_i : in std_logic;
rst_tdc_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
irq_o : out std_logic;
enable_i : in std_logic;
tick_i : in std_logic;
irq_threshold_i : in std_logic_vector(9 downto 0);
irq_timeout_i : in std_logic_vector(9 downto 0);
timestamp_i : in std_logic_vector(127 downto 0);
timestamp_valid_i : in std_logic);
end component timestamp_fifo;
---------------------------------------------------------------------------------------------------
-- SDB CONSTANTS --
---------------------------------------------------------------------------------------------------
-- Note: All address in sdb and crossbar are BYTE addresses!
-- Master ports on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 9;
constant c_WB_SLAVE_TDC_ONEWIRE : integer := 0; -- TDC mezzanine board UnidueID&Thermometer 1-wire
constant c_WB_SLAVE_TDC_CORE_CONFIG : integer := 1; -- TDC core configuration registers
constant c_WB_SLAVE_TDC_EIC : integer := 2; -- TDC interrupts
constant c_WB_SLAVE_TDC_I2C : integer := 3; -- TDC mezzanine board system EEPROM I2C
constant c_WB_SLAVE_TDC_FIFO0 : integer := 4; -- Access to TDC core FIFO for timestamps retrieval
constant c_WB_SLAVE_TDC_DMA : integer := 9; -- Access to TDC core DMA controller
-- Slave port on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 1;
......@@ -239,8 +224,10 @@ architecture rtl of fmc_tdc_mezzanine is
-- sdb header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
constant c_NUM_WB_MASTERS : integer := 10;
-- WISHBONE crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(8 downto 0) :=
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS-1 downto 0) :=
(0 => f_sdb_embed_device(c_ONEWIRE_SDB_DEVICE, x"00001000"),
1 => f_sdb_embed_device(c_TDC_CONFIG_SDB_DEVICE, x"00002000"),
2 => f_sdb_embed_device(c_TDC_EIC_DEVICE, x"00003000"),
......@@ -249,10 +236,10 @@ architecture rtl of fmc_tdc_mezzanine is
5 => f_sdb_embed_device(c_TDC_FIFO_SDB_DEVICE, x"00005100"),
6 => f_sdb_embed_device(c_TDC_FIFO_SDB_DEVICE, x"00005200"),
7 => f_sdb_embed_device(c_TDC_FIFO_SDB_DEVICE, x"00005300"),
8 => f_sdb_embed_device(c_TDC_FIFO_SDB_DEVICE, x"00005400")
8 => f_sdb_embed_device(c_TDC_FIFO_SDB_DEVICE, x"00005400"),
9 => f_sdb_embed_device(c_TDC_DMA_SDB_DEVICE, x"00006000")
);
---------------------------------------------------------------------------------------------------
-- Signals --
---------------------------------------------------------------------------------------------------
......@@ -278,14 +265,17 @@ architecture rtl of fmc_tdc_mezzanine is
signal wrabbit_utc_p : std_logic;
signal wrabbit_synched : std_logic;
signal irq_channel : std_logic_vector(4 downto 0);
signal irq_fifo, irq_dma : std_logic_vector(4 downto 0);
signal timestamp : t_tdc_timestamp_array(4 downto 0);
signal timestamp_valid, timestamp_ready, timestamp_stb : std_logic_vector(4 downto 0);
signal tdc_timestamp : t_tdc_timestamp_array(4 downto 0);
signal tdc_timestamp_valid, tdc_timestamp_ready : std_logic_vector(4 downto 0);
signal channel_enable : std_logic_vector(4 downto 0);
signal irq_threshold, irq_timeout : std_logic_vector(9 downto 0);
signal tick_1ms : std_logic;
signal counter_1ms : unsigned(17 downto 0);
signal timestamp : std_logic_vector(127 downto 0);
signal timestamp_stb : std_logic;
signal channel_enable : std_logic_vector(4 downto 0);
signal irq_threshold, irq_timeout : std_logic_vector(9 downto 0);
signal tick_1ms : std_logic;
signal counter_1ms : unsigned(17 downto 0);
function f_wb_shift_address_word (w : t_wishbone_master_out) return t_wishbone_master_out is
variable r : t_wishbone_master_out;
......@@ -304,8 +294,6 @@ architecture rtl of fmc_tdc_mezzanine is
--=================================================================================================
begin
rst_ref_0_n <= not(rst_tdc_i);
cmp_sdb_crossbar : xwb_sdb_crossbar
generic map
(g_num_masters => c_NUM_WB_SLAVES,
......@@ -326,17 +314,20 @@ begin
---------------------------------------------------------------------------------------------------
-- TDC CORE --
---------------------------------------------------------------------------------------------------
cmp_tdc_core : fmc_tdc_core
cmp_tdc_core : entity work.fmc_tdc_core
generic map
(g_span => g_span,
g_width => g_width,
g_simulation => g_simulation)
(g_span => g_span,
g_width => g_width,
g_simulation => g_simulation,
g_with_dma_readout => g_use_dma_readout,
g_with_fifo_readout => true)
port map
( -- clks, rst
clk_tdc_i => clk_tdc_i,
rst_tdc_i => rst_tdc_i,
clk_sys_i => clk_sys_i,
rst_n_sys_i => rst_sys_n_i,
clk_tdc_i => clk_tdc_i,
rst_tdc_n_i => rst_tdc_n_i,
clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i,
acam_refclk_r_edge_p_i => acam_refclk_r_edge_p_i,
-- DAC configuration
send_dac_word_p_o => send_dac_word_p_o,
......@@ -362,12 +353,6 @@ begin
term_en_3_o => term_en_3_o,
term_en_4_o => term_en_4_o,
term_en_5_o => term_en_5_o,
-- Input channels to FPGA (not used currently)
tdc_in_fpga_1_i => tdc_in_fpga_1_i,
tdc_in_fpga_2_i => tdc_in_fpga_2_i,
tdc_in_fpga_3_i => tdc_in_fpga_3_i,
tdc_in_fpga_4_i => tdc_in_fpga_4_i,
tdc_in_fpga_5_i => tdc_in_fpga_5_i,
-- TDC board LEDs
tdc_led_status_o => tdc_led_status_o,
tdc_led_trig1_o => tdc_led_trig1_o,
......@@ -387,26 +372,57 @@ begin
cfg_slave_i => f_wb_shift_address_word(cnx_master_out(c_WB_SLAVE_TDC_CORE_CONFIG)),
cfg_slave_o => cnx_master_in(c_WB_SLAVE_TDC_CORE_CONFIG),
timestamp_o => timestamp,
timestamp_stb_o => timestamp_stb,
timestamp_o => tdc_timestamp,
timestamp_valid_o => tdc_timestamp_valid,
timestamp_ready_i => tdc_timestamp_ready,
irq_threshold_o => irq_threshold,
irq_timeout_o => irq_timeout,
channel_enable_o => channel_enable
);
gen_use_fake_timestamps: if g_use_fake_timestamps_for_sim generate
process(sim_timestamp_i, sim_timestamp_valid_i)
begin
timestamp_valid <=(others => '0');
for i in 0 to 4 loop
if unsigned(sim_timestamp_i.channel) = i then
timestamp(i) <= sim_timestamp_i;
timestamp_valid(i) <= sim_timestamp_valid_i;
end if;
end loop;
end process;
timestamp_ready <= (others => '1');
end generate gen_use_fake_timestamps;
gen_use_real_timestamps: if not g_use_fake_timestamps_for_sim generate
timestamp <= tdc_timestamp;
timestamp_valid <= tdc_timestamp_valid;
tdc_timestamp_ready <= timestamp_ready;
end generate gen_use_real_timestamps;
gen_fifos : for i in 0 to 4 generate
U_TheFifo : timestamp_fifo
U_TheFifo : entity work.timestamp_fifo
generic map (
g_channel => i)
port map (
clk_sys_i => clk_sys_i,
clk_tdc_i => clk_tdc_i,
rst_n_sys_i => rst_sys_n_i,
rst_tdc_i => rst_tdc_i,
rst_sys_n_i => rst_sys_n_i,
slave_i => cnx_master_out(c_WB_SLAVE_TDC_FIFO0 + i),
slave_o => cnx_master_in(c_WB_SLAVE_TDC_FIFO0 + i),
irq_o => irq_channel(i),
irq_o => irq_fifo(i),
enable_i => channel_enable(i),
tick_i => tick_1ms,
irq_threshold_i => irq_threshold,
......@@ -414,12 +430,41 @@ begin
timestamp_i => timestamp,
timestamp_valid_i => timestamp_stb);
timestamp_stb(i) <= timestamp_valid(i) and timestamp_ready(i);
end generate gen_fifos;
gen_with_dma_readout : if g_use_dma_readout generate
U_DMA_Engine : entity work.tdc_dma_engine
generic map (
g_CLOCK_FREQ => 62500000)
port map (
clk_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
ts_i => timestamp,
ts_valid_i => timestamp_valid,
ts_ready_o => timestamp_ready,
slave_i => cnx_master_out(c_WB_SLAVE_TDC_DMA),
slave_o => cnx_master_in(c_WB_SLAVE_TDC_DMA),
irq_o => irq_dma,
dma_wb_o => dma_wb_o,
dma_wb_i => dma_wb_i);
end generate gen_with_dma_readout;
gen_without_dma : if not g_use_dma_readout generate
irq_dma <= (others => '0');
cnx_master_in(c_WB_SLAVE_TDC_DMA).stall <= '0';
cnx_master_in(c_WB_SLAVE_TDC_DMA).err <= '0';
cnx_master_in(c_WB_SLAVE_TDC_DMA).rty <= '0';
cnx_master_in(c_WB_SLAVE_TDC_DMA).ack <= '1';
timestamp_ready <= (others => '1');
end generate gen_without_dma;
p_gen_1ms_tick : process(clk_tdc_i)
begin
if rising_edge(clk_tdc_i) then
if rst_tdc_i = '1' then
if rst_tdc_n_i = '0' then
tick_1ms <= '0';
counter_1ms <= (others => '0');
else
......@@ -445,7 +490,7 @@ begin
(clk_sys_i => clk_sys_i,
rst_n_sys_i => rst_sys_n_i,
clk_ref_i => clk_tdc_i,
rst_n_ref_i => rst_ref_0_n,
rst_n_ref_i => rst_tdc_n_i,
wrabbit_dac_value_i => wrabbit_dac_value_i,
wrabbit_dac_wr_p_i => wrabbit_dac_wr_p_i,
wrabbit_link_up_i => wrabbit_link_up_i,
......@@ -461,7 +506,7 @@ begin
wrabbit_one_hz_pulse : process(clk_tdc_i)
begin
if rising_edge(clk_tdc_i) then
if rst_ref_0_n = '0' then
if rst_tdc_n_i = '0' then
wrabbit_utc_p <= '0';
else
if wrabbit_clk_aux_locked_i = '1' and g_with_wrabbit_core then
......@@ -510,11 +555,11 @@ begin
-- 0 -> number of accumulated timestamps reached threshold
-- 1 -> number of seconds passed reached threshold and number of accumulated tstamps > 0
-- 2 -> ACAM error
cmp_tdc_eic : tdc_eic
cmp_tdc_eic : entity work.tdc_eic
port map
(clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
wb_adr_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).adr(3 downto 2),
wb_adr_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).adr(5 downto 2),
wb_dat_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).cyc,
......@@ -524,17 +569,22 @@ begin
wb_ack_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).stall,
wb_int_o => wb_irq_o,
irq_tdc_fifo1_i => irq_channel(0),
irq_tdc_fifo2_i => irq_channel(1),
irq_tdc_fifo3_i => irq_channel(2),
irq_tdc_fifo4_i => irq_channel(3),
irq_tdc_fifo5_i => irq_channel(4));
irq_tdc_fifo1_i => irq_fifo(0),
irq_tdc_fifo2_i => irq_fifo(1),
irq_tdc_fifo3_i => irq_fifo(2),
irq_tdc_fifo4_i => irq_fifo(3),
irq_tdc_fifo5_i => irq_fifo(4),
irq_tdc_dma1_i => irq_dma(0),
irq_tdc_dma2_i => irq_dma(1),
irq_tdc_dma3_i => irq_dma(2),
irq_tdc_dma4_i => irq_dma(3),
irq_tdc_dma5_i => irq_dma(4)
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_TDC_EIC).err <= '0';
cnx_master_in(c_WB_SLAVE_TDC_EIC).rty <= '0';
cnx_master_in(c_WB_SLAVE_TDC_EIC).int <= '0';
---------------------------------------------------------------------------------------------------
......
hdl/rtl/fmc_tdc_wrapper.vhd
View file @ 0724de2e
......@@ -131,7 +131,10 @@ entity fmc_tdc_wrapper is
-- reduces some timeouts to speed up simulation
g_simulation : boolean := false;
-- implement direct TDC timestamp readout FIFO, used in the WR Node projects
g_with_direct_readout : boolean := false
g_with_direct_readout : boolean := false;
g_use_dma_readout : boolean := false;
g_use_fake_timestamps_for_sim : boolean := false
);
port
......@@ -184,12 +187,6 @@ entity fmc_tdc_wrapper is
tdc_led_trig4_o : out std_logic; -- amber led on front pannel, Ch.4 enable
tdc_led_trig5_o : out std_logic; -- amber led on front pannel, Ch.5 enable
-- Input Logic on TDC mezzanine (not used currently)
tdc_in_fpga_1_i : in std_logic; -- Ch.1 for ACAM, also received by FPGA
tdc_in_fpga_2_i : in std_logic; -- Ch.2 for ACAM, also received by FPGA
tdc_in_fpga_3_i : in std_logic; -- Ch.3 for ACAM, also received by FPGA
tdc_in_fpga_4_i : in std_logic; -- Ch.4 for ACAM, also received by FPGA
tdc_in_fpga_5_i : in std_logic; -- Ch.5 for ACAM, also received by FPGA
-- I2C EEPROM interface on TDC mezzanine
mezz_scl_o : out std_logic;
......@@ -220,13 +217,21 @@ entity fmc_tdc_wrapper is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
direct_slave_i : in t_wishbone_slave_in;
direct_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
direct_slave_o : out t_wishbone_slave_out;
dma_wb_o : out t_wishbone_master_out;
dma_wb_i : in t_wishbone_master_in := cc_dummy_master_in;
irq_o : out std_logic;
-- local PLL clock output (for WR PTP Core clock disciplining)
clk_125m_tdc_o : out std_logic
clk_125m_tdc_o : out std_logic;
sim_timestamp_i : in t_tdc_timestamp := c_dummy_timestamp;
sim_timestamp_valid_i : in std_logic := '0';
sim_timestamp_ready_o : out std_logic
);
end fmc_tdc_wrapper;
......@@ -366,23 +371,28 @@ begin
---------------------------------------------------------------------------------------------------
-- TDC BOARD --
---------------------------------------------------------------------------------------------------
cmp_tdc_mezz : fmc_tdc_mezzanine
cmp_tdc_mezz : entity work.fmc_tdc_mezzanine
generic map
(g_span => 32,
g_width => 32,
g_simulation => g_simulation)
g_simulation => g_simulation,
g_use_dma_readout => g_use_dma_readout,
g_use_fake_timestamps_for_sim => g_use_fake_timestamps_for_sim)
port map
-- 62M5 clk and reset
(clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i,
-- 125M clk and reset
clk_tdc_i => clk_125m_mezz,
rst_tdc_i => rst_125m_mezz,
rst_tdc_n_i => rst_125m_mezz_n,
-- Wishbone
slave_i => cnx_master_out(c_slave_regs),
slave_o => cnx_master_in(c_slave_regs),
dma_wb_i => dma_wb_i,
dma_wb_o => dma_wb_o,
-- Interrupt line from EIC
wb_irq_o => irq_o,
......@@ -418,12 +428,6 @@ begin
tdc_led_trig3_o => tdc_led_trig3_o,
tdc_led_trig4_o => tdc_led_trig4_o,
tdc_led_trig5_o => tdc_led_trig5_o,
-- Input channels to FPGA (not used)
tdc_in_fpga_1_i => tdc_in_fpga_1_i,
tdc_in_fpga_2_i => tdc_in_fpga_2_i,
tdc_in_fpga_3_i => tdc_in_fpga_3_i,
tdc_in_fpga_4_i => tdc_in_fpga_4_i,
tdc_in_fpga_5_i => tdc_in_fpga_5_i,
-- WISHBONE interface with the GN4124 core
-- White Rabbit
......@@ -447,7 +451,11 @@ begin
-- 1-Wire on TDC mezzanine
onewire_b => mezz_one_wire_b,
direct_timestamp_o => direct_timestamp,
direct_timestamp_stb_o => direct_timestamp_wr);
direct_timestamp_stb_o => direct_timestamp_wr,
sim_timestamp_ready_o => sim_timestamp_ready_o,
sim_timestamp_valid_i => sim_timestamp_valid_i,
sim_timestamp_i => sim_timestamp_i);
mezz_scl_o <= '0' when tdc_scl_out ='0' and tdc_scl_oen = '0' else '1';
......
hdl/rtl/reg_ctrl.vhd
View file @ 0724de2e
......@@ -67,11 +67,11 @@
-- Standard library
library IEEE;
use IEEE.std_logic_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
use IEEE.std_logic_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.tdc_core_pkg.all; -- definitions of types, constants, entities
use work.tdc_core_pkg.all; -- definitions of types, constants, entities
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
......@@ -81,70 +81,72 @@ use work.wishbone_pkg.all;
entity reg_ctrl is
generic
(g_span : integer := 32;
g_width : integer := 32);
(
g_span : integer := 32;
g_width : integer := 32
);
port
(
clk_sys_i : in std_logic;
rst_n_sys_i : in std_logic; -- global reset, synched to clk_sys
clk_tdc_i : in std_logic;
rst_tdc_i : in std_logic;
slave_i: in t_wishbone_slave_in; -- WB interface (clk_sys domain)
slave_o: out t_wishbone_slave_out;
-- Signals from the data_engine unit: configuration regs read back from the ACAM
acam_config_rdbk_i : in config_vector; -- array keeping values read back from ACAM regs 0-7, 11, 12, 14
acam_ififo1_i : in std_logic_vector(g_width-1 downto 0); -- keeps value read back from ACAM reg 8; for debug reasons only
acam_ififo2_i : in std_logic_vector(g_width-1 downto 0); -- keeps value read back from ACAM reg 9; for debug reasons only
acam_start01_i : in std_logic_vector(g_width-1 downto 0); -- keeps value read back from ACAM reg 10; for debug reasons only
-- Signals from the one_hz_gen unit
local_utc_i : in std_logic_vector(g_width-1 downto 0); -- local utc time
-- Signals not used so far
core_status_i : in std_logic_vector(g_width-1 downto 0); -- TDC core status word
irq_code_i : in std_logic_vector(g_width-1 downto 0); -- TDC core interrupt code word
-- White Rabbit status
wrabbit_status_reg_i : in std_logic_vector(g_width-1 downto 0); --
-- OUTPUTS
-- Signals to the data_engine unit: config regs for the ACAM
acam_config_o : out config_vector;
-- Signals to the data_engine unit: TDC core functionality
activate_acq_p_o : out std_logic; -- activates tstamps aquisition from ACAM
deactivate_acq_p_o : out std_logic; -- activates ACAM configuration readings/ writings
acam_wr_config_p_o : out std_logic; -- enables writing to ACAM regs 0-7, 11, 12, 14
acam_rdbk_config_p_o : out std_logic; -- enables reading of ACAM regs 0-7, 11, 12, 14
acam_rst_p_o : out std_logic; -- enables writing the c_RESET_WORD to ACAM reg 4
acam_rdbk_status_p_o : out std_logic; -- enables reading of ACAM reg 12
acam_rdbk_ififo1_p_o : out std_logic; -- enables reading of ACAM reg 8
acam_rdbk_ififo2_p_o : out std_logic; -- enables reading of ACAM reg 9
acam_rdbk_start01_p_o : out std_logic; -- enables reading of ACAM reg 10
-- Signals to the clks_resets_manager unit
send_dac_word_p_o : out std_logic; -- initiates the reconfiguration of the DAC
dac_word_o : out std_logic_vector(23 downto 0);
-- Signal to the one_hz_gen unit
load_utc_p_o : out std_logic;
starting_utc_o : out std_logic_vector(g_width-1 downto 0);
irq_tstamp_threshold_o: out std_logic_vector(g_width-1 downto 0); -- threshold in number of timestamps
irq_time_threshold_o : out std_logic_vector(g_width-1 downto 0); -- threshold in number of ms
one_hz_phase_o : out std_logic_vector(g_width-1 downto 0); -- for debug only
-- Signal to the TDC mezzanine board
acam_inputs_en_o : out std_logic_vector(g_width-1 downto 0); -- enables all five input channels
-- White Rabbit control
wrabbit_ctrl_reg_o : out std_logic_vector(g_width-1 downto 0); --
-- Signal to the acam_timecontrol_interface unit -- eva: i think it s not needed
start_phase_o : out std_logic_vector(g_width-1 downto 0));
rst_sys_n_i : in std_logic; -- global reset, synched to clk_sys
clk_tdc_i : in std_logic;
rst_tdc_n_i : in std_logic;
slave_i : in t_wishbone_slave_in; -- WB interface (clk_sys domain)
slave_o : out t_wishbone_slave_out;
-- Signals from the data_engine unit: configuration regs read back from the ACAM
acam_config_rdbk_i : in config_vector; -- array keeping values read back from ACAM regs 0-7, 11, 12, 14
acam_ififo1_i : in std_logic_vector(g_width-1 downto 0); -- keeps value read back from ACAM reg 8; for debug reasons only
acam_ififo2_i : in std_logic_vector(g_width-1 downto 0); -- keeps value read back from ACAM reg 9; for debug reasons only
acam_start01_i : in std_logic_vector(g_width-1 downto 0); -- keeps value read back from ACAM reg 10; for debug reasons only
-- Signals from the one_hz_gen unit
local_utc_i : in std_logic_vector(g_width-1 downto 0); -- local utc time
-- Signals not used so far
core_status_i : in std_logic_vector(g_width-1 downto 0); -- TDC core status word
irq_code_i : in std_logic_vector(g_width-1 downto 0); -- TDC core interrupt code word
-- White Rabbit status
wrabbit_status_reg_i : in std_logic_vector(g_width-1 downto 0); --
-- OUTPUTS
-- Signals to the data_engine unit: config regs for the ACAM
acam_config_o : out config_vector;
-- Signals to the data_engine unit: TDC core functionality
activate_acq_p_o : out std_logic; -- activates tstamps aquisition from ACAM
deactivate_acq_p_o : out std_logic; -- activates ACAM configuration readings/ writings
acam_wr_config_p_o : out std_logic; -- enables writing to ACAM regs 0-7, 11, 12, 14
acam_rdbk_config_p_o : out std_logic; -- enables reading of ACAM regs 0-7, 11, 12, 14
acam_rst_p_o : out std_logic; -- enables writing the c_RESET_WORD to ACAM reg 4
acam_rdbk_status_p_o : out std_logic; -- enables reading of ACAM reg 12
acam_rdbk_ififo1_p_o : out std_logic; -- enables reading of ACAM reg 8
acam_rdbk_ififo2_p_o : out std_logic; -- enables reading of ACAM reg 9
acam_rdbk_start01_p_o : out std_logic; -- enables reading of ACAM reg 10
-- Signals to the clks_resets_manager unit
send_dac_word_p_o : out std_logic; -- initiates the reconfiguration of the DAC
dac_word_o : out std_logic_vector(23 downto 0);
-- Signal to the one_hz_gen unit
load_utc_p_o : out std_logic;
starting_utc_o : out std_logic_vector(g_width-1 downto 0);
irq_tstamp_threshold_o : out std_logic_vector(g_width-1 downto 0); -- threshold in number of timestamps
irq_time_threshold_o : out std_logic_vector(g_width-1 downto 0); -- threshold in number of ms
one_hz_phase_o : out std_logic_vector(g_width-1 downto 0); -- for debug only
-- Signal to the TDC mezzanine board
acam_inputs_en_o : out std_logic_vector(g_width-1 downto 0); -- enables all five input channels
-- White Rabbit control
wrabbit_ctrl_reg_o : out std_logic_vector(g_width-1 downto 0); --
-- Signal to the acam_timecontrol_interface unit -- eva: i think it s not needed
start_phase_o : out std_logic_vector(g_width-1 downto 0));
end reg_ctrl;
......@@ -155,7 +157,7 @@ end reg_ctrl;
architecture rtl of reg_ctrl is
signal acam_config : config_vector;
signal reg_adr,reg_adr_pipe0 : std_logic_vector(7 downto 0);
signal reg_adr, reg_adr_pipe0 : std_logic_vector(7 downto 0);
signal starting_utc, acam_inputs_en, start_phase : std_logic_vector(g_width-1 downto 0);
signal ctrl_reg, one_hz_phase, irq_tstamp_threshold : std_logic_vector(g_width-1 downto 0);
signal irq_time_threshold : std_logic_vector(g_width-1 downto 0);
......@@ -163,7 +165,7 @@ architecture rtl of reg_ctrl is
signal dac_word : std_logic_vector(23 downto 0);
signal pulse_extender_en : std_logic;
signal pulse_extender_c : std_logic_vector(2 downto 0);
signal dat_out, wrabbit_ctrl_reg : std_logic_vector(g_span-1 downto 0);
signal dat_out, wrabbit_ctrl_reg : std_logic_vector(g_span-1 downto 0);
signal ack_out_pipe0, ack_out_pipe1 : std_logic;
......@@ -175,44 +177,41 @@ architecture rtl of reg_ctrl is
signal cyc_in_progress : std_logic;
signal wb_in : t_wishbone_slave_in;
signal wb_out : t_wishbone_slave_out;
signal rst_n_tdc : std_logic;
signal wb_in : t_wishbone_slave_in;
signal wb_out : t_wishbone_slave_out;
--=================================================================================================
-- architecture begin
--=================================================================================================
signal cc_rst_n : std_logic;
signal cc_rst_n : std_logic;
signal cc_rst_n_or_sys : std_logic;
begin
rst_n_tdc <= not rst_tdc_i;
wb_out.stall <= '0';
wb_out.err <= '0';
wb_out.rty <= '0';
u_sync_tdc_reset : gc_sync_ffs
u_sync_tdc_reset : gc_sync_ffs
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_sys_i,
data_i => rst_n_tdc,
rst_n_i => rst_sys_n_i,
data_i => rst_tdc_n_i,
synced_o => cc_rst_n);
cc_rst_n_or_sys <= cc_rst_n and rst_n_sys_i;
cc_rst_n_or_sys <= cc_rst_n and rst_sys_n_i;
cmp_clks_crossing : xwb_clock_crossing
port map
(slave_clk_i => clk_sys_i, -- Slave control port: VME interface at 62.5 MHz
slave_rst_n_i => cc_rst_n_or_sys, -- reset the slave port also when resetting the TDC
slave_rst_n_i => cc_rst_n_or_sys, -- reset the slave port also when resetting the TDC
slave_i => slave_i,
slave_o => slave_o,
master_clk_i => clk_tdc_i,
master_rst_n_i => rst_n_tdc,
master_rst_n_i => rst_tdc_n_i,
master_i => wb_out,
master_o => wb_in);
......@@ -228,20 +227,20 @@ begin
TDCconfig_ack_generator : process (clk_tdc_i)
begin
if rising_edge (clk_tdc_i) then
if rst_n_tdc = '0' then
wb_out.ack <= '0';
ack_out_pipe1 <= '0';
ack_out_pipe0 <= '0';
cyc_in_progress <= '0';
elsif(wb_in.cyc = '0') then
if rst_tdc_n_i = '0' then
wb_out.ack <= '0';
ack_out_pipe1 <= '0';
ack_out_pipe0 <= '0';
cyc_in_progress <= '0';
elsif(wb_in.cyc /= '1') then
ack_out_pipe1 <= '0';
ack_out_pipe0 <= '0';
cyc_in_progress <= '0';
else
cyc_in_progress <= '1';
wb_out.ack <= ack_out_pipe1;
ack_out_pipe1 <= ack_out_pipe0;
ack_out_pipe0 <= wb_in.stb and wb_in.cyc and not cyc_in_progress;
cyc_in_progress <= '1';
wb_out.ack <= ack_out_pipe1;
ack_out_pipe1 <= ack_out_pipe0;
ack_out_pipe0 <= wb_in.stb and wb_in.cyc and not cyc_in_progress;
end if;
end if;
end process;
......@@ -259,26 +258,26 @@ begin
ACAM_config_reg_reception : process (clk_tdc_i)
begin
if rising_edge (clk_tdc_i) then
if rst_tdc_i = '1' then
acam_config(0) <= (others =>'0');
acam_config(1) <= (others =>'0');
acam_config(2) <= (others =>'0');
acam_config(3) <= (others =>'0');
acam_config(4) <= (others =>'0');
acam_config(5) <= (others =>'0');
acam_config(6) <= (others =>'0');
acam_config(7) <= (others =>'0');
acam_config(8) <= (others =>'0');
acam_config(9) <= (others =>'0');
acam_config(10) <= (others =>'0');
elsif wb_in.cyc = '1' and wb_in.stb = '1' and wb_in.we = '1' then -- WISHBONE writes
if rst_tdc_n_i = '0' then
acam_config(0) <= (others => '0');
acam_config(1) <= (others => '0');
acam_config(2) <= (others => '0');
acam_config(3) <= (others => '0');
acam_config(4) <= (others => '0');
acam_config(5) <= (others => '0');
acam_config(6) <= (others => '0');
acam_config(7) <= (others => '0');
acam_config(8) <= (others => '0');
acam_config(9) <= (others => '0');
acam_config(10) <= (others => '0');
elsif wb_in.cyc = '1' and wb_in.stb = '1' and wb_in.we = '1' then -- WISHBONE writes
if reg_adr = c_ACAM_REG0_ADR then
acam_config(0) <= wb_in.dat;
end if;
if reg_adr = c_ACAM_REG1_ADR then
if reg_adr = c_ACAM_REG1_ADR then
acam_config(1) <= wb_in.dat;
end if;
......@@ -321,7 +320,7 @@ begin
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- --
acam_config_o <= acam_config;
acam_config_o <= acam_config;
---------------------------------------------------------------------------------------------------
......@@ -339,18 +338,18 @@ begin
-- o one_hz_phase : eva: think it s not used
-- o start_phase : eva: think it s not used
TDCcore_config_reg_reception: process (clk_tdc_i)
TDCcore_config_reg_reception : process (clk_tdc_i)
begin
if rising_edge (clk_tdc_i) then
if rst_tdc_i ='1' then
acam_inputs_en <= (others =>'0');
starting_utc <= (others =>'0');
start_phase <= (others =>'0');
one_hz_phase <= (others =>'0');
wrabbit_ctrl_reg <= (others =>'0');
irq_tstamp_threshold <= x"00000001"; -- default 256 timestamps: full memory
irq_time_threshold <= x"00000001"; -- default 200 ms
dac_word <= c_DEFAULT_DAC_WORD; -- default DAC Vout = 1.65
if rst_tdc_n_i = '0' then
acam_inputs_en <= (others => '0');
starting_utc <= (others => '0');
start_phase <= (others => '0');
one_hz_phase <= (others => '0');
wrabbit_ctrl_reg <= (others => '0');
irq_tstamp_threshold <= x"00000001"; -- default 256 timestamps: full memory
irq_time_threshold <= x"00000001"; -- default 200 ms
dac_word <= c_DEFAULT_DAC_WORD; -- default DAC Vout = 1.65
elsif wb_in.cyc = '1' and wb_in.stb = '1' and wb_in.we = '1' then
......@@ -383,22 +382,22 @@ begin
end if;
if reg_adr = c_WRABBIT_CTRL_ADR then
wrabbit_ctrl_reg <= wb_in.dat;
wrabbit_ctrl_reg <= wb_in.dat;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- --
starting_utc_o <= starting_utc;
acam_inputs_en_o <= acam_inputs_en;
start_phase_o <= start_phase;
one_hz_phase_o <= one_hz_phase;
irq_tstamp_threshold_o <= irq_tstamp_threshold;
irq_time_threshold_o <= irq_time_threshold;
dac_word_o <= dac_word;
wrabbit_ctrl_reg_o <= wrabbit_ctrl_reg;
starting_utc_o <= starting_utc;
acam_inputs_en_o <= acam_inputs_en;
start_phase_o <= start_phase;
one_hz_phase_o <= one_hz_phase;
irq_tstamp_threshold_o <= irq_tstamp_threshold;
irq_time_threshold_o <= irq_time_threshold;
dac_word_o <= dac_word;
wrabbit_ctrl_reg_o <= wrabbit_ctrl_reg;
---------------------------------------------------------------------------------------------------
-- Reception of TDC core Control Register --
......@@ -408,17 +407,17 @@ begin
-- defines the action to be taken by the TDC core.
-- Note that only one bit of the register should be written at a time. The process receives
-- the register, defines the action to be taken and after 1 clk cycle clears the register.
TDCcore_ctrl_reg_reception : process (clk_tdc_i)
TDCcore_ctrl_reg_reception : process (clk_tdc_i)
begin
if rising_edge (clk_tdc_i) then
if rst_tdc_i = '1' then
ctrl_reg <= (others =>'0');
clear_ctrl_reg <= '0';
if rst_tdc_n_i = '0' then
ctrl_reg <= (others => '0');
clear_ctrl_reg <= '0';
elsif clear_ctrl_reg = '1' then
ctrl_reg <= (others =>'0');
clear_ctrl_reg <= '0';
ctrl_reg <= (others => '0');
clear_ctrl_reg <= '0';
elsif wb_in.cyc = '1' and wb_in.stb = '1' and wb_in.we = '1' then
if reg_adr = c_CTRL_REG_ADR then
......@@ -430,27 +429,27 @@ begin
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- --
activate_acq_p_o <= ctrl_reg(0);
deactivate_acq_p_o <= ctrl_reg(1);
acam_wr_config_p_o <= ctrl_reg(2);
acam_rdbk_config_p_o <= ctrl_reg(3);
acam_rdbk_status_p_o <= ctrl_reg(4);
acam_rdbk_ififo1_p_o <= ctrl_reg(5);
acam_rdbk_ififo2_p_o <= ctrl_reg(6);
acam_rdbk_start01_p_o <= ctrl_reg(7);
acam_rst_p_o <= ctrl_reg(8);
load_utc_p_o <= ctrl_reg(9);
send_dac_word_p <= ctrl_reg(11);
activate_acq_p_o <= ctrl_reg(0);
deactivate_acq_p_o <= ctrl_reg(1);
acam_wr_config_p_o <= ctrl_reg(2);
acam_rdbk_config_p_o <= ctrl_reg(3);
acam_rdbk_status_p_o <= ctrl_reg(4);
acam_rdbk_ififo1_p_o <= ctrl_reg(5);
acam_rdbk_ififo2_p_o <= ctrl_reg(6);
acam_rdbk_start01_p_o <= ctrl_reg(7);
acam_rst_p_o <= ctrl_reg(8);
load_utc_p_o <= ctrl_reg(9);
send_dac_word_p <= ctrl_reg(11);
-- ctrl_reg bits 12 to 31 not used for the moment!
-- -- -- -- -- -- -- -- -- -- -- --
-- Pulse_stretcher: Increases the width of the send_dac_word_p pulse so that it can be sampled
-- by the 20 MHz clock of the clks_rsts_manager that is communicating with the DAC.
Pulse_stretcher: incr_counter
generic map
(width => 3)
port map
Pulse_stretcher : incr_counter
generic map
(width => 3)
port map
(clk_i => clk_tdc_i,
rst_i => send_dac_word_p,
counter_top_i => "111",
......@@ -458,8 +457,8 @@ begin
counter_is_full_o => open,
counter_o => pulse_extender_c);
-- -- -- -- -- -- -- -- -- -- -- --
pulse_extender_en <= '1' when pulse_extender_c < "111" else '0';
send_dac_word_p_o <= pulse_extender_en;
pulse_extender_en <= '1' when pulse_extender_c < "111" else '0';
send_dac_word_p_o <= pulse_extender_en;
---------------------------------------------------------------------------------------------------
......@@ -472,13 +471,13 @@ begin
WISHBONEreads : process (clk_tdc_i)
begin
if rising_edge (clk_tdc_i) then
reg_adr_pipe0 <= reg_adr;
reg_adr_pipe0 <= reg_adr;
dat_out_pipe0 <= dat_out_comb0;
dat_out_pipe1 <= dat_out_comb1;
dat_out_pipe2 <= dat_out_comb2;
dat_out_pipe3 <= dat_out_comb3;
wb_out.dat <= dat_out_pipe0 or dat_out_pipe1 or dat_out_pipe2 or dat_out_pipe3;
--end if;
wb_out.dat <= dat_out_pipe0 or dat_out_pipe1 or dat_out_pipe2 or dat_out_pipe3;
--end if;
end if;
end process;
......@@ -531,7 +530,7 @@ begin
-- regs written locally by the TDC core units
local_utc_i when c_LOCAL_UTC_ADR,
irq_code_i when c_IRQ_CODE_ADR,
x"00000000" when c_WR_INDEX_ADR,
x"00000000" when c_WR_INDEX_ADR,
core_status_i when c_CORE_STATUS_ADR,
-- White Rabbit regs
wrabbit_status_reg_i when c_WRABBIT_STATUS_ADR,
......
hdl/rtl/tdc_buffer_control_regs.vhd 0 → 100644
View file @ 0724de2e
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for TDC DMA Buffer Control Registers
---------------------------------------------------------------------------------------
-- File : tdc_buffer_control_regs.vhd
-- Author : auto-generated by wbgen2 from wbgen/tdc_buffer_control_regs.wb
-- Created : Mon Aug 6 23:30:18 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/tdc_buffer_control_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.TDC_BUF_wbgen2_pkg.all;
entity tdc_buffer_control_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
regs_i : in t_TDC_BUF_in_registers;
regs_o : out t_TDC_BUF_out_registers
);
end tdc_buffer_control_wb;
architecture syn of tdc_buffer_control_wb is
signal tdc_buf_csr_enable_int : std_logic ;
signal tdc_buf_csr_irq_timeout_int : std_logic_vector(9 downto 0);
signal tdc_buf_csr_burst_size_int : std_logic_vector(9 downto 0);
signal tdc_buf_csr_switch_buffers_dly0 : std_logic ;
signal tdc_buf_csr_switch_buffers_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(2 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments
wrdata_reg <= slave_i.dat;
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
tdc_buf_csr_enable_int <= '0';
tdc_buf_csr_irq_timeout_int <= "0000000000";
tdc_buf_csr_burst_size_int <= "0000000000";
tdc_buf_csr_switch_buffers_int <= '0';
regs_o.tdc_buf_csr_done_load_o <= '0';
regs_o.tdc_buf_csr_overflow_load_o <= '0';
regs_o.tdc_buf_cur_base_load_o <= '0';
regs_o.tdc_buf_cur_size_size_load_o <= '0';
regs_o.tdc_buf_cur_size_valid_load_o <= '0';
regs_o.tdc_buf_next_base_load_o <= '0';
regs_o.tdc_buf_next_size_size_load_o <= '0';
regs_o.tdc_buf_next_size_valid_load_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
tdc_buf_csr_switch_buffers_int <= '0';
regs_o.tdc_buf_csr_done_load_o <= '0';
regs_o.tdc_buf_csr_overflow_load_o <= '0';
regs_o.tdc_buf_cur_base_load_o <= '0';
regs_o.tdc_buf_cur_size_size_load_o <= '0';
regs_o.tdc_buf_cur_size_valid_load_o <= '0';
regs_o.tdc_buf_next_base_load_o <= '0';
regs_o.tdc_buf_next_size_size_load_o <= '0';
regs_o.tdc_buf_next_size_valid_load_o <= '0';
ack_in_progress <= '0';
else
regs_o.tdc_buf_csr_done_load_o <= '0';
regs_o.tdc_buf_csr_overflow_load_o <= '0';
regs_o.tdc_buf_cur_base_load_o <= '0';
regs_o.tdc_buf_cur_size_size_load_o <= '0';
regs_o.tdc_buf_cur_size_valid_load_o <= '0';
regs_o.tdc_buf_next_base_load_o <= '0';
regs_o.tdc_buf_next_size_size_load_o <= '0';
regs_o.tdc_buf_next_size_valid_load_o <= '0';
end if;
else
if ((slave_i.cyc = '1') and (slave_i.stb = '1')) then
case rwaddr_reg(2 downto 0) is
when "000" =>
if (slave_i.we = '1') then
tdc_buf_csr_enable_int <= wrdata_reg(0);
tdc_buf_csr_irq_timeout_int <= wrdata_reg(10 downto 1);
tdc_buf_csr_burst_size_int <= wrdata_reg(20 downto 11);
tdc_buf_csr_switch_buffers_int <= wrdata_reg(21);
regs_o.tdc_buf_csr_done_load_o <= '1';
regs_o.tdc_buf_csr_overflow_load_o <= '1';
end if;
rddata_reg(0) <= tdc_buf_csr_enable_int;
rddata_reg(10 downto 1) <= tdc_buf_csr_irq_timeout_int;
rddata_reg(20 downto 11) <= tdc_buf_csr_burst_size_int;
rddata_reg(21) <= '0';
rddata_reg(22) <= regs_i.tdc_buf_csr_done_i;
rddata_reg(23) <= regs_i.tdc_buf_csr_overflow_i;
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "001" =>
if (slave_i.we = '1') then
regs_o.tdc_buf_cur_base_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= regs_i.tdc_buf_cur_base_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010" =>
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.tdc_buf_cur_count_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011" =>
if (slave_i.we = '1') then
regs_o.tdc_buf_cur_size_size_load_o <= '1';
regs_o.tdc_buf_cur_size_valid_load_o <= '1';
end if;
rddata_reg(29 downto 0) <= regs_i.tdc_buf_cur_size_size_i;
rddata_reg(30) <= regs_i.tdc_buf_cur_size_valid_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
if (slave_i.we = '1') then
regs_o.tdc_buf_next_base_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= regs_i.tdc_buf_next_base_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101" =>
if (slave_i.we = '1') then
regs_o.tdc_buf_next_size_size_load_o <= '1';
regs_o.tdc_buf_next_size_valid_load_o <= '1';
end if;
rddata_reg(29 downto 0) <= regs_i.tdc_buf_next_size_size_i;
rddata_reg(30) <= regs_i.tdc_buf_next_size_valid_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
slave_o.dat <= rddata_reg;
-- Enable acquisition
regs_o.tdc_buf_csr_enable_o <= tdc_buf_csr_enable_int;
-- IRQ Timeout (ms)
regs_o.tdc_buf_csr_irq_timeout_o <= tdc_buf_csr_irq_timeout_int;
-- Burst size (timestamps)
regs_o.tdc_buf_csr_burst_size_o <= tdc_buf_csr_burst_size_int;
-- Switch buffers
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
tdc_buf_csr_switch_buffers_dly0 <= '0';
regs_o.tdc_buf_csr_switch_buffers_o <= '0';
elsif rising_edge(clk_sys_i) then
tdc_buf_csr_switch_buffers_dly0 <= tdc_buf_csr_switch_buffers_int;
regs_o.tdc_buf_csr_switch_buffers_o <= tdc_buf_csr_switch_buffers_int and (not tdc_buf_csr_switch_buffers_dly0);
end if;
end process;
-- Burst complete
regs_o.tdc_buf_csr_done_o <= wrdata_reg(22);
-- DMA overflow
regs_o.tdc_buf_csr_overflow_o <= wrdata_reg(23);
-- Base address
regs_o.tdc_buf_cur_base_o <= wrdata_reg(31 downto 0);
-- Number of data samples
-- Size
regs_o.tdc_buf_cur_size_size_o <= wrdata_reg(29 downto 0);
-- Valid flag
regs_o.tdc_buf_cur_size_valid_o <= wrdata_reg(30);
-- Base address
regs_o.tdc_buf_next_base_o <= wrdata_reg(31 downto 0);
-- Size (in transfers)
regs_o.tdc_buf_next_size_size_o <= wrdata_reg(29 downto 0);
-- Valid flag
regs_o.tdc_buf_next_size_valid_o <= wrdata_reg(30);
rwaddr_reg <= slave_i.adr(4 downto 2);
slave_o.stall <= (not ack_sreg(0)) and (slave_i.stb and slave_i.cyc);
slave_o.err <= '0';
slave_o.rty <= '0';
-- ACK signal generation. Just pass the LSB of ACK counter.
slave_o.ack <= ack_sreg(0);
end syn;
hdl/rtl/tdc_buffer_control_regs_wbgen2_pkg.vhd 0 → 100644
View file @ 0724de2e
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for TDC DMA Buffer Control Registers
---------------------------------------------------------------------------------------
-- File : tdc_buffer_control_regs_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wbgen/tdc_buffer_control_regs.wb
-- Created : Mon Aug 6 23:30:18 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/tdc_buffer_control_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package TDC_BUF_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_TDC_BUF_in_registers is record
tdc_buf_csr_done_i : std_logic;
tdc_buf_csr_overflow_i : std_logic;
tdc_buf_cur_base_i : std_logic_vector(31 downto 0);
tdc_buf_cur_count_i : std_logic_vector(31 downto 0);
tdc_buf_cur_size_size_i : std_logic_vector(29 downto 0);
tdc_buf_cur_size_valid_i : std_logic;
tdc_buf_next_base_i : std_logic_vector(31 downto 0);
tdc_buf_next_size_size_i : std_logic_vector(29 downto 0);
tdc_buf_next_size_valid_i : std_logic;
end record;
constant c_TDC_BUF_in_registers_init_value: t_TDC_BUF_in_registers := (
tdc_buf_csr_done_i => '0',
tdc_buf_csr_overflow_i => '0',
tdc_buf_cur_base_i => (others => '0'),
tdc_buf_cur_count_i => (others => '0'),
tdc_buf_cur_size_size_i => (others => '0'),
tdc_buf_cur_size_valid_i => '0',
tdc_buf_next_base_i => (others => '0'),
tdc_buf_next_size_size_i => (others => '0'),
tdc_buf_next_size_valid_i => '0'
);
-- Output registers (WB slave -> user design)
type t_TDC_BUF_out_registers is record
tdc_buf_csr_enable_o : std_logic;
tdc_buf_csr_irq_timeout_o : std_logic_vector(9 downto 0);
tdc_buf_csr_burst_size_o : std_logic_vector(9 downto 0);
tdc_buf_csr_switch_buffers_o : std_logic;
tdc_buf_csr_done_o : std_logic;
tdc_buf_csr_done_load_o : std_logic;
tdc_buf_csr_overflow_o : std_logic;
tdc_buf_csr_overflow_load_o : std_logic;
tdc_buf_cur_base_o : std_logic_vector(31 downto 0);
tdc_buf_cur_base_load_o : std_logic;
tdc_buf_cur_size_size_o : std_logic_vector(29 downto 0);
tdc_buf_cur_size_size_load_o : std_logic;
tdc_buf_cur_size_valid_o : std_logic;
tdc_buf_cur_size_valid_load_o : std_logic;
tdc_buf_next_base_o : std_logic_vector(31 downto 0);
tdc_buf_next_base_load_o : std_logic;
tdc_buf_next_size_size_o : std_logic_vector(29 downto 0);
tdc_buf_next_size_size_load_o : std_logic;
tdc_buf_next_size_valid_o : std_logic;
tdc_buf_next_size_valid_load_o : std_logic;
end record;
constant c_TDC_BUF_out_registers_init_value: t_TDC_BUF_out_registers := (
tdc_buf_csr_enable_o => '0',
tdc_buf_csr_irq_timeout_o => (others => '0'),
tdc_buf_csr_burst_size_o => (others => '0'),
tdc_buf_csr_switch_buffers_o => '0',
tdc_buf_csr_done_o => '0',
tdc_buf_csr_done_load_o => '0',
tdc_buf_csr_overflow_o => '0',
tdc_buf_csr_overflow_load_o => '0',
tdc_buf_cur_base_o => (others => '0'),
tdc_buf_cur_base_load_o => '0',
tdc_buf_cur_size_size_o => (others => '0'),
tdc_buf_cur_size_size_load_o => '0',
tdc_buf_cur_size_valid_o => '0',
tdc_buf_cur_size_valid_load_o => '0',
tdc_buf_next_base_o => (others => '0'),
tdc_buf_next_base_load_o => '0',
tdc_buf_next_size_size_o => (others => '0'),
tdc_buf_next_size_size_load_o => '0',
tdc_buf_next_size_valid_o => '0',
tdc_buf_next_size_valid_load_o => '0'
);
function "or" (left, right: t_TDC_BUF_in_registers) return t_TDC_BUF_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
component tdc_buffer_control_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
regs_i : in t_TDC_BUF_in_registers;
regs_o : out t_TDC_BUF_out_registers
);
end component;
end package;
package body TDC_BUF_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_TDC_BUF_in_registers) return t_TDC_BUF_in_registers is
variable tmp: t_TDC_BUF_in_registers;
begin
tmp.tdc_buf_csr_done_i := f_x_to_zero(left.tdc_buf_csr_done_i) or f_x_to_zero(right.tdc_buf_csr_done_i);
tmp.tdc_buf_csr_overflow_i := f_x_to_zero(left.tdc_buf_csr_overflow_i) or f_x_to_zero(right.tdc_buf_csr_overflow_i);
tmp.tdc_buf_cur_base_i := f_x_to_zero(left.tdc_buf_cur_base_i) or f_x_to_zero(right.tdc_buf_cur_base_i);
tmp.tdc_buf_cur_count_i := f_x_to_zero(left.tdc_buf_cur_count_i) or f_x_to_zero(right.tdc_buf_cur_count_i);
tmp.tdc_buf_cur_size_size_i := f_x_to_zero(left.tdc_buf_cur_size_size_i) or f_x_to_zero(right.tdc_buf_cur_size_size_i);
tmp.tdc_buf_cur_size_valid_i := f_x_to_zero(left.tdc_buf_cur_size_valid_i) or f_x_to_zero(right.tdc_buf_cur_size_valid_i);
tmp.tdc_buf_next_base_i := f_x_to_zero(left.tdc_buf_next_base_i) or f_x_to_zero(right.tdc_buf_next_base_i);
tmp.tdc_buf_next_size_size_i := f_x_to_zero(left.tdc_buf_next_size_size_i) or f_x_to_zero(right.tdc_buf_next_size_size_i);
tmp.tdc_buf_next_size_valid_i := f_x_to_zero(left.tdc_buf_next_size_valid_i) or f_x_to_zero(right.tdc_buf_next_size_valid_i);
return tmp;
end function;
end package body;
hdl/rtl/tdc_core_pkg.vhd
View file @ 0724de2e
......@@ -60,6 +60,29 @@ use work.gencores_pkg.all;
--=================================================================================================
package tdc_core_pkg is
type t_raw_acam_timestamp is record
slope : std_logic;
channel : std_logic_vector(2 downto 0);
n_bins : std_logic_vector(16 downto 0);
coarse : std_logic_vector(31 downto 0);
tai : std_logic_vector(31 downto 0);
end record;
type t_tdc_timestamp is record
slope : std_logic;
channel : std_logic_vector(2 downto 0);
frac : std_logic_vector(11 downto 0);
coarse : std_logic_vector(31 downto 0);
tai : std_logic_vector(31 downto 0);
seq : std_logic_vector(31 downto 0);
end record;
constant c_dummy_timestamp : t_tdc_timestamp :=
( '0', "000", x"000", x"00000000", x"00000000", x"00000000" );
type t_tdc_timestamp_array is array(integer range<>) of t_tdc_timestamp;
---------------------------------------------------------------------------------------------------
-- Constant regarding the Mezzanine DAC configuration --
---------------------------------------------------------------------------------------------------
......@@ -187,6 +210,23 @@ package tdc_core_pkg is
name => "WB-TDC-TsFIFO ")));
constant c_TDC_DMA_SDB_DEVICE : t_sdb_device :=
(abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component =>
(addr_first => x"0000000000000000",
addr_last => x"00000000000001FF",
product =>
(vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000623", -- "WB-TDC-Mem " | md5sum | cut -c1-8
version => x"00000001",
date => x"20150415",
name => "WB-TDC-TsDMAEngine ")));
---------------------------------------------------------------------------------------------------
-- Constants regarding 1 Hz pulse generation --
---------------------------------------------------------------------------------------------------
......@@ -396,12 +436,6 @@ package tdc_core_pkg is
tdc_led_trig3_o : out std_logic;
tdc_led_trig4_o : out std_logic;
tdc_led_trig5_o : out std_logic;
-- Input pulses arriving also to the FPGA, currently not treated
tdc_in_fpga_1_i : in std_logic;
tdc_in_fpga_2_i : in std_logic;
tdc_in_fpga_3_i : in std_logic;
tdc_in_fpga_4_i : in std_logic;
tdc_in_fpga_5_i : in std_logic;
-- White Rabbit core
wrabbit_link_up_i : in std_logic;
wrabbit_time_valid_i : in std_logic;
......@@ -470,11 +504,6 @@ package tdc_core_pkg is
tdc_led_trig3_o : out std_logic;
tdc_led_trig4_o : out std_logic;
tdc_led_trig5_o : out std_logic;
tdc_in_fpga_1_i : in std_logic;
tdc_in_fpga_2_i : in std_logic;
tdc_in_fpga_3_i : in std_logic;
tdc_in_fpga_4_i : in std_logic;
tdc_in_fpga_5_i : in std_logic;
wrabbit_status_reg_i : in std_logic_vector(g_width-1 downto 0);
wrabbit_ctrl_reg_o : out std_logic_vector(g_width-1 downto 0);
wrabbit_synched_i : in std_logic;
......@@ -482,7 +511,7 @@ package tdc_core_pkg is
wrabbit_tai_i : in std_logic_vector(31 downto 0);
cfg_slave_i : in t_wishbone_slave_in;
cfg_slave_o : out t_wishbone_slave_out;
timestamp_o : out std_logic_vector(127 downto 0);
timestamp_o : out t_tdc_timestamp;
timestamp_stb_o : out std_logic;
channel_enable_o : out std_logic_vector(4 downto 0);
irq_threshold_o : out std_logic_vector(9 downto 0);
......@@ -910,11 +939,6 @@ package tdc_core_pkg is
tdc_led_trig3_o : out std_logic;
tdc_led_trig4_o : out std_logic;
tdc_led_trig5_o : out std_logic;
tdc_in_fpga_1_i : in std_logic;
tdc_in_fpga_2_i : in std_logic;
tdc_in_fpga_3_i : in std_logic;
tdc_in_fpga_4_i : in std_logic;
tdc_in_fpga_5_i : in std_logic;
mezz_scl_o : out std_logic;
mezz_sda_o : out std_logic;
mezz_scl_i : in std_logic;
......@@ -936,6 +960,7 @@ package tdc_core_pkg is
irq_o : out std_logic;
clk_125m_tdc_o : out std_logic);
end component fmc_tdc_wrapper;
function f_pick(cond:boolean; if_true: std_logic_vector; if_false: std_logic_vector) return std_logic_vector;
......
hdl/rtl/tdc_dma_channel.vhd 0 → 100644
View file @ 0724de2e
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.tdc_core_pkg.all;
use work.wishbone_pkg.all;
use work.genram_pkg.all;
use work.tdc_buf_wbgen2_pkg.all;
entity tdc_dma_channel is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
ts_i : in t_tdc_timestamp;
ts_valid_i : in std_logic;
ts_ready_o : out std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
irq_tick_i : in std_logic;
irq_o : out std_logic;
dma_wb_o : out t_wishbone_master_out;
dma_wb_i : in t_wishbone_master_in
);
end tdc_dma_channel;
architecture rtl of tdc_dma_channel is
signal cur_base : unsigned(31 downto 0);
signal cur_size : unsigned(31 downto 0);
signal cur_valid : std_logic;
signal cur_pos : unsigned(31 downto 0);
signal next_base : unsigned(31 downto 0);
signal next_size : unsigned(31 downto 0);
signal next_valid : std_logic;
signal addr : unsigned(31 downto 0);
signal count : unsigned(31 downto 0);
signal burst_count : unsigned(8 downto 0);
signal irq_timer : unsigned(15 downto 0);
signal regs_out : t_TDC_BUF_out_registers;
signal regs_in : t_TDC_BUF_in_registers;
type t_STATE is (IDLE, SWITCH_BUFFERS, WAIT_NEXT_TS, SER0, SER1, SER2, SER3);
type t_DMA_STATE is (WAIT_BURST, EXECUTE_BURST, WAIT_ACKS);
signal fifo_in : std_logic_vector(33 downto 0);
alias fifo_in_data is fifo_in(31 downto 0);
alias fifo_in_is_addr is fifo_in(32);
alias fifo_in_last_in_buffer is fifo_in(33);
signal fifo_out : std_logic_vector(33 downto 0);
alias fifo_out_data is fifo_out(31 downto 0);
alias fifo_out_is_addr is fifo_out(32);
alias fifo_out_last_in_buffer is fifo_out(33);
signal fifo_rd, fifo_wr, fifo_full, fifo_empty, fifo_clear, fifo_valid : std_logic;
signal fifo_count : std_logic_vector(7 downto 0);
signal state : t_STATE;
signal dma_state : t_DMA_STATE;
signal ts : t_tdc_timestamp;
signal buffer_switch_latched : std_logic;
signal dma_addr : unsigned(31 downto 0);
signal burst_add : std_logic;
signal burst_sub : std_logic;
signal bursts_in_fifo : unsigned(3 downto 0);
signal ack_count : unsigned(5 downto 0);
signal dma_wb_out : t_wishbone_master_out;
signal irq_req : std_logic;
signal overflow : std_logic;
begin
U_WB_Regs : tdc_buffer_control_wb
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_i,
slave_i => slave_i,
slave_o => slave_o,
-- int_o => int_o,
regs_i => regs_in,
regs_o => regs_out);
p_irq_timer : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
irq_timer <= (others => '0');
irq_o <= '0';
else
irq_o <= '0';
if irq_req = '0' then
irq_timer <= (others => '0');
elsif irq_timer = unsigned(regs_out.tdc_buf_csr_irq_timeout_o) then
irq_o <= '1';
elsif irq_req = '1' and irq_tick_i = '1' then
irq_timer <= irq_timer + 1;
end if;
end if;
end if;
end process;
p_write_fsm : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
state <= IDLE;
fifo_wr <= '0';
fifo_clear <= '1';
buffer_switch_latched <= '0';
cur_valid <= '0';
next_valid <= '0';
addr <= (others => '0');
count <= (others => '0');
burst_add <= '0';
ts_ready_o <= '0';
irq_req <= '0';
else
fifo_wr <= '0';
fifo_clear <= '0';
fifo_in_last_in_buffer <= '0';
fifo_in_is_addr <= '0';
burst_add <= '0';
ts_ready_o <= '0';
if(regs_out.tdc_buf_csr_switch_buffers_o = '1') then
buffer_switch_latched <= '1';
end if;
if(regs_out.tdc_buf_cur_base_load_o = '1') then
cur_base <= resize(unsigned(regs_out.tdc_buf_cur_base_o), cur_base'length);
addr <= resize(unsigned(regs_out.tdc_buf_cur_base_o), cur_base'length);
end if;
if(regs_out.tdc_buf_cur_size_size_load_o = '1') then
cur_size <= resize(unsigned(regs_out.tdc_buf_cur_size_size_o), cur_size'length);
end if;
if(regs_out.tdc_buf_cur_size_valid_load_o = '1') then
cur_valid <= regs_out.tdc_buf_cur_size_valid_o;
end if;
if(regs_out.tdc_buf_next_base_load_o = '1') then
next_base <= resize(unsigned(regs_out.tdc_buf_next_base_o), next_base'length);
end if;
if(regs_out.tdc_buf_next_size_size_load_o = '1') then
next_size <= resize(unsigned(regs_out.tdc_buf_next_size_size_o), next_size'length);
end if;
if(regs_out.tdc_buf_next_size_valid_load_o = '1') then
next_valid <= regs_out.tdc_buf_next_size_valid_o;
end if;
case state is
when SWITCH_BUFFERS =>
count <= (others => '0');
cur_base <= next_base;
cur_valid <= next_valid;
cur_size <= next_size;
addr <= next_base;
next_valid <= '0';
buffer_switch_latched <= '0';
cur_pos <= count;
fifo_in_last_in_buffer <= '1';
fifo_wr <= '1';
if(next_valid = '1') then
irq_req <= '0';
end if;
state <= IDLE;
when IDLE =>
if(buffer_switch_latched = '1') then
state <= SWITCH_BUFFERS;
end if;
if regs_out.tdc_buf_csr_enable_o = '1' and ts_valid_i = '1' then
if cur_valid = '1' then
if count < cur_size then
ts <= ts_i;
state <= SER0;
fifo_in_is_addr <= '1';
fifo_in_data <= std_logic_vector(addr);
fifo_wr <= '1';
burst_count <= (others => '0');
irq_req <= '1';
ts_ready_o <= '1';
else
buffer_switch_latched <= '1';
end if;
overflow <= '0';
else
ts_ready_o <= '1';
overflow <= '1';
end if;
end if;
when WAIT_NEXT_TS =>
fifo_in_is_addr <= '0';
if regs_out.tdc_buf_csr_enable_o = '0' or burst_count = unsigned(regs_out.tdc_buf_csr_burst_size_o) or buffer_switch_latched = '1' then
burst_add <= '1';
state <= IDLE;
elsif ts_valid_i = '1' then
state <= SER0;
ts <= ts_i;
ts_ready_o <= '1';
end if;
--word 0 TAI
--word 1 coarse
--word 2 frac
--word 3
-- bit 31-4 sequence Id (mask: 0xFFFFFFF0)(it becomes smaller, is it possible?)
-- bit 3 slope (mask: 0x8)
-- bit 2-0 chan (mask: 0x7)
when SER0 =>
fifo_in_data <= ts.tai;
fifo_in_is_addr <= '0';
fifo_wr <= '1';
state <= SER1;
when SER1 =>
fifo_in_data <= ts.coarse;
fifo_in_is_addr <= '0';
fifo_wr <= '1';
state <= SER2;
when SER2 =>
fifo_in_data <= x"00000" & ts.frac;
fifo_in_is_addr <= '0';
fifo_wr <= '1';
state <= SER3;
when SER3 =>
fifo_in_data <= ts.seq(27 downto 0) & ts.slope & ts.channel(2 downto 0);
fifo_in_is_addr <= '0';
fifo_wr <= '1';
state <= WAIT_NEXT_TS;
count <= count + 1;
addr <= addr + 16;
burst_count <= burst_count + 1;
end case;
end if;
end if;
end process;
p_burst_counter : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
bursts_in_fifo <= (others => '0');
else
if burst_add = '1' and burst_sub = '0' then
bursts_in_fifo <= bursts_in_fifo + 1;
elsif burst_add = '0' and burst_sub = '1' then
bursts_in_fifo <= bursts_in_fifo - 1;
end if;
end if;
end if;
end process;
U_FIFO : generic_sync_fifo
generic map (
g_data_width => 34,
g_size => 256,
g_show_ahead => true)
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
d_i => fifo_in,
we_i => fifo_wr,
q_o => fifo_out,
rd_i => fifo_rd,
empty_o => fifo_empty,
full_o => fifo_full,
count_o => fifo_count);
------------------------------------------------------------------------------
-- Wishbone master (to DDR)
------------------------------------------------------------------------------
p_wb_master : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
dma_wb_out.cyc <= '0';
fifo_valid <= '0';
burst_sub <= '0';
dma_state <= WAIT_BURST;
regs_in.tdc_buf_csr_done_i <= '0';
else
burst_sub <= '0';
if regs_out.tdc_buf_csr_done_o = '1' and regs_out.tdc_buf_csr_done_load_o = '1' then
regs_in.tdc_buf_csr_done_i <= '0';
elsif fifo_empty = '0' and fifo_out_last_in_buffer = '1' then
regs_in.tdc_buf_csr_done_i <= '1';
end if;
case dma_state is
when WAIT_BURST =>
if bursts_in_fifo /= 0 and fifo_empty = '0' and fifo_out_is_addr = '1' and fifo_out_last_in_buffer = '0' then
dma_wb_out.cyc <= '1';
dma_addr <= unsigned(fifo_out_data);
dma_state <= EXECUTE_BURST;
burst_sub <= '1';
end if;
when EXECUTE_BURST =>
if fifo_rd = '1' then
dma_addr <= dma_addr + 4;
end if;
if fifo_empty = '1' then
dma_state <= WAIT_ACKS;
elsif fifo_out_is_addr = '1' and fifo_out_last_in_buffer = '0' then
dma_state <= WAIT_ACKS;
end if;
when WAIT_ACKS =>
if ack_count = 0 then
dma_wb_out.cyc <= '0';
dma_state <= WAIT_BURST;
end if;
end case;
end if;
end if;
end process;
p_fifo_control : process(dma_wb_i, bursts_in_fifo, fifo_empty, dma_state, fifo_out_is_addr, fifo_out_last_in_buffer)
begin
fifo_rd <= '0';
if (fifo_out_last_in_buffer = '1' and fifo_empty = '0') then
fifo_rd <= '1';
else
case dma_state is
when WAIT_BURST =>
if bursts_in_fifo /= 0 and fifo_empty = '0' and fifo_out_is_addr = '1' then
fifo_rd <= '1';
end if;
when EXECUTE_BURST =>
if fifo_empty = '0' and dma_wb_i.stall = '0' and fifo_out_is_addr = '0' then
fifo_rd <= '1';
end if;
when WAIT_ACKS =>
fifo_rd <= '0';
end case;
end if;
end process;
p_count_acks : process(clk_i)
begin
if rising_edge(clk_i) then
if dma_wb_out.cyc = '0' then
ack_count <= (others => '0');
elsif(dma_wb_out.cyc = '1' and dma_wb_out.stb = '1' and dma_wb_i.stall = '0' and dma_wb_i.ack = '0') then
ack_count <= ack_count + 1;
elsif((dma_wb_out.stb = '0' or dma_wb_i.stall = '1') and dma_wb_i.ack = '1') then
ack_count <= ack_count - 1;
end if;
end if;
end process;
dma_wb_out.adr <= std_logic_vector(dma_addr);
dma_wb_out.dat <= fifo_out_data;
dma_wb_out.stb <= not fifo_empty and not fifo_out_is_addr when (dma_state = EXECUTE_BURST) else '0';
dma_wb_out.we <= '1';
dma_wb_out.sel <= (others => '1');
dma_wb_o <= dma_wb_out;
regs_in.tdc_buf_cur_base_i <= std_logic_vector(resize(cur_base, 32));
regs_in.tdc_buf_cur_size_size_i <= std_logic_vector(resize(cur_size, 30));
regs_in.tdc_buf_cur_size_valid_i <= cur_valid;
regs_in.tdc_buf_next_base_i <= std_logic_vector(resize(next_base, 32));
regs_in.tdc_buf_next_size_size_i <= std_logic_vector(resize(next_size, 30));
regs_in.tdc_buf_next_size_valid_i <= next_valid;
regs_in.tdc_buf_cur_count_i <= std_logic_vector(resize(cur_pos, 32));
end rtl;
hdl/rtl/tdc_dma_channel_regs.vhd 0 → 100644
View file @ 0724de2e
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for TDC DMA Channel Control Registers
---------------------------------------------------------------------------------------
-- File : tdc_dma_channel_regs.vhd
-- Author : auto-generated by wbgen2 from wbgen/tdc_dma_channel_regs.wb
-- Created : Wed Jul 18 23:25:00 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/tdc_dma_channel_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.TDMA_wbgen2_pkg.all;
entity tdc_dma_channel_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
regs_i : in t_TDMA_in_registers;
regs_o : out t_TDMA_out_registers
);
end tdc_dma_channel_wb;
architecture syn of tdc_dma_channel_wb is
signal tdma_csr_enable_int : std_logic ;
signal tdma_csr_irq_timeout_int : std_logic_vector(9 downto 0);
signal tdma_csr_burst_size_int : std_logic_vector(9 downto 0);
signal tdma_csr_switch_buffers_dly0 : std_logic ;
signal tdma_csr_switch_buffers_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(2 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments
wrdata_reg <= slave_i.dat;
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
tdma_csr_enable_int <= '0';
tdma_csr_irq_timeout_int <= "0000000000";
tdma_csr_burst_size_int <= "0000000000";
tdma_csr_switch_buffers_int <= '0';
regs_o.tdma_csr_done_load_o <= '0';
regs_o.tdma_csr_overflow_load_o <= '0';
regs_o.tdma_cur_base_load_o <= '0';
regs_o.tdma_cur_size_size_load_o <= '0';
regs_o.tdma_cur_size_valid_load_o <= '0';
regs_o.tdma_next_base_load_o <= '0';
regs_o.tdma_next_size_size_load_o <= '0';
regs_o.tdma_next_size_valid_load_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
tdma_csr_switch_buffers_int <= '0';
regs_o.tdma_csr_done_load_o <= '0';
regs_o.tdma_csr_overflow_load_o <= '0';
regs_o.tdma_cur_base_load_o <= '0';
regs_o.tdma_cur_size_size_load_o <= '0';
regs_o.tdma_cur_size_valid_load_o <= '0';
regs_o.tdma_next_base_load_o <= '0';
regs_o.tdma_next_size_size_load_o <= '0';
regs_o.tdma_next_size_valid_load_o <= '0';
ack_in_progress <= '0';
else
regs_o.tdma_csr_done_load_o <= '0';
regs_o.tdma_csr_overflow_load_o <= '0';
regs_o.tdma_cur_base_load_o <= '0';
regs_o.tdma_cur_size_size_load_o <= '0';
regs_o.tdma_cur_size_valid_load_o <= '0';
regs_o.tdma_next_base_load_o <= '0';
regs_o.tdma_next_size_size_load_o <= '0';
regs_o.tdma_next_size_valid_load_o <= '0';
end if;
else
if ((slave_i.cyc = '1') and (slave_i.stb = '1')) then
case rwaddr_reg(2 downto 0) is
when "000" =>
if (slave_i.we = '1') then
tdma_csr_enable_int <= wrdata_reg(0);
tdma_csr_irq_timeout_int <= wrdata_reg(10 downto 1);
tdma_csr_burst_size_int <= wrdata_reg(20 downto 11);
tdma_csr_switch_buffers_int <= wrdata_reg(21);
regs_o.tdma_csr_done_load_o <= '1';
regs_o.tdma_csr_overflow_load_o <= '1';
end if;
rddata_reg(0) <= tdma_csr_enable_int;
rddata_reg(10 downto 1) <= tdma_csr_irq_timeout_int;
rddata_reg(20 downto 11) <= tdma_csr_burst_size_int;
rddata_reg(21) <= '0';
rddata_reg(22) <= regs_i.tdma_csr_done_i;
rddata_reg(23) <= regs_i.tdma_csr_overflow_i;
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "001" =>
if (slave_i.we = '1') then
regs_o.tdma_cur_base_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= regs_i.tdma_cur_base_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010" =>
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.tdma_cur_count_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011" =>
if (slave_i.we = '1') then
regs_o.tdma_cur_size_size_load_o <= '1';
regs_o.tdma_cur_size_valid_load_o <= '1';
end if;
rddata_reg(29 downto 0) <= regs_i.tdma_cur_size_size_i;
rddata_reg(30) <= regs_i.tdma_cur_size_valid_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
if (slave_i.we = '1') then
regs_o.tdma_next_base_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= regs_i.tdma_next_base_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101" =>
if (slave_i.we = '1') then
regs_o.tdma_next_size_size_load_o <= '1';
regs_o.tdma_next_size_valid_load_o <= '1';
end if;
rddata_reg(29 downto 0) <= regs_i.tdma_next_size_size_i;
rddata_reg(30) <= regs_i.tdma_next_size_valid_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
slave_o.dat <= rddata_reg;
-- Enable DMA
regs_o.tdma_csr_enable_o <= tdma_csr_enable_int;
-- IRQ Timeout (ms)
regs_o.tdma_csr_irq_timeout_o <= tdma_csr_irq_timeout_int;
-- Burst size (timestamps)
regs_o.tdma_csr_burst_size_o <= tdma_csr_burst_size_int;
-- Switch buffers
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
tdma_csr_switch_buffers_dly0 <= '0';
regs_o.tdma_csr_switch_buffers_o <= '0';
elsif rising_edge(clk_sys_i) then
tdma_csr_switch_buffers_dly0 <= tdma_csr_switch_buffers_int;
regs_o.tdma_csr_switch_buffers_o <= tdma_csr_switch_buffers_int and (not tdma_csr_switch_buffers_dly0);
end if;
end process;
-- DMA complete
regs_o.tdma_csr_done_o <= wrdata_reg(22);
-- DMA overflow
regs_o.tdma_csr_overflow_o <= wrdata_reg(23);
-- Base address
regs_o.tdma_cur_base_o <= wrdata_reg(31 downto 0);
-- Number of data samples in the buffer
-- Size (in transfers)
regs_o.tdma_cur_size_size_o <= wrdata_reg(29 downto 0);
-- Valid flag
regs_o.tdma_cur_size_valid_o <= wrdata_reg(30);
-- Base address
regs_o.tdma_next_base_o <= wrdata_reg(31 downto 0);
-- Size (in transfers)
regs_o.tdma_next_size_size_o <= wrdata_reg(29 downto 0);
-- Valid flag
regs_o.tdma_next_size_valid_o <= wrdata_reg(30);
rwaddr_reg <= slave_i.adr(4 downto 2);
slave_o.stall <= (not ack_sreg(0)) and (slave_i.stb and slave_i.cyc);
slave_o.err <= '0';
slave_o.rty <= '0';
-- ACK signal generation. Just pass the LSB of ACK counter.
slave_o.ack <= ack_sreg(0);
end syn;
hdl/rtl/tdc_dma_channel_wbgen2_pkg.vhd 0 → 100644
View file @ 0724de2e
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for TDC DMA Channel Control Registers
---------------------------------------------------------------------------------------
-- File : tdc_dma_channel_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wbgen/tdc_dma_channel_regs.wb
-- Created : Wed Jul 18 23:25:00 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/tdc_dma_channel_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package TDMA_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_TDMA_in_registers is record
tdma_csr_done_i : std_logic;
tdma_csr_overflow_i : std_logic;
tdma_cur_base_i : std_logic_vector(31 downto 0);
tdma_cur_count_i : std_logic_vector(31 downto 0);
tdma_cur_size_size_i : std_logic_vector(29 downto 0);
tdma_cur_size_valid_i : std_logic;
tdma_next_base_i : std_logic_vector(31 downto 0);
tdma_next_size_size_i : std_logic_vector(29 downto 0);
tdma_next_size_valid_i : std_logic;
end record;
constant c_TDMA_in_registers_init_value: t_TDMA_in_registers := (
tdma_csr_done_i => '0',
tdma_csr_overflow_i => '0',
tdma_cur_base_i => (others => '0'),
tdma_cur_count_i => (others => '0'),
tdma_cur_size_size_i => (others => '0'),
tdma_cur_size_valid_i => '0',
tdma_next_base_i => (others => '0'),
tdma_next_size_size_i => (others => '0'),
tdma_next_size_valid_i => '0'
);
-- Output registers (WB slave -> user design)
type t_TDMA_out_registers is record
tdma_csr_enable_o : std_logic;
tdma_csr_irq_timeout_o : std_logic_vector(9 downto 0);
tdma_csr_burst_size_o : std_logic_vector(9 downto 0);
tdma_csr_switch_buffers_o : std_logic;
tdma_csr_done_o : std_logic;
tdma_csr_done_load_o : std_logic;
tdma_csr_overflow_o : std_logic;
tdma_csr_overflow_load_o : std_logic;
tdma_cur_base_o : std_logic_vector(31 downto 0);
tdma_cur_base_load_o : std_logic;
tdma_cur_size_size_o : std_logic_vector(29 downto 0);
tdma_cur_size_size_load_o : std_logic;
tdma_cur_size_valid_o : std_logic;
tdma_cur_size_valid_load_o : std_logic;
tdma_next_base_o : std_logic_vector(31 downto 0);
tdma_next_base_load_o : std_logic;
tdma_next_size_size_o : std_logic_vector(29 downto 0);
tdma_next_size_size_load_o : std_logic;
tdma_next_size_valid_o : std_logic;
tdma_next_size_valid_load_o : std_logic;
end record;
constant c_TDMA_out_registers_init_value: t_TDMA_out_registers := (
tdma_csr_enable_o => '0',
tdma_csr_irq_timeout_o => (others => '0'),
tdma_csr_burst_size_o => (others => '0'),
tdma_csr_switch_buffers_o => '0',
tdma_csr_done_o => '0',
tdma_csr_done_load_o => '0',
tdma_csr_overflow_o => '0',
tdma_csr_overflow_load_o => '0',
tdma_cur_base_o => (others => '0'),
tdma_cur_base_load_o => '0',
tdma_cur_size_size_o => (others => '0'),
tdma_cur_size_size_load_o => '0',
tdma_cur_size_valid_o => '0',
tdma_cur_size_valid_load_o => '0',
tdma_next_base_o => (others => '0'),
tdma_next_base_load_o => '0',
tdma_next_size_size_o => (others => '0'),
tdma_next_size_size_load_o => '0',
tdma_next_size_valid_o => '0',
tdma_next_size_valid_load_o => '0'
);
function "or" (left, right: t_TDMA_in_registers) return t_TDMA_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
component tdc_dma_channel_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
regs_i : in t_TDMA_in_registers;
regs_o : out t_TDMA_out_registers
);
end component;
end package;
package body TDMA_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_TDMA_in_registers) return t_TDMA_in_registers is
variable tmp: t_TDMA_in_registers;
begin
tmp.tdma_csr_done_i := f_x_to_zero(left.tdma_csr_done_i) or f_x_to_zero(right.tdma_csr_done_i);
tmp.tdma_csr_overflow_i := f_x_to_zero(left.tdma_csr_overflow_i) or f_x_to_zero(right.tdma_csr_overflow_i);
tmp.tdma_cur_base_i := f_x_to_zero(left.tdma_cur_base_i) or f_x_to_zero(right.tdma_cur_base_i);
tmp.tdma_cur_count_i := f_x_to_zero(left.tdma_cur_count_i) or f_x_to_zero(right.tdma_cur_count_i);
tmp.tdma_cur_size_size_i := f_x_to_zero(left.tdma_cur_size_size_i) or f_x_to_zero(right.tdma_cur_size_size_i);
tmp.tdma_cur_size_valid_i := f_x_to_zero(left.tdma_cur_size_valid_i) or f_x_to_zero(right.tdma_cur_size_valid_i);
tmp.tdma_next_base_i := f_x_to_zero(left.tdma_next_base_i) or f_x_to_zero(right.tdma_next_base_i);
tmp.tdma_next_size_size_i := f_x_to_zero(left.tdma_next_size_size_i) or f_x_to_zero(right.tdma_next_size_size_i);
tmp.tdma_next_size_valid_i := f_x_to_zero(left.tdma_next_size_valid_i) or f_x_to_zero(right.tdma_next_size_valid_i);
return tmp;
end function;
end package body;
hdl/rtl/tdc_dma_engine.vhd 0 → 100644
View file @ 0724de2e
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.tdc_core_pkg.all;
use work.wishbone_pkg.all;
use work.genram_pkg.all;
use work.gencores_pkg.all;
entity tdc_dma_engine is
generic (
g_CLOCK_FREQ : integer := 62500000
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
ts_i : in t_tdc_timestamp_array(4 downto 0);
ts_valid_i : in std_logic_vector(4 downto 0);
ts_ready_o : out std_logic_vector(4 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
irq_o : out std_logic_vector(4 downto 0);
dma_wb_o : out t_wishbone_master_out;
dma_wb_i : in t_wishbone_master_in
);
end tdc_dma_engine;
architecture rtl of tdc_dma_engine is
signal cr_cnx_master_out : t_wishbone_master_out_array(4 downto 0);
signal cr_cnx_master_in : t_wishbone_master_in_array(4 downto 0);
signal dma_cnx_slave_out : t_wishbone_slave_out_array(4 downto 0);
signal dma_cnx_slave_in : t_wishbone_slave_in_array(4 downto 0);
signal c_CR_CNX_BASE_ADDR : t_wishbone_address_array(4 downto 0) :=
(0 => x"00000000",
1 => x"00000040",
2 => x"00000080",
3 => x"000000c0",
4 => x"00000100");
signal c_CR_CNX_BASE_MASK : t_wishbone_address_array(4 downto 0) :=
(0 => x"000001c0",
1 => x"000001c0",
2 => x"000001c0",
3 => x"000001c0",
4 => x"000001c0");
constant c_TIMER_PERIOD_MS : integer := 1;
constant c_TIMER_DIVIDER_VALUE : integer := g_CLOCK_FREQ * c_TIMER_PERIOD_MS / 1000 - 1;
signal irq_tick_div : unsigned(15 downto 0);
signal irq_tick : std_logic;
begin
p_irq_tick : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
irq_tick <= '0';
irq_tick_div <= (others => '0');
else
if irq_tick_div = c_TIMER_DIVIDER_VALUE then
irq_tick <= '1';
irq_tick_div <= (others => '0');
else
irq_tick <= '0';
irq_tick_div <= irq_tick_div + 1;
end if;
end if;
end if;
end process;
U_CR_Crossbar : xwb_crossbar
generic map (
g_num_masters => 1,
g_num_slaves => 5,
g_registered => true,
g_address => c_CR_CNX_BASE_ADDR,
g_mask => c_CR_CNX_BASE_MASK)
port map (
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
slave_i(0) => slave_i,
slave_o(0) => slave_o,
master_i => cr_cnx_master_in,
master_o => cr_cnx_master_out);
U_DMA_Crossbar : xwb_crossbar
generic map (
g_num_masters => 5,
g_num_slaves => 1,
g_registered => true,
g_address => (0 => x"00000000"),
g_mask => (0 => x"00000000"))
port map (
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
slave_i => dma_cnx_slave_in,
slave_o => dma_cnx_slave_out,
master_i(0) => dma_wb_i,
master_o(0) => dma_wb_o);
gen_channels : for i in 0 to 4 generate
U_DMA_Channel : entity work.tdc_dma_channel
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
ts_i => ts_i(i),
ts_valid_i => ts_valid_i(i),
ts_ready_o => ts_ready_o(i),
slave_i => cr_cnx_master_out(i),
slave_o => cr_cnx_master_in(i),
irq_o => irq_o(i),
irq_tick_i => irq_tick,
dma_wb_o => dma_cnx_slave_in(i),
dma_wb_i => dma_cnx_slave_out(i));
end generate gen_channels;
end rtl;
hdl/rtl/tdc_eic.vhd
View file @ 0724de2e
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : tdc_eic.vhd
-- Author : auto-generated by wbgen2 from wbgen/tdc_eic.wb
-- Created : Mon Apr 20 17:34:12 2015
-- Created : Mon Aug 6 23:30:18 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/tdc_eic.wb
......@@ -19,7 +19,7 @@ entity tdc_eic is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -27,33 +27,40 @@ entity tdc_eic is
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
irq_tdc_fifo1_i : in std_logic;
irq_tdc_fifo2_i : in std_logic;
irq_tdc_fifo3_i : in std_logic;
irq_tdc_fifo4_i : in std_logic;
irq_tdc_fifo5_i : in std_logic
irq_tdc_fifo5_i : in std_logic;
irq_tdc_dma1_i : in std_logic;
irq_tdc_dma2_i : in std_logic;
irq_tdc_dma3_i : in std_logic;
irq_tdc_dma4_i : in std_logic;
irq_tdc_dma5_i : in std_logic
);
end tdc_eic;
architecture syn of tdc_eic is
signal eic_idr_int : std_logic_vector(4 downto 0);
signal eic_idr_int : std_logic_vector(9 downto 0);
signal eic_idr_write_int : std_logic ;
signal eic_ier_int : std_logic_vector(4 downto 0);
signal eic_ier_int : std_logic_vector(9 downto 0);
signal eic_ier_write_int : std_logic ;
signal eic_imr_int : std_logic_vector(4 downto 0);
signal eic_isr_clear_int : std_logic_vector(4 downto 0);
signal eic_isr_status_int : std_logic_vector(4 downto 0);
signal eic_irq_ack_int : std_logic_vector(4 downto 0);
signal eic_imr_int : std_logic_vector(9 downto 0);
signal eic_isr_clear_int : std_logic_vector(9 downto 0);
signal eic_isr_status_int : std_logic_vector(9 downto 0);
signal eic_irq_ack_int : std_logic_vector(9 downto 0);
signal eic_isr_write_int : std_logic ;
signal irq_inputs_vector_int : std_logic_vector(4 downto 0);
signal irq_inputs_vector_int : std_logic_vector(9 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal rwaddr_reg : std_logic_vector(3 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
......@@ -61,13 +68,8 @@ signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
......@@ -93,8 +95,8 @@ begin
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
case rwaddr_reg(3 downto 0) is
when "0000" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
end if;
......@@ -132,7 +134,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
when "0001" =>
if (wb_we_i = '1') then
eic_ier_write_int <= '1';
end if;
......@@ -170,15 +172,10 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
when "0010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(4 downto 0) <= eic_imr_int(4 downto 0);
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(9 downto 0) <= eic_imr_int(9 downto 0);
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
......@@ -203,16 +200,11 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
when "0011" =>
if (wb_we_i = '1') then
eic_isr_write_int <= '1';
end if;
rddata_reg(4 downto 0) <= eic_isr_status_int(4 downto 0);
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(9 downto 0) <= eic_isr_status_int(9 downto 0);
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
......@@ -251,25 +243,25 @@ begin
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int(4 downto 0) <= wrdata_reg(4 downto 0);
eic_idr_int(9 downto 0) <= wrdata_reg(9 downto 0);
-- extra code for reg/fifo/mem: Interrupt enable register
eic_ier_int(4 downto 0) <= wrdata_reg(4 downto 0);
eic_ier_int(9 downto 0) <= wrdata_reg(9 downto 0);
-- extra code for reg/fifo/mem: Interrupt status register
eic_isr_clear_int(4 downto 0) <= wrdata_reg(4 downto 0);
eic_isr_clear_int(9 downto 0) <= wrdata_reg(9 downto 0);
-- extra code for reg/fifo/mem: IRQ_CONTROLLER
eic_irq_controller_inst : wbgen2_eic
eic_irq_controller_inst : entity work.wbgen2_eic_nomask
generic map (
g_num_interrupts => 5,
g_num_interrupts => 10,
g_irq00_mode => 3,
g_irq01_mode => 3,
g_irq02_mode => 3,
g_irq03_mode => 3,
g_irq04_mode => 3,
g_irq05_mode => 0,
g_irq06_mode => 0,
g_irq07_mode => 0,
g_irq08_mode => 0,
g_irq09_mode => 0,
g_irq05_mode => 3,
g_irq06_mode => 3,
g_irq07_mode => 3,
g_irq08_mode => 3,
g_irq09_mode => 3,
g_irq0a_mode => 0,
g_irq0b_mode => 0,
g_irq0c_mode => 0,
......@@ -314,8 +306,15 @@ begin
irq_inputs_vector_int(2) <= irq_tdc_fifo3_i;
irq_inputs_vector_int(3) <= irq_tdc_fifo4_i;
irq_inputs_vector_int(4) <= irq_tdc_fifo5_i;
irq_inputs_vector_int(5) <= irq_tdc_dma1_i;
irq_inputs_vector_int(6) <= irq_tdc_dma2_i;
irq_inputs_vector_int(7) <= irq_tdc_dma3_i;
irq_inputs_vector_int(8) <= irq_tdc_dma4_i;
irq_inputs_vector_int(9) <= irq_tdc_dma5_i;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
wb_err_o <= '0';
wb_rty_o <= '0';
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/rtl/tdc_ts_sub.vhd 0 → 100644
View file @ 0724de2e
-------------------------------------------------------------------------------
-- Title : Pipelined timestamp subtractor
-- Project : FMC TDC Core
-------------------------------------------------------------------------------
-- File : tdc_ts_sub.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-29
-- Last update: 2018-08-06
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Pipelined timestamp adder with re-normalization of the result.
-- Adds a to b, producing normalized timestamp q. A timestmap is normalized when
-- the 0 <= frac < 2**g_frac_bits, 0 <= coarse <= g_coarse_range-1 and utc >= 0.
-- For correct operation of renormalizer, input timestamps must meet the
-- following constraints:
-- 1. 0 <= (a/b)_frac_i <= 2**g_frac_bits-1
-- 2. -g_coarse_range+1 <= (a_coarse_i + b_coarse_i) <= 3*g_coarse_range-1
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN / BE-CO-HT
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.tdc_core_pkg.all;
entity tdc_ts_sub is
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
valid_i : in std_logic; -- when HI, a_* and b_* contain valid timestamps
enable_i : in std_logic := '1'; -- pipeline enable
a_i : in t_tdc_timestamp;
b_i : in t_tdc_timestamp;
valid_o : out std_logic;
q_o : out t_tdc_timestamp
);
end tdc_ts_sub;
architecture rtl of tdc_ts_sub is
constant c_NUM_PIPELINE_STAGES : integer := 4;
constant c_frac_bits : integer := 12;
constant c_coarse_range : integer := 125000000;
type t_internal_sum is record
tai : signed(32 downto 0);
coarse : signed(31 downto 0);
frac : signed(15 downto 0);
end record;
type t_internal_sum_array is array (integer range <>) of t_internal_sum;
signal pipe : std_logic_vector(c_NUM_PIPELINE_STAGES-1 downto 0);
signal sums : t_internal_sum_array(0 to c_NUM_PIPELINE_STAGES-1);
signal ovf_frac : std_logic;
signal ovf_coarse : std_logic;
signal unf_coarse : std_logic_vector(1 downto 0);
begin -- rtl
-- Pipeline stage 0: just subtract the two timestamps field by field
p_stage0 : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
pipe(0) <= '0';
elsif(enable_i = '1') then
pipe(0) <= valid_i;
sums(0).frac <= signed( resize(unsigned(a_i.frac) - unsigned(b_i.frac), 16) );
sums(0).coarse <= resize(signed(a_i.coarse), sums(0).coarse'length) -
resize(signed(b_i.coarse), sums(0).coarse'length);
sums(0).tai <= signed( resize(unsigned(a_i.tai) - unsigned(b_i.tai), 33) );
else
pipe(0) <= '0';
end if;
end if;
end process;
ovf_frac <= std_logic(sums(0).frac(sums(0).frac'length-1));
-- Pipeline stage 1: check the fractional difference for underflow and eventually adjust
-- the coarse difference
p_stage1 : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
pipe(1) <= '0';
else
pipe(1) <= pipe(0);
if(ovf_frac = '1') then
sums(1).frac <= sums(0).frac + 2**c_frac_bits;
sums(1).coarse <= sums(0).coarse - 1;
else
sums(1).frac <= sums(0).frac;
sums(1).coarse <= sums(0).coarse;
end if;
sums(1).tai <= sums(0).tai;
end if;
end if;
end process;
-- Pipeline stage 2: check the coarse sum for under/overflows
p_stage2 : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
pipe(2) <= '0';
else
sums(2) <= sums(1);
pipe(2) <= pipe(1);
if(sums(1).coarse < 0) then
unf_coarse <= "10";
elsif(sums(1).coarse <= -c_coarse_range) then
unf_coarse <= "01";
else
unf_coarse <= "00";
end if;
end if;
end if;
end process;
-- Pipeline stage 3: adjust the coarse & TAI sums according to normalize the
-- previously detected under/overflows
p_stage3 : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
pipe(3) <= '0';
else
pipe(3) <= pipe(2);
if(unf_coarse = "10") then
sums(3).coarse <= sums(2).coarse + c_coarse_range;
sums(3).tai <= sums(2).tai - 1;
elsif(unf_coarse = "01") then
sums(3).coarse <= sums(2).coarse + 2*c_coarse_range;
sums(3).tai <= sums(2).tai - 2;
else
sums(3).coarse <= sums(2).coarse;
sums(3).tai <= sums(2).tai;
end if;
sums(3).frac <= sums(2).frac;
end if;
end if;
end process;
-- clip the extra bits and output the result
valid_o <= pipe(c_NUM_PIPELINE_STAGES-1);
q_o.tai <= std_logic_vector(sums(c_NUM_PIPELINE_STAGES-1).tai(31 downto 0));
q_o.coarse <= std_logic_vector(sums(c_NUM_PIPELINE_STAGES-1).coarse(31 downto 0));
q_o.frac <= std_logic_vector(sums(c_NUM_PIPELINE_STAGES-1).frac(11 downto 0));
end rtl;
hdl/rtl/timestamp_convert_filter.vhd 0 → 100644
View file @ 0724de2e
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.tdc_core_pkg.all;
use work.gencores_pkg.all;
entity timestamp_convert_filter is
port (
clk_tdc_i : in std_logic;
rst_tdc_n_i : in std_logic;
clk_sys_i : in std_logic;
rst_sys_n_i : in std_logic;
enable_i : in std_logic_vector(4 downto 0);
-- raw timestamp input, clk_tdc_i domain
ts_i : in t_raw_acam_timestamp;
ts_valid_i : in std_logic;
-- converted and filtered timestamp output, clk_sys_i domain
ts_o : out t_tdc_timestamp_array(4 downto 0);
ts_valid_o : out std_logic_vector(4 downto 0);
ts_ready_i : in std_logic_vector(4 downto 0)
);
end timestamp_convert_filter;
architecture rtl of timestamp_convert_filter is
constant c_MIN_PULSE_WIDTH_TICKS : integer := 12; -- 12 * 8 ns = 96 ns
constant c_FINE_SF : unsigned(17 downto 0) := to_unsigned(84934, 18);
constant c_FINE_SHIFT : integer := 11;
type t_channel_state is record
expected_edge : std_logic;
last_ts : t_tdc_timestamp;
last_valid : std_logic;
seq : unsigned(31 downto 0);
s1_delta_coarse : unsigned(31 downto 0);
s1_delta_tai : unsigned(31 downto 0);
s2_delta_coarse : unsigned(31 downto 0);
s2_delta_tai : unsigned(31 downto 0);
s1_valid, s2_valid : std_logic;
end record;
type t_channel_state_array is array(integer range<>) of t_channel_state;
signal channels : t_channel_state_array(0 to 4);
signal s1_frac_scaled : unsigned(31 downto 0);
signal s1_tai, s2_tai, s3_tai : unsigned(31 downto 0);
signal s1_valid, s2_valid, s3_valid : std_logic;
signal s1_coarse, s2_coarse, s3_coarse : unsigned(31 downto 0);
signal s2_frac, s3_frac : unsigned(11 downto 0);
signal coarse_adj : std_logic_vector(31 downto 0);
signal s1_channel, s2_channel, s3_channel : std_logic_vector(2 downto 0);
signal s1_edge, s2_edge, s3_edge : std_logic;
signal s3_ts : t_tdc_timestamp;
signal ts_valid_sys : std_logic;
begin
U_Sync_TS_Valid : gc_pulse_synchronizer2
port map (
clk_in_i => clk_tdc_i,
rst_in_n_i => rst_tdc_n_i,
clk_out_i => clk_sys_i,
rst_out_n_i => rst_sys_n_i,
d_ready_o => open,
d_p_i => ts_valid_i,
q_p_o => ts_valid_sys);
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_sys_n_i = '0' then
s1_valid <= '0';
s2_valid <= '0';
s3_valid <= '0';
else
-- 64/125 = 4096/8000: reduce fraction to avoid 64-bit division
-- frac = hwts->bins * 81 * 64 / 125;
-- stage 1: scale frac
s1_frac_scaled <= resize ((unsigned(ts_i.n_bins) * c_FINE_SF) srl c_FINE_SHIFT, 32);
s1_coarse <= unsigned(ts_i.coarse);
s1_tai <= unsigned(ts_i.tai);
s1_edge <= ts_i.slope;
s1_channel <= ts_i.channel;
s1_valid <= ts_valid_sys;
-- stage 2: adjust coarse
s2_frac <= s1_frac_scaled(11 downto 0);
s2_coarse <= unsigned(s1_coarse) + s1_frac_scaled(31 downto 12);
s2_tai <= s1_tai;
s2_edge <= s1_edge;
s2_channel <= s1_channel;
s2_valid <= s1_valid;
-- stage 3: roll-over coarse
if s2_coarse(31) = '1' then
s3_coarse <= s2_coarse + to_unsigned(125000000, 32);
s3_tai <= s2_tai - 1;
elsif (s2_coarse >= 125000000) then
s3_coarse <= s2_coarse - to_unsigned(125000000, 32);
s3_tai <= s2_tai + 1;
else
s3_coarse <= s2_coarse;
s3_tai <= s2_tai;
end if;
s3_frac <= s2_frac;
s3_edge <= s2_edge;
s3_channel <= s2_channel;
s3_valid <= s2_valid;
end if;
end if;
end process;
s3_ts.frac <= std_logic_vector(s3_frac);
s3_ts.coarse <= std_logic_vector(s3_coarse);
s3_ts.tai <= std_logic_vector(s3_tai);
s3_ts.slope <= s3_edge;
s3_ts.channel <= s3_channel;
gen_channels : for i in 0 to 4 generate
p_fsm : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_sys_n_i = '0' or enable_i(i) = '0' then
ts_valid_o(i) <= '0';
channels(i).expected_edge <= '1';
channels(i).s1_valid <= '0';
channels(i).s2_valid <= '0';
channels(i).last_valid <= '0';
channels(i).seq <= (others => '0');
else
channels(i).s1_valid <= '0';
if s3_valid = '1' and unsigned(s3_channel) = i then
-- report "s3_valid";
if (s3_ts.slope = '1') then -- rising edge
channels(i).last_ts <= s3_ts;
channels(i).last_valid <= '1';
channels(i).s1_valid <= '0';
-- report "rise";
else
channels(i).last_valid <= '0';
channels(i).s1_valid <= '1';
-- report "fall";
end if;
channels(i).s1_delta_coarse <= unsigned(s3_ts.coarse) - unsigned(channels(i).last_ts.coarse);
channels(i).s1_delta_tai <= unsigned(s3_ts.tai) - unsigned(channels(i).last_ts.tai);
end if;
if channels(i).s1_delta_coarse(31) = '1' then
channels(i).s2_delta_coarse <= channels(i).s1_delta_coarse + to_unsigned(125000000, 32);
channels(i).s2_delta_tai <= channels(i).s1_delta_tai - 1;
else
channels(i).s2_delta_coarse <= channels(i).s1_delta_coarse;
channels(i).s2_delta_tai <= channels(i).s1_delta_tai;
end if;
channels(i).s2_valid <= channels(i).s1_valid;
if(ts_ready_i(i) = '1') then
ts_valid_o(i) <= '0';
end if;
if channels(i).s2_valid = '1' then
if channels(i).s2_delta_tai = 0 and channels(i).s2_delta_coarse >= 12 then
ts_o(i).tai <= channels(i).last_ts.tai;
ts_o(i).coarse <= channels(i).last_ts.coarse;
ts_o(i).frac <= channels(i).last_ts.frac;
ts_o(i).channel <= channels(i).last_ts.channel;
ts_o(i).slope <= channels(i).last_ts.slope;
ts_o(i).seq <= std_logic_vector(channels(i).seq);
ts_valid_o(i) <= '1';
channels(i).seq <= channels(i).seq + 1;
end if;
end if;
end if;
end if;
end process;
end generate gen_channels;
--edge = hwts->metadata & (1 << 4) ? 1 : 0;
-- /* first, convert the timestamp from the HDL units (81 ps bins)
-- to the WR format (where fractional part is 8 ns rescaled to
-- 4096 units) */
-- ts.channel = channel + 1; /* We want to see channels starting from 1*/
-- ts.seconds = hwts->utc;
-- /* 64/125 = 4096/8000: reduce fraction to avoid 64-bit division */
-- frac = hwts->bins * 81 * 64 / 125;
-- ts.coarse = hwts->coarse + frac / 4096;
-- ts.frac = frac % 4096;
-- /* the addition above may result with the coarse counter going
-- out of range: */
-- if (unlikely(ts.coarse >= 125000000)) {
-- ts.coarse -= 125000000;
-- ts.seconds++;
-- }
-- /* A trivial state machine to remove glitches, react on rising edge only
-- and drop pulses that are narrower than 100 ns.
-- We are waiting for a falling edge,
-- but a rising one occurs - ignore it.
-- */
-- if (unlikely(edge != st->expected_edge)) {
-- /* wait unconditionally for next rising edge */
-- st->expected_edge = 1;
-- return 0;
-- }
-- /* From this point we are working with the expected EDGE */
-- if (st->expected_edge == 1) {
-- /* We received a raising edge, save the time stamp and
-- wait for the falling edge */
-- st->prev_ts = ts;
-- st->expected_edge = 0;
-- return 0;
-- }
-- /* got a falling edge after a rising one */
-- diff = ts;
-- ft_ts_sub(&diff, &st->prev_ts);
-- /* Check timestamp width. Must be at least 100 ns
-- (coarse = 12, frac = 2048) */
-- if (likely(diff.seconds || diff.coarse > 12
-- || (diff.coarse == 12 && diff.frac >= 2048))) {
-- ts = st->prev_ts;
-- ft_ts_apply_offset(&ts, ft->calib.zero_offset[channel - 1]);
-- ft_ts_apply_offset(&ts, -ft->calib.wr_offset);
-- if (st->user_offset)
-- ft_ts_apply_offset(&ts, st->user_offset);
-- ts.gseq_id = ft->sequence++;
-- /* Got a dacapo flag? make a gap in the sequence ID to indicate
-- an unknown loss of timestamps */
-- ts.dseq_id = st->cur_seq_id++;
-- if (dacapo_flag) {
-- ts.dseq_id++;
-- st->cur_seq_id++;
-- }
-- ts.hseq_id = hwts->metadata >> 5;
-- /* Return a valid timestamp */
-- *wrts = ts;
-- ret = 1;
-- }
-- /* Wait for the next raising edge */
-- st->expected_edge = 1;
end rtl;
hdl/rtl/timestamp_fifo.vhd
View file @ 0724de2e
......@@ -23,6 +23,7 @@ use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
use work.tsf_wbgen2_pkg.all;
use work.tdc_core_pkg.all;
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
......@@ -32,9 +33,7 @@ entity timestamp_fifo is
);
port (
clk_sys_i : in std_logic;
clk_tdc_i : in std_logic;
rst_n_sys_i : in std_logic;
rst_tdc_i : in std_logic;
rst_sys_n_i : in std_logic;
-- WB slave, system clock
slave_i : in t_wishbone_slave_in;
......@@ -45,36 +44,17 @@ entity timestamp_fifo is
enable_i : in std_logic; -- channel enable, TDC clock
tick_i : in std_logic; -- 1ms tick, TDC clock
irq_threshold_i : in std_logic_vector(9 downto 0);
irq_timeout_i : in std_logic_vector(9 downto 0);
irq_timeout_i : in std_logic_vector(9 downto 0);
timestamp_i : in std_logic_vector(127 downto 0);
timestamp_valid_i : in std_logic
timestamp_i : in t_tdc_timestamp_array(4 downto 0);
timestamp_valid_i : in std_logic_vector(4 downto 0)
);
end entity;
architecture rtl of timestamp_fifo is
component timestamp_fifo_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
clk_tdc_i : in std_logic;
regs_i : in t_tsf_in_registers;
regs_o : out t_tsf_out_registers);
end component timestamp_fifo_wb;
signal tmr_timeout : unsigned(9 downto 0);
signal buf_irq_int : std_logic;
signal buf_count : unsigned(9 downto 0);
......@@ -86,44 +66,45 @@ architecture rtl of timestamp_fifo is
signal ts_match : std_logic;
signal seq_counter : unsigned(31 downto 0);
signal timestamp_with_seq : std_logic_vector(127 downto 0);
signal ref_valid : std_logic;
signal ref_ts : t_tdc_timestamp;
signal ref_channel : integer range 0 to 4;
signal sub_valid : std_logic;
signal sub_in_valid, sub_out_valid : std_logic;
signal sub_result : t_tdc_timestamp;
begin
timestamp_with_seq(95 downto 0) <= timestamp_i(95 downto 0); -- TS
timestamp_with_seq(98 downto 96) <= timestamp_i(98 downto 96); -- channel
timestamp_with_seq(100) <= timestamp_i(100); -- slope
timestamp_with_seq(127 downto 101) <= std_logic_vector(seq_counter(26 downto 0));
U_WB_Slave : timestamp_fifo_wb
timestamp_with_seq(31 downto 0) <= std_logic_vector(resize(unsigned(timestamp_i(g_channel).tai), 32));
timestamp_with_seq(63 downto 32) <= std_logic_vector(resize(unsigned(timestamp_i(g_channel).coarse), 32));
timestamp_with_seq(95 downto 64) <= std_logic_vector(resize(unsigned(timestamp_i(g_channel).frac), 32));
timestamp_with_seq(98 downto 96) <= timestamp_i(g_channel).channel;
timestamp_with_seq(99) <= timestamp_i(g_channel).slope;
timestamp_with_seq(127 downto 100) <= timestamp_i(g_channel).seq(27 downto 0);
U_WB_Slave : entity work.timestamp_fifo_wb
port map (
rst_n_i => rst_n_sys_i,
clk_sys_i => clk_sys_i,
wb_adr_i => slave_i.adr(5 downto 2),
wb_dat_i => slave_i.dat,
wb_dat_o => slave_o.dat,
wb_cyc_i => slave_i.cyc,
wb_sel_i => slave_i.sel,
wb_stb_i => slave_i.stb,
wb_we_i => slave_i.we,
wb_ack_o => slave_o.ack,
wb_stall_o => slave_o.stall,
clk_tdc_i => clk_tdc_i,
regs_i => regs_in,
regs_o => regs_out);
rst_n_i => rst_sys_n_i,
clk_sys_i => clk_sys_i,
slave_i => slave_i,
slave_o => slave_o,
regs_i => regs_in,
regs_o => regs_out);
buf_count <= resize(unsigned(regs_out.fifo_wr_usedw_o), 10);
ts_match <= '1' when timestamp_valid_i = '1' and unsigned(timestamp_i(98 downto 96)) = g_channel else '0';
p_fifo_write : process(clk_tdc_i)
ts_match <= timestamp_valid_i(g_channel);
p_fifo_write : process(clk_sys_i)
begin
if rising_edge(clk_tdc_i) then
if rst_tdc_i = '1' then
if rising_edge(clk_sys_i) then
if rst_sys_n_i = '0' then
regs_in.fifo_wr_req_i <= '0';
else
if(enable_i = '1' and regs_out.fifo_wr_full_o = '0' and ts_match = '1') then
regs_in.fifo_wr_req_i <= '1';
else
......@@ -138,47 +119,38 @@ begin
regs_in.fifo_ts2_i <= timestamp_with_seq(95 downto 64);
regs_in.fifo_ts3_i <= timestamp_with_seq(127 downto 96);
p_seq_counter : process(clk_tdc_i)
p_latch_ref_timestamp : process(clk_sys_i)
begin
if rising_edge(clk_tdc_i) then
if rst_tdc_i = '1' or regs_out.csr_rst_seq_o = '1' then
seq_counter <= (others => '0');
else
if(enable_i = '1' and ts_match = '1') then
seq_counter <= seq_counter + 1;
end if;
end if;
end if;
end process;
p_latch_last_timestamp : process(clk_tdc_i)
begin
if rising_edge(clk_tdc_i) then
if rst_tdc_i = '1' then
regs_in.csr_last_valid_i <= '0';
if rising_edge(clk_sys_i) then
if rst_sys_n_i = '0' or enable_i = '0' then
ref_valid <= '0';
else
-- latch only the last rising edge TS
if (enable_i = '1' and ts_match = '1' and timestamp_with_seq(100) = '1') then
regs_in.csr_last_valid_i <= '1';
last_ts <= timestamp_with_seq;
elsif (regs_out.csr_last_valid_o = '0' and regs_out.csr_last_valid_load_o = '1') then
regs_in.csr_last_valid_i <= '0';
end if;
if (regs_out.csr_last_valid_o = '0' and regs_out.csr_last_valid_load_o = '1') then
regs_in.lts0_i <= last_ts(31 downto 0);
regs_in.lts1_i <= last_ts(63 downto 32);
regs_in.lts2_i <= last_ts(95 downto 64);
regs_in.lts3_i <= last_ts(127 downto 96);
if (enable_i = '1' and timestamp_valid_i(ref_channel) = '1') then
ref_valid <= '1';
ref_ts <= timestamp_i(ref_channel);
end if;
end if;
end if;
end process;
p_coalesce_irq : process(clk_tdc_i)
sub_valid <= ref_valid and ts_match;
U_Subtractor: entity work.tdc_ts_sub
port map (
clk_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
valid_i => sub_in_valid,
enable_i => enable_i,
a_i => timestamp_i(g_channel),
b_i => ref_ts,
valid_o => sub_out_valid,
q_o => sub_result);
p_coalesce_irq : process(clk_sys_i)
begin
if rising_edge(clk_tdc_i) then
if rst_tdc_i = '1' or enable_i = '0' then
if rising_edge(clk_sys_i) then
if rst_sys_n_i = '0' or enable_i = '0' then
buf_irq_int <= '0';
else
if(regs_out.fifo_wr_empty_o = '1') then
......@@ -209,11 +181,6 @@ begin
end if;
end process;
U_Sync_IRQ : gc_sync_ffs
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_sys_i,
data_i => buf_irq_int,
synced_o => irq_o);
irq_o <= buf_irq_int;
end rtl;
hdl/rtl/timestamp_fifo_wb.vhd
View file @ 0724de2e
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : timestamp_fifo_wb.vhd
-- Author : auto-generated by wbgen2 from wbgen/timestamp_fifo_wb.wb
-- Created : Wed Sep 20 18:41:08 2017
-- Created : Mon Aug 6 23:30:18 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/timestamp_fifo_wb.wb
......@@ -14,27 +14,21 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
use work.wishbone_pkg.all;
use work.tsf_wbgen2_pkg.all;
entity timestamp_fifo_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
clk_tdc_i : in std_logic;
regs_i : in t_tsf_in_registers;
regs_o : out t_tsf_out_registers
);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
regs_i : in t_tsf_in_registers;
regs_o : out t_tsf_out_registers
);
end timestamp_fifo_wb;
architecture syn of timestamp_fifo_wb is
......@@ -44,469 +38,260 @@ signal tsf_fifo_in_int : std_logic_vector(127 downto 0)
signal tsf_fifo_out_int : std_logic_vector(127 downto 0);
signal tsf_fifo_rdreq_int : std_logic ;
signal tsf_fifo_rdreq_int_d0 : std_logic ;
signal tsf_lts0_int : std_logic_vector(31 downto 0);
signal tsf_lts0_lwb : std_logic ;
signal tsf_lts0_lwb_delay : std_logic ;
signal tsf_lts0_lwb_in_progress : std_logic ;
signal tsf_lts0_lwb_s0 : std_logic ;
signal tsf_lts0_lwb_s1 : std_logic ;
signal tsf_lts0_lwb_s2 : std_logic ;
signal tsf_lts1_int : std_logic_vector(31 downto 0);
signal tsf_lts1_lwb : std_logic ;
signal tsf_lts1_lwb_delay : std_logic ;
signal tsf_lts1_lwb_in_progress : std_logic ;
signal tsf_lts1_lwb_s0 : std_logic ;
signal tsf_lts1_lwb_s1 : std_logic ;
signal tsf_lts1_lwb_s2 : std_logic ;
signal tsf_lts2_int : std_logic_vector(31 downto 0);
signal tsf_lts2_lwb : std_logic ;
signal tsf_lts2_lwb_delay : std_logic ;
signal tsf_lts2_lwb_in_progress : std_logic ;
signal tsf_lts2_lwb_s0 : std_logic ;
signal tsf_lts2_lwb_s1 : std_logic ;
signal tsf_lts2_lwb_s2 : std_logic ;
signal tsf_lts3_int : std_logic_vector(31 downto 0);
signal tsf_lts3_lwb : std_logic ;
signal tsf_lts3_lwb_delay : std_logic ;
signal tsf_lts3_lwb_in_progress : std_logic ;
signal tsf_lts3_lwb_s0 : std_logic ;
signal tsf_lts3_lwb_s1 : std_logic ;
signal tsf_lts3_lwb_s2 : std_logic ;
signal tsf_csr_last_valid_int_read : std_logic ;
signal tsf_csr_last_valid_int_write : std_logic ;
signal tsf_csr_last_valid_lw : std_logic ;
signal tsf_csr_last_valid_lw_delay : std_logic ;
signal tsf_csr_last_valid_lw_read_in_progress : std_logic ;
signal tsf_csr_last_valid_lw_s0 : std_logic ;
signal tsf_csr_last_valid_lw_s1 : std_logic ;
signal tsf_csr_last_valid_lw_s2 : std_logic ;
signal tsf_csr_last_valid_rwsel : std_logic ;
signal tsf_csr_rst_seq_dly0 : std_logic ;
signal tsf_csr_rst_seq_int : std_logic ;
signal tsf_csr_rst_seq_int_delay : std_logic ;
signal tsf_csr_rst_seq_sync0 : std_logic ;
signal tsf_csr_rst_seq_sync1 : std_logic ;
signal tsf_csr_rst_seq_sync2 : std_logic ;
signal tsf_csr_delta_ref_int : std_logic_vector(2 downto 0);
signal tsf_fifo_full_int : std_logic ;
signal tsf_fifo_empty_int : std_logic ;
signal tsf_fifo_clear_bus_int : std_logic ;
signal tsf_fifo_usedw_int : std_logic_vector(8 downto 0);
signal tsf_fifo_usedw_int : std_logic_vector(5 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(3 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
wrdata_reg <= slave_i.dat;
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
tsf_lts0_lwb <= '0';
tsf_lts0_lwb_delay <= '0';
tsf_lts0_lwb_in_progress <= '0';
tsf_lts1_lwb <= '0';
tsf_lts1_lwb_delay <= '0';
tsf_lts1_lwb_in_progress <= '0';
tsf_lts2_lwb <= '0';
tsf_lts2_lwb_delay <= '0';
tsf_lts2_lwb_in_progress <= '0';
tsf_lts3_lwb <= '0';
tsf_lts3_lwb_delay <= '0';
tsf_lts3_lwb_in_progress <= '0';
tsf_csr_last_valid_lw <= '0';
tsf_csr_last_valid_lw_delay <= '0';
tsf_csr_last_valid_lw_read_in_progress <= '0';
tsf_csr_last_valid_rwsel <= '0';
tsf_csr_last_valid_int_write <= '0';
tsf_csr_rst_seq_int <= '0';
tsf_csr_rst_seq_int_delay <= '0';
tsf_fifo_clear_bus_int <= '0';
tsf_fifo_rdreq_int <= '0';
elsif rising_edge(clk_sys_i) then
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
regs_o.csr_delta_valid_load_o <= '0';
tsf_csr_rst_seq_int <= '0';
tsf_csr_delta_ref_int <= "000";
tsf_fifo_clear_bus_int <= '0';
tsf_fifo_rdreq_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
tsf_fifo_clear_bus_int <= '0';
ack_in_progress <= '0';
else
tsf_lts0_lwb <= tsf_lts0_lwb_delay;
tsf_lts0_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (tsf_lts0_lwb_in_progress = '1')) then
rddata_reg(31 downto 0) <= tsf_lts0_int;
tsf_lts0_lwb_in_progress <= '0';
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
regs_o.csr_delta_valid_load_o <= '0';
tsf_csr_rst_seq_int <= '0';
tsf_fifo_clear_bus_int <= '0';
ack_in_progress <= '0';
else
regs_o.csr_delta_valid_load_o <= '0';
end if;
else
if ((slave_i.cyc = '1') and (slave_i.stb = '1')) then
case rwaddr_reg(3 downto 0) is
when "0000" =>
if (slave_i.we = '1') then
end if;
tsf_lts1_lwb <= tsf_lts1_lwb_delay;
tsf_lts1_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (tsf_lts1_lwb_in_progress = '1')) then
rddata_reg(31 downto 0) <= tsf_lts1_int;
tsf_lts1_lwb_in_progress <= '0';
rddata_reg(31 downto 0) <= regs_i.delta0_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0001" =>
if (slave_i.we = '1') then
end if;
tsf_lts2_lwb <= tsf_lts2_lwb_delay;
tsf_lts2_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (tsf_lts2_lwb_in_progress = '1')) then
rddata_reg(31 downto 0) <= tsf_lts2_int;
tsf_lts2_lwb_in_progress <= '0';
rddata_reg(31 downto 0) <= regs_i.delta1_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010" =>
if (slave_i.we = '1') then
end if;
tsf_lts3_lwb <= tsf_lts3_lwb_delay;
tsf_lts3_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (tsf_lts3_lwb_in_progress = '1')) then
rddata_reg(31 downto 0) <= tsf_lts3_int;
tsf_lts3_lwb_in_progress <= '0';
rddata_reg(31 downto 0) <= regs_i.delta2_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011" =>
if (slave_i.we = '1') then
end if;
tsf_csr_last_valid_lw <= tsf_csr_last_valid_lw_delay;
tsf_csr_last_valid_lw_delay <= '0';
if ((ack_sreg(1) = '1') and (tsf_csr_last_valid_lw_read_in_progress = '1')) then
rddata_reg(0) <= tsf_csr_last_valid_int_read;
tsf_csr_last_valid_lw_read_in_progress <= '0';
rddata_reg(31 downto 0) <= regs_i.delta3_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100" =>
if (slave_i.we = '1') then
regs_o.csr_delta_valid_load_o <= '1';
tsf_csr_rst_seq_int <= wrdata_reg(1);
tsf_csr_delta_ref_int <= wrdata_reg(4 downto 2);
end if;
tsf_csr_rst_seq_int <= tsf_csr_rst_seq_int_delay;
tsf_csr_rst_seq_int_delay <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(3 downto 0) is
when "0000" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
tsf_lts0_lwb <= '1';
tsf_lts0_lwb_delay <= '1';
tsf_lts0_lwb_in_progress <= '1';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "0001" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
tsf_lts1_lwb <= '1';
tsf_lts1_lwb_delay <= '1';
tsf_lts1_lwb_in_progress <= '1';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "0010" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
tsf_lts2_lwb <= '1';
tsf_lts2_lwb_delay <= '1';
tsf_lts2_lwb_in_progress <= '1';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "0011" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
tsf_lts3_lwb <= '1';
tsf_lts3_lwb_delay <= '1';
tsf_lts3_lwb_in_progress <= '1';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "0100" =>
if (wb_we_i = '1') then
tsf_csr_last_valid_int_write <= wrdata_reg(0);
tsf_csr_last_valid_lw <= '1';
tsf_csr_last_valid_lw_delay <= '1';
tsf_csr_last_valid_lw_read_in_progress <= '0';
tsf_csr_last_valid_rwsel <= '1';
tsf_csr_rst_seq_int <= wrdata_reg(1);
tsf_csr_rst_seq_int_delay <= wrdata_reg(1);
end if;
if (wb_we_i = '0') then
rddata_reg(0) <= 'X';
tsf_csr_last_valid_lw <= '1';
tsf_csr_last_valid_lw_delay <= '1';
tsf_csr_last_valid_lw_read_in_progress <= '1';
tsf_csr_last_valid_rwsel <= '0';
end if;
rddata_reg(1) <= '0';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "0101" =>
if (wb_we_i = '1') then
end if;
if (tsf_fifo_rdreq_int_d0 = '0') then
tsf_fifo_rdreq_int <= not tsf_fifo_rdreq_int;
else
rddata_reg(31 downto 0) <= tsf_fifo_out_int(31 downto 0);
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
when "0110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= tsf_fifo_out_int(63 downto 32);
ack_sreg(0) <= '1';
rddata_reg(0) <= regs_i.csr_delta_valid_i;
rddata_reg(1) <= '0';
rddata_reg(4 downto 2) <= tsf_csr_delta_ref_int;
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "0101" =>
if (slave_i.we = '1') then
end if;
if (tsf_fifo_rdreq_int_d0 = '0') then
tsf_fifo_rdreq_int <= not tsf_fifo_rdreq_int;
else
rddata_reg(31 downto 0) <= tsf_fifo_out_int(31 downto 0);
ack_in_progress <= '1';
when "0111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= tsf_fifo_out_int(95 downto 64);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= tsf_fifo_out_int(127 downto 96);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001" =>
if (wb_we_i = '1') then
if (wrdata_reg(18) = '1') then
tsf_fifo_clear_bus_int <= '1';
end if;
end if;
when "0110" =>
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= tsf_fifo_out_int(63 downto 32);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111" =>
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= tsf_fifo_out_int(95 downto 64);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" =>
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= tsf_fifo_out_int(127 downto 96);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001" =>
if (slave_i.we = '1') then
if (wrdata_reg(18) = '1') then
tsf_fifo_clear_bus_int <= '1';
end if;
rddata_reg(16) <= tsf_fifo_full_int;
rddata_reg(17) <= tsf_fifo_empty_int;
rddata_reg(18) <= '0';
rddata_reg(8 downto 0) <= tsf_fifo_usedw_int;
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
end if;
rddata_reg(16) <= tsf_fifo_full_int;
rddata_reg(17) <= tsf_fifo_empty_int;
rddata_reg(18) <= '0';
rddata_reg(5 downto 0) <= tsf_fifo_usedw_int;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end process;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
slave_o.dat <= rddata_reg;
-- extra code for reg/fifo/mem: Timestamp FIFO
tsf_fifo_in_int(31 downto 0) <= regs_i.fifo_ts0_i;
tsf_fifo_in_int(63 downto 32) <= regs_i.fifo_ts1_i;
tsf_fifo_in_int(95 downto 64) <= regs_i.fifo_ts2_i;
tsf_fifo_in_int(127 downto 96) <= regs_i.fifo_ts3_i;
tsf_fifo_rst_n <= rst_n_i and (not tsf_fifo_clear_bus_int);
tsf_fifo_INST : wbgen2_fifo_async
generic map (
g_size => 512,
g_width => 128,
g_usedw_size => 9
)
port map (
wr_req_i => regs_i.fifo_wr_req_i,
wr_full_o => regs_o.fifo_wr_full_o,
wr_empty_o => regs_o.fifo_wr_empty_o,
wr_usedw_o => regs_o.fifo_wr_usedw_o,
rd_full_o => tsf_fifo_full_int,
rd_empty_o => tsf_fifo_empty_int,
rd_usedw_o => tsf_fifo_usedw_int,
rd_req_i => tsf_fifo_rdreq_int,
rst_n_i => tsf_fifo_rst_n,
wr_clk_i => clk_tdc_i,
rd_clk_i => clk_sys_i,
wr_data_i => tsf_fifo_in_int,
rd_data_o => tsf_fifo_out_int
);
-- Last Timestamp Word 0
-- asynchronous std_logic_vector register : Last Timestamp Word 0 (type RO/WO, clk_tdc_i <-> clk_sys_i)
process (clk_tdc_i, rst_n_i)
begin
if (rst_n_i = '0') then
tsf_lts0_lwb_s0 <= '0';
tsf_lts0_lwb_s1 <= '0';
tsf_lts0_lwb_s2 <= '0';
tsf_lts0_int <= "00000000000000000000000000000000";
elsif rising_edge(clk_tdc_i) then
tsf_lts0_lwb_s0 <= tsf_lts0_lwb;
tsf_lts0_lwb_s1 <= tsf_lts0_lwb_s0;
tsf_lts0_lwb_s2 <= tsf_lts0_lwb_s1;
if ((tsf_lts0_lwb_s1 = '1') and (tsf_lts0_lwb_s2 = '0')) then
tsf_lts0_int <= regs_i.lts0_i;
end if;
end if;
end process;
-- Last Timestamp Word 1
-- asynchronous std_logic_vector register : Last Timestamp Word 1 (type RO/WO, clk_tdc_i <-> clk_sys_i)
process (clk_tdc_i, rst_n_i)
begin
if (rst_n_i = '0') then
tsf_lts1_lwb_s0 <= '0';
tsf_lts1_lwb_s1 <= '0';
tsf_lts1_lwb_s2 <= '0';
tsf_lts1_int <= "00000000000000000000000000000000";
elsif rising_edge(clk_tdc_i) then
tsf_lts1_lwb_s0 <= tsf_lts1_lwb;
tsf_lts1_lwb_s1 <= tsf_lts1_lwb_s0;
tsf_lts1_lwb_s2 <= tsf_lts1_lwb_s1;
if ((tsf_lts1_lwb_s1 = '1') and (tsf_lts1_lwb_s2 = '0')) then
tsf_lts1_int <= regs_i.lts1_i;
end if;
end if;
end process;
-- Last Timestamp Word 2
-- asynchronous std_logic_vector register : Last Timestamp Word 2 (type RO/WO, clk_tdc_i <-> clk_sys_i)
process (clk_tdc_i, rst_n_i)
begin
if (rst_n_i = '0') then
tsf_lts2_lwb_s0 <= '0';
tsf_lts2_lwb_s1 <= '0';
tsf_lts2_lwb_s2 <= '0';
tsf_lts2_int <= "00000000000000000000000000000000";
elsif rising_edge(clk_tdc_i) then
tsf_lts2_lwb_s0 <= tsf_lts2_lwb;
tsf_lts2_lwb_s1 <= tsf_lts2_lwb_s0;
tsf_lts2_lwb_s2 <= tsf_lts2_lwb_s1;
if ((tsf_lts2_lwb_s1 = '1') and (tsf_lts2_lwb_s2 = '0')) then
tsf_lts2_int <= regs_i.lts2_i;
end if;
end if;
end process;
-- Last Timestamp Word 3
-- asynchronous std_logic_vector register : Last Timestamp Word 3 (type RO/WO, clk_tdc_i <-> clk_sys_i)
process (clk_tdc_i, rst_n_i)
begin
if (rst_n_i = '0') then
tsf_lts3_lwb_s0 <= '0';
tsf_lts3_lwb_s1 <= '0';
tsf_lts3_lwb_s2 <= '0';
tsf_lts3_int <= "00000000000000000000000000000000";
elsif rising_edge(clk_tdc_i) then
tsf_lts3_lwb_s0 <= tsf_lts3_lwb;
tsf_lts3_lwb_s1 <= tsf_lts3_lwb_s0;
tsf_lts3_lwb_s2 <= tsf_lts3_lwb_s1;
if ((tsf_lts3_lwb_s1 = '1') and (tsf_lts3_lwb_s2 = '0')) then
tsf_lts3_int <= regs_i.lts3_i;
end if;
end if;
end process;
-- Last Timestamp Valid
-- asynchronous BIT register : Last Timestamp Valid (type RW/WO, clk_tdc_i <-> clk_sys_i)
process (clk_tdc_i, rst_n_i)
begin
if (rst_n_i = '0') then
tsf_csr_last_valid_lw_s0 <= '0';
tsf_csr_last_valid_lw_s1 <= '0';
tsf_csr_last_valid_lw_s2 <= '0';
tsf_csr_last_valid_int_read <= '0';
regs_o.csr_last_valid_load_o <= '0';
regs_o.csr_last_valid_o <= '0';
elsif rising_edge(clk_tdc_i) then
tsf_csr_last_valid_lw_s0 <= tsf_csr_last_valid_lw;
tsf_csr_last_valid_lw_s1 <= tsf_csr_last_valid_lw_s0;
tsf_csr_last_valid_lw_s2 <= tsf_csr_last_valid_lw_s1;
if ((tsf_csr_last_valid_lw_s2 = '0') and (tsf_csr_last_valid_lw_s1 = '1')) then
if (tsf_csr_last_valid_rwsel = '1') then
regs_o.csr_last_valid_o <= tsf_csr_last_valid_int_write;
regs_o.csr_last_valid_load_o <= '1';
else
regs_o.csr_last_valid_load_o <= '0';
tsf_csr_last_valid_int_read <= regs_i.csr_last_valid_i;
end if;
else
regs_o.csr_last_valid_load_o <= '0';
end if;
end if;
end process;
tsf_fifo_in_int(31 downto 0) <= regs_i.fifo_ts0_i;
tsf_fifo_in_int(63 downto 32) <= regs_i.fifo_ts1_i;
tsf_fifo_in_int(95 downto 64) <= regs_i.fifo_ts2_i;
tsf_fifo_in_int(127 downto 96) <= regs_i.fifo_ts3_i;
tsf_fifo_rst_n <= rst_n_i and (not tsf_fifo_clear_bus_int);
tsf_fifo_INST : wbgen2_fifo_sync
generic map (
g_size => 64,
g_width => 128,
g_usedw_size => 6
)
port map (
wr_req_i => regs_i.fifo_wr_req_i,
wr_full_o => regs_o.fifo_wr_full_o,
wr_empty_o => regs_o.fifo_wr_empty_o,
wr_usedw_o => regs_o.fifo_wr_usedw_o,
rd_full_o => tsf_fifo_full_int,
rd_empty_o => tsf_fifo_empty_int,
rd_usedw_o => tsf_fifo_usedw_int,
rd_req_i => tsf_fifo_rdreq_int,
rst_n_i => tsf_fifo_rst_n,
clk_i => clk_sys_i,
wr_data_i => tsf_fifo_in_int,
rd_data_o => tsf_fifo_out_int
);
-- Delta Timestamp Word 0
-- Delta Timestamp Word 1
-- Delta Timestamp Word 2
-- Delta Timestamp Word 3
-- Delta Timestamp Valid
regs_o.csr_delta_valid_o <= wrdata_reg(0);
-- Reset Sequence Counter
process (clk_tdc_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.csr_rst_seq_o <= '0';
tsf_csr_rst_seq_sync0 <= '0';
tsf_csr_rst_seq_sync1 <= '0';
tsf_csr_rst_seq_sync2 <= '0';
elsif rising_edge(clk_tdc_i) then
tsf_csr_rst_seq_sync0 <= tsf_csr_rst_seq_int;
tsf_csr_rst_seq_sync1 <= tsf_csr_rst_seq_sync0;
tsf_csr_rst_seq_sync2 <= tsf_csr_rst_seq_sync1;
regs_o.csr_rst_seq_o <= tsf_csr_rst_seq_sync2 and (not tsf_csr_rst_seq_sync1);
end if;
end process;
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
tsf_csr_rst_seq_dly0 <= '0';
regs_o.csr_rst_seq_o <= '0';
elsif rising_edge(clk_sys_i) then
tsf_csr_rst_seq_dly0 <= tsf_csr_rst_seq_int;
regs_o.csr_rst_seq_o <= tsf_csr_rst_seq_int and (not tsf_csr_rst_seq_dly0);
end if;
end process;
-- Delta Timestamp Reference Channel
regs_o.csr_delta_ref_o <= tsf_csr_delta_ref_int;
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 0
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
tsf_fifo_rdreq_int_d0 <= '0';
elsif rising_edge(clk_sys_i) then
tsf_fifo_rdreq_int_d0 <= tsf_fifo_rdreq_int;
end if;
end process;
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
tsf_fifo_rdreq_int_d0 <= '0';
elsif rising_edge(clk_sys_i) then
tsf_fifo_rdreq_int_d0 <= tsf_fifo_rdreq_int;
end if;
end process;
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 2
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 3
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
rwaddr_reg <= slave_i.adr(5 downto 2);
slave_o.stall <= (not ack_sreg(0)) and (slave_i.stb and slave_i.cyc);
slave_o.err <= '0';
slave_o.rty <= '0';
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
slave_o.ack <= ack_sreg(0);
end syn;
hdl/rtl/timestamp_fifo_wbgen2_pkg.vhd
View file @ 0724de2e
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : timestamp_fifo_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wbgen/timestamp_fifo_wb.wb
-- Created : Wed Sep 20 18:41:08 2017
-- Created : Mon Aug 6 23:30:18 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/timestamp_fifo_wb.wb
......@@ -14,6 +14,7 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
use work.wishbone_pkg.all;
package tsf_wbgen2_pkg is
......@@ -26,12 +27,12 @@ package tsf_wbgen2_pkg is
fifo_ts1_i : std_logic_vector(31 downto 0);
fifo_ts2_i : std_logic_vector(31 downto 0);
fifo_ts3_i : std_logic_vector(31 downto 0);
lts0_i : std_logic_vector(31 downto 0);
lts1_i : std_logic_vector(31 downto 0);
lts2_i : std_logic_vector(31 downto 0);
lts3_i : std_logic_vector(31 downto 0);
csr_last_valid_i : std_logic;
end record;
delta0_i : std_logic_vector(31 downto 0);
delta1_i : std_logic_vector(31 downto 0);
delta2_i : std_logic_vector(31 downto 0);
delta3_i : std_logic_vector(31 downto 0);
csr_delta_valid_i : std_logic;
end record;
constant c_tsf_in_registers_init_value: t_tsf_in_registers := (
fifo_wr_req_i => '0',
......@@ -39,71 +40,90 @@ package tsf_wbgen2_pkg is
fifo_ts1_i => (others => '0'),
fifo_ts2_i => (others => '0'),
fifo_ts3_i => (others => '0'),
lts0_i => (others => '0'),
lts1_i => (others => '0'),
lts2_i => (others => '0'),
lts3_i => (others => '0'),
csr_last_valid_i => '0'
);
-- Output registers (WB slave -> user design)
type t_tsf_out_registers is record
fifo_wr_full_o : std_logic;
fifo_wr_empty_o : std_logic;
fifo_wr_usedw_o : std_logic_vector(8 downto 0);
csr_last_valid_o : std_logic;
csr_last_valid_load_o : std_logic;
csr_rst_seq_o : std_logic;
end record;
constant c_tsf_out_registers_init_value: t_tsf_out_registers := (
fifo_wr_full_o => '0',
fifo_wr_empty_o => '0',
fifo_wr_usedw_o => (others => '0'),
csr_last_valid_o => '0',
csr_last_valid_load_o => '0',
csr_rst_seq_o => '0'
);
function "or" (left, right: t_tsf_in_registers) return t_tsf_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
delta0_i => (others => '0'),
delta1_i => (others => '0'),
delta2_i => (others => '0'),
delta3_i => (others => '0'),
csr_delta_valid_i => '0'
);
-- Output registers (WB slave -> user design)
type t_tsf_out_registers is record
fifo_wr_full_o : std_logic;
fifo_wr_empty_o : std_logic;
fifo_wr_usedw_o : std_logic_vector(5 downto 0);
csr_delta_valid_o : std_logic;
csr_delta_valid_load_o : std_logic;
csr_rst_seq_o : std_logic;
csr_delta_ref_o : std_logic_vector(2 downto 0);
end record;
constant c_tsf_out_registers_init_value: t_tsf_out_registers := (
fifo_wr_full_o => '0',
fifo_wr_empty_o => '0',
fifo_wr_usedw_o => (others => '0'),
csr_delta_valid_o => '0',
csr_delta_valid_load_o => '0',
csr_rst_seq_o => '0',
csr_delta_ref_o => (others => '0')
);
function "or" (left, right: t_tsf_in_registers) return t_tsf_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
component timestamp_fifo_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
regs_i : in t_tsf_in_registers;
regs_o : out t_tsf_out_registers
);
end component;
end package;
package body tsf_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_tsf_in_registers) return t_tsf_in_registers is
variable tmp: t_tsf_in_registers;
variable tmp: t_tsf_in_registers;
begin
tmp.fifo_wr_req_i := f_x_to_zero(left.fifo_wr_req_i) or f_x_to_zero(right.fifo_wr_req_i);
tmp.fifo_ts0_i := f_x_to_zero(left.fifo_ts0_i) or f_x_to_zero(right.fifo_ts0_i);
tmp.fifo_ts1_i := f_x_to_zero(left.fifo_ts1_i) or f_x_to_zero(right.fifo_ts1_i);
tmp.fifo_ts2_i := f_x_to_zero(left.fifo_ts2_i) or f_x_to_zero(right.fifo_ts2_i);
tmp.fifo_ts3_i := f_x_to_zero(left.fifo_ts3_i) or f_x_to_zero(right.fifo_ts3_i);
tmp.lts0_i := f_x_to_zero(left.lts0_i) or f_x_to_zero(right.lts0_i);
tmp.lts1_i := f_x_to_zero(left.lts1_i) or f_x_to_zero(right.lts1_i);
tmp.lts2_i := f_x_to_zero(left.lts2_i) or f_x_to_zero(right.lts2_i);
tmp.lts3_i := f_x_to_zero(left.lts3_i) or f_x_to_zero(right.lts3_i);
tmp.csr_last_valid_i := f_x_to_zero(left.csr_last_valid_i) or f_x_to_zero(right.csr_last_valid_i);
return tmp;
tmp.fifo_wr_req_i := f_x_to_zero(left.fifo_wr_req_i) or f_x_to_zero(right.fifo_wr_req_i);
tmp.fifo_ts0_i := f_x_to_zero(left.fifo_ts0_i) or f_x_to_zero(right.fifo_ts0_i);
tmp.fifo_ts1_i := f_x_to_zero(left.fifo_ts1_i) or f_x_to_zero(right.fifo_ts1_i);
tmp.fifo_ts2_i := f_x_to_zero(left.fifo_ts2_i) or f_x_to_zero(right.fifo_ts2_i);
tmp.fifo_ts3_i := f_x_to_zero(left.fifo_ts3_i) or f_x_to_zero(right.fifo_ts3_i);
tmp.delta0_i := f_x_to_zero(left.delta0_i) or f_x_to_zero(right.delta0_i);
tmp.delta1_i := f_x_to_zero(left.delta1_i) or f_x_to_zero(right.delta1_i);
tmp.delta2_i := f_x_to_zero(left.delta2_i) or f_x_to_zero(right.delta2_i);
tmp.delta3_i := f_x_to_zero(left.delta3_i) or f_x_to_zero(right.delta3_i);
tmp.csr_delta_valid_i := f_x_to_zero(left.csr_delta_valid_i) or f_x_to_zero(right.csr_delta_valid_i);
return tmp;
end function;
end package body;
hdl/rtl/wbgen/tdc_buffer_control_regs.wb 0 → 100644
View file @ 0724de2e
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "TDC DMA Buffer Control Registers";
prefix="TDC_BUF";
hdl_entity="tdc_buffer_control_wb";
reg {
name = "Control/Status register";
prefix = "CSR";
field {
name = "Enable acquisition";
description = "1: timestamps of the given channel will be sequentially written to the current buffer, provided it's valid (CUR_SIZE.VALID=1) \
0: acquisition off";
prefix = "ENABLE";
type = BIT;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "IRQ Timeout (ms)";
prefix = "IRQ_TIMEOUT";
description = "Interrupt coalescing timeout in milliseconds. Pick a high enough value to avoid too frequent interrupts and a low enough one to prevent buffer contention. 10 ms should be OK for most of the cases";
size = 10;
type = SLV;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Burst size (timestamps)";
prefix = "BURST_SIZE";
description = "Number of timestamps in a single burst to the DDR memory. Default = 16";
size = 10;
type = SLV;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Switch buffers";
description = "write 1: atomically switches the acquisition buffer from the current one (base/size in CUR_BASE/CUR_SIZE) to the next one (described in NEXT_BASE/NEXT_SIZE registers)\
write 0: no action";
prefix = "SWITCH_BUFFERS";
type = MONOSTABLE;
};
field {
name = "Burst complete";
prefix = "DONE";
description = "read 1: the current buffer has been fully committed to the DDR memory after writing 1 to SWITCH_BUFFERS field.\
read 0: still some transfers pending";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "DMA overflow";
prefix = "OVERFLOW";
description = "read 1: both the current and the next buffer have been filled with timestamps. Dropping all new incoming TS.";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Current buffer base address register";
prefix = "CUR_BASE";
field {
name = "Base address";
description = "Base address of the current buffer (in bytes) relative to the DDR3 chip (0 = first word in the memory)";
size = 32;
type = SLV;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Current buffer base count register";
prefix = "CUR_COUNT";
field {
name = "Number of data samples";
description="Number of data samples in the buffer (1 sample = 1 timestamp)";
size = 32;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "Current buffer base size/valid flag register";
prefix = "CUR_SIZE";
field {
name = "Size";
description="Number of data samples the buffer can hold (1 sample = 1 timestamp)";
prefix = "SIZE";
size = 30;
type = SLV;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Valid flag";
prefix = "VALID";
description="write 1: indicate that this buffer is ready for acquisition and correctly configured";
size = 30;
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Next buffer base address register";
prefix = "NEXT_BASE";
field {
name = "Base address";
size = 32;
type = SLV;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Next buffer base size/valid flag register";
prefix = "NEXT_SIZE";
field {
name = "Size (in transfers)";
prefix = "SIZE";
size = 30;
type = SLV;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Valid flag";
prefix = "VALID";
size = 30;
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
};
};
hdl/rtl/wbgen/tdc_eic.wb
View file @ 0724de2e
......@@ -40,6 +40,41 @@ peripheral {
trigger = LEVEL_1;
};
irq {
name = "FMC TDC timestamps interrupt (DMA1)";
description = "FMC TDC DMA1 acquisition ready.";
prefix = "tdc_dma1";
trigger = LEVEL_1;
};
irq {
name = "FMC TDC timestamps interrupt (DMA2)";
description = "FMC TDC DMA1 acquisition ready.";
prefix = "tdc_dma2";
trigger = LEVEL_1;
};
irq {
name = "FMC TDC timestamps interrupt (DMA3)";
description = "FMC TDC DMA3 acquisition ready.";
prefix = "tdc_dma3";
trigger = LEVEL_1;
};
irq {
name = "FMC TDC timestamps interrupt (DMA4)";
description = "FMC TDC DMA4 acquisition ready.";
prefix = "tdc_dma4";
trigger = LEVEL_1;
};
irq {
name = "FMC TDC timestamps interrupt (DMA5)";
description = "FMC TDC DMA5 acquisition ready.";
prefix = "tdc_dma5";
trigger = LEVEL_1;
};
};
hdl/rtl/wbgen/timestamp_fifo_wb.wb
View file @ 0724de2e
......@@ -9,11 +9,10 @@ peripheral {
-- TXTSU shared FIFO
fifo_reg {
size = 512; -- or more. We'll see :)
size = 64; -- or more. We'll see :)
direction = CORE_TO_BUS;
prefix = "fifo";
name = "Timestamp FIFO";
clock = "clk_tdc_i";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT, FIFO_CLEAR};
flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
......@@ -40,7 +39,7 @@ peripheral {
};
field {
name = "The timestamp (word 4)";
name = "The timestamp (word 3)";
prefix = "ts3";
type = SLV;
size = 32;
......@@ -49,12 +48,11 @@ peripheral {
reg {
name = "Last Timestamp Word 0";
prefix = "LTS0";
name = "Delta Timestamp word 0";
prefix = "DELTA0";
field {
name = "Last Timestamp Word 0";
clock = "clk_tdc_i";
name = "Delta Timestamp Word 0";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -63,12 +61,11 @@ peripheral {
};
};
reg {
name = "Last Timestamp Word 1";
prefix = "LTS1";
name = "Delta Timestamp Word 1";
prefix = "DELTA1";
field {
name = "Last Timestamp Word 1";
clock = "clk_tdc_i";
name = "Delta Timestamp Word 1";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -77,12 +74,11 @@ peripheral {
};
reg {
name = "Last Timestamp Word 2";
prefix = "LTS2";
name = "Delta Timestamp Word 2";
prefix = "DELTA2";
field {
name = "Last Timestamp Word 2";
clock = "clk_tdc_i";
name = "Delta Timestamp Word 2";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -92,12 +88,11 @@ peripheral {
};
reg {
name = "Last Timestamp Word 3";
prefix = "LTS3";
name = "Delta Timestamp Word 3";
prefix = "DELTA3";
field {
name = "Last Timestamp Word 3";
clock = "clk_tdc_i";
name = "Delta Timestamp Word 3";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -113,9 +108,8 @@ peripheral {
prefix = "CSR";
field {
name = "Last Timestamp Valid";
clock = "clk_tdc_i";
prefix = "LAST_VALID";
name = "Delta Timestamp Valid";
prefix = "DELTA_VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
......@@ -124,11 +118,20 @@ peripheral {
field {
name = "Reset Sequence Counter";
clock = "clk_tdc_i";
prefix = "RST_SEQ";
type = MONOSTABLE;
};
field {
name = "Delta Timestamp Reference Channel";
description = "Channel (0-4) to take as the reference for the delta timestamps";
prefix = "DELTA_REF";
type = SLV;
size = 3;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
......
hdl/rtl/wbgen2_eic_nomask.vhd 0 → 100644
View file @ 0724de2e
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
entity wbgen2_eic_nomask is
generic (
g_num_interrupts : natural := 1;
g_irq00_mode : integer := 0;
g_irq01_mode : integer := 0;
g_irq02_mode : integer := 0;
g_irq03_mode : integer := 0;
g_irq04_mode : integer := 0;
g_irq05_mode : integer := 0;
g_irq06_mode : integer := 0;
g_irq07_mode : integer := 0;
g_irq08_mode : integer := 0;
g_irq09_mode : integer := 0;
g_irq0a_mode : integer := 0;
g_irq0b_mode : integer := 0;
g_irq0c_mode : integer := 0;
g_irq0d_mode : integer := 0;
g_irq0e_mode : integer := 0;
g_irq0f_mode : integer := 0;
g_irq10_mode : integer := 0;
g_irq11_mode : integer := 0;
g_irq12_mode : integer := 0;
g_irq13_mode : integer := 0;
g_irq14_mode : integer := 0;
g_irq15_mode : integer := 0;
g_irq16_mode : integer := 0;
g_irq17_mode : integer := 0;
g_irq18_mode : integer := 0;
g_irq19_mode : integer := 0;
g_irq1a_mode : integer := 0;
g_irq1b_mode : integer := 0;
g_irq1c_mode : integer := 0;
g_irq1d_mode : integer := 0;
g_irq1e_mode : integer := 0;
g_irq1f_mode : integer := 0
);
port(
rst_n_i : in std_logic; -- reset & system clock, as always :)
clk_i : in std_logic;
-- raw interrupt inputs
irq_i : in std_logic_vector(g_num_interrupts-1 downto 0);
-- interrupt acknowledge signal, used for level-active interrupts to
-- indicate that the interrupt has been handled
irq_ack_o: out std_logic_vector(g_num_interrupts-1 downto 0);
-- interrupt mask regsiter (slv/bus read-only)
reg_imr_o : out std_logic_vector(g_num_interrupts-1 downto 0);
-- interrupt enable/disable registers (slv/bus pass-through)
reg_ier_i : in std_logic_vector(g_num_interrupts-1 downto 0);
reg_ier_wr_stb_i : in std_logic;
reg_idr_i : in std_logic_vector(g_num_interrupts-1 downto 0);
reg_idr_wr_stb_i : in std_logic;
-- interrupt status register (slv/bus write with LOAD_EXT)
reg_isr_o : out std_logic_vector(g_num_interrupts-1 downto 0);
reg_isr_i : in std_logic_vector(g_num_interrupts-1 downto 0);
reg_isr_wr_stb_i : in std_logic;
-- multiplexed wishbone irq output
wb_irq_o : out std_logic
);
end wbgen2_eic_nomask;
architecture syn of wbgen2_eic_nomask is
subtype t_irq_mode is integer;
type t_irq_mode_vec is array (0 to 31) of t_irq_mode;
constant c_IRQ_MODE_RISING_EDGE : t_irq_mode := 0;
constant c_IRQ_MODE_FALLING_EDGE : t_irq_mode := 1;
constant c_IRQ_MODE_LEVEL_0 : t_irq_mode := 2;
constant c_IRQ_MODE_LEVEL_1 : t_irq_mode := 3;
signal irq_mode : t_irq_mode_vec;
signal irq_mask : std_logic_vector(g_num_interrupts-1 downto 0);
signal irq_pending : std_logic_vector(g_num_interrupts-1 downto 0);
signal irq_i_d0 : std_logic_vector(g_num_interrupts-1 downto 0);
signal irq_i_d1 : std_logic_vector(g_num_interrupts-1 downto 0);
signal irq_i_d2 : std_logic_vector(g_num_interrupts-1 downto 0);
begin -- syn
irq_mode(0) <= g_irq00_mode;
irq_mode(1) <= g_irq01_mode;
irq_mode(2) <= g_irq02_mode;
irq_mode(3) <= g_irq03_mode;
irq_mode(4) <= g_irq04_mode;
irq_mode(5) <= g_irq05_mode;
irq_mode(6) <= g_irq06_mode;
irq_mode(7) <= g_irq07_mode;
irq_mode(8) <= g_irq08_mode;
irq_mode(9) <= g_irq09_mode;
irq_mode(10) <= g_irq0a_mode;
irq_mode(11) <= g_irq0b_mode;
irq_mode(12) <= g_irq0c_mode;
irq_mode(13) <= g_irq0d_mode;
irq_mode(14) <= g_irq0e_mode;
irq_mode(15) <= g_irq0f_mode;
irq_mode(16) <= g_irq10_mode;
irq_mode(17) <= g_irq11_mode;
irq_mode(18) <= g_irq12_mode;
irq_mode(19) <= g_irq13_mode;
irq_mode(20) <= g_irq14_mode;
irq_mode(21) <= g_irq15_mode;
irq_mode(22) <= g_irq16_mode;
irq_mode(23) <= g_irq17_mode;
irq_mode(24) <= g_irq18_mode;
irq_mode(25) <= g_irq19_mode;
irq_mode(26) <= g_irq1a_mode;
irq_mode(27) <= g_irq1b_mode;
irq_mode(28) <= g_irq1c_mode;
irq_mode(29) <= g_irq1d_mode;
irq_mode(30) <= g_irq1e_mode;
irq_mode(31) <= g_irq1f_mode;
process(clk_i, rst_n_i)
begin
if(rst_n_i = '0') then
irq_i_d0 <= (others => '0');
irq_i_d1 <= (others => '0');
irq_i_d1 <= (others => '0');
irq_pending <= (others => '0');
irq_mask <= (others => '0');
elsif rising_edge(clk_i) then
for i in 0 to g_num_interrupts-1 loop
irq_i_d0(i) <= irq_i(i);
irq_i_d1(i) <= irq_i_d0(i);
irq_i_d2(i) <= irq_i_d1(i);
if((reg_isr_i(i) = '1' and reg_isr_wr_stb_i = '1')) then
irq_pending(i) <= '0';
irq_i_d0(i) <= '0';
irq_i_d1(i) <= '0';
irq_i_d2(i) <= '0';
else
case irq_mode(i) is
when c_IRQ_MODE_LEVEL_0 => irq_pending(i) <= not irq_i_d2(i);
when c_IRQ_MODE_LEVEL_1 => irq_pending(i) <= irq_i_d2(i);
when c_IRQ_MODE_RISING_EDGE => irq_pending(i) <= irq_pending(i) or ((not irq_i_d2(i)) and irq_i_d1(i));
when c_IRQ_MODE_FALLING_EDGE => irq_pending(i) <= irq_pending(i) or ((not irq_i_d1(i)) and irq_i_d2(i));
when others => null;
end case;
end if;
end loop; -- i
if(reg_ier_wr_stb_i = '1') then
for i in 0 to g_num_interrupts-1 loop
if(reg_ier_i(i) = '1') then
irq_mask(i) <= '1';
end if;
end loop;
end if;
if(reg_idr_wr_stb_i = '1') then
for i in 0 to g_num_interrupts-1 loop
if(reg_idr_i(i) = '1') then
irq_mask(i) <= '0';
end if;
end loop;
end if;
end if;
end process;
-- generation of wb_irq_o
process(clk_i, rst_n_i)
begin
if(rst_n_i = '0') then
wb_irq_o <= '0';
elsif rising_edge(clk_i) then
if( (irq_pending and irq_mask) = std_logic_vector(to_unsigned(0, g_num_interrupts))) then
wb_irq_o <= '0';
else
wb_irq_o <= '1';
end if;
end if;
end process;
gen_irq_ack: for i in 0 to g_num_interrupts-1 generate
irq_ack_o(i) <= '1' when (reg_isr_wr_stb_i = '1' and reg_isr_i(i) = '1') else '0';
end generate gen_irq_ack;
reg_imr_o <= irq_mask;
reg_isr_o <= irq_pending;
end syn;
hdl/syn/spec/Makefile
View file @ 0724de2e
......@@ -3,436 +3,397 @@
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := wr_spec_tdc.xise
ISE_CRAP := *.b wr_spec_tdc_summary.html *.tcl wr_spec_tdc.bld wr_spec_tdc.cmd_log *.drc wr_spec_tdc.lso *.ncd wr_spec_tdc.ngc wr_spec_tdc.ngd wr_spec_tdc.ngr wr_spec_tdc.pad wr_spec_tdc.par wr_spec_tdc.pcf wr_spec_tdc.prj wr_spec_tdc.ptwx wr_spec_tdc.stx wr_spec_tdc.syr wr_spec_tdc.twr wr_spec_tdc.twx wr_spec_tdc.gise $(PROJECT).gise wr_spec_tdc.bgn wr_spec_tdc.unroutes wr_spec_tdc.ut wr_spec_tdc.xpi wr_spec_tdc.xst wr_spec_tdc_bitgen.xwbt wr_spec_tdc_envsettings.html wr_spec_tdc_guide.ncd wr_spec_tdc_map.map wr_spec_tdc_map.mrp wr_spec_tdc_map.ncd wr_spec_tdc_map.ngm wr_spec_tdc_map.xrpt wr_spec_tdc_ngdbuild.xrpt wr_spec_tdc_pad.csv wr_spec_tdc_pad.txt wr_spec_tdc_par.xrpt wr_spec_tdc_summary.xml wr_spec_tdc_usage.xml wr_spec_tdc_xst.xrpt usage_statistics_webtalk.html par_usage_statistics.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local: syn_pre_cmd check_tool generate_tcl synthesis syn_post_cmd
generate_tcl:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Synthesize - XST}" >> run.tcl
echo "process run {Translate}" >> run.tcl
echo "process run {Map}" >> run.tcl
echo "process run {Place & Route}" >> run.tcl
echo "process run {Generate Programming File}" >> run.tcl
synthesis:
/home/greg/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xtclsh run.tcl
check_tool:
syn_post_cmd:
syn_pre_cmd:
#target for cleaning all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
TOP_MODULE := wr_spec_tdc
PWD := $(shell pwd)
PROJECT := wr_spec_tdc
PROJECT_FILE := $(PROJECT).xise
TOOL_PATH := /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64
TCL_INTERPRETER := xtclsh
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
SYN_FAMILY := Spartan6
SYN_DEVICE := xc6slx45t
SYN_PACKAGE := fgg484
SYN_GRADE := -3
.PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis local check_tool
TCL_CREATE := project new $(PROJECT_FILE)
TCL_OPEN := project open $(PROJECT_FILE)
TCL_SAVE := project save
TCL_CLOSE := project close
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
USER:=$(HDLMAKE_RSYNTH_USER)# take the value from the environment
SERVER:=$(HDLMAKE_RSYNTH_SERVER)# take the value from the environment
ISE_PATH:=$(HDLMAKE_RSYNTH_ISE_PATH)
R_NAME:=greg/wr_spec_tdc
PORT:=22
#target for performing local synthesis
all: bitstream
__test_for_remote_synthesis_variables:
ifeq (x$(USER),x)
@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile or setting env. variable HDLMAKE_RSYNTH_USER." && false
endif
ifeq (x$(SERVER),x)
@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile or setting env. variable HDLMAKE_RSYNTH_SERVER." && false
endif
ifeq (x$(ISE_PATH),x)
@echo "Remote synthesis server is not set. You can set it by editing variable ISE_PATH in the makefile or setting env. variable HDLMAKE_RSYNTH_ISE_PATH." && false
endif
SOURCES_NGCFile := \
../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_icon.ngc \
../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_ila.ngc \
../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc
CWD := $(shell pwd)
SOURCES_UCFFile := \
../../top/spec/wr_spec_tdc.ucf
FILES := ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd \
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_queue_auto_pkg.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_walker.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd \
../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_offset.vhd \
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd \
../../rtl/local_pps_gen.vhd \
../../rtl/start_retrig_ctrl.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_queue.vhd \
../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd \
../../rtl/acam_timecontrol_interface.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd \
../../rtl/fmc_tdc_core.vhd \
SOURCES_VerilogFile := \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v
SOURCES_VHDLFile := \
../../rtl/tdc_dma_channel.vhd \
../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/mcb_soft_calibration.vhd \
../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/streamers_pkg.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../rtl/timestamp_fifo.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd \
../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd \
../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd \
../../rtl/tdc_eic.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_crc_inserter.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_scan.vhd \
../../ip_cores/wr-cores/modules/wr_tlu/tlu.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd \
../../rtl/fmc_tdc_direct_readout.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamers_stats.vhd \
../../rtl/clks_rsts_manager.vhd \
../../rtl/reg_ctrl.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd \
../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_sdp.vhd \
../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd \
../../rtl/fmc_tdc_direct_readout_slave_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamer.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd \
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd \
../../ip_cores/wr-cores/board/spec/xwrc_board_spec.vhd \
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run.tcl \
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wr_spec_tdc.xise \
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../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd \
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../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_eca/wr_eca.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd \
../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd \
../../ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/memc3_infrastructure.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_auto.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamer.vhd \
../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_pkg.vhd \
../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../rtl/tdc_buffer_control_regs.vhd \
../../rtl/timestamp_fifo_wbgen2_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_packet_injection.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd \
../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd \
../../ip_cores/wr-cores/board/common/xwrc_board_common.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd \
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../rtl/wrabbit_sync.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd \
../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_auto_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_tlu.vhd \
../../ip_cores/wr-cores/board/spec/xwrc_board_spec.vhd \
../../rtl/tdc_core_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_path.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd \
../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd \
../../ip_cores/general-cores/modules/common/gc_big_adder.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd \
../../top/spec/synthesis_descriptor.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../../rtl/clks_rsts_manager.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd \
../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
../../rtl/fmc_tdc_wrapper.vhd \
../../ip_cores/general-cores/modules/common/gc_reset.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_msi.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_free.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_packet_injection.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd \
../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_vlan_unit.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/dropping_buffer.vhd \
../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_data.vhd \
../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_ila.ngc \
../../rtl/timestamp_fifo_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../../ip_cores/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../ip_cores/wr-cores/board/spec/wrc_board_spec.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd \
../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd \
../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd \
../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_rmw.vhd \
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_header_processor.vhd \
../../rtl/fmc_tdc_mezzanine.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/mcb_raw_wrapper.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
../../rtl/free_counter.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_32b_32b.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../rtl/acam_timecontrol_interface.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/xrtx_streamers_stats.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd \
../../rtl/data_engine.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_search.vhd \
../../ip_cores/wr-cores/board/common/wr_board_pkg.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd \
../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
../../ip_cores/wr-cores/modules/wr_streamers/rx_streamer.vhd \
../../rtl/local_pps_gen.vhd \
../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd \
../../rtl/data_formatting.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_internals_pkg.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_queue_auto.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd \
../../ip_cores/wr-cores/modules/wr_eca/eca_tdp.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd \
../../ip_cores/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../rtl/start_retrig_ctrl.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd \
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/memc3_wrapper.vhd \
../../top/spec/synthesis_descriptor.vhd \
../../ip_cores/wr-cores/modules/wr_streamers/escape_detector.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../rtl/fmc_tdc_direct_readout.vhd \
../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd
#target for running synthesis in the remote location
remote: __test_for_remote_synthesis_variables generate_tcl __send __do_synthesis
__send_back: __do_synthesis
__do_synthesis: __send
__send: __test_for_remote_synthesis_variables
files.tcl:
@$(foreach sourcefile, $(SOURCES_NGCFile), echo "xfile add $(sourcefile)" >> $@ &)
@$(foreach sourcefile, $(SOURCES_UCFFile), echo "xfile add $(sourcefile)" >> $@ &)
@$(foreach sourcefile, $(SOURCES_VerilogFile), echo "xfile add $(sourcefile)" >> $@ &)
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "xfile add $(sourcefile)" >> $@ &)
__send:
ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
rsync -e 'ssh -p $(PORT)' -Ravl $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
__do_synthesis:
ifeq (x$(HDLMAKE_RSYNTH_USE_SCREEN), x1)
ssh -t $(USER)@$(SERVER) 'screen bash -c "cd $(R_NAME)$(CWD) && $(HDLMAKE_RSYNTH_ISE_PATH)/xtclsh run.tcl"'
else
ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && $(HDLMAKE_RSYNTH_ISE_PATH)/xtclsh run.tcl'
endif
SYN_PRE_SYNTHESIZE_CMD :=
SYN_POST_SYNTHESIZE_CMD :=
SYN_PRE_TRANSLATE_CMD :=
SYN_POST_TRANSLATE_CMD :=
SYN_PRE_MAP_CMD :=
SYN_POST_MAP_CMD :=
SYN_PRE_PAR_CMD :=
SYN_POST_PAR_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo $(TCL_CREATE) >> $@
echo source files.tcl >> $@
echo project set \"family\" \"$(SYN_FAMILY)\" >> $@
echo project set \"device\" \"$(SYN_DEVICE)\" >> $@
echo project set \"package\" \"$(SYN_PACKAGE)\" >> $@
echo project set \"speed\" \"$(SYN_GRADE)\" >> $@
echo project set \"Manual Implementation Compile Order\" \"false\" >> $@
echo project set \"Auto Implementation Top\" \"false\" >> $@
echo project set \"Create Binary Configuration File\" \"true\" >> $@
echo set compile_directory . >> $@
echo project set top $(TOP_MODULE) >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
synthesize.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Synthesize - XST} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
sync:
cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)/$(CWD) . && cd $(CWD)
synthesize: project synthesize.tcl
$(SYN_PRE_SYNTHESIZE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_SYNTHESIZE_CMD)
touch $@
translate.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Translate} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
translate: synthesize translate.tcl
$(SYN_PRE_TRANSLATE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_TRANSLATE_CMD)
touch $@
map.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Map} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
map: translate map.tcl
$(SYN_PRE_MAP_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_MAP_CMD)
touch $@
par.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Place '&' Route} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
par: map par.tcl
$(SYN_PRE_PAR_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PAR_CMD)
touch $@
bitstream.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Generate Programming File} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
bitstream: par bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) xst xlnx_auto_0_xdb iseconfig _xmsgs _ngo *.b *_summary.html *.bld *.cmd_log *.drc *.lso *.ncd *.ngc *.ngd *.ngr *.pad *.par *.pcf *.prj *.ptwx *.stx *.syr *.twr *.twx *.gise *.gise *.bgn *.unroutes *.ut *.xpi *.xst *.xise *.xwbt *_envsettings.html *_guide.ncd *_map.map *_map.mrp *_map.ncd *_map.ngm *_map.xrpt *_ngdbuild.xrpt *_pad.csv *_pad.txt *_par.xrpt *_summary.xml *_usage.xml *_xst.xrpt usage_statistics_webtalk.html webtalk.log par_usage_statistics.html webtalk_pn.xml
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
#target for removing stuff from the remote location
cleanremote:
ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
mrproper: clean
rm -rf *.bit *.bin *.mcs
.PHONY: mrproper clean all
hdl/syn/spec/Manifest.py
View file @ 0724de2e
......@@ -12,3 +12,4 @@ syn_tool = "ise"
top_module = "wr_spec_tdc"
modules = { "local" : [ "../../top/spec" ] }
ctrls = ["bank3_32b_32b"]
hdl/syn/spec/wr_spec_tdc.xise
View file @ 0724de2e
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/testbench/include/vhd_wishbone_master.svh
View file @ 0724de2e
`include "simdrv_defs.svh"
`include "if_wb_master.svh"
`include "if_wb_slave.svh"
interface IVHDWishboneMaster
(
......@@ -57,3 +58,60 @@ interface IVHDWishboneMaster
endinterface // IVHDWishboneMaster
interface IVHDWishboneSlave
(
input clk_i,
input rst_n_i
);
parameter g_addr_width = 32;
parameter g_data_width = 32;
typedef virtual IWishboneSlave VIWishboneSlave;
IWishboneSlave #(g_addr_width, g_data_width) TheSlave (clk_i, rst_n_i);
t_wishbone_slave_in in;
t_wishbone_slave_out out;
modport slave
(
input in,
output out
);
assign TheSlave.cyc = in.cyc;
assign TheSlave.stb = in.stb;
assign TheSlave.we = in.we;
assign TheSlave.sel = in.sel;
assign TheSlave.adr = in.adr;
assign TheSlave.dat_i = in.dat;
assign out.ack = TheSlave.ack;
assign out.stall = TheSlave.stall;
assign out.rty = TheSlave.rty;
assign out.err = TheSlave.err;
assign out.dat = TheSlave.dat_o;
function automatic CWishboneAccessor get_accessor();
return TheSlave.get_accessor();
endfunction // get_accessor
initial begin
@(posedge rst_n_i);
@(posedge clk_i);
TheSlave.settings.mode = PIPELINED;
TheSlave.settings.stall_prob = 0.1;
TheSlave.settings.gen_random_stalls = 1;
TheSlave.settings.stall_min_duration = 1;
TheSlave.settings.stall_max_duration = 5;
end
endinterface // IVHDWishboneSlave
hdl/testbench/spec/Manifest.py
View file @ 0724de2e
sim_tool = "modelsim"
top_module="main"
syn_device="xc6slx45t"
sim_top="main"
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
include_dirs=[ "../../sim", "../include", "../../ip_cores/gn4124-core/hdl/gn4124core/sim/gn4124_bfm" ]
include_dirs=[ "../../sim", "../include" ]
vcom_opt = "-mixedsvvh l"
files = [ "main.sv" ]
modules = { "local" : [ "../../top/spec", "../../ip_cores/gn4124-core/hdl/gn4124core/sim/gn4124_bfm" ] }
ctrls = ["bank3_32b_32b"]
\ No newline at end of file
hdl/testbench/spec/main.sv
View file @ 0724de2e
`include "simdrv_defs.svh"
`include "gn4124_bfm.svh"
`include "timestamp_fifo_regs.vh"
module fake_acam(
input [3:0] addr,
output reg [27:0] data,
input wr,
input rd,
output reg ef1,
output reg ef2
);
typedef struct {
int channel;
time ts;
} acam_fifo_entry;
acam_fifo_entry fifo1[$], fifo2[$];
task pulse(int channel, time ts);
acam_fifo_entry ent;
import wishbone_pkg::*;
import tdc_core_pkg::*;
ent.channel = channel % 4;
ent.ts = ts;
if (channel >= 0 && channel <= 3)
fifo1.push_back(ent);
else
fifo2.push_back(ent);
#100ns;
if(fifo1.size())
ef1 = 0;
if(fifo2.size())
ef2 = 0;
endtask // pulse
initial begin
ef1 = 1;
ef2 = 1;
data = 28'bz;
end
always@(negedge rd) begin
if (addr == 8) begin
acam_fifo_entry ent;
ent=fifo1.pop_front();
data <= ent.ts | (ent.channel << 26) | (1<<17);
end else if (addr == 9) begin
acam_fifo_entry ent;
ent=fifo2.pop_front();
data <= ent.ts | (ent.channel << 26) | (1<<17);
end else
data <= 28'bz;
#10ns;
ef1 <= (fifo1.size() ? 0 : 1);
ef2 <= (fifo2.size() ? 0 : 1);
end
endmodule
`include "simdrv_defs.svh"
`include "timestamp_fifo_regs.vh"
`include "if_wb_master.svh"
`include "vhd_wishbone_master.svh"
`include "acam_model.svh"
module main;
......@@ -87,7 +22,7 @@ module main;
end
reg clk_acam = 0;
reg clk_acam = 0; // 31.25 MHz
reg clk_62m5 = 0;
always@(posedge clk_125m)
......@@ -95,18 +30,58 @@ module main;
always@(posedge clk_62m5)
clk_acam <= ~clk_acam;
wire [3:0] tdc_addr;
wire [27:0] tdc_data;
reg [8:1] tdc_stop = 0;
wire tdc_start, tdc_start_dis, tdc_stop_dis;
wire tdc_alutrigger = 0;
wire tdc_cs_n, tdc_oe_n, tdc_rd_n, tdc_wr_n;
wire tdc_err_flag, tdc_int_flag;
wire tdc_ef1, tdc_ef2;
IGN4124PCIMaster I_Gennum ();
tdc_gpx_model ACAM
(
.PuResN(1'b1),
.Alutrigger(tdc_alutrigger),
.RefClk(clk_acam),
.WRN(tdc_wr_n),
.RDN(tdc_rd_n),
.CSN(tdc_cs_n),
.OEN(tdc_oe_n),
.Adr(tdc_addr),
.TStart(tdc_start),
.TStop(tdc_stop),
.StartDis(tdc_start_dis),
.StopDis(tdc_stop_dis),
.IrFlag(tdc_int_flag),
.ErrFlag(tdc_err_flag),
.EF1(tdc_ef1),
.EF2(tdc_ef2),
.LF1(),
.LF2(),
.D(tdc_data)
);
wr_spec_tdc #(
.g_with_wr_phy(0),
.g_simulation(1)
.g_simulation(1),
.g_calib_soft_ip(0),
.g_sim_bypass_gennum(1)
) DUT (
.clk_125m_pllref_p_i(clk_125m),
.clk_125m_pllref_n_i(~clk_125m),
......@@ -122,29 +97,36 @@ module main;
.clk_20m_vcxo_i(clk_20m),
.pll_status_i(1'b1),
.ef1_i(tdc_ef1),
.ef2_i(tdc_ef2),
.err_flag_i(1'b0),
.int_flag_i(1'b0),
.err_flag_i(tdc_err_flag),
.int_flag_i(tdc_int_flag),
.rd_n_o(tdc_rd_n),
.wr_n_o(tdc_wr_n),
.oe_n_o(tdc_oe_n),
.cs_n_o(tdc_cs_n),
.data_bus_io(tdc_data),
.address_o(tdc_addr),
`GENNUM_WIRE_SPEC_PINS(I_Gennum)
.start_from_fpga_o(tdc_start),
// .start_dis_o(tdc_start_dis),
// .stop_dis_o(tdc_stop_dis),
.sim_wb_i(Host.out),
.sim_wb_o(Host.in)
);
fake_acam ACAM(
.addr(tdc_addr),
.data(tdc_data),
.wr(1'b0),
.rd(tdc_rd_n),
.ef1(tdc_ef1),
.ef2(tdc_ef2)
);
IVHDWishboneMaster Host
(
.clk_i (DUT.clk_62m5_sys),
.rst_n_i (DUT.rst_n_sys));
assign tdc_start_dis = 0;
assign tdc_stop_dis = 0;
......@@ -157,10 +139,10 @@ module main;
CBusAccessor acc;
const uint64_t tdc1_base = 'h40000;
uint64_t d;
acc = I_Gennum.get_accessor();
acc = Host.get_accessor();
#100us;
#10us;
$display("Accessor: %x", acc);
......@@ -168,11 +150,18 @@ module main;
acc.write('h02000c, 'h3);
#500us;
#5us;
acc.read('h040000, d);
$display("TDC SDB ID : %x", d);
acc.read('h050000, d);
$display("TDC DMA R0 : %x", d);
acc.write('h045000, 'hdeadbeef);
acc.read('h045000, d);
$display("TDC Buf CSR : %x", d);
acc.write('h420a0, 1234); // set UTC
acc.write('h420fc, 1<<9); // load UTC
......@@ -186,14 +175,14 @@ module main;
acc.write('h42090, 2); // thr = 2 ts
acc.write('h42094, 10); // thr = 10 ms
$display("Start operation");
#300us;
fork
forever begin
acc.read('h45000 + `ADDR_TSF_CSR, d);
$display("TSF CSR %x", d);
// $display("TSF CSR %x", d);
if(d&1) begin
uint64_t t0,t1,t2,t3;
......@@ -209,7 +198,7 @@ module main;
end
acc.read('h45000 + `ADDR_TSF_FIFO_CSR, d);
// acc.read('h45000 + `ADDR_TSF_FIFO_CSR, d);
// $display("FIFO CSR %x", d);
/* -----\/----- EXCLUDED -----\/-----
......@@ -229,11 +218,13 @@ module main;
forever begin
$display("Pulse!");
ACAM.pulse(0, 0);
ACAM.pulse(1, 0);
ACAM.pulse(2, 0);
#10us;
$display("pulse @ %t", $time);
tdc_stop[1] <= 1;
#110ns;
tdc_stop[1] <= 0;
#10us;
end
join
......
hdl/testbench/spec/wave.do
View file @ 0724de2e
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/rst_n_a_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/status_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_clk_p_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_clk_n_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_data_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dframe_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_valid_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_rdy_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_wr_req_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_wr_rdy_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/rx_error_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/vc_rdy_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_clk_p_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_clk_n_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_data_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dframe_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_valid_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_edb_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_rdy_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l_wr_rdy_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_rd_d_rdy_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/tx_error_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_irq_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/irq_p_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/irq_p_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_clk_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_adr_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_dat_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_sel_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_stb_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_we_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_cyc_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_dat_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_ack_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_stall_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_clk_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_adr_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_dat_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_sel_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_stb_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_we_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_cyc_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_dat_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_ack_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_stall_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_err_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_rty_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_int_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_clk_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_adr_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_dat_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_sel_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_stb_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_we_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_cyc_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_dat_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ack_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_stall_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_err_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_rty_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_int_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/sys_clk
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/io_clk
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/serdes_strobe
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_pll_locked
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/rst_reg
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/rst_n
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/rst
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/des_pd_valid
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/des_pd_dframe
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/des_pd_data
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_wr_rdy
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_rdy_wbm
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_rdy_pdm
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_hdr_start
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_hdr_length
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_hdr_cid
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_hdr_last
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_hdr_stat
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_target_mrd
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_target_mwr
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_master_cpld
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_master_cpln
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_d_valid
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_d_last
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_d
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_be
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_addr
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_addr_start
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/arb_ser_valid
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/arb_ser_dframe
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/arb_ser_data
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l_wr_rdy_t
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l_wr_rdy_t2
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l_wr_rdy
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_rd_d_rdy_t
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_rd_d_rdy_t2
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_rd_d_rdy
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_rdy_t
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_rdy_t2
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_rdy
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_edb
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_edb_t
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_edb_t2
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/tx_error_t2
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/tx_error_t
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/tx_error
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/wbm_arb_valid
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/wbm_arb_dframe
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/wbm_arb_data
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/wbm_arb_req
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/arb_wbm_gnt
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/ldm_arb_req
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/arb_ldm_gnt
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/ldm_arb_valid
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/ldm_arb_dframe
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/ldm_arb_data
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/pdm_arb_valid
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/pdm_arb_dframe
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/pdm_arb_data
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/pdm_arb_req
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/arb_pdm_gnt
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_carrier_addr
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_host_addr_h
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_host_addr_l
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_len
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_start_l2p
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_start_p2l
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_start_next
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_done
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_error
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_l2p_done
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_l2p_error
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_p2l_done
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_p2l_error
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_byte_swap
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_abort
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_carrier_addr
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_host_addr_h
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_host_addr_l
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_len
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_next_l
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_next_h
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_attrib
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_valid
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_irq
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_adr
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_adr
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_dat_s2m
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_dat_m2s
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_sel
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_cyc
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_stb
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_we
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_ack
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_stall
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_adr
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_dat_s2m
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_dat_m2s
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_sel
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_cyc
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_stb
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_we
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_ack
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_stall
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/clk_sys_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/rst_sys_n_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/clk_tdc_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/rst_tdc_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/acam_refclk_r_edge_p_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/send_dac_word_p_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/dac_word_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/start_from_fpga_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/err_flag_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/int_flag_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/start_dis_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/stop_dis_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/data_bus_io
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/address_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cs_n_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/oe_n_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/rd_n_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wr_n_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/ef1_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/ef2_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/enable_inputs_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/term_en_1_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/term_en_2_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/term_en_3_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/term_en_4_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/term_en_5_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_led_status_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_led_trig1_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_led_trig2_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_led_trig3_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_led_trig4_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_led_trig5_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_in_fpga_1_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_in_fpga_2_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_in_fpga_3_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_in_fpga_4_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_in_fpga_5_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_link_up_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_time_valid_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_cycles_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_utc_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_clk_aux_lock_en_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_clk_aux_locked_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_clk_dmtd_locked_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_dac_value_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_dac_wr_p_i
add wave -noupdate -expand -group Mezz -expand /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/slave_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/slave_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wb_irq_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/i2c_scl_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/i2c_scl_oen_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/i2c_scl_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/i2c_sda_oen_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/i2c_sda_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/i2c_sda_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/onewire_b
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/direct_timestamp_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/direct_timestamp_stb_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/general_rst_n
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/rst_ref_0_n
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cnx_master_out
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cnx_master_in
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_core_wb_adr
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_mem_wb_adr
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/mezz_owr_en
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/mezz_owr_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/sys_scl_in
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/sys_scl_out
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/sys_scl_oe_n
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/sys_sda_in
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/sys_sda_out
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/sys_sda_oe_n
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/irq_tstamp
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/reg_to_wr
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/reg_from_wr
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_utc_p
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_synched
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/irq_channel
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/timestamp
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/timestamp_stb
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/channel_enable
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/irq_threshold
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/irq_timeout
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tick_1ms
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/counter_1ms
add wave -noupdate /main/DUT/cnx_master_out
add wave -noupdate -group Acam /main/ACAM/PuResN
add wave -noupdate -group Acam /main/ACAM/Alutrigger
add wave -noupdate -group Acam /main/ACAM/RefClk
add wave -noupdate -group Acam /main/ACAM/WRN
add wave -noupdate -group Acam /main/ACAM/RDN
add wave -noupdate -group Acam /main/ACAM/CSN
add wave -noupdate -group Acam /main/ACAM/OEN
add wave -noupdate -group Acam /main/ACAM/Adr
add wave -noupdate -group Acam /main/ACAM/TStart
add wave -noupdate -group Acam /main/ACAM/TStop
add wave -noupdate -group Acam /main/ACAM/StartDis
add wave -noupdate -group Acam /main/ACAM/StopDis
add wave -noupdate -group Acam /main/ACAM/IrFlag
add wave -noupdate -group Acam /main/ACAM/ErrFlag
add wave -noupdate -group Acam /main/ACAM/EF1
add wave -noupdate -group Acam /main/ACAM/EF2
add wave -noupdate -group Acam /main/ACAM/LF1
add wave -noupdate -group Acam /main/ACAM/LF2
add wave -noupdate -group Acam /main/ACAM/D
add wave -noupdate -group Acam /main/ACAM/c_empty_flag_delay
add wave -noupdate -group Acam /main/ACAM/start_masked
add wave -noupdate -group Acam /main/ACAM/stop1_masked
add wave -noupdate -group Acam /main/ACAM/r_MasterAluTrig
add wave -noupdate -group Acam /main/ACAM/r_StartDisStart
add wave -noupdate -group Acam /main/ACAM/DQ
add wave -noupdate -group Acam /main/ACAM/EF1_int
add wave -noupdate -group Acam /main/ACAM/EF2_int
add wave -noupdate -group Acam /main/ACAM/start_disabled_int
add wave -noupdate -group Acam /main/ACAM/imode_start_offset
add wave -noupdate -group Acam /main/ACAM/t
add wave -noupdate -group Acam /main/ACAM/t_prev
add wave -noupdate -group Acam /main/ACAM/fifo_empty
add wave -noupdate -group Acam /main/ACAM/fifo_notempty
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/clk_sys_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/rst_n_sys_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/rst_sys_n_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/clk_tdc_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/rst_tdc_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/rst_tdc_n_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_refclk_r_edge_p_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/send_dac_word_p_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/dac_word_o
......@@ -282,11 +66,6 @@ add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig3_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig4_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig5_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_1_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_2_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_3_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_4_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_5_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/wrabbit_status_reg_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/wrabbit_ctrl_reg_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/wrabbit_synched_i
......@@ -295,7 +74,8 @@ add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/cfg_slave_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/cfg_slave_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/timestamp_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/timestamp_stb_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/timestamp_valid_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/timestamp_ready_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/channel_enable_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/irq_threshold_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/irq_timeout_o
......@@ -353,201 +133,277 @@ add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/utc
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/wrabbit_ctrl_reg
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_channel
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_1
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_2
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_3
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_4
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_5
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp_channel
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/raw_timestamp_valid
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/raw_timestamp
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/final_timestamp_valid
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/final_timestamp_ready
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/final_timestamp
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/channel_enable_int
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/rst_sys
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/timestamp_valid
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/timestamp
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/clk_sys_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/clk_tdc_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/rst_n_sys_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/rst_tdc_i
add wave -noupdate -expand -group FIFO0 -expand /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/slave_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/slave_o
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/irq_o
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/enable_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/tick_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/irq_threshold_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/irq_timeout_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/timestamp_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/timestamp_valid_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/tmr_timeout
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/buf_irq_int
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/buf_count
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/last_ts
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/regs_in
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/regs_out
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/channel_id
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/ts_match
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/seq_counter
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/timestamp_with_seq
add wave -noupdate /main/DUT/clk_125m_pllref_p_i
add wave -noupdate /main/DUT/clk_125m_pllref_n_i
add wave -noupdate /main/DUT/clk_125m_gtp_n_i
add wave -noupdate /main/DUT/clk_125m_gtp_p_i
add wave -noupdate /main/DUT/clk_20m_vcxo_i
add wave -noupdate /main/DUT/dac_sclk_o
add wave -noupdate /main/DUT/dac_din_o
add wave -noupdate /main/DUT/dac_cs1_n_o
add wave -noupdate /main/DUT/dac_cs2_n_o
add wave -noupdate /main/DUT/sfp_txp_o
add wave -noupdate /main/DUT/sfp_txn_o
add wave -noupdate /main/DUT/sfp_rxp_i
add wave -noupdate /main/DUT/sfp_rxn_i
add wave -noupdate /main/DUT/sfp_mod_def0_b
add wave -noupdate /main/DUT/sfp_mod_def1_b
add wave -noupdate /main/DUT/sfp_mod_def2_b
add wave -noupdate /main/DUT/sfp_rate_select_b
add wave -noupdate /main/DUT/sfp_tx_fault_i
add wave -noupdate /main/DUT/sfp_tx_disable_o
add wave -noupdate /main/DUT/sfp_los_i
add wave -noupdate /main/DUT/uart_rxd_i
add wave -noupdate /main/DUT/uart_txd_o
add wave -noupdate /main/DUT/carrier_scl_b
add wave -noupdate /main/DUT/carrier_sda_b
add wave -noupdate /main/DUT/carrier_onewire_b
add wave -noupdate /main/DUT/button1_i
add wave -noupdate /main/DUT/button2_i
add wave -noupdate /main/DUT/l_rst_n
add wave -noupdate /main/DUT/gpio
add wave -noupdate /main/DUT/p2l_rdy
add wave -noupdate /main/DUT/p2l_clkn
add wave -noupdate /main/DUT/p2l_clkp
add wave -noupdate /main/DUT/p2l_data
add wave -noupdate /main/DUT/p2l_dframe
add wave -noupdate /main/DUT/p2l_valid
add wave -noupdate /main/DUT/p_wr_req
add wave -noupdate /main/DUT/p_wr_rdy
add wave -noupdate /main/DUT/rx_error
add wave -noupdate /main/DUT/l2p_data
add wave -noupdate /main/DUT/l2p_dframe
add wave -noupdate /main/DUT/l2p_valid
add wave -noupdate /main/DUT/l2p_clkn
add wave -noupdate /main/DUT/l2p_clkp
add wave -noupdate /main/DUT/l2p_edb
add wave -noupdate /main/DUT/l2p_rdy
add wave -noupdate /main/DUT/l_wr_rdy
add wave -noupdate /main/DUT/p_rd_d_rdy
add wave -noupdate /main/DUT/tx_error
add wave -noupdate /main/DUT/vc_rdy
add wave -noupdate /main/DUT/pll_sclk_o
add wave -noupdate /main/DUT/pll_sdi_o
add wave -noupdate /main/DUT/pll_cs_o
add wave -noupdate /main/DUT/pll_dac_sync_o
add wave -noupdate /main/DUT/pll_sdo_i
add wave -noupdate /main/DUT/pll_status_i
add wave -noupdate /main/DUT/tdc_clk_125m_p_i
add wave -noupdate /main/DUT/tdc_clk_125m_n_i
add wave -noupdate /main/DUT/acam_refclk_p_i
add wave -noupdate /main/DUT/acam_refclk_n_i
add wave -noupdate /main/DUT/start_from_fpga_o
add wave -noupdate /main/DUT/err_flag_i
add wave -noupdate /main/DUT/int_flag_i
add wave -noupdate /main/DUT/start_dis_o
add wave -noupdate /main/DUT/stop_dis_o
add wave -noupdate /main/DUT/data_bus_io
add wave -noupdate /main/DUT/address_o
add wave -noupdate /main/DUT/cs_n_o
add wave -noupdate /main/DUT/oe_n_o
add wave -noupdate /main/DUT/rd_n_o
add wave -noupdate /main/DUT/wr_n_o
add wave -noupdate /main/DUT/ef1_i
add wave -noupdate /main/DUT/ef2_i
add wave -noupdate /main/DUT/enable_inputs_o
add wave -noupdate /main/DUT/term_en_2_o
add wave -noupdate /main/DUT/term_en_3_o
add wave -noupdate /main/DUT/term_en_4_o
add wave -noupdate /main/DUT/term_en_5_o
add wave -noupdate /main/DUT/tdc_led_status_o
add wave -noupdate /main/DUT/tdc_led_trig1_o
add wave -noupdate /main/DUT/tdc_led_trig2_o
add wave -noupdate /main/DUT/tdc_led_trig3_o
add wave -noupdate /main/DUT/tdc_led_trig4_o
add wave -noupdate /main/DUT/tdc_led_trig5_o
add wave -noupdate /main/DUT/tdc_in_fpga_1_i
add wave -noupdate /main/DUT/tdc_in_fpga_2_i
add wave -noupdate /main/DUT/tdc_in_fpga_3_i
add wave -noupdate /main/DUT/tdc_in_fpga_4_i
add wave -noupdate /main/DUT/tdc_in_fpga_5_i
add wave -noupdate /main/DUT/mezz_sys_scl_b
add wave -noupdate /main/DUT/mezz_sys_sda_b
add wave -noupdate /main/DUT/mezz_onewire_b
add wave -noupdate /main/DUT/led_red
add wave -noupdate /main/DUT/led_green
add wave -noupdate /main/DUT/pcb_ver_i
add wave -noupdate /main/DUT/prsnt_m2c_n_i
add wave -noupdate /main/DUT/pllout_clk_sys
add wave -noupdate /main/DUT/pllout_clk_dmtd
add wave -noupdate /main/DUT/pllout_clk_fb_pllref
add wave -noupdate /main/DUT/pllout_clk_fb_dmtd
add wave -noupdate /main/DUT/clk_125m_pllref
add wave -noupdate /main/DUT/clk_125m_gtp
add wave -noupdate /main/DUT/clk_dmtd
add wave -noupdate /main/DUT/clk_20m_vcxo
add wave -noupdate /main/DUT/clk_20m_vcxo_buf
add wave -noupdate /main/DUT/clk_62m5_sys
add wave -noupdate /main/DUT/sys_locked
add wave -noupdate /main/DUT/rst_n_sys
add wave -noupdate /main/DUT/cnx_master_out
add wave -noupdate /main/DUT/cnx_master_in
add wave -noupdate /main/DUT/cnx_slave_out
add wave -noupdate /main/DUT/cnx_slave_in
add wave -noupdate /main/DUT/gn_wb_adr
add wave -noupdate /main/DUT/gn4124_status
add wave -noupdate /main/DUT/carrier_owr_en
add wave -noupdate /main/DUT/carrier_owr_i
add wave -noupdate /main/DUT/irq_to_gn4124
add wave -noupdate /main/DUT/tm_link_up
add wave -noupdate /main/DUT/tm_time_valid
add wave -noupdate /main/DUT/tm_dac_wr_p
add wave -noupdate /main/DUT/tm_tai
add wave -noupdate /main/DUT/tm_cycles
add wave -noupdate /main/DUT/tm_dac_value
add wave -noupdate /main/DUT/tm_dac_value_reg
add wave -noupdate /main/DUT/tm_clk_aux_lock_en
add wave -noupdate /main/DUT/tm_clk_aux_locked
add wave -noupdate /main/DUT/phy_tx_data
add wave -noupdate /main/DUT/phy_rx_data
add wave -noupdate /main/DUT/phy_tx_k
add wave -noupdate /main/DUT/phy_tx_disparity
add wave -noupdate /main/DUT/phy_rx_k
add wave -noupdate /main/DUT/phy_tx_enc_err
add wave -noupdate /main/DUT/phy_rx_rbclk
add wave -noupdate /main/DUT/phy_rx_enc_err
add wave -noupdate /main/DUT/phy_rst
add wave -noupdate /main/DUT/phy_loopen
add wave -noupdate /main/DUT/phy_rx_bitslide
add wave -noupdate /main/DUT/dac_hpll_load_p1
add wave -noupdate /main/DUT/dac_dpll_load_p1
add wave -noupdate /main/DUT/dac_hpll_data
add wave -noupdate /main/DUT/dac_dpll_data
add wave -noupdate /main/DUT/wrc_scl_out
add wave -noupdate /main/DUT/wrc_scl_in
add wave -noupdate /main/DUT/wrc_sda_out
add wave -noupdate /main/DUT/wrc_sda_in
add wave -noupdate /main/DUT/tdc_scl_out
add wave -noupdate /main/DUT/tdc_scl_in
add wave -noupdate /main/DUT/tdc_sda_out
add wave -noupdate /main/DUT/tdc_sda_in
add wave -noupdate /main/DUT/tdc_scl_oen
add wave -noupdate /main/DUT/tdc_sda_oen
add wave -noupdate /main/DUT/sfp_scl_out
add wave -noupdate /main/DUT/sfp_scl_in
add wave -noupdate /main/DUT/sfp_sda_out
add wave -noupdate /main/DUT/sfp_sda_in
add wave -noupdate /main/DUT/wrc_owr_en
add wave -noupdate /main/DUT/wrc_owr_in
add wave -noupdate /main/DUT/tdc0_irq
add wave -noupdate /main/DUT/tdc0_clk_125m
add wave -noupdate /main/DUT/tdc0_soft_rst_n
add wave -noupdate /main/DUT/powerup_rst_cnt
add wave -noupdate /main/DUT/carrier_info_fmc_rst
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/rst_tdc
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/clk_sys_i
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/rst_sys_n_i
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/clk_tdc_i
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/rst_tdc_n_i
add wave -noupdate -group Regs -expand /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/slave_i
add wave -noupdate -group Regs -expand /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/slave_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_config_rdbk_i
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_ififo1_i
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_ififo2_i
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_start01_i
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/local_utc_i
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/core_status_i
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_code_i
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wrabbit_status_reg_i
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_config_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/activate_acq_p_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/deactivate_acq_p_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_wr_config_p_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_config_p_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rst_p_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_status_p_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_ififo1_p_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_ififo2_p_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_start01_p_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/send_dac_word_p_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dac_word_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/load_utc_p_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/starting_utc_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_tstamp_threshold_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_time_threshold_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/one_hz_phase_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_inputs_en_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wrabbit_ctrl_reg_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/start_phase_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_config
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr_pipe0
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/starting_utc
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_inputs_en
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/start_phase
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/ctrl_reg
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/one_hz_phase
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_tstamp_threshold
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_time_threshold
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/clear_ctrl_reg
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/send_dac_word_p
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dac_word
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/pulse_extender_en
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/pulse_extender_c
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wrabbit_ctrl_reg
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/ack_out_pipe0
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/ack_out_pipe1
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_comb0
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_comb1
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_comb2
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_comb3
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_pipe0
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_pipe1
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_pipe2
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_pipe3
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/cyc_in_progress
add wave -noupdate -group Regs -expand /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wb_in
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wb_out
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/cc_rst_n
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/cc_rst_n_or_sys
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/clk_i
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/rst_i
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/acam_refclk_r_edge_p_i
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/utc_p_i
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/state_active_p_i
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/activate_acq_p_i
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/deactivate_acq_p_i
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/err_flag_i
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/int_flag_i
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/start_from_fpga_o
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/stop_dis_o
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/acam_errflag_r_edge_p_o
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/acam_errflag_f_edge_p_o
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/acam_intflag_f_edge_p_o
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/int_flag_synch
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/err_flag_synch
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/acam_intflag_f_edge_p
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/start_pulse
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/wait_for_utc
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/rst_n
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/wait_for_state_active
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/clk_i
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/rst_i
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/ef1_i
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/ef2_i
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/data_bus_io
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/cyc_i
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/stb_i
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/we_i
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/adr_i
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/dat_i
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/ef1_o
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/ef1_meta_o
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/ef2_o
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/ef2_meta_o
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/adr_o
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/cs_n_o
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/oe_n_o
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/rd_n_o
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/wr_n_o
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/ack_o
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/dat_o
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/acam_data_st
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/nxt_acam_data_st
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/ef1_synch
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/ef2_synch
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/ack
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/rd
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/rd_extend
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/wr
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/wr_extend
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/wr_remove
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/clk_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/rst_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/activate_acq_p_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/deactivate_acq_p_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_wr_config_p_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_rst_p_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_rdbk_config_p_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_rdbk_status_p_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_rdbk_ififo1_p_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_rdbk_ififo2_p_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_rdbk_start01_p_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_config_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ef1_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ef1_meta_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ef2_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ef2_meta_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ack_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_dat_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/start_from_fpga_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/state_active_p_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_adr_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_cyc_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_stb_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_dat_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_we_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_config_rdbk_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ififo1_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ififo2_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_start01_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_tstamp1_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_tstamp2_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_tstamp1_ok_p_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_tstamp2_ok_p_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/engine_st
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/nxt_engine_st
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_cyc
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_stb
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_we
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_adr
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/config_adr_c
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_config_rdbk
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/reset_word
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_config_reg4
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/time_c_full_p
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/time_c_en
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/time_c_rst
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/time_c
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/clk_i
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/rst_i
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_tstamp1_ok_p_i
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_tstamp1_i
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_tstamp2_ok_p_i
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_tstamp2_i
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/utc_i
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/roll_over_incr_recent_i
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/clk_i_cycles_offset_i
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/roll_over_nb_i
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/retrig_nb_offset_i
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/utc_p_i
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/timestamp_o
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/timestamp_valid_o
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_channel
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_slope
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_fine_timestamp
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_start_nb
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_start_nb
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_clk_i_cycles_offset
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_roll_over
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_nb_of_retrig
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_nb_offset
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_nb_of_cycles
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_start_nb_32
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/full_timestamp
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/metadata
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/utc
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/coarse_time
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/fine_time
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/tstamp_on_first_retrig_case1
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/tstamp_on_first_retrig_case2
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/coarse_zero
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_previous_clk_i_cycles_offset
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_previous_retrig_nb_offset
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_previous_roll_over_nb
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_current_retrig_nb_offset
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_current_roll_over_nb
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_current_retrig_from_roll_over
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_fine_time
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/previous_utc
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/timestamp_valid_int
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/clk_tdc_i
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/rst_tdc_n_i
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/clk_sys_i
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/rst_sys_n_i
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/enable_i
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/ts_i
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/ts_valid_i
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/ts_o
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/ts_valid_o
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/ts_ready_i
add wave -noupdate -group FilterAndCvt -expand -subitemconfig {/main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/channels(0) -expand} /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/channels
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s1_frac_scaled
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s1_tai
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s2_tai
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s3_tai
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s1_valid
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s2_valid
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s3_valid
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s1_coarse
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s2_coarse
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s3_coarse
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s2_frac
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s3_frac
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/coarse_adj
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s1_channel
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s2_channel
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s3_channel
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s1_edge
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s2_edge
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s3_edge
add wave -noupdate -group FilterAndCvt -expand /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s3_ts
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/ts_valid_sys
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/clk_sys_i
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/rst_sys_n_i
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/slave_i
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/slave_o
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/irq_o
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/enable_i
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/tick_i
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/irq_threshold_i
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/irq_timeout_i
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/timestamp_i
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/timestamp_valid_i
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/tmr_timeout
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/buf_irq_int
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/buf_count
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/last_ts
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/regs_in
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/regs_out
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/channel_id
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/ts_match
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/timestamp_with_seq
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {916212143 ps} 0}
WaveRestoreCursors {{Cursor 1} {648894565 ps} 0}
configure wave -namecolwidth 177
configure wave -valuecolwidth 100
configure wave -justifyvalue left
......@@ -562,4 +418,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {3698688 ns}
WaveRestoreZoom {0 ps} {2097152 ns}
hdl/top/spec/Manifest.py
View file @ 0724de2e
......@@ -9,10 +9,8 @@ modules = {
"../../ip_cores/gn4124-core",
"../../ip_cores/general-cores",
"../../ip_cores/wr-cores",
"../../ip_cores/wr-cores/board/spec"
],
"git" : [
"git://ohwr.org/hdl-core-lib/etherbone-core.git",
],
"../../ip_cores/wr-cores/board/spec",
"../../ip_cores/ddr3-sp6-core"
]
}
hdl/top/spec/wr_spec_tdc.ucf
View file @ 0724de2e
......@@ -386,6 +386,123 @@ NET "uart_rxd_i" IOSTANDARD=LVCMOS25;
NET "uart_txd_o" LOC= B2;
NET "uart_txd_o" IOSTANDARD=LVCMOS25;
#----------------------------------------
# DDR3 interface
#----------------------------------------
NET "DDR3_CAS_N" LOC = M4;
NET "DDR3_CAS_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_CK_N" LOC = K3;
NET "DDR3_CK_N" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_CK_P" LOC = K4;
NET "DDR3_CK_P" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_CKE" LOC = F2;
NET "DDR3_CKE" IOSTANDARD = "SSTL15_II";
NET "DDR3_LDM" LOC = N4;
NET "DDR3_LDM" IOSTANDARD = "SSTL15_II";
NET "DDR3_LDQS_N" LOC = N1;
NET "DDR3_LDQS_N" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_LDQS_P" LOC = N3;
NET "DDR3_LDQS_P" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_ODT" LOC = L6;
NET "DDR3_ODT" IOSTANDARD = "SSTL15_II";
NET "DDR3_RAS_N" LOC = M5;
NET "DDR3_RAS_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_RESET_N" LOC = E3;
NET "DDR3_RESET_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_UDM" LOC = P3;
NET "DDR3_UDM" IOSTANDARD = "SSTL15_II";
NET "DDR3_UDQS_N" LOC = V1;
NET "DDR3_UDQS_N" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_UDQS_P" LOC = V2;
NET "DDR3_UDQS_P" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_WE_N" LOC = H2;
NET "DDR3_WE_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_RZQ" LOC = K7;
NET "DDR3_RZQ" IOSTANDARD = "SSTL15_II";
NET "DDR3_ZIO" LOC = M7;
NET "DDR3_ZIO" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[0]" LOC = K2;
NET "DDR3_A[0]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[1]" LOC = K1;
NET "DDR3_A[1]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[2]" LOC = K5;
NET "DDR3_A[2]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[3]" LOC = M6;
NET "DDR3_A[3]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[4]" LOC = H3;
NET "DDR3_A[4]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[5]" LOC = M3;
NET "DDR3_A[5]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[6]" LOC = L4;
NET "DDR3_A[6]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[7]" LOC = K6;
NET "DDR3_A[7]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[8]" LOC = G3;
NET "DDR3_A[8]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[9]" LOC = G1;
NET "DDR3_A[9]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[10]" LOC = J4;
NET "DDR3_A[10]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[11]" LOC = E1;
NET "DDR3_A[11]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[12]" LOC = F1;
NET "DDR3_A[12]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[13]" LOC = J6;
NET "DDR3_A[13]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_A[14]" LOC = H5;
#NET "DDR3_A[14]" IOSTANDARD = "SSTL15_II";
NET "DDR3_BA[0]" LOC = J3;
NET "DDR3_BA[0]" IOSTANDARD = "SSTL15_II";
NET "DDR3_BA[1]" LOC = J1;
NET "DDR3_BA[1]" IOSTANDARD = "SSTL15_II";
NET "DDR3_BA[2]" LOC = H1;
NET "DDR3_BA[2]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[0]" LOC = R3;
NET "DDR3_DQ[0]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[1]" LOC = R1;
NET "DDR3_DQ[1]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[2]" LOC = P2;
NET "DDR3_DQ[2]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[3]" LOC = P1;
NET "DDR3_DQ[3]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[4]" LOC = L3;
NET "DDR3_DQ[4]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[5]" LOC = L1;
NET "DDR3_DQ[5]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[6]" LOC = M2;
NET "DDR3_DQ[6]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[7]" LOC = M1;
NET "DDR3_DQ[7]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[8]" LOC = T2;
NET "DDR3_DQ[8]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[9]" LOC = T1;
NET "DDR3_DQ[9]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[10]" LOC = U3;
NET "DDR3_DQ[10]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[11]" LOC = U1;
NET "DDR3_DQ[11]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[12]" LOC = W3;
NET "DDR3_DQ[12]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[13]" LOC = W1;
NET "DDR3_DQ[13]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[14]" LOC = Y2;
NET "DDR3_DQ[14]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[15]" LOC = Y1;
NET "DDR3_DQ[15]" IOSTANDARD = "SSTL15_II";
#===============================================================================
# Terminations
#===============================================================================
# DDR3
NET "DDR3_DQ[*]" IN_TERM = NONE;
NET "DDR3_LDQS_P" IN_TERM = NONE;
NET "DDR3_LDQS_N" IN_TERM = NONE;
NET "DDR3_UDQS_P" IN_TERM = NONE;
NET "DDR3_UDQS_N" IN_TERM = NONE;
#----------------------------------------
# Flash memory SPI interface
#----------------------------------------
......@@ -404,10 +521,8 @@ NET "flash_miso_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# GN4124
NET "gn_rst_n" TIG;
NET "cmp_gn4124_core/rst_*" TIG;
NET "cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = cmp_gn4124_core/cmp_clk_in/P_clk;
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
#NET "gen_with_gennum/cmp_gn4124_core/rst_*" TIG;
#NET "gen_with_gennum/cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = cmp_gn4124_core/cmp_clk_in/P_clk;
NET "clk_sys_62m5" TNM_NET = clk_sys_62m5;
TIMESPEC ts_ignore_crossclock = FROM "clk_sys_62m5" TO "tdc_clk_125m_p_i" 10ns DATAPATHONLY;
......@@ -422,10 +537,17 @@ TIMESPEC TS_x4 = FROM "U_GTP_ch1_rx_divclk" TO "clk_sys_62m5" 10ns DATAPATHONLY;
#Created by Constraints Editor (xc6slx150t-fgg900-3) - 2017/12/06
NET "cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>;
TIMESPEC TS_cmp_xwrc_board_spec_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch1_gtp_clkout_int_1_ = PERIOD "cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
NET "cmp_gn4124_core/cmp_clk_in/feedback" TNM_NET = cmp_gn4124_core/cmp_clk_in/feedback;
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_feedback = PERIOD "cmp_gn4124_core/cmp_clk_in/feedback" 5 ns HIGH 50%;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_skew_limit = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
TIMESPEC TS_skew_limit = FROM "skew_limit" TO "FFS" 2 ns DATAPATHONLY;
NET "*/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "*/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/hard_done_cal" TIG;
NET "*/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2018/07/26
NET "gen_with_gennum.cmp_gn4124_core/cmp_clk_in/feedback" TNM_NET = gen_with_gennum.cmp_gn4124_core/cmp_clk_in/feedback;
TIMESPEC TS_gen_with_gennum_cmp_gn4124_core_cmp_clk_in_feedback = PERIOD "gen_with_gennum.cmp_gn4124_core/cmp_clk_in/feedback" 5 ns HIGH 50%;
NET "gen_with_gennum.cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = gen_with_gennum.cmp_gn4124_core/cmp_clk_in/P_clk;
TIMESPEC TS_gen_with_gennum_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "gen_with_gennum.cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
hdl/top/spec/wr_spec_tdc.vhd
View file @ 0724de2e
......@@ -131,7 +131,12 @@ use UNISIM.vcomponents.all;
entity wr_spec_tdc is
generic
(g_simulation : boolean := false); -- this generic is set to TRUE
(g_simulation : boolean := false;
g_CALIB_SOFT_IP : boolean := true;
g_sim_bypass_gennum : boolean := false;
g_use_dma_readout : boolean := true;
g_use_fake_timestamps_for_sim : boolean := false
);
-- when instantiated in a test-bench
port(
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
......@@ -140,7 +145,7 @@ entity wr_spec_tdc is
clk_125m_gtp_p_i : in std_logic;
clk_20m_vcxo_i : in std_logic; -- 20 MHz VCXO
wr_dac_sclk_o : out std_logic; -- PLL VCXO DAC Drive
wr_dac_sclk_o : out std_logic; -- PLL VCXO DAC Drive
wr_dac_din_o : out std_logic;
wr_25dac_cs_n_o : out std_logic;
wr_20dac_cs_n_o : out std_logic;
......@@ -166,47 +171,68 @@ entity wr_spec_tdc is
carrier_onewire_b : inout std_logic; -- SPEC 1-wire
button1_i : in std_logic := '1';
-- DDR3 interface
DDR3_CAS_N : out std_logic;
DDR3_CK_N : out std_logic;
DDR3_CK_P : out std_logic;
DDR3_CKE : out std_logic;
DDR3_LDM : out std_logic;
DDR3_LDQS_N : inout std_logic;
DDR3_LDQS_P : inout std_logic;
DDR3_ODT : out std_logic;
DDR3_RAS_N : out std_logic;
DDR3_RESET_N : out std_logic;
DDR3_UDM : out std_logic;
DDR3_UDQS_N : inout std_logic;
DDR3_UDQS_P : inout std_logic;
DDR3_WE_N : out std_logic;
DDR3_DQ : inout std_logic_vector(15 downto 0);
DDR3_A : out std_logic_vector(13 downto 0);
DDR3_BA : out std_logic_vector(2 downto 0);
DDR3_ZIO : inout std_logic;
DDR3_RZQ : inout std_logic;
------------------------------------------------------------------------
-- GN4124 PCI bridge pins
------------------------------------------------------------------------
gn_rst_n : in std_logic; -- reset from gn4124 (rstout18_n)
gn_rst_n : in std_logic; -- reset from gn4124 (rstout18_n)
-- general purpose interface
gn_gpio : inout std_logic_vector(1 downto 0); -- gpio[0] -> gn4124 gpio8
gn_gpio : out std_logic_vector(1 downto 0); -- gpio[0] -> gn4124 gpio8
-- pcie to local [inbound data] - rx
gn_p2l_rdy : out std_logic; -- rx buffer full flag
gn_p2l_clkn : in std_logic; -- receiver source synchronous clock-
gn_p2l_clkp : in std_logic; -- receiver source synchronous clock+
gn_p2l_rdy : out std_logic; -- rx buffer full flag
gn_p2l_clkn : in std_logic; -- receiver source synchronous clock-
gn_p2l_clkp : in std_logic; -- receiver source synchronous clock+
gn_p2l_data : in std_logic_vector(15 downto 0); -- parallel receive data
gn_p2l_dframe : in std_logic; -- receive frame
gn_p2l_valid : in std_logic; -- receive data valid
gn_p2l_dframe : in std_logic; -- receive frame
gn_p2l_valid : in std_logic; -- receive data valid
-- inbound buffer request/status
gn_p_wr_req : in std_logic_vector(1 downto 0); -- pcie write request
gn_p_wr_rdy : out std_logic_vector(1 downto 0); -- pcie write ready
gn_rx_error : out std_logic; -- receive error
gn_p_wr_req : in std_logic_vector(1 downto 0); -- pcie write request
gn_p_wr_rdy : out std_logic_vector(1 downto 0); -- pcie write ready
gn_rx_error : out std_logic; -- receive error
-- local to parallel [outbound data] - tx
gn_l2p_data : out std_logic_vector(15 downto 0); -- parallel transmit data
gn_l2p_dframe : out std_logic; -- transmit data frame
gn_l2p_valid : out std_logic; -- transmit data valid
gn_l2p_clkn : out std_logic; -- transmitter source synchronous clock-
gn_l2p_clkp : out std_logic; -- transmitter source synchronous clock+
gn_l2p_edb : out std_logic; -- packet termination and discard
gn_l2p_data : out std_logic_vector(15 downto 0); -- parallel transmit data
gn_l2p_dframe : out std_logic; -- transmit data frame
gn_l2p_valid : out std_logic; -- transmit data valid
gn_l2p_clkn : out std_logic; -- transmitter source synchronous clock-
gn_l2p_clkp : out std_logic; -- transmitter source synchronous clock+
gn_l2p_edb : out std_logic; -- packet termination and discard
-- outbound buffer status
gn_l2p_rdy : in std_logic; -- tx buffer full flag
gn_l_wr_rdy : in std_logic_vector(1 downto 0); -- local-to-pcie write
gn_p_rd_d_rdy : in std_logic_vector(1 downto 0); -- pcie-to-local read response data ready
gn_tx_error : in std_logic; -- transmit error
gn_vc_rdy : in std_logic_vector(1 downto 0); -- channel ready
gn_l2p_rdy : in std_logic; -- tx buffer full flag
gn_l_wr_rdy : in std_logic_vector(1 downto 0); -- local-to-pcie write
gn_p_rd_d_rdy : in std_logic_vector(1 downto 0); -- pcie-to-local read response data ready
gn_tx_error : in std_logic; -- transmit error
gn_vc_rdy : in std_logic_vector(1 downto 0); -- channel ready
------------------------------------------------------------------------
-- Interface with the PLL AD9516 and DAC AD5662 on TDC mezzanine
------------------------------------------------------------------------
pll_sclk_o : out std_logic; -- SPI clock
pll_sdi_o : out std_logic; -- data line for PLL and DAC
pll_cs_o : out std_logic; -- PLL chip select
pll_dac_sync_o : out std_logic; -- DAC chip select
pll_sdo_i : in std_logic; -- not used for the moment
pll_status_i : in std_logic; -- PLL Digital Lock Detect, active high
pll_sclk_o : out std_logic; -- SPI clock
pll_sdi_o : out std_logic; -- data line for PLL and DAC
pll_cs_o : out std_logic; -- PLL chip select
pll_dac_sync_o : out std_logic; -- DAC chip select
pll_sdo_i : in std_logic; -- not used for the moment
pll_status_i : in std_logic; -- PLL Digital Lock Detect, active high
tdc_clk_125m_p_i : in std_logic; -- 125 MHz differential clock: system clock
tdc_clk_125m_n_i : in std_logic; -- 125 MHz differential clock: system clock
acam_refclk_p_i : in std_logic; -- 31.25 MHz differential clock: ACAM ref clock
......@@ -228,37 +254,51 @@ entity wr_spec_tdc is
ef1_i : in std_logic; -- empty flag iFIFO1
ef2_i : in std_logic; -- empty flag iFIFO2
-- Enable of input Logic on TDC mezzanine
enable_inputs_o : out std_logic; -- enables all 5 inputs
term_en_1_o : out std_logic; -- Ch.1 termination enable of 50 Ohm termination
term_en_2_o : out std_logic; -- Ch.2 termination enable of 50 Ohm termination
term_en_3_o : out std_logic; -- Ch.3 termination enable of 50 Ohm termination
term_en_4_o : out std_logic; -- Ch.4 termination enable of 50 Ohm termination
term_en_5_o : out std_logic; -- Ch.5 termination enable of 50 Ohm termination
enable_inputs_o : out std_logic; -- enables all 5 inputs
term_en_1_o : out std_logic; -- Ch.1 termination enable of 50 Ohm termination
term_en_2_o : out std_logic; -- Ch.2 termination enable of 50 Ohm termination
term_en_3_o : out std_logic; -- Ch.3 termination enable of 50 Ohm termination
term_en_4_o : out std_logic; -- Ch.4 termination enable of 50 Ohm termination
term_en_5_o : out std_logic; -- Ch.5 termination enable of 50 Ohm termination
-- LEDs on TDC mezzanine
tdc_led_status_o : out std_logic; -- amber led on front pannel, division of 125 MHz tdc_clk
tdc_led_trig1_o : out std_logic; -- amber led on front pannel, Ch.1 enable
tdc_led_trig2_o : out std_logic; -- amber led on front pannel, Ch.2 enable
tdc_led_trig3_o : out std_logic; -- amber led on front pannel, Ch.3 enable
tdc_led_trig4_o : out std_logic; -- amber led on front pannel, Ch.4 enable
tdc_led_trig5_o : out std_logic; -- amber led on front pannel, Ch.5 enable
tdc_led_status_o : out std_logic; -- amber led on front pannel, division of 125 MHz tdc_clk
tdc_led_trig1_o : out std_logic; -- amber led on front pannel, Ch.1 enable
tdc_led_trig2_o : out std_logic; -- amber led on front pannel, Ch.2 enable
tdc_led_trig3_o : out std_logic; -- amber led on front pannel, Ch.3 enable
tdc_led_trig4_o : out std_logic; -- amber led on front pannel, Ch.4 enable
tdc_led_trig5_o : out std_logic; -- amber led on front pannel, Ch.5 enable
-- Input Logic on TDC mezzanine (not used currently)
tdc_in_fpga_1_i : in std_logic; -- Ch.1 for ACAM, also received by FPGA
tdc_in_fpga_2_i : in std_logic; -- Ch.2 for ACAM, also received by FPGA
tdc_in_fpga_3_i : in std_logic; -- Ch.3 for ACAM, also received by FPGA
tdc_in_fpga_4_i : in std_logic; -- Ch.4 for ACAM, also received by FPGA
tdc_in_fpga_5_i : in std_logic; -- Ch.5 for ACAM, also received by FPGA
tdc_in_fpga_1_i : in std_logic; -- Ch.1 for ACAM, also received by FPGA
tdc_in_fpga_2_i : in std_logic; -- Ch.2 for ACAM, also received by FPGA
tdc_in_fpga_3_i : in std_logic; -- Ch.3 for ACAM, also received by FPGA
tdc_in_fpga_4_i : in std_logic; -- Ch.4 for ACAM, also received by FPGA
tdc_in_fpga_5_i : in std_logic; -- Ch.5 for ACAM, also received by FPGA
-- I2C EEPROM interface on TDC mezzanine
mezz_sys_scl_b : inout std_logic := '1'; -- Mezzanine system EEPROM I2C clock
mezz_sys_sda_b : inout std_logic := '1'; -- Mezzanine system EEPROM I2C data
-- 1-wire interface on TDC mezzanine
mezz_onewire_b : inout std_logic;
mezz_onewire_b : inout std_logic; -- Mezzanine presence (active low)
-- font panel leds
led_act_o : out std_logic;
led_link_o : out std_logic;
-- Carrier other signals
pcb_ver_i : in std_logic_vector(3 downto 0); -- PCB version
prsnt_m2c_n_i : in std_logic); -- Mezzanine presence (active low)
pcb_ver_i : in std_logic_vector(3 downto 0); -- PCB version
prsnt_m2c_n_i : in std_logic
-- Bypass GN4124 core, useful only in simulation
-- Feed fake timestamps bypassing acam - used only in simulation
-- synthesis translate_off
;
sim_wb_i : in t_wishbone_slave_in := cc_dummy_slave_in;
sim_wb_o : out t_wishbone_slave_out;
sim_timestamp_i : in t_tdc_timestamp := c_dummy_timestamp;
sim_timestamp_valid_i : in std_logic := '0';
sim_timestamp_ready_o : out std_logic
-- synthesis translate_on
);
end wr_spec_tdc;
......@@ -267,6 +307,118 @@ end wr_spec_tdc;
--=================================================================================================
architecture rtl of wr_spec_tdc is
component ddr3_ctrl is
generic (
--! Bank and port size selection
g_BANK_PORT_SELECT : string := "SPEC_BANK3_32B_32B";
--! Core's clock period in ps
g_MEMCLK_PERIOD : integer := 3000;
--! If TRUE, uses Xilinx calibration core (Input term, DQS centering)
g_CALIB_SOFT_IP : string := "TRUE";
--! User ports addresses maping (BANK_ROW_COLUMN or ROW_BANK_COLUMN)
g_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
--! Simulation mode
g_SIMULATION : string := "FALSE";
--! DDR3 data port width
g_NUM_DQ_PINS : integer := 16;
--! DDR3 address port width
g_MEM_ADDR_WIDTH : integer := 14;
--! DDR3 bank address width
g_MEM_BANKADDR_WIDTH : integer := 3;
--! Wishbone port 0 data mask size (8-bit granularity)
g_P0_MASK_SIZE : integer := 4;
--! Wishbone port 0 data width
g_P0_DATA_PORT_SIZE : integer := 32;
--! Port 0 byte address width
g_P0_BYTE_ADDR_WIDTH : integer := 30;
--! Wishbone port 1 data mask size (8-bit granularity)
g_P1_MASK_SIZE : integer := 4;
--! Wishbone port 1 data width
g_P1_DATA_PORT_SIZE : integer := 32;
--! Port 1 byte address width
g_P1_BYTE_ADDR_WIDTH : integer := 30);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
status_o : out std_logic_vector(31 downto 0);
ddr3_dq_b : inout std_logic_vector(g_NUM_DQ_PINS-1 downto 0);
ddr3_a_o : out std_logic_vector(g_MEM_ADDR_WIDTH-1 downto 0);
ddr3_ba_o : out std_logic_vector(g_MEM_BANKADDR_WIDTH-1 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_odt_o : out std_logic;
ddr3_rst_n_o : out std_logic;
ddr3_cke_o : out std_logic;
ddr3_dm_o : out std_logic;
ddr3_udm_o : out std_logic;
ddr3_dqs_p_b : inout std_logic;
ddr3_dqs_n_b : inout std_logic;
ddr3_udqs_p_b : inout std_logic;
ddr3_udqs_n_b : inout std_logic;
ddr3_clk_p_o : out std_logic;
ddr3_clk_n_o : out std_logic;
ddr3_rzq_b : inout std_logic;
ddr3_zio_b : inout std_logic;
wb0_rst_n_i : in std_logic;
wb0_clk_i : in std_logic;
wb0_sel_i : in std_logic_vector(g_P0_MASK_SIZE - 1 downto 0);
wb0_cyc_i : in std_logic;
wb0_stb_i : in std_logic;
wb0_we_i : in std_logic;
wb0_addr_i : in std_logic_vector(31 downto 0);
wb0_data_i : in std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
wb0_data_o : out std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
wb0_ack_o : out std_logic;
wb0_stall_o : out std_logic;
p0_cmd_empty_o : out std_logic;
p0_cmd_full_o : out std_logic;
p0_rd_full_o : out std_logic;
p0_rd_empty_o : out std_logic;
p0_rd_count_o : out std_logic_vector(6 downto 0);
p0_rd_overflow_o : out std_logic;
p0_rd_error_o : out std_logic;
p0_wr_full_o : out std_logic;
p0_wr_empty_o : out std_logic;
p0_wr_count_o : out std_logic_vector(6 downto 0);
p0_wr_underrun_o : out std_logic;
p0_wr_error_o : out std_logic;
wb1_rst_n_i : in std_logic;
wb1_clk_i : in std_logic;
wb1_sel_i : in std_logic_vector(g_P1_MASK_SIZE - 1 downto 0);
wb1_cyc_i : in std_logic;
wb1_stb_i : in std_logic;
wb1_we_i : in std_logic;
wb1_addr_i : in std_logic_vector(31 downto 0);
wb1_data_i : in std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
wb1_data_o : out std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
wb1_ack_o : out std_logic;
wb1_stall_o : out std_logic;
p1_cmd_empty_o : out std_logic;
p1_cmd_full_o : out std_logic;
p1_rd_full_o : out std_logic;
p1_rd_empty_o : out std_logic;
p1_rd_count_o : out std_logic_vector(6 downto 0);
p1_rd_overflow_o : out std_logic;
p1_rd_error_o : out std_logic;
p1_wr_full_o : out std_logic;
p1_wr_empty_o : out std_logic;
p1_wr_count_o : out std_logic_vector(6 downto 0);
p1_wr_underrun_o : out std_logic;
p1_wr_error_o : out std_logic);
end component ddr3_ctrl;
function f_bool2int (x : boolean) return integer is
begin
if(x) then
return 1;
else
return 0;
end if;
end f_bool2int;
---------------------------------------------------------------------------------------------------
-- SDB CONSTANTS --
---------------------------------------------------------------------------------------------------
......@@ -290,11 +442,12 @@ architecture rtl of wr_spec_tdc is
-- Note: All address in sdb and crossbar are BYTE addresses!
-- Master ports on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 4;
constant c_NUM_WB_MASTERS : integer := 5;
constant c_WB_SLAVE_SPEC_INFO : integer := 0; -- Info on SPEC control and status registers
constant c_WB_SLAVE_VIC : integer := 1; -- Interrupt controller
constant c_WB_SLAVE_TDC : integer := 2; -- TDC core configuration
constant c_WB_SLAVE_WRC : integer := 3; -- White Rabbit PTP core
constant c_WB_SLAVE_DMA : integer := 3;
constant c_WB_SLAVE_WRC : integer := 4; -- White Rabbit PTP core
-- SDB header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
......@@ -306,68 +459,156 @@ architecture rtl of wr_spec_tdc is
constant c_FMC_TDC_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0000FFFF", x"00000000");
constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(5 downto 0) :=
constant c_wb_dma_ctrl_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000003F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000601",
version => x"00000001",
date => x"20121116",
name => "WB-DMA.Control ")));
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(6 downto 0) :=
(0 => f_sdb_embed_device (c_SPEC_INFO_SDB_DEVICE, x"00020000"),
1 => f_sdb_embed_device (c_xwb_vic_sdb, x"00030000"), -- c_xwb_vic_sdb described in the wishbone_pkg
2 => f_sdb_embed_bridge (c_FMC_TDC_SDB_BRIDGE, x"00040000"),
3 => f_sdb_embed_bridge (c_WRCORE_BRIDGE_SDB, x"00080000"),
4 => f_sdb_embed_repo_url (c_SDB_REPO_URL),
5 => f_sdb_embed_synthesis (c_sdb_synthesis_info));
3 => f_sdb_embed_device(c_wb_dma_ctrl_sdb, x"00050000"),
4 => f_sdb_embed_bridge (c_WRCORE_BRIDGE_SDB, x"00080000"),
5 => f_sdb_embed_repo_url (c_SDB_REPO_URL),
6 => f_sdb_embed_synthesis (c_sdb_synthesis_info));
---------------------------------------------------------------------------------------------------
-- VIC CONSTANT --
---------------------------------------------------------------------------------------------------
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 0) :=
(0 => x"00043000");
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 1) :=
(0 => x"00043000",
1 => x"00043001");
---------------------------------------------------------------------------------------------------
-- Signals --
---------------------------------------------------------------------------------------------------
-- Clocks and resets
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
-- DAC configuration through PCIe/VME
-- WISHBONE from crossbar master port
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
-- WISHBONE to crossbar slave port
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
signal gn_wb_adr : std_logic_vector(31 downto 0);
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
signal gn_wb_adr : std_logic_vector(31 downto 0);
-- Carrier CSR info
signal gn4124_status : std_logic_vector(31 downto 0);
signal gn4124_status : std_logic_vector(31 downto 0);
-- VIC
signal irq_to_gn4124 : std_logic;
signal irq_to_gn4124 : std_logic;
-- WRabbit time
signal tm_link_up, tm_time_valid: std_logic;
signal tm_dac_wr_p : std_logic;
signal tm_tai : std_logic_vector(39 downto 0);
signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_dac_value : std_logic_vector(23 downto 0);
signal tm_clk_aux_lock_en : std_logic;
signal tm_clk_aux_locked : std_logic;
signal tm_link_up, tm_time_valid : std_logic;
signal tm_dac_wr_p : std_logic;
signal tm_tai : std_logic_vector(39 downto 0);
signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_dac_value : std_logic_vector(23 downto 0);
signal tm_clk_aux_lock_en : std_logic;
signal tm_clk_aux_locked : std_logic;
-- EEPROM on mezzanine
signal tdc_scl_oen, tdc_scl_in : std_logic;
signal tdc_sda_oen, tdc_sda_in : std_logic;
signal tdc_scl_oen, tdc_scl_in : std_logic;
signal tdc_sda_oen, tdc_sda_in : std_logic;
-- SFP EEPROM on mezzanine
signal sfp_scl_out, sfp_scl_in : std_logic;
signal sfp_sda_out, sfp_sda_in : std_logic;
signal sfp_scl_out, sfp_scl_in : std_logic;
signal sfp_sda_out, sfp_sda_in : std_logic;
-- Carrier 1-Wire
signal wrc_owr_oe, wrc_owr_data : std_logic;
signal wrc_owr_oe, wrc_owr_data : std_logic;
-- aux
signal tdc0_irq : std_logic;
signal tdc0_clk_125m : std_logic;
signal tdc0_soft_rst_n : std_logic;
signal tdc0_irq : std_logic;
signal tdc0_clk_125m : std_logic;
signal tdc0_soft_rst_n : std_logic;
signal ddr3_tdc_adr : std_logic_vector(31 downto 0);
signal powerup_rst_cnt : unsigned(7 downto 0) := "00000000";
signal carrier_info_fmc_rst : std_logic_vector(30 downto 0);
-- GN4124 core DMA port to DDR wishbone bus
signal wb_dma_adr : std_logic_vector(31 downto 0);
signal wb_dma_dat_i : std_logic_vector(31 downto 0);
signal wb_dma_dat_o : std_logic_vector(31 downto 0);
signal wb_dma_sel : std_logic_vector(3 downto 0);
signal wb_dma_cyc : std_logic;
signal wb_dma_stb : std_logic;
signal wb_dma_we : std_logic;
signal wb_dma_ack : std_logic;
signal wb_dma_stall : std_logic;
signal wb_dma_err : std_logic;
signal wb_dma_rty : std_logic;
signal wb_dma_int : std_logic;
signal tdc_dma_out : t_wishbone_master_out;
signal tdc_dma_in : t_wishbone_master_in;
signal clk_ddr_333m : std_logic;
signal ddr3_calib_done : std_logic;
signal dma_irq : std_logic_vector(1 downto 0);
signal ddr_wr_fifo_empty : std_logic;
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector(35 downto 0));
end component;
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0));
end component;
signal control0 : std_logic_vector(35 downto 0);
signal trig0, trig1, trig2, trig3 : std_logic_vector(31 downto 0);
signal ddr3_status : std_logic_vector(31 downto 0);
function f_to_string(x : boolean) return string is
begin
if x then
return "TRUE";
else
return "FALSE";
end if;
end f_to_string;
signal dma_reg_adr : std_logic_vector(31 downto 0);
signal sim_ts_valid, sim_ts_ready : std_logic;
signal sim_ts : t_tdc_timestamp;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- synthesis translate_off
sim_ts <= sim_timestamp_i;
sim_ts_valid <= sim_timestamp_valid_i;
sim_timestamp_ready_o <= sim_ts_ready;
-- synthesis translate_on
tdc0_soft_rst_n <= carrier_info_fmc_rst(0) and rst_sys_62m5_n;
-------------------------------------------------------------------------------
......@@ -377,66 +618,67 @@ begin
cmp_xwrc_board_spec : xwrc_board_spec
generic map (
g_simulation => f_bool2int(g_simulation),
g_with_external_clock_input => FALSE,
g_with_external_clock_input => false,
g_aux_clks => 1,
g_dpram_initf => "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram",
g_fabric_iface => PLAIN)
port map (
areset_n_i => button1_i,
areset_edge_n_i => gn_rst_n,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_sys_62m5_o => clk_sys_62m5,
clk_aux_i(0) => tdc0_clk_125m,
rst_sys_62m5_n_o => rst_sys_62m5_n,
plldac_sclk_o => wr_dac_sclk_o,
plldac_din_o => wr_dac_din_o,
pll25dac_cs_n_o => wr_25dac_cs_n_o,
pll20dac_cs_n_o => wr_20dac_cs_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_det_i => sfp_mod_def0_i,
sfp_sda_i => sfp_sda_in,
sfp_sda_o => sfp_sda_out,
sfp_scl_i => sfp_scl_in,
sfp_scl_o => sfp_scl_out,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
onewire_i => wrc_owr_data,
onewire_oen_o => wrc_owr_oe,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
flash_sclk_o => flash_sclk_o,
flash_ncs_o => flash_ncs_o,
flash_mosi_o => flash_mosi_o,
flash_miso_i => flash_miso_i,
wb_slave_o => cnx_master_in(c_WB_SLAVE_WRC),
wb_slave_i => cnx_master_out(c_WB_SLAVE_WRC),
tm_link_up_o => tm_link_up,
tm_dac_value_o => tm_dac_value,
areset_n_i => button1_i,
areset_edge_n_i => gn_rst_n,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_ddr_o => clk_ddr_333m,
clk_sys_62m5_o => clk_sys_62m5,
clk_aux_i(0) => tdc0_clk_125m,
rst_sys_62m5_n_o => rst_sys_62m5_n,
plldac_sclk_o => wr_dac_sclk_o,
plldac_din_o => wr_dac_din_o,
pll25dac_cs_n_o => wr_25dac_cs_n_o,
pll20dac_cs_n_o => wr_20dac_cs_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_det_i => sfp_mod_def0_i,
sfp_sda_i => sfp_sda_in,
sfp_sda_o => sfp_sda_out,
sfp_scl_i => sfp_scl_in,
sfp_scl_o => sfp_scl_out,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
onewire_i => wrc_owr_data,
onewire_oen_o => wrc_owr_oe,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
flash_sclk_o => flash_sclk_o,
flash_ncs_o => flash_ncs_o,
flash_mosi_o => flash_mosi_o,
flash_miso_i => flash_miso_i,
wb_slave_o => cnx_master_in(c_WB_SLAVE_WRC),
wb_slave_i => cnx_master_out(c_WB_SLAVE_WRC),
tm_link_up_o => tm_link_up,
tm_dac_value_o => tm_dac_value,
tm_dac_wr_o(0) => tm_dac_wr_p,
tm_clk_aux_lock_en_i(0) => tm_clk_aux_lock_en,
tm_clk_aux_locked_o(0) => tm_clk_aux_locked,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai,
tm_cycles_o => tm_cycles,
led_link_o => led_link_o,
led_act_o => led_act_o);
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai,
tm_cycles_o => tm_cycles,
led_link_o => led_link_o,
led_act_o => led_act_o);
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
-- Tristates for 1-wire thermometer
carrier_onewire_b <= '0' when wrc_owr_oe = '1' else 'Z';
carrier_onewire_b <= '0' when wrc_owr_oe = '1' else 'Z';
wrc_owr_data <= carrier_onewire_b;
---------------------------------------------------------------------------------------------------
......@@ -472,84 +714,114 @@ begin
---------------------------------------------------------------------------------------------------
-- GN4124 CORE --
---------------------------------------------------------------------------------------------------
cmp_gn4124_core : gn4124_core
port map
(rst_n_a_i => gn_rst_n,
status_o => gn4124_status,
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i => gn_p2l_clkp,
p2l_clk_n_i => gn_p2l_clkn,
p2l_data_i => gn_p2l_data,
p2l_dframe_i => gn_p2l_dframe,
p2l_valid_i => gn_p2l_valid,
-- P2L Control
p2l_rdy_o => gn_p2l_rdy,
p_wr_req_i => gn_p_wr_req,
p_wr_rdy_o => gn_p_wr_rdy,
rx_error_o => gn_rx_error,
vc_rdy_i => gn_vc_rdy,
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o => gn_l2p_clkp,
l2p_clk_n_o => gn_l2p_clkn,
l2p_data_o => gn_l2p_data,
l2p_dframe_o => gn_l2p_dframe,
l2p_valid_o => gn_l2p_valid,
-- L2P Control
l2p_edb_o => gn_l2p_edb,
l2p_rdy_i => gn_l2p_rdy,
l_wr_rdy_i => gn_l_wr_rdy,
p_rd_d_rdy_i => gn_p_rd_d_rdy,
tx_error_i => gn_tx_error,
dma_irq_o => open,
irq_p_i => '0',
irq_p_o => open,
-- CSR WISHBONE interface (master pipelined)
csr_clk_i => clk_sys_62m5,
csr_adr_o => gn_wb_adr,
csr_dat_o => cnx_slave_in(c_MASTER_GENNUM).dat,
csr_sel_o => cnx_slave_in(c_MASTER_GENNUM).sel,
csr_stb_o => cnx_slave_in(c_MASTER_GENNUM).stb,
csr_we_o => cnx_slave_in(c_MASTER_GENNUM).we,
csr_cyc_o => cnx_slave_in(c_MASTER_GENNUM).cyc,
csr_dat_i => cnx_slave_out(c_MASTER_GENNUM).dat,
csr_ack_i => cnx_slave_out(c_MASTER_GENNUM).ack,
csr_stall_i => cnx_slave_out(c_MASTER_GENNUM).stall,
csr_err_i => cnx_slave_out(c_MASTER_GENNUM).err,
csr_rty_i => cnx_slave_out(c_MASTER_GENNUM).rty,
csr_int_i => cnx_slave_out(c_MASTER_GENNUM).int,
-- DMA: not used
dma_clk_i => clk_sys_62m5,
dma_ack_i => '1',
dma_dat_i => (others => '0'),
dma_stall_i => '0',
dma_err_i => '0',
dma_rty_i => '0',
dma_int_i => '0',
dma_reg_clk_i => clk_sys_62m5,
dma_reg_adr_i => (others => '0'),
dma_reg_dat_i => (others => '0'),
dma_reg_sel_i => (others => '0'),
dma_reg_stb_i => '0',
dma_reg_we_i => '0',
dma_reg_cyc_i => '0');
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Convert 32-bit word address into byte address for crossbar
cnx_slave_in(c_MASTER_GENNUM).adr <= gn_wb_adr(29 downto 0) & "00";
gen_with_gennum : if g_sim_bypass_gennum = false generate
cmp_gn4124_core : gn4124_core
port map
(rst_n_a_i => gn_rst_n,
status_o => gn4124_status,
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i => gn_p2l_clkp,
p2l_clk_n_i => gn_p2l_clkn,
p2l_data_i => gn_p2l_data,
p2l_dframe_i => gn_p2l_dframe,
p2l_valid_i => gn_p2l_valid,
-- P2L Control
p2l_rdy_o => gn_p2l_rdy,
p_wr_req_i => gn_p_wr_req,
p_wr_rdy_o => gn_p_wr_rdy,
rx_error_o => gn_rx_error,
vc_rdy_i => gn_vc_rdy,
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o => gn_l2p_clkp,
l2p_clk_n_o => gn_l2p_clkn,
l2p_data_o => gn_l2p_data,
l2p_dframe_o => gn_l2p_dframe,
l2p_valid_o => gn_l2p_valid,
-- L2P Control
l2p_edb_o => gn_l2p_edb,
l2p_rdy_i => gn_l2p_rdy,
l_wr_rdy_i => gn_l_wr_rdy,
p_rd_d_rdy_i => gn_p_rd_d_rdy,
tx_error_i => gn_tx_error,
dma_irq_o => dma_irq,
irq_p_i => '0',
irq_p_o => open,
cmp_tdc_mezzanine : fmc_tdc_wrapper
-- CSR WISHBONE interface (master pipelined)
csr_clk_i => clk_sys_62m5,
csr_adr_o => gn_wb_adr,
csr_dat_o => cnx_slave_in(c_MASTER_GENNUM).dat,
csr_sel_o => cnx_slave_in(c_MASTER_GENNUM).sel,
csr_stb_o => cnx_slave_in(c_MASTER_GENNUM).stb,
csr_we_o => cnx_slave_in(c_MASTER_GENNUM).we,
csr_cyc_o => cnx_slave_in(c_MASTER_GENNUM).cyc,
csr_dat_i => cnx_slave_out(c_MASTER_GENNUM).dat,
csr_ack_i => cnx_slave_out(c_MASTER_GENNUM).ack,
csr_stall_i => cnx_slave_out(c_MASTER_GENNUM).stall,
csr_err_i => '0',
csr_rty_i => '0',
csr_int_i => '0',
dma_clk_i => clk_sys_62m5,
dma_adr_o => wb_dma_adr,
dma_dat_o => wb_dma_dat_o,
dma_sel_o => wb_dma_sel,
dma_stb_o => wb_dma_stb,
dma_we_o => wb_dma_we,
dma_cyc_o => wb_dma_cyc,
dma_dat_i => wb_dma_dat_i,
dma_ack_i => wb_dma_ack,
dma_stall_i => wb_dma_stall,
dma_err_i => wb_dma_err,
dma_rty_i => wb_dma_rty,
dma_int_i => wb_dma_int,
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i => clk_sys_62m5,
dma_reg_adr_i => dma_reg_adr,
dma_reg_dat_i => cnx_master_out(c_WB_SLAVE_DMA).dat,
dma_reg_sel_i => cnx_master_out(c_WB_SLAVE_DMA).sel,
dma_reg_stb_i => cnx_master_out(c_WB_SLAVE_DMA).stb,
dma_reg_we_i => cnx_master_out(c_WB_SLAVE_DMA).we,
dma_reg_cyc_i => cnx_master_out(c_WB_SLAVE_DMA).cyc,
dma_reg_dat_o => cnx_master_in(c_WB_SLAVE_DMA).dat,
dma_reg_ack_o => cnx_master_in(c_WB_SLAVE_DMA).ack,
dma_reg_stall_o => cnx_master_in(c_WB_SLAVE_DMA).stall
);
dma_reg_adr <= "00" & cnx_master_out(c_WB_SLAVE_DMA).adr(31 downto 2);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Convert 32-bit word address into byte address for crossbar
cnx_slave_in(c_MASTER_GENNUM).adr <= gn_wb_adr(29 downto 0) & "00";
end generate gen_with_gennum;
gen_without_gennum : if g_sim_bypass_gennum generate
-- synthesis translate_off
cnx_slave_in(c_MASTER_GENNUM) <= sim_wb_i;
sim_wb_o <= cnx_slave_out(c_MASTER_GENNUM);
wb_dma_cyc <= '0';
-- synthesis translate_on
end generate gen_without_gennum;
cmp_tdc_mezzanine : entity work.fmc_tdc_wrapper
generic map (
g_simulation => g_simulation,
g_with_direct_readout => false)
g_with_direct_readout => false,
g_use_dma_readout => g_use_dma_readout,
g_use_fake_timestamps_for_sim => g_use_fake_timestamps_for_sim)
port map (
clk_sys_i => clk_sys_62m5,
rst_sys_n_i => rst_sys_62m5_n,
......@@ -589,11 +861,6 @@ begin
tdc_led_trig3_o => tdc_led_trig3_o,
tdc_led_trig4_o => tdc_led_trig4_o,
tdc_led_trig5_o => tdc_led_trig5_o,
tdc_in_fpga_1_i => tdc_in_fpga_1_i,
tdc_in_fpga_2_i => tdc_in_fpga_2_i,
tdc_in_fpga_3_i => tdc_in_fpga_3_i,
tdc_in_fpga_4_i => tdc_in_fpga_4_i,
tdc_in_fpga_5_i => tdc_in_fpga_5_i,
mezz_scl_o => tdc_scl_oen,
mezz_sda_o => tdc_sda_oen,
mezz_scl_i => tdc_scl_in,
......@@ -610,6 +877,8 @@ begin
tm_dac_wr_i => tm_dac_wr_p,
slave_i => cnx_master_out(c_WB_SLAVE_TDC),
slave_o => cnx_master_in(c_WB_SLAVE_TDC),
dma_wb_o => tdc_dma_out,
dma_wb_i => tdc_dma_in,
irq_o => tdc0_irq,
clk_125m_tdc_o => tdc0_clk_125m);
......@@ -621,7 +890,7 @@ begin
generic map
(g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_interrupts => 1,
g_num_interrupts => 2,
g_init_vectors => c_VIC_VECTOR_TABLE)
port map
(clk_sys_i => clk_sys_62m5,
......@@ -629,10 +898,11 @@ begin
slave_i => cnx_master_out(c_WB_SLAVE_VIC),
slave_o => cnx_master_in(c_WB_SLAVE_VIC),
irqs_i(0) => tdc0_irq,
irqs_i(1) => dma_irq(0),
irq_master_o => irq_to_gn4124);
gn_gpio(0) <= irq_to_gn4124;
gn_gpio(1) <= '0';
gn_gpio(1) <= irq_to_gn4124;
---------------------------------------------------------------------------------------------------
-- Carrier CSR information --
......@@ -660,7 +930,7 @@ begin
-- SPEC board wrapper releases rst_sys_62m5_n only when system clock pll is
-- locked. Therefore we report here '1' - pll locked
carrier_info_stat_sys_pll_lck_i => '1',
carrier_info_stat_ddr3_cal_done_i => '0',
carrier_info_stat_ddr3_cal_done_i => ddr3_calib_done,
carrier_info_stat_reserved_i => x"0000000",
carrier_info_ctrl_led_green_o => open,
......@@ -672,11 +942,141 @@ begin
carrier_info_rst_fmc0_n_load_o => open,
carrier_info_rst_reserved_o => carrier_info_fmc_rst);
------------------------------------------------------------------------------
-- DMA wishbone bus slaves
-- -> DDR3 controller
------------------------------------------------------------------------------
cmp_ddr_ctrl : ddr3_ctrl
generic map(
g_BANK_PORT_SELECT => "SPEC_BANK3_32B_32B",
g_MEMCLK_PERIOD => 3000,
g_SIMULATION => f_to_string(g_SIMULATION),
g_CALIB_SOFT_IP => f_to_string(g_CALIB_SOFT_IP),
g_P0_MASK_SIZE => 4,
g_P0_DATA_PORT_SIZE => 32,
g_P0_BYTE_ADDR_WIDTH => 30,
g_P1_MASK_SIZE => 4,
g_P1_DATA_PORT_SIZE => 32,
g_P1_BYTE_ADDR_WIDTH => 30)
port map (
clk_i => clk_ddr_333m,
rst_n_i => rst_sys_62m5_n,
status_o => ddr3_status,
ddr3_dq_b => DDR3_DQ,
ddr3_a_o => DDR3_A,
ddr3_ba_o => DDR3_BA,
ddr3_ras_n_o => DDR3_RAS_N,
ddr3_cas_n_o => DDR3_CAS_N,
ddr3_we_n_o => DDR3_WE_N,
ddr3_odt_o => DDR3_ODT,
ddr3_rst_n_o => DDR3_RESET_N,
ddr3_cke_o => DDR3_CKE,
ddr3_dm_o => DDR3_LDM,
ddr3_udm_o => DDR3_UDM,
ddr3_dqs_p_b => DDR3_LDQS_P,
ddr3_dqs_n_b => DDR3_LDQS_N,
ddr3_udqs_p_b => DDR3_UDQS_P,
ddr3_udqs_n_b => DDR3_UDQS_N,
ddr3_clk_p_o => DDR3_CK_P,
ddr3_clk_n_o => DDR3_CK_N,
ddr3_rzq_b => DDR3_RZQ,
ddr3_zio_b => DDR3_ZIO,
wb0_rst_n_i => rst_sys_62m5_n,
wb0_clk_i => clk_sys_62m5,
wb0_sel_i => tdc_dma_out.sel,
wb0_cyc_i => tdc_dma_out.cyc,
wb0_stb_i => tdc_dma_out.stb,
wb0_we_i => tdc_dma_out.we,
wb0_addr_i => ddr3_tdc_adr,
wb0_data_i => tdc_dma_out.dat,
wb0_data_o => open,
wb0_ack_o => tdc_dma_in.ack,
wb0_stall_o => tdc_dma_in.stall,
p0_cmd_empty_o => open,
p0_cmd_full_o => open,
p0_rd_full_o => open,
p0_rd_empty_o => open,
p0_rd_count_o => open,
p0_rd_overflow_o => open,
p0_rd_error_o => open,
p0_wr_full_o => open,
p0_wr_empty_o => ddr_wr_fifo_empty,
p0_wr_count_o => open,
p0_wr_underrun_o => open,
p0_wr_error_o => open,
wb1_rst_n_i => rst_sys_62m5_n,
wb1_clk_i => clk_sys_62m5,
wb1_sel_i => wb_dma_sel,
wb1_cyc_i => wb_dma_cyc,
wb1_stb_i => wb_dma_stb,
wb1_we_i => wb_dma_we,
wb1_addr_i => wb_dma_adr,
wb1_data_i => wb_dma_dat_o,
wb1_data_o => wb_dma_dat_i,
wb1_ack_o => wb_dma_ack,
wb1_stall_o => wb_dma_stall,
p1_cmd_empty_o => open,
p1_cmd_full_o => open,
p1_rd_full_o => open,
p1_rd_empty_o => open,
p1_rd_count_o => open,
p1_rd_overflow_o => open,
p1_rd_error_o => open,
p1_wr_full_o => open,
p1_wr_empty_o => open,
p1_wr_count_o => open,
p1_wr_underrun_o => open,
p1_wr_error_o => open
);
ddr3_tdc_adr <= "00" & tdc_dma_out.adr(31 downto 2);
--CS_ICON : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL0);
--CS_ILA : chipscope_ila
-- port map (
-- CONTROL => CONTROL0,
-- CLK => clk_sys_62m5,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3);
trig0(0) <= ddr3_calib_done;
trig0(1) <= wb_dma_cyc;
trig0(2) <= wb_dma_we;
trig0(3) <= wb_dma_stb;
trig0(4) <= wb_dma_ack;
trig0(5) <= wb_dma_stall;
trig0(6) <= irq_to_gn4124;
trig0(7) <= tdc0_irq;
trig0(8) <= dma_irq(0);
trig1 <= wb_dma_dat_o;
trig2 <= wb_dma_dat_i;
trig3 <= wb_dma_adr;
ddr3_calib_done <= ddr3_status(0);
-- unused Wishbone signals
wb_dma_err <= '0';
wb_dma_rty <= '0';
wb_dma_int <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_SPEC_INFO).err <= '0';
cnx_master_in(c_WB_SLAVE_SPEC_INFO).rty <= '0';
cnx_master_in(c_WB_SLAVE_SPEC_INFO).int <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Tristates for TDC mezzanine EEPROM
......
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