Maintenance scheduled 24th July -- expect downtime along that day

Commit 07d08c43 authored by penacoba's avatar penacoba

Operational version with full timestamps and no timing errors


git-svn-id: http://svn.ohwr.org/fmc-tdc@56 85dfdc96-de2c-444c-878d-45b388be74a9
parent 9800f270
......@@ -208,6 +208,10 @@ begin
we <= we_i;
-- outputs to other blocks
acam_ef1_o <= ef1;
acam_ef2_o <= ef2;
acam_lf1_o <= lf1;
acam_lf2_o <= lf2;
ack_o <= ack;
dat_o <= ef1 & ef2 & lf1 & lf2 & data_bus_io;
......@@ -231,10 +235,6 @@ begin
-- outputs to the ACAM
address_o <= adr(3 downto 0);
acam_ef1_o <= ef1;
acam_ef2_o <= ef2;
acam_lf1_o <= lf1;
acam_lf2_o <= lf2;
output_registers: process
begin
......
......@@ -86,6 +86,8 @@ architecture rtl of acam_timecontrol_interface is
);
end component;
constant constant_delay : unsigned(g_width-1 downto 0):=x"00000004";
signal acam_refclk : std_logic;
signal clk : std_logic;
signal counter_reset : std_logic;
......@@ -104,6 +106,7 @@ signal start_trig_edge : std_logic;
signal start_trig_received : std_logic;
signal waitingfor_refclk : std_logic;
signal window_active : std_logic;
signal total_delay : std_logic_vector(g_width-1 downto 0);
signal window_delay : std_logic_vector(g_width-1 downto 0);
signal window_inverted : std_logic;
signal window_prepulse : std_logic;
......@@ -155,7 +158,7 @@ begin
clk => clk,
reset => reset,
start => window_prepulse,
start_value => window_delay,
start_value => total_delay,
count_done => window_start,
current_value => open
......@@ -256,6 +259,7 @@ begin
window_prepulse <= waitingfor_refclk and refclk_edge;
counter_reset <= reset or window_start;
total_delay <= std_logic_vector(unsigned(window_delay)+constant_delay);
-- inputs
clk <= clk_i;
......
......@@ -275,7 +275,7 @@ begin
mem_data_rd <= dat_i;
-- outputs
wr_pointer_o <= dacapo_flag & std_logic_vector(wr_pointer(g_width-4 downto 0)) & "00";
wr_pointer_o <= dacapo_flag & std_logic_vector(wr_pointer(g_width-6 downto 0)) & x"0";
adr_o <= mem_adr;
cyc_o <= mem_cyc;
......
......@@ -79,7 +79,7 @@ architecture rtl of one_hz_gen is
);
end component;
constant constant_delay : unsigned(3 downto 0):=x"4";
constant constant_delay : unsigned(g_width-1 downto 0):=x"00000004";
signal clk : std_logic;
signal local_utc : unsigned(g_width-1 downto 0);
......
......@@ -56,7 +56,7 @@ entity reg_ctrl is
read_start01_o : out std_logic;
reset_acam_o : out std_logic;
load_utc_o : out std_logic;
load_tdc_config_o : out std_logic;
-- load_tdc_config_o : out std_logic;
clear_dacapo_flag_o : out std_logic;
-- configuration registers from and for the ACAM and the modules of the TDC core
......@@ -72,11 +72,11 @@ entity reg_ctrl is
acam_config_o : out config_vector;
starting_utc_o : out std_logic_vector(g_width-1 downto 0);
clk_freq_o : out std_logic_vector(g_width-1 downto 0);
ref_clk_freq_o : out std_logic_vector(g_width-1 downto 0);
-- clk_freq_o : out std_logic_vector(g_width-1 downto 0);
-- ref_clk_freq_o : out std_logic_vector(g_width-1 downto 0);
start_phase_o : out std_logic_vector(g_width-1 downto 0);
one_hz_phase_o : out std_logic_vector(g_width-1 downto 0);
retrig_freq_o : out std_logic_vector(g_width-1 downto 0)
one_hz_phase_o : out std_logic_vector(g_width-1 downto 0)
-- retrig_freq_o : out std_logic_vector(g_width-1 downto 0)
);
end reg_ctrl;
......@@ -126,11 +126,11 @@ signal wr_pointer : std_logic_vector(g_width-1 downto 0);
signal acam_config : config_vector;
signal starting_utc : std_logic_vector(g_width-1 downto 0);
signal clk_freq : std_logic_vector(g_width-1 downto 0);
signal ref_clk_freq : std_logic_vector(g_width-1 downto 0);
--signal clk_freq : std_logic_vector(g_width-1 downto 0);
--signal ref_clk_freq : std_logic_vector(g_width-1 downto 0);
signal start_phase : std_logic_vector(g_width-1 downto 0);
signal one_hz_phase : std_logic_vector(g_width-1 downto 0);
signal retrig_freq : std_logic_vector(g_width-1 downto 0);
--signal retrig_freq : std_logic_vector(g_width-1 downto 0);
signal control_register : std_logic_vector(g_width-1 downto 0);
signal clear_ctrl_reg : std_logic;
......@@ -220,11 +220,11 @@ begin
begin
if reg_reset ='1' then
starting_utc <= (others =>'0');
clk_freq <= (others =>'0');
ref_clk_freq <= (others =>'0');
-- clk_freq <= (others =>'0');
-- ref_clk_freq <= (others =>'0');
start_phase <= (others =>'0');
one_hz_phase <= (others =>'0');
retrig_freq <= (others =>'0');
-- retrig_freq <= (others =>'0');
elsif reg_cyc ='1' and reg_stb ='1' and reg_we ='1' then
if reg_adr = x"20" then -- corresponds to address 80080 of the gnum BAR 0
......@@ -232,24 +232,24 @@ begin
end if;
if reg_adr = x"21" then -- corresponds to address 80084 of the gnum BAR 0
clk_freq <= reg_data_wr;
end if;
if reg_adr = x"22" then -- corresponds to address 80088 of the gnum BAR 0
ref_clk_freq <= reg_data_wr;
end if;
if reg_adr = x"23" then -- corresponds to address 8008C of the gnum BAR 0
start_phase <= reg_data_wr;
end if;
if reg_adr = x"24" then -- corresponds to address 80090 of the gnum BAR 0
if reg_adr = x"22" then -- corresponds to address 80088 of the gnum BAR 0
one_hz_phase <= reg_data_wr;
end if;
if reg_adr = x"25" then -- corresponds to address 80094 of the gnum BAR 0
retrig_freq <= reg_data_wr;
end if;
-- if reg_adr = x"23" then -- corresponds to address 8008C of the gnum BAR 0
-- start_phase <= reg_data_wr;
-- end if;
--
-- if reg_adr = x"24" then -- corresponds to address 80090 of the gnum BAR 0
-- one_hz_phase <= reg_data_wr;
-- end if;
--
-- if reg_adr = x"25" then -- corresponds to address 80094 of the gnum BAR 0
-- retrig_freq <= reg_data_wr;
-- end if;
end if;
wait until reg_clk ='1';
end process;
......@@ -305,15 +305,14 @@ begin
acam_config_rdbk(10) when x"1E",
starting_utc when x"20",
clk_freq when x"21",
ref_clk_freq when x"22",
start_phase when x"23",
one_hz_phase when x"24",
retrig_freq when x"25",
local_utc when x"26",
irq_code when x"27",
start_phase when x"21",
one_hz_phase when x"22",
-- when x"23",
irq_code when x"24",
local_utc when x"25",
-- when x"26",
wr_pointer when x"27",
core_status when x"28",
wr_pointer when x"29",
x"FFFFFFFF" when others;
-- inputs from other blocks
......@@ -333,8 +332,9 @@ begin
acam_ififo2 <= acam_ififo2_i;
acam_start01 <= acam_start01_i;
irq_code <= irq_code_i;
core_status <= core_status_i;
local_utc <= local_utc_i;
wr_pointer <= wr_pointer_i;
core_status <= core_status_i;
-- outputs to other blocks
reg_ack_o <= reg_ack;
......@@ -351,15 +351,14 @@ begin
read_start01_o <= control_register(7);
reset_acam_o <= control_register(8);
load_utc_o <= control_register(9);
load_tdc_config_o <= control_register(10);
clear_dacapo_flag_o <= control_register(11);
clear_dacapo_flag_o <= control_register(10);
starting_utc_o <= starting_utc;
clk_freq_o <= clk_freq;
ref_clk_freq_o <= ref_clk_freq;
-- clk_freq_o <= clk_freq;
-- ref_clk_freq_o <= ref_clk_freq;
start_phase_o <= start_phase;
one_hz_phase_o <= one_hz_phase;
retrig_freq_o <= retrig_freq;
-- retrig_freq_o <= retrig_freq;
end rtl;
----------------------------------------------------------------------------------------------------
......
......@@ -373,7 +373,7 @@ architecture rtl of top_tdc is
read_start01_o : out std_logic;
reset_acam_o : out std_logic;
load_utc_o : out std_logic;
load_tdc_config_o : out std_logic;
-- load_tdc_config_o : out std_logic;
clear_dacapo_flag_o : out std_logic;
-- configuration registers from and for the ACAM and the modules of the TDC core
......@@ -389,11 +389,11 @@ architecture rtl of top_tdc is
acam_config_o : out config_vector;
starting_utc_o : out std_logic_vector(g_width-1 downto 0);
clk_freq_o : out std_logic_vector(g_width-1 downto 0);
ref_clk_freq_o : out std_logic_vector(g_width-1 downto 0);
-- clk_freq_o : out std_logic_vector(g_width-1 downto 0);
-- ref_clk_freq_o : out std_logic_vector(g_width-1 downto 0);
start_phase_o : out std_logic_vector(g_width-1 downto 0);
one_hz_phase_o : out std_logic_vector(g_width-1 downto 0);
retrig_freq_o : out std_logic_vector(g_width-1 downto 0)
one_hz_phase_o : out std_logic_vector(g_width-1 downto 0)
-- retrig_freq_o : out std_logic_vector(g_width-1 downto 0)
);
end component;
......@@ -630,11 +630,11 @@ signal read_ififo1 : std_logic;
signal read_ififo2 : std_logic;
signal read_start01 : std_logic;
signal starting_utc : std_logic_vector(g_width-1 downto 0);
signal clk_freq : std_logic_vector(g_width-1 downto 0);
signal ref_clk_freq : std_logic_vector(g_width-1 downto 0);
--signal clk_freq : std_logic_vector(g_width-1 downto 0);
--signal ref_clk_freq : std_logic_vector(g_width-1 downto 0);
signal start_phase : std_logic_vector(g_width-1 downto 0);
signal one_hz_phase : std_logic_vector(g_width-1 downto 0);
signal retrig_freq : std_logic_vector(g_width-1 downto 0);
--signal retrig_freq : std_logic_vector(g_width-1 downto 0);
signal acam_config_rdbk : config_vector;
signal acam_status : std_logic_vector(g_width-1 downto 0);
......@@ -891,7 +891,7 @@ begin
read_start01_o => read_start01,
reset_acam_o => reset_acam,
load_utc_o => load_utc,
load_tdc_config_o => load_tdc_config,
-- load_tdc_config_o => load_tdc_config,
clear_dacapo_flag_o => clear_dacapo_flag,
-- configuration registers for the ACAM and the modules of the TDC core
......@@ -907,11 +907,13 @@ begin
acam_config_o => acam_config,
starting_utc_o => starting_utc,
clk_freq_o => clk_freq,
ref_clk_freq_o => ref_clk_freq,
start_phase_o => start_phase,
one_hz_phase_o => one_hz_phase,
retrig_freq_o => retrig_freq
-- clk_freq_o => clk_freq,
-- ref_clk_freq_o => ref_clk_freq,
-- start_phase_o => start_phase,
-- one_hz_phase_o => one_hz_phase,
start_phase_o => window_delay,
one_hz_phase_o => pulse_delay
-- retrig_freq_o => retrig_freq
);
clks_rsts_mgment: clk_rst_managr
......@@ -1029,6 +1031,31 @@ begin
current_value => open
);
-- (address decoding: memory used has 512 bytes depth)
-----------------------------------------------------
mem_pipe_cyc <= '1' when dma_cyc='1' and dma_adr(31 downto 9)=x"00000" & "000" else '0';
mem_pipe_adr <= dma_adr;
mem_pipe_stb <= dma_stb;
mem_pipe_we <= dma_we;
mem_pipe_data_wr <= dma_dat_w;
dma_ack <= mem_pipe_ack;
dma_dat_r <= mem_pipe_data_rd;
dma_stall <= mem_pipe_stall;
-- CSR master connected to register control slave
--------------------------------------------------
-- address decoding: first 512 kB for GNUM core, second 512 kB for TDC application (of which only 256 bytes are reserved)
reg_cyc <= '1' when csr_cyc(0)='1' and csr_adr(18 downto 8)="010" & x"00" else '0';
reg_adr(31 downto 19) <= (others=>'0');
reg_adr(18 downto 0) <= csr_adr;
reg_stb <= csr_stb;
reg_we <= csr_we;
reg_data_wr <= csr_dat_w;
csr_ack(0) <= reg_ack;
csr_dat_r <= reg_data_rd;
spec_led: process
begin
if gnum_reset ='1' then
......@@ -1065,56 +1092,6 @@ begin
-- internal signals
spec_led_green <= pll_ld_i;
-- CSR master connected directly to ACAM slave
-----------------------------------------------
-- acm_adr(19) <= '0';
-- acm_adr(18 downto 0) <= csr_adr;
-- acm_cyc <= csr_cyc(0);
-- acm_stb <= csr_stb;
-- acm_we <= csr_we;
-- acm_dat_w <= csr_dat_w;
-- csr_ack(0) <= acm_ack;
-- csr_dat_r <= acm_dat_r;
-- CSR master connected to circular buffer slave
-- DMA master connected to circular buffer pipelined slave
-----------------------------------------------------------
-- -- (address decoding)
-- mem_class_cyc <= '1' when csr_cyc(0)='1' and csr_adr(18 downto 7)=x"400" else '0';
-- mem_class_adr(31 downto 19) <= (others=>'0');
-- mem_class_adr(18 downto 0) <= csr_adr;
--
-- mem_class_stb <= csr_stb;
-- mem_class_we <= csr_we;
-- mem_class_data_wr(127 downto 32) <= (others=>'0');
-- mem_class_data_wr(31 downto 0) <= csr_dat_w;
-- csr_ack(0) <= mem_class_ack;
-- csr_dat_r <= mem_class_data_rd(31 downto 0);
-- (address decoding: memory used has 512 bytes depth)
mem_pipe_cyc <= '1' when dma_cyc='1' and dma_adr(31 downto 9)=x"00000" & "000" else '0';
mem_pipe_adr <= dma_adr;
mem_pipe_stb <= dma_stb;
mem_pipe_we <= dma_we;
mem_pipe_data_wr <= dma_dat_w;
dma_ack <= mem_pipe_ack;
dma_dat_r <= mem_pipe_data_rd;
dma_stall <= mem_pipe_stall;
-- CSR master connected to register memory slave
-----------------------------------------------------------
-- address decoding: first 512 kB for GNUM core, second 512 kB for TDC application (of which only 256 bytes are reserved)
reg_cyc <= '1' when csr_cyc(0)='1' and csr_adr(18 downto 8)="010" & x"00" else '0';
reg_adr(31 downto 19) <= (others=>'0');
reg_adr(18 downto 0) <= csr_adr;
reg_stb <= csr_stb;
reg_we <= csr_we;
reg_data_wr <= csr_dat_w;
csr_ack(0) <= reg_ack;
csr_dat_r <= reg_data_rd;
-- inputs
-- gnum_reset <= not(rst_n_a_i) or not(spec_aux1_i);
gnum_reset <= not(rst_n_a_i);
......@@ -1131,10 +1108,11 @@ begin
tdc_led_trig4_o <= lf1_i;
tdc_led_trig5_o <= tdc_led_trig5;
-- these will evolve as we implement all the features
-- all the section below may evolve as we implement all the features
--------------------------------------------------------------------
irq_p <= dma_irq(0) or dma_irq(1);
pulse_delay <= x"00000001";
window_delay <= x"00000002";
-- pulse_delay <= x"00000001";
-- window_delay <= x"00000002";
mute_inputs_o <= '1';
term_en_1_o <= '1';
term_en_2_o <= '1';
......@@ -1165,7 +1143,8 @@ begin
wait until clk ='1';
end process;
start_trig <= tdc_in_fpga_5_i;
-- start_trig <= tdc_in_fpga_5_i;
start_trig <= activate_acq;
end rtl;
----------------------------------------------------------------------------------------------------
......
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