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FMC TDC 1ns 5cha - Gateware
Commit 07fa5b23 authored by penacoba's avatar penacoba
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First version of binary file that obtains correct timestamps from the ACAM for any delay. 


git-svn-id: http://svn.ohwr.org/fmc-tdc@45 85dfdc96-de2c-444c-878d-45b388be74a9
parent e4bc3c96
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hdl/spec/syn/tdc_syn_constraints.sdc
View file @ 07fa5b23
......@@ -14,8 +14,8 @@ define_clock {n:gnum_interface_block.cmp_clk_in.rx_pllout_x1}
# -clockgroup default_clkgroup_0
# Inputs/Outputs
#
define_input_delay -default 2.00 -ref tdc_clk125:r
define_output_delay -default 2.00 -ref tdc_clk125:r
define_input_delay -default 2.00 -ref tdc_clk125:r
define_output_delay -default 2.00 -ref tdc_clk125:r
define_input_delay {p:p2l_clk_p_i } 2.00 -ref gnum_clk200:r
define_input_delay {p:p2l_clk_n_i } 2.00 -ref gnum_clk200:r
......@@ -51,10 +51,6 @@ define_input_delay {p:pll_refmon_i} 2.00 -ref spec_clk20:r
define_input_delay {p:pll_sdo_i} 2.00 -ref spec_clk20:r
define_input_delay {p:pll_status_i} 2.00 -ref spec_clk20:r
define_false_path -to {p:cs_n_o}
define_false_path -to {p:wr_n_o}
define_false_path -to {p:rd_n_o}
define_false_path -from {p:spec_aux0_i}
define_false_path -from {p:spec_aux1_i}
define_false_path -to {p:spec_aux2_o}
......@@ -71,10 +67,6 @@ define_false_path -to {p:tdc_led_trig3_o}
define_false_path -to {p:tdc_led_trig4_o}
define_false_path -to {p:tdc_led_trig5_o}
define_false_path -to {p:start_from_fpga_o}
#define_path_delay -from {p:adress_o} -to {p:wr_n_o} -max 2
# Attributes
# Global attribute definitions for improving implementation targetting Xilinx
define_global_attribute {syn_useioff} {1}
......@@ -210,6 +202,8 @@ define_attribute {p:term_en_3_o} {syn_loc} {A20}
define_attribute {p:term_en_4_o} {syn_loc} {H10}
define_attribute {p:term_en_5_o} {syn_loc} {E6}
define_attribute {p:tdc_in_fpga_5_i} {syn_loc} {AA14}
define_attribute {p:spec_aux0_i} {syn_loc} {C22}
define_attribute {p:spec_aux1_i} {syn_loc} {D21}
define_attribute {p:spec_aux2_o} {syn_loc} {G19}
......@@ -290,6 +284,8 @@ define_io_standard {term_en_3_o} syn_pad_type {LVCMOS_25}
define_io_standard {term_en_4_o} syn_pad_type {LVCMOS_25}
define_io_standard {term_en_5_o} syn_pad_type {LVCMOS_25}
define_io_standard {tdc_in_fpga_5_i} syn_pad_type {LVCMOS_25}
define_io_standard {spec_aux0_i} syn_pad_type {LVCMOS18}
define_io_standard {spec_aux1_i} syn_pad_type {LVCMOS18}
define_io_standard {spec_aux2_o} syn_pad_type {LVCMOS18}
......
hdl/spec/syn/tdc_syn_script.prj
View file @ 07fa5b23
......@@ -32,14 +32,15 @@ add_file -vhdl -lib work "../src/rtl/incr_counter.vhd"
add_file -vhdl -lib work "../src/rtl/countdown_counter.vhd"
add_file -vhdl -lib work "../src/rtl/clk_rst_managr.vhd"
add_file -vhdl -lib work "../src/rtl/one_hz_gen.vhd"
add_file -vhdl -lib work "../src/rtl/start_nb_offset_gen.vhd"
add_file -vhdl -lib work "../src/rtl/start_retrigger_control.vhd"
add_file -vhdl -lib work "../src/rtl/data_formatting.vhd"
add_file -vhdl -lib work "../src/rtl/data_engine.vhd"
add_file -vhdl -lib work "../src/rtl/acam_timecontrol_interface.vhd"
add_file -vhdl -lib work "../src/rtl/acam_databus_interface.vhd"
#add_file -vhdl -lib work "../src/rtl/top_tdc.vhd"
add_file -vhdl -lib work "../src/rtl/top_tdc.vhd"
#add_file -vhdl -lib work "../src/rtl/test_tdc_pll/top_test_pll.vhd"
add_file -vhdl -lib work "../src/rtl/test_tdc_acam/top_test_acam.vhd"
#add_file -vhdl -lib work "../src/rtl/test_tdc_acam/top_test_acam.vhd"
add_file -constraint -lib work "./tdc_syn_constraints.sdc"
......@@ -102,7 +103,8 @@ set_option -write_vif 0
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./syn_tdc.edf"
#project -result_file "./test_tdc_pll/syn_tdc.edf"
project -result_file "./test_tdc_acam/syn_tdc.edf"
#project -result_file "./test_tdc_acam/syn_tdc.edf"
#project -run -fg synthesis
#project -run -fg timing
hdl/spec/syn/test_tdc_acam/rpt_top_tdc.areasrr
View file @ 07fa5b23
......@@ -11,10 +11,10 @@ SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
------------------------------------------------------
REGISTERS 2683 100 %
REGISTERS 2721 100 %
LATCHES 0 0 %
======================================================
Total SEQUENTIAL ELEMENTS in the block top_tdc: 2683 (47.45 % Utilization)
Total SEQUENTIAL ELEMENTS in the block top_tdc: 2721 (46.41 % Utilization)
COMBINATIONAL LOGIC
......@@ -22,13 +22,13 @@ COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-----------------------------------------------------------------
LUTS 1736 100 %
MUXCY 314 100 %
XORCY 317 100 %
LUTS 1806 100 %
MUXCY 344 100 %
XORCY 348 100 %
MULT18x18/MULT18x18S 2 100 %
SRL16 0 0 %
=================================================================
Total COMBINATIONAL LOGIC in the block top_tdc: 2369 (41.90 % Utilization)
Total COMBINATIONAL LOGIC in the block top_tdc: 2500 (42.64 % Utilization)
MEMORY ELEMENTS
......@@ -69,7 +69,7 @@ Name Total elements Utilization Notes
-------------------------------------------------
PADS 122 100 %
=================================================
Total IO PADS in the block top_tdc: 122 (2.16 % Utilization)
Total IO PADS in the block top_tdc: 122 (2.08 % Utilization)
#### START OF Block RAM DETAILED REPORT ####
......
hdl/spec/syn/test_tdc_acam/rpt_top_tdc_areasrr.htm
View file @ 07fa5b23
......@@ -13,10 +13,10 @@ SEQUENTIAL ELEMENTS
Name Total elements Utilization Notes
------------------------------------------------------
REGISTERS 2683 100 %
REGISTERS 2721 100 %
LATCHES 0 0 %
======================================================
Total SEQUENTIAL ELEMENTS in the block top_tdc: 2683 (47.45 % Utilization)
Total SEQUENTIAL ELEMENTS in the block top_tdc: 2721 (46.41 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
......@@ -25,13 +25,13 @@ COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-----------------------------------------------------------------
LUTS 1736 100 %
MUXCY 314 100 %
XORCY 317 100 %
LUTS 1806 100 %
MUXCY 344 100 %
XORCY 348 100 %
MULT18x18/MULT18x18S 2 100 %
SRL16 0 0 %
=================================================================
Total COMBINATIONAL LOGIC in the block top_tdc: 2369 (41.90 % Utilization)
Total COMBINATIONAL LOGIC in the block top_tdc: 2500 (42.64 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
......@@ -76,7 +76,7 @@ Name Total elements Utilization Notes
-------------------------------------------------
PADS 122 100 %
=================================================
Total IO PADS in the block top_tdc: 122 (2.16 % Utilization)
Total IO PADS in the block top_tdc: 122 (2.08 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
#### START OF Block RAM DETAILED REPORT ####
......
hdl/spec/syn/test_tdc_acam/run_options.txt
View file @ 07fa5b23
#-- Synopsys, Inc.
#-- Version D-2010.03
#-- Project file /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam/run_options.txt
#-- Written on Thu Jul 21 19:57:38 2011
#-- Written on Tue Aug 2 16:06:31 2011
#project files
......@@ -30,11 +30,12 @@ add_file -vhdl -lib work "../src/rtl/incr_counter.vhd"
add_file -vhdl -lib work "../src/rtl/countdown_counter.vhd"
add_file -vhdl -lib work "../src/rtl/clk_rst_managr.vhd"
add_file -vhdl -lib work "../src/rtl/one_hz_gen.vhd"
add_file -vhdl -lib work "../src/rtl/start_nb_offset_gen.vhd"
add_file -vhdl -lib work "../src/rtl/start_retrigger_control.vhd"
add_file -vhdl -lib work "../src/rtl/data_formatting.vhd"
add_file -vhdl -lib work "../src/rtl/data_engine.vhd"
add_file -vhdl -lib work "../src/rtl/acam_timecontrol_interface.vhd"
add_file -vhdl -lib work "../src/rtl/acam_databus_interface.vhd"
add_file -vhdl -lib work "../src/rtl/test_tdc_acam/top_test_acam.vhd"
add_file -vhdl -lib work "../src/rtl/top_tdc.vhd"
add_file -constraint "./tdc_syn_constraints.sdc"
......
hdl/spec/syn/test_tdc_acam/scratchproject.prs
View file @ 07fa5b23
#-- Synopsys, Inc.
#-- Version D-2010.03
#-- Project file /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_acam/scratchproject.prs
#-- Written on Thu Jul 21 19:57:38 2011
#-- Written on Tue Aug 2 16:06:31 2011
#project files
......@@ -30,11 +30,12 @@ add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/s
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/countdown_counter.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/one_hz_gen.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/start_nb_offset_gen.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/start_retrigger_control.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/data_formatting.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/data_engine.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_timecontrol_interface.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_databus_interface.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_acam/top_test_acam.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd"
add_file -constraint "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/tdc_syn_constraints.sdc"
......
hdl/spec/syn/test_tdc_acam/syn_tdc.edf
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hdl/spec/syn/test_tdc_acam/syn_tdc.map
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hdl/spec/syn/test_tdc_acam/syn_tdc.sap
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hdl/spec/syn/test_tdc_acam/syn_tdc.srl
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hdl/spec/syn/test_tdc_acam/syn_tdc.srm
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hdl/spec/syn/test_tdc_acam/syn_tdc.srr
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hdl/spec/syn/test_tdc_acam/syn_tdc.srs
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hdl/spec/syn/test_tdc_acam/syn_tdc.tlg
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hdl/spec/syn/test_tdc_acam/synplicity.ucf
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......@@ -22,9 +22,14 @@ NET "pll_cs_o" TNM = "pll_cs_o";
NET "pll_sdi_o" TNM = "pll_cs_o";
NET "pll_sclk_o" TNM = "pll_cs_o";
TIMEGRP "pll_cs_o" OFFSET = OUT: 48.000 : AFTER spec_clk_i;
NET "data_bus_io(*)" TNM = "data_bus_io___";
NET "address_o(*)" TNM = "data_bus_io___";
TIMEGRP "data_bus_io___" OFFSET = OUT: 6.000 : AFTER tdc_clk_p_i;
NET "start_dis_o" TNM = "start_dis_o";
NET "start_from_fpga_o" TNM = "start_dis_o";
NET "cs_n_o" TNM = "start_dis_o";
NET "rd_n_o" TNM = "start_dis_o";
NET "wr_n_o" TNM = "start_dis_o";
NET "data_bus_io(*)" TNM = "start_dis_o";
NET "address_o(*)" TNM = "start_dis_o";
TIMEGRP "start_dis_o" OFFSET = OUT: 6.000 : AFTER tdc_clk_p_i;
NET "rx_error_o" TNM = "rx_error_o";
NET "l2p_edb_o" TNM = "rx_error_o";
TIMESPEC TS_rx_error_o_gnum_interface_block_cmp_clk_in_rx_pllout_x1 = FROM "gnum_interface_block_cmp_clk_in_rx_pllout_x1" TO "rx_error_o" 3.000 ns;
......@@ -39,65 +44,40 @@ TIMEGRP "acam_refclk_i" OFFSET = IN: 6.000 : BEFORE tdc_clk_p_i;
NET "l2p_rdy_i" TNM = "l2p_rdy_i";
TIMESPEC TS_l2p_rdy_i_gnum_interface_block_cmp_clk_in_rx_pllout_x1 = FROM "l2p_rdy_i" TO "gnum_interface_block_cmp_clk_in_rx_pllout_x1" 3.000 ns;
# 1037 : define_false_path -to { p:cs_n_o }
# 1037 : define_false_path -from { p:spec_aux0_i }
NET "cs_n_o" TNM = "to_1037_0";
TIMESPEC "TS_1037_0" = TO "to_1037_0" TIG;
NET "spec_aux0_i" TNM = "from_1037_0";
TIMESPEC "TS_1037_0" = FROM "from_1037_0" TIG;
# 1038 : define_false_path -to { p:wr_n_o }
# 1038 : define_false_path -from { p:spec_aux1_i }
NET "wr_n_o" TNM = "to_1038_0";
TIMESPEC "TS_1038_0" = TO "to_1038_0" TIG;
NET "spec_aux1_i" TNM = "from_1038_0";
TIMESPEC "TS_1038_0" = FROM "from_1038_0" TIG;
# 1039 : define_false_path -to { p:rd_n_o }
# 1039 : define_false_path -to { p:spec_aux2_o }
NET "rd_n_o" TNM = "to_1039_0";
NET "spec_aux2_o" TNM = "to_1039_0";
TIMESPEC "TS_1039_0" = TO "to_1039_0" TIG;
# 1040 : define_false_path -from { p:spec_aux0_i }
# 1040 : define_false_path -to { p:spec_aux3_o }
NET "spec_aux0_i" TNM = "from_1040_0";
TIMESPEC "TS_1040_0" = FROM "from_1040_0" TIG;
NET "spec_aux3_o" TNM = "to_1040_0";
TIMESPEC "TS_1040_0" = TO "to_1040_0" TIG;
# 1041 : define_false_path -from { p:spec_aux1_i }
# 1043 : define_false_path -to { p:spec_led_green_o }
NET "spec_aux1_i" TNM = "from_1041_0";
TIMESPEC "TS_1041_0" = FROM "from_1041_0" TIG;
# 1042 : define_false_path -to { p:spec_aux2_o }
NET "spec_aux2_o" TNM = "to_1042_0";
TIMESPEC "TS_1042_0" = TO "to_1042_0" TIG;
# 1043 : define_false_path -to { p:spec_aux3_o }
NET "spec_aux3_o" TNM = "to_1043_0";
NET "spec_led_green_o" TNM = "to_1043_0";
TIMESPEC "TS_1043_0" = TO "to_1043_0" TIG;
# 1046 : define_false_path -to { p:spec_led_green_o }
NET "spec_led_green_o" TNM = "to_1046_0";
TIMESPEC "TS_1046_0" = TO "to_1046_0" TIG;
# 1047 : define_false_path -to { p:spec_led_red_o }
NET "spec_led_red_o" TNM = "to_1047_0";
TIMESPEC "TS_1047_0" = TO "to_1047_0" TIG;
# 1048 : define_false_path -to { p:tdc_led_status_o }
NET "tdc_led_status_o" TNM = "to_1048_0";
TIMESPEC "TS_1048_0" = TO "to_1048_0" TIG;
# 1053 : define_false_path -to { p:tdc_led_trig5_o }
# 1044 : define_false_path -to { p:spec_led_red_o }
NET "tdc_led_trig5_o" TNM = "to_1053_0";
TIMESPEC "TS_1053_0" = TO "to_1053_0" TIG;
NET "spec_led_red_o" TNM = "to_1044_0";
TIMESPEC "TS_1044_0" = TO "to_1044_0" TIG;
# 1054 : define_false_path -to { p:start_from_fpga_o }
# 1045 : define_false_path -to { p:tdc_led_status_o }
NET "start_from_fpga_o" TNM = "to_1054_0";
TIMESPEC "TS_1054_0" = TO "to_1054_0" TIG;
NET "tdc_led_status_o" TNM = "to_1045_0";
TIMESPEC "TS_1045_0" = TO "to_1045_0" TIG;
# Unused constraints (intentionally commented out)
......@@ -107,6 +87,7 @@ TIMESPEC "TS_1054_0" = TO "to_1054_0" TIG;
# define_false_path -to { p:tdc_led_trig2_o }
# define_false_path -to { p:tdc_led_trig3_o }
# define_false_path -to { p:tdc_led_trig4_o }
# define_false_path -to { p:tdc_led_trig5_o }
# Location Constraints
PIN "clks_rsts_mgment.spec_clk_gbuf.O" CLOCK_DEDICATED_ROUTE = FALSE;
......
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