Commit 1216d1c6 authored by penacoba's avatar penacoba

Synthesis results


git-svn-id: http://svn.ohwr.org/fmc-tdc@64 85dfdc96-de2c-444c-878d-45b388be74a9
parent 7bc6f27d
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Bitgen" num="341" delta="new" >This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, requires a special bit stream format. For more information, please reference Xilinx Answer Record 39999.
</msg>
<msg type="warning" file="PhysDesignRules" num="2410" delta="new" >This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, may be incorrect and should not be used. For more information, please reference Xilinx Answer Record 39999.
</msg>
</messages>
This diff is collapsed.
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="NgdBuild" num="931" delta="new" >The value of SIM_DEVICE on instance &apos;<arg fmt="%s" index="1">gnum_interface_block.cmp_clk_in.rx_pll_adv_inst</arg>&apos; of type <arg fmt="%s" index="2">PLL_ADV</arg> has been changed from &apos;<arg fmt="%s" index="3">VIRTEX5</arg>&apos; to &apos;<arg fmt="%s" index="4">SPARTAN6</arg>&apos; to correct post-ngdbuild and timing simulation for this primitive. In order for functional simulation to be correct, the value of SIM_DEVICE should be changed in this same manner in the source netlist or constraint file.
</msg>
<msg type="info" file="ConstraintSystem" num="178" delta="new" ><arg fmt="%s" index="1">TNM</arg> &apos;<arg fmt="%s" index="2">gnum_interface_block_cmp_clk_in_buf_P_clk</arg>&apos;, used in period specification &apos;<arg fmt="%s" index="3">TS_gnum_interface_block_cmp_clk_in_buf_P_clk</arg>&apos;, was traced into <arg fmt="%s" index="4">PLL_ADV</arg> instance <arg fmt="%s" index="5">gnum_interface_block.cmp_clk_in.rx_pll_adv_inst</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">PLL_ADV</arg> output(s):
<arg fmt="%s" index="7">CLKOUT0</arg>: <arg fmt="%s" index="8">&lt;TIMESPEC TS_gnum_interface_block_un1_cmp_clk_in = PERIOD &quot;gnum_interface_block_un1_cmp_clk_in&quot; TS_gnum_interface_block_cmp_clk_in_buf_P_clk / 2 HIGH 50%&gt;</arg>
</msg>
<msg type="info" file="ConstraintSystem" num="178" delta="new" ><arg fmt="%s" index="1">TNM</arg> &apos;<arg fmt="%s" index="2">gnum_interface_block_cmp_clk_in_buf_P_clk</arg>&apos;, used in period specification &apos;<arg fmt="%s" index="3">TS_gnum_interface_block_cmp_clk_in_buf_P_clk</arg>&apos;, was traced into <arg fmt="%s" index="4">PLL_ADV</arg> instance <arg fmt="%s" index="5">gnum_interface_block.cmp_clk_in.rx_pll_adv_inst</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">PLL_ADV</arg> output(s):
<arg fmt="%s" index="7">CLKOUT2</arg>: <arg fmt="%s" index="8">&lt;TIMESPEC TS_gnum_interface_block_cmp_clk_in_rx_pllout_x1_0 = PERIOD &quot;gnum_interface_block_cmp_clk_in_rx_pllout_x1_0&quot; TS_gnum_interface_block_cmp_clk_in_buf_P_clk PHASE 1.25 ns HIGH 50%&gt;</arg>
</msg>
<msg type="warning" file="ConstraintSystem" num="0" >The Offset constraint &lt;TIMEGRP &quot;acam_refclk_i&quot; OFFSET = IN: 6.000 : BEFORE tdc_clk_p_i;&gt; [synplicity.ucf(49)], is specified without a duration. This will result in a lack of hold time checks in timing reports. If hold time checks are desired a duration value should be specified following the &apos;VALID&apos; keyword.
</msg>
</messages>
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="ConstraintSystem" num="0" >The Offset constraint &lt;TIMEGRP &quot;acam_refclk_i&quot; OFFSET = IN 6 ns BEFORE COMP &quot;tdc_clk_p_i&quot;;&gt; [syn_tdc.pcf(11480)], is specified without a duration. This will result in a lack of hold time checks in timing reports. If hold time checks are desired a duration value should be specified following the &apos;VALID&apos; keyword.
</msg>
<msg type="warning" file="Timing" num="3223" delta="new" >Timing constraint <arg fmt="%s" index="1">TS_1035_1 = MAXDELAY FROM TIMEGRP &quot;from_1035_1&quot; TO TIMEGRP &quot;to_1035_0&quot; 20 ns;</arg> ignored during timing analysis.</msg>
<msg type="info" file="Timing" num="3386" delta="new" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">tdc_in_fpga_5_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">vc_rdy_i(0)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">vc_rdy_i(1)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p_wr_req_i(0)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p_wr_req_i(1)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">tx_error_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">pll_sdo_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">pll_refmon_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">err_flag_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">pll_status_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="468" delta="new" >Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design.
Review the timing report using Timing Analyzer (In ISE select &quot;Post-Place &amp;
Route Static Timing Report&quot;). Go to the failing constraint(s) and evaluate the failing paths for each constraint.
Try the Design Goal and Strategies for Timing Performance(In ISE select Project -&gt; Design Goals &amp; Strategies) to ensure the best options are set in the tools for timing closure.
</msg>
<msg type="info" file="Timing" num="2761" delta="new" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
<msg type="warning" file="ParHelpers" num="361" delta="new" >There are <arg fmt="%d" index="1">10</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg>
<msg type="warning" file="Par" num="283" delta="new" >There are <arg fmt="%d" index="1">10</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg>
</messages>
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="ConstraintSystem" num="0" >The Offset constraint &lt;TIMEGRP &quot;acam_refclk_i&quot; OFFSET = IN 6 ns BEFORE COMP &quot;tdc_clk_p_i&quot;;&gt; [syn_tdc.pcf(11480)], is specified without a duration. This will result in a lack of hold time checks in timing reports. If hold time checks are desired a duration value should be specified following the &apos;VALID&apos; keyword.
</msg>
<msg type="warning" file="Timing" num="3223" delta="new" >Timing constraint <arg fmt="%s" index="1">TS_1035_1 = MAXDELAY FROM TIMEGRP &quot;from_1035_1&quot; TO TIMEGRP &quot;to_1035_0&quot; 20 ns;</arg> ignored during timing analysis.</msg>
<msg type="info" file="Timing" num="3386" delta="new" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg>
<msg type="info" file="Timing" num="3339" delta="new" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
</messages>
This diff is collapsed.
......@@ -50,8 +50,8 @@ rm par_tdc.unroutes
rm par_tdc.xpi
rm par_usage_statistics.html
rm par_tdc.twr
rm par_tdc.twx
rm timing_report.twr
rm timing_report.twx
rm tdc.bgn
rm tdc.bit
......
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/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/syn_tdc.edf 1320402962
/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/blk_mem_circ_buff_v6_4.ngc 1320402903
/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/fifo_64x512.ngc 1320402903
/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/fifo_32x512.ngc 1320402903
OK
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Release 13.3 - par O.76xd (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Fri Nov 4 11:46:33 2011
All signals are completely routed.
WARNING:ParHelpers:361 - There are 10 loadless signals in this design. This design will cause Bitgen to issue DRC
warnings.
err_flag_i_IBUF
p_wr_req_i(0)_IBUF
p_wr_req_i(1)_IBUF
pll_refmon_i_IBUF
pll_sdo_i_IBUF
pll_status_i_IBUF
tdc_in_fpga_5_i_IBUF
tx_error_i_IBUF
vc_rdy_i(0)_IBUF
vc_rdy_i(1)_IBUF
PROGRAM=PAR
STATE=ROUTED
TIMESPECS_MET=NO
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<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>7789</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>21523</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>21523</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>20075</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>16.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>18.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>37.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>50.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>73.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>74.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>90.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>90.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>91.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>93.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>4.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>4.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>4.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>4.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>5.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>6.1</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>9.2</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>10.1</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>4.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>2.7973</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>
#### START OF AREA REPORT #####[
Part: XC6SLX45TFGG484-3 (Xilinx)
-----------------------------------------------------------------------
######## Utilization report for Top level view: top_tdc ########
=======================================================================
SEQUENTIAL ELEMENTS
*******************
Name Total elements Utilization Notes
------------------------------------------------------
REGISTERS 4175 100 %
LATCHES 22 100 %
======================================================
Total SEQUENTIAL ELEMENTS in the block top_tdc: 4197 (42.90 % Utilization)
COMBINATIONAL LOGIC
*******************
Name Total elements Utilization Notes
-----------------------------------------------------------------
LUTS 3407 100 %
MUXCY 893 100 %
XORCY 876 100 %
MULT18x18/MULT18x18S 3 100 %
SRL16 0 0 %
=================================================================
Total COMBINATIONAL LOGIC in the block top_tdc: 5179 (52.93 % Utilization)
MEMORY ELEMENTS
***************
Name Total elements Utilization Notes
------------------------------------------------------
SYNC RAMS 1 100 %
======================================================
Total MEMORY ELEMENTS in the block top_tdc: 1 (0.01 % Utilization)
Name Total elements Number of bits Utilization Notes
--------------------------------------------------------------------
ROMS 0 0 0 %
====================================================================
Total in the block top_tdc: 0 (0.00 % Utilization)
Distributed RAM
***************
Name Total elements Number of LUTs Utilization Notes
-------------------------------------------------------------------------------
DISTRIBUTED RAM 0 0 0 %
===============================================================================
Total Distributed RAM in the block top_tdc: 0 (0.00 % Utilization)
IO PADS
*******
Name Total elements Utilization Notes
-------------------------------------------------
PADS 123 100 %
=================================================
Total IO PADS in the block top_tdc: 123 (1.26 % Utilization)
#### START OF Block RAM DETAILED REPORT ####
Total Block RAMs: 1
clks_rsts_mgment.un7_word_being_sent_0_0
----------------------------
----------------------------
#### END OF Block RAM DETAILED REPORT ####
##### END OF AREA REPORT #####]
<html><head><title></title></head><body><a name=TopSummary>
#### START OF AREA REPORT #####[<pre>
Part: XC6SLX45TFGG484-3 (Xilinx)
Click here to go to specific block report:
<a href="rpt_top_tdc_areasrr.htm#top_tdc"><h5 align="center">top_tdc</h5></a><br><a name=top_tdc>
-----------------------------------------------------------------------
######## Utilization report for Top level view: top_tdc ########
=======================================================================
SEQUENTIAL ELEMENTS
*******************
Name Total elements Utilization Notes
------------------------------------------------------
REGISTERS 4175 100 %
LATCHES 22 100 %
======================================================
Total SEQUENTIAL ELEMENTS in the block top_tdc: 4197 (42.90 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
COMBINATIONAL LOGIC
*******************
Name Total elements Utilization Notes
-----------------------------------------------------------------
LUTS 3407 100 %
MUXCY 893 100 %
XORCY 876 100 %
MULT18x18/MULT18x18S 3 100 %
SRL16 0 0 %
=================================================================
Total COMBINATIONAL LOGIC in the block top_tdc: 5179 (52.93 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
MEMORY ELEMENTS
***************
Name Total elements Utilization Notes
------------------------------------------------------
SYNC RAMS 1 100 %
======================================================
Total MEMORY ELEMENTS in the block top_tdc: 1 (0.01 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
Name Total elements Number of bits Utilization Notes
--------------------------------------------------------------------
ROMS 0 0 0 %
====================================================================
Total in the block top_tdc: 0 (0.00 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
Distributed RAM
***************
Name Total elements Number of LUTs Utilization Notes
-------------------------------------------------------------------------------
DISTRIBUTED RAM 0 0 0 %
===============================================================================
Total Distributed RAM in the block top_tdc: 0 (0.00 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
IO PADS
*******
Name Total elements Utilization Notes
-------------------------------------------------
PADS 123 100 %
=================================================
Total IO PADS in the block top_tdc: 123 (1.26 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
#### START OF Block RAM DETAILED REPORT ####
Total Block RAMs: 1
clks_rsts_mgment.un7_word_being_sent_0_0
----------------------------
----------------------------
#### END OF Block RAM DETAILED REPORT ####
##### END OF AREA REPORT #####]
</a></body></html>
#########################
### DEFINE VARIABLES ###
#########################
set DesignName "syn_tdc"
set FamilyName "SPARTAN6"
set DeviceName "XC6SLX45T"
set PackageName "FGG484"
set SpeedGrade "-3"
set TopModule "top_tdc"
set EdifFile "syn_tdc.edf"
if {![file exists $DesignName.ise]} {
project new $DesignName.ise
project set family $FamilyName
project set device $DeviceName
project set package $PackageName
project set speed $SpeedGrade
xfile add $EdifFile
if {[file exists synplicity.ucf]} {
xfile add synplicity.ucf
}
project set "Netlist Translation Type" "Timestamp"
project set "Other NGDBuild Command Line Options" "-verbose"
project set "Generate Detailed MAP Report" TRUE
project close
}
file delete -force $DesignName\_xdb
project open $DesignName.ise
process run "Implement Design" -force rerun_all
project close
#-- Synopsys, Inc.
#-- Version D-2010.03
#-- Project file /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/run_options.txt
#-- Written on Fri Nov 4 11:35:03 2011
#project files
add_file -include "../src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.ngc"
add_file -include "../src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.ngc"
add_file -include "../src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.ngc"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/gn4124_core_pkg_s6.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_n_to_1_s2_diff.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_n_to_1_s2_se.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_ser_s6.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_1_to_n_data_s2_se.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_des_s6.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_1_to_n_clk_pll_s2_diff.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_decode32.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/wbmaster32.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/dma_controller_wb_slave.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/dma_controller.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_dma_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_dma_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_arbiter.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/gn4124_core_s6.vhd"
add_file -vhdl -lib work "../src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.vhd"
add_file -vhdl -lib work "../src/rtl/tdc_core_pkg.vhd"
add_file -vhdl -lib work "../src/rtl/free_counter.vhd"
add_file -vhdl -lib work "../src/rtl/incr_counter.vhd"
add_file -vhdl -lib work "../src/rtl/countdown_counter.vhd"
add_file -vhdl -lib work "../src/rtl/clk_rst_managr.vhd"
add_file -vhdl -lib work "../src/rtl/one_hz_gen.vhd"
add_file -vhdl -lib work "../src/rtl/start_retrigger_control.vhd"
add_file -vhdl -lib work "../src/rtl/data_formatting.vhd"
add_file -vhdl -lib work "../src/rtl/data_engine.vhd"
add_file -vhdl -lib work "../src/rtl/acam_timecontrol_interface.vhd"
add_file -vhdl -lib work "../src/rtl/acam_databus_interface.vhd"
add_file -vhdl -lib work "../src/rtl/circular_buffer.vhd"
add_file -vhdl -lib work "../src/rtl/reg_ctrl.vhd"
add_file -vhdl -lib work "../src/rtl/top_tdc.vhd"
add_file -constraint "./tdc_syn_constraints.sdc"
#implementation: "syn"
impl -add syn -type fpga
#
#implementation attributes
set_option -vlog_std v2001
set_option -num_critical_paths 5
set_option -project_relative_includes 1
#device options
set_option -technology Spartan6
set_option -part XC6SLX45T
set_option -package FGG484
set_option -speed_grade -3
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top_tdc"
# mapper_options
set_option -frequency 200
set_option -default_enum_encoding onehot
set_option -write_verilog 0
set_option -write_vhdl 0
# Xilinx Spartan3
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -retiming 0
set_option -update_models_cp 0
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3
set_option -no_sequential_opt 0
# Xilinx Spartan6
set_option -enable_prepacking 1
# NFilter
set_option -popfeed 1
set_option -constprop 1
set_option -createhierarchy 0
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 0
#VIF options
set_option -write_vif 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./syn_tdc.edf"
impl -active "syn"
#-- Synopsys, Inc.
#-- Version D-2010.03
#-- Project file /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/scratchproject.prs
#-- Written on Fri Nov 4 11:35:03 2011
#project files
add_file -include "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.ngc"
add_file -include "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.ngc"
add_file -include "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.ngc"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/gn4124_core_pkg_s6.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/serdes_n_to_1_s2_diff.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/serdes_n_to_1_s2_se.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/l2p_ser_s6.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/serdes_1_to_n_data_s2_se.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/p2l_des_s6.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/serdes_1_to_n_clk_pll_s2_diff.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/p2l_decode32.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/wbmaster32.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/dma_controller_wb_slave.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/dma_controller.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/l2p_dma_master.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/p2l_dma_master.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/l2p_arbiter.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/gn4124_core_s6.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/tdc_core_pkg.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/free_counter.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/incr_counter.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/countdown_counter.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/one_hz_gen.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/start_retrigger_control.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/data_formatting.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/data_engine.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_timecontrol_interface.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_databus_interface.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/circular_buffer.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/reg_ctrl.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd"
add_file -constraint "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/tdc_syn_constraints.sdc"
#implementation: "syn"
impl -add /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn -type fpga
#
#implementation attributes
set_option -vlog_std v2001
set_option -num_critical_paths 5
set_option -project_relative_includes 1
set_option -include_path /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/
#device options
set_option -technology Spartan6
set_option -part XC6SLX45T
set_option -package FGG484
set_option -speed_grade -3
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top_tdc"
# mapper_options
set_option -frequency 200
set_option -default_enum_encoding onehot
set_option -write_verilog 0
set_option -write_vhdl 0
# Xilinx Spartan3
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -retiming 0
set_option -update_models_cp 0
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3
set_option -no_sequential_opt 0
# Xilinx Spartan6
set_option -enable_prepacking 1
# NFilter
set_option -popfeed 1
set_option -constprop 1
set_option -createhierarchy 0
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 0
#VIF options
set_option -write_vif 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/syn_tdc.edf"
impl -active "syn"
rrcmd w 0:80000 0000FC81
rrcmd w 0:80004 00000000
rrcmd w 0:80008 00000F02
rrcmd w 0:8000C 00000000
rrcmd w 0:80010 02000063
rrcmd w 0:80014 000007D0
rrcmd w 0:80018 00000003
rrcmd w 0:8001C 00001FEA
rrcmd w 0:8002C 00FF0000
rrcmd w 0:80030 04000000
rrcmd w 0:80038 00000000
rrcmd r 0:80000
rrcmd r 0:80004
rrcmd r 0:80008
rrcmd r 0:8000C
rrcmd r 0:80010
rrcmd r 0:80014
rrcmd r 0:80018
rrcmd r 0:8001C
rrcmd r 0:8002C
rrcmd r 0:80030
rrcmd r 0:80038
rrcmd r 0:80020
rrcmd r 0:80024
rrcmd r 0:80028
rrcmd w 0:80000 0000FC81
rrcmd w 0:80004 00000000
rrcmd w 0:80008 00000F02
rrcmd w 0:8000C 00000000