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FMC TDC 1ns 5cha - Gateware
Commit 14637348 authored by egousiou's avatar egousiou
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I) Use of latest gn4124_core version (with pipelined CSR) 

II) Use of wb_addr_decoder.vhd
III) Added I2C for mezzanine, 1-wire for mezzanine and 1-wire for carrier 
IV) Implemented irq_generator.vhd
V) Use of irq_controller.vhd
VI) clks_rsts_manager.vhd: Changed the internal reset generation; added DFFs to pll_sdi_o, pll_cs_o outputs
VII) General revamping, comments added, units and signals renamed

git-svn-id: http://svn.ohwr.org/fmc-tdc@75 85dfdc96-de2c-444c-878d-45b388be74a9
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hdl/spec/src/ip_cores/gencores_pkg.vhd 0 → 100644
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hdl/spec/src/ip_cores/genram_pkg.vhd 0 → 100644
View file @ 14637348
-------------------------------------------------------------------------------
-- Title : Main package file
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : genram_pkg.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-01-24
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package genram_pkg is
function f_log2_size (A : natural) return natural;
function f_gen_dummy_vec (val : std_logic; size : natural) return std_logic_vector;
type t_generic_ram_init is array (integer range <>, integer range <>) of std_logic;
-- Generic RAM initialized with nothing.
constant c_generic_ram_nothing : t_generic_ram_init(-1 downto 0, -1 downto 0) :=
(others => (others => '0'));
-- Single-port synchronous RAM
component generic_spram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_init_file : string := "";
g_addr_conflict_resolution : string := "read_first") ;
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
bwe_i : in std_logic_vector((g_data_width+7)/8-1 downto 0):= f_gen_dummy_vec('1', (g_data_width+7)/8);
we_i : in std_logic;
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
d_i : in std_logic_vector(g_data_width-1 downto 0) := f_gen_dummy_vec('0', g_data_width);
q_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_dpram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_init_value : t_generic_ram_init := c_generic_ram_nothing;
g_dual_clock : boolean := true);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
wea_i : in std_logic := '0';
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0) := f_gen_dummy_vec('0', g_data_width);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
clkb_i : in std_logic;
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
web_i : in std_logic := '0';
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0) := f_gen_dummy_vec('0', g_data_width);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_async_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
g_with_rd_empty : boolean := true;
g_with_rd_full : boolean := false;
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false;
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
port (
rst_n_i : in std_logic := '1';
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
component generic_sync_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
g_with_empty : boolean := true;
g_with_full : boolean := true;
g_with_almost_empty : boolean := false;
g_with_almost_full : boolean := false;
g_with_count : boolean := false;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
component generic_shiftreg_fifo
generic (
g_data_width : integer;
g_size : integer);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
full_o : out std_logic;
almost_full_o : out std_logic;
q_valid_o : out std_logic
);
end component;
end genram_pkg;
package body genram_pkg is
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
function f_gen_dummy_vec (val : std_logic; size : natural) return std_logic_vector is
variable tmp : std_logic_vector(size-1 downto 0);
begin
for i in 0 to size-1 loop
tmp(i) := val;
end loop; -- i
return tmp;
end f_gen_dummy_vec;
end genram_pkg;
hdl/spec/src/ip_cores/gnum_core/clock_generator_ddr_s2_diff.vhd deleted 100644 → 0
View file @ fea36da1
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: clock_generator_ddr_s2_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: BUFIO2 Based DDR clock generator. Takes in a differential clock
-- and instantiates two sets of 2 BUFIO2s, one for each half bank
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity clock_generator_ddr_s2_diff is
generic (
S : integer := 2; -- Parameter to set the serdes factor
DIFF_TERM : boolean := false) ; -- Enable or disable internal differential termination
port (
clkin_p, clkin_n : in std_logic; -- differential clock input
ioclkap : out std_logic; -- A P ioclock from BUFIO2
ioclkan : out std_logic; -- A N ioclock from BUFIO2
serdesstrobea : out std_logic; -- A serdes strobe from BUFIO2
ioclkbp : out std_logic; -- B P ioclock from BUFIO2 - leave open if not required
ioclkbn : out std_logic; -- B N ioclock from BUFIO2 - leave open if not required
serdesstrobeb : out std_logic; -- B serdes strobe from BUFIO2 - leave open if not required
gclk : out std_logic) ; -- global clock output from BUFIO2
end clock_generator_ddr_s2_diff;
architecture arch_clock_generator_ddr_s2_diff of clock_generator_ddr_s2_diff is
signal clkint : std_logic; --
signal gclk_int : std_logic; --
signal freqgen_in_p : std_logic; --
signal tx_bufio2_x1 : std_logic; --
begin
gclk <= gclk_int;
iob_freqgen_in : IBUFGDS generic map(
DIFF_TERM => DIFF_TERM)
port map (
I => clkin_p,
IB => clkin_n,
O => freqgen_in_p);
bufio2_inst1 : BUFIO2 generic map(
DIVIDE => S, -- The DIVCLK divider divide-by value; default 1
I_INVERT => false, --
DIVIDE_BYPASS => false, --
USE_DOUBLER => true) --
port map (
I => freqgen_in_p, -- Input source clock 0 degrees
IOCLK => ioclkap, -- Output Clock for IO
DIVCLK => tx_bufio2_x1, -- Output Divided Clock
SERDESSTROBE => serdesstrobea) ; -- Output SERDES strobe (Clock Enable)
bufio2_inst2 : BUFIO2 generic map(
I_INVERT => true, --
DIVIDE_BYPASS => false, --
USE_DOUBLER => false) --
port map (
I => freqgen_in_p, -- N_clk input from IDELAY
IOCLK => ioclkan, -- Output Clock
DIVCLK => open, -- Output Divided Clock
SERDESSTROBE => open) ; -- Output SERDES strobe (Clock Enable)
bufio2_inst3 : BUFIO2 generic map(
DIVIDE => S, -- The DIVCLK divider divide-by value; default 1
I_INVERT => false, --
DIVIDE_BYPASS => false, --
USE_DOUBLER => true) --
port map (
I => freqgen_in_p, -- Input source clock 0 degrees
IOCLK => ioclkbp, -- Output Clock for IO
DIVCLK => open, -- Output Divided Clock
SERDESSTROBE => serdesstrobeb) ; -- Output SERDES strobe (Clock Enable)
bufio2_inst4 : BUFIO2 generic map(
I_INVERT => true, --
DIVIDE_BYPASS => false, --
USE_DOUBLER => false) --
port map (
I => freqgen_in_p, -- N_clk input from IDELAY
IOCLK => ioclkbn, -- Output Clock
DIVCLK => open, -- Output Divided Clock
SERDESSTROBE => open) ; -- Output SERDES strobe (Clock Enable)
bufg_tx : BUFG port map (I => tx_bufio2_x1, O => gclk_int);
end arch_clock_generator_ddr_s2_diff;
hdl/spec/src/ip_cores/gnum_core/dma_controller.vhd
View file @ 14637348
......@@ -19,6 +19,18 @@
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: 30-09-2010 (mcattin) Add status, error and abort
--------------------------------------------------------------------------------
......@@ -355,6 +367,7 @@ begin
if (unsigned(dma_len_reg(31 downto 2)) = 0) then
-- Requesting a DMA of 0 word length gives a error
dma_error_irq <= '1';
dma_ctrl_current_state <= DMA_ERROR;
else
-- Start the DMA if the length is not 0
......
hdl/spec/src/ip_cores/gnum_core/dummy_ctrl_regs.vhd deleted 100644 → 0
View file @ fea36da1
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Dummy control registers
---------------------------------------------------------------------------------------
-- File : ../../GN4124_core/hdl/gn4124core/design/rtl/dummy_ctrl_regs.vhd
-- Author : auto-generated by wbgen2 from ../../GN4124_core/hdl/gn4124core/design/wb_gen/dummy_ctrl_regs_wb_slave.wb
-- Created : Wed Nov 10 14:40:05 2010
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ../../GN4124_core/hdl/gn4124core/design/wb_gen/dummy_ctrl_regs_wb_slave.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dummy_ctrl_regs_wb_slave is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- Port for std_logic_vector field: 'Dummy register 1' in reg: 'DUMMY_1'
dummy_reg_1_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Dummy register 2' in reg: 'DUMMY_2'
dummy_reg_2_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Dummy register 3' in reg: 'DUMMY_3'
dummy_reg_3_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Dummy register for LED control' in reg: 'DUMMY_LED'
dummy_reg_led_o : out std_logic_vector(31 downto 0)
);
end dummy_ctrl_regs_wb_slave;
architecture syn of dummy_ctrl_regs_wb_slave is
signal dummy_reg_1_int : std_logic_vector(31 downto 0);
signal dummy_reg_2_int : std_logic_vector(31 downto 0);
signal dummy_reg_3_int : std_logic_vector(31 downto 0);
signal dummy_reg_led_int : std_logic_vector(31 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal bus_clock_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_data_i;
bwsel_reg <= wb_sel_i;
bus_clock_int <= wb_clk_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (bus_clock_int, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
dummy_reg_1_int <= "00000000000000000000000000000000";
dummy_reg_2_int <= "00000000000000000000000000000000";
dummy_reg_3_int <= "00000000000000000000000000000000";
dummy_reg_led_int <= "00000000000000000000000000000000";
elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
dummy_reg_1_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= dummy_reg_1_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
dummy_reg_2_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= dummy_reg_2_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
dummy_reg_3_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= dummy_reg_3_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
dummy_reg_led_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= dummy_reg_led_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_data_o <= rddata_reg;
-- Dummy register 1
dummy_reg_1_o <= dummy_reg_1_int;
-- Dummy register 2
dummy_reg_2_o <= dummy_reg_2_int;
-- Dummy register 3
dummy_reg_3_o <= dummy_reg_3_int;
-- Dummy register for LED control
dummy_reg_led_o <= dummy_reg_led_int;
rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/spec/src/ip_cores/gnum_core/genram_pkg.vhd 0 → 100644
View file @ 14637348
-------------------------------------------------------------------------------
-- Title : Main package file
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : genram_pkg.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2011-05-11
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package genram_pkg is
function f_log2_size (A : natural) return natural;
-- Single-port synchronous RAM
component generic_spram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_init_file : string := "";
g_addr_conflict_resolution : string := "read_first") ;
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
bwe_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
we_i : in std_logic;
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
d_i : in std_logic_vector(g_data_width-1 downto 0);
q_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_dpram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_dual_clock : boolean := true);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector(g_data_width/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
clkb_i : in std_logic;
bweb_i : in std_logic_vector(g_data_width/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_async_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
g_with_rd_empty : boolean := true;
g_with_rd_full : boolean := false;
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false;
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
port (
rst_n_i : in std_logic := '1';
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
component generic_sync_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
g_with_empty : boolean := true;
g_with_full : boolean := true;
g_with_almost_empty : boolean := false;
g_with_almost_full : boolean := false;
g_with_count : boolean := false;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
end genram_pkg;
package body genram_pkg is
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
end genram_pkg;
\ No newline at end of file
hdl/spec/src/ip_cores/gnum_core/gn4124_core_pkg_s6.vhd deleted 100644 → 0
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hdl/spec/src/ip_cores/gnum_core/l2p_arbiter.vhd
View file @ 14637348
......@@ -18,6 +18,18 @@
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- last changes: 23-09-2010 (mcattin) Add FF on data path and
-- change valid request logic
......
hdl/spec/src/ip_cores/gnum_core/l2p_dma_master.vhd
View file @ 14637348
......@@ -16,10 +16,23 @@
-- description: Provides a pipelined Wishbone interface to performs DMA
-- transfers from local application to PCI express host.
--
-- dependencies: Xilinx FIFOs (fifo_32x512.xco)
-- dependencies: general-cores library (genrams package)
--
--------------------------------------------------------------------------------
-- last changes: see svn log
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: 11-07-2011 (mcattin) Replaced Xilinx Coregen FIFOs with genrams
-- library cores from ohwr.org
--------------------------------------------------------------------------------
-- TODO: - byte enable support
--------------------------------------------------------------------------------
......@@ -28,6 +41,7 @@ library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
use work.genram_pkg.all;
entity l2p_dma_master is
......@@ -95,9 +109,9 @@ architecture behaviour of l2p_dma_master is
-- c_L2P_MAX_PAYLOAD is the maximum size (in 32-bit words) of the payload of a packet.
-- Allowed c_L2P_MAX_PAYLOAD values are: 32, 64, 128, 256, 512, 1024.
-- This constant must be set according to the GN4124 and motherboard chipset capabilities.
constant c_L2P_MAX_PAYLOAD : unsigned(10 downto 0) := to_unsigned(32, 11); -- in 32-bit words
constant c_ADDR_FIFO_FULL_THRES : std_logic_vector(8 downto 0) := std_logic_vector(to_unsigned(500, 9));
constant c_DATA_FIFO_FULL_THRES : std_logic_vector(8 downto 0) := std_logic_vector(to_unsigned(500, 9));
constant c_L2P_MAX_PAYLOAD : unsigned(10 downto 0) := to_unsigned(32, 11); -- in 32-bit words
constant c_ADDR_FIFO_FULL_THRES : integer := 500;
constant c_DATA_FIFO_FULL_THRES : integer := 500;
-----------------------------------------------------------------------------
-- Signals declaration
......@@ -108,7 +122,7 @@ architecture behaviour of l2p_dma_master is
signal dma_length_cnt : unsigned(29 downto 0);
-- Sync FIFOs
signal fifo_rst : std_logic;
signal fifo_rst_n : std_logic;
signal addr_fifo_rd : std_logic;
signal addr_fifo_valid : std_logic;
signal addr_fifo_empty : std_logic;
......@@ -158,11 +172,11 @@ begin
------------------------------------------------------------------------------
-- Creates an active high reset for fifos regardless of c_RST_ACTIVE value
gen_fifo_rst_n : if c_RST_ACTIVE = '0' generate
fifo_rst <= not(rst_n_i);
fifo_rst_n <= rst_n_i;
end generate;
gen_fifo_rst : if c_RST_ACTIVE = '1' generate
fifo_rst <= rst_n_i;
fifo_rst_n <= not(rst_n_i);
end generate;
------------------------------------------------------------------------------
......@@ -359,7 +373,7 @@ begin
end if;
else
-- arbiter or GN4124 not ready to receive a new packet
ldm_arb_valid_o <= '0';
ldm_arb_valid_o <= '0';
end if;
when L2P_ADDR_H =>
......@@ -486,37 +500,91 @@ begin
------------------------------------------------------------------------------
-- FIFOs for transition between GN4124 core and wishbone clock domain
------------------------------------------------------------------------------
cmp_addr_fifo : fifo_32x512
cmp_addr_fifo : generic_async_fifo
generic map (
g_data_width => 32,
g_size => 512,
g_show_ahead => false,
g_with_rd_empty => true,
g_with_rd_full => false,
g_with_rd_almost_empty => false,
g_with_rd_almost_full => false,
g_with_rd_count => false,
g_with_wr_empty => false,
g_with_wr_full => false,
g_with_wr_almost_empty => false,
g_with_wr_almost_full => true,
g_with_wr_count => false,
g_almost_empty_threshold => 0,
g_almost_full_threshold => c_ADDR_FIFO_FULL_THRES)
port map (
rst => fifo_rst,
wr_clk => clk_i,
rd_clk => l2p_dma_clk_i,
din => addr_fifo_din,
wr_en => addr_fifo_wr,
rd_en => addr_fifo_rd,
prog_full_thresh_assert => c_ADDR_FIFO_FULL_THRES,
prog_full_thresh_negate => c_ADDR_FIFO_FULL_THRES,
dout => addr_fifo_dout,
full => open,
empty => addr_fifo_empty,
valid => addr_fifo_valid,
prog_full => addr_fifo_full);
cmp_data_fifo : fifo_32x512
rst_n_i => fifo_rst_n,
clk_wr_i => clk_i,
d_i => addr_fifo_din,
we_i => addr_fifo_wr,
wr_empty_o => open,
wr_full_o => open,
wr_almost_empty_o => open,
wr_almost_full_o => addr_fifo_full,
wr_count_o => open,
clk_rd_i => l2p_dma_clk_i,
q_o => addr_fifo_dout,
rd_i => addr_fifo_rd,
rd_empty_o => addr_fifo_empty,
rd_full_o => open,
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => open);
p_gen_addr_fifo_valid : process(l2p_dma_clk_i)
begin
if rising_edge(l2p_dma_clk_i) then
addr_fifo_valid <= addr_fifo_rd and (not addr_fifo_empty);
end if;
end process;
cmp_data_fifo : generic_async_fifo
generic map (
g_data_width => 32,
g_size => 512,
g_show_ahead => false,
g_with_rd_empty => true,
g_with_rd_full => false,
g_with_rd_almost_empty => false,
g_with_rd_almost_full => false,
g_with_rd_count => false,
g_with_wr_empty => false,
g_with_wr_full => false,
g_with_wr_almost_empty => false,
g_with_wr_almost_full => true,
g_with_wr_count => false,
g_almost_empty_threshold => 0,
g_almost_full_threshold => c_DATA_FIFO_FULL_THRES)
port map (
rst => fifo_rst,
wr_clk => l2p_dma_clk_i,
rd_clk => clk_i,
din => data_fifo_din,
wr_en => data_fifo_wr,
rd_en => data_fifo_rd,
prog_full_thresh_assert => c_DATA_FIFO_FULL_THRES,
prog_full_thresh_negate => c_DATA_FIFO_FULL_THRES,
dout => data_fifo_dout,
full => open,
empty => data_fifo_empty,
valid => data_fifo_valid,
prog_full => data_fifo_full);
rst_n_i => fifo_rst_n,
clk_wr_i => l2p_dma_clk_i,
d_i => data_fifo_din,
we_i => data_fifo_wr,
wr_empty_o => open,
wr_full_o => open,
wr_almost_empty_o => open,
wr_almost_full_o => data_fifo_full,
wr_count_o => open,
clk_rd_i => clk_i,
q_o => data_fifo_dout,
rd_i => data_fifo_rd,
rd_empty_o => data_fifo_empty,
rd_full_o => open,
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => open);
p_gen_data_fifo_valid : process(clk_i)
begin
if rising_edge(clk_i) then
data_fifo_valid <= data_fifo_rd and (not data_fifo_empty);
end if;
end process;
data_fifo_din <= l2p_dma_dat_i;
-- latch data when receiving ack and the cycle has been initiated by this master
......
hdl/spec/src/ip_cores/gnum_core/l2p_ser.vhd
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--------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core --
--------------------------------------------------------------------------------
--
-- unit name: L2P serializer (l2p_ser_s6.vhd)
--
-- authors: Simon Deprez (simon.deprez@cern.ch)
-- Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 31-08-2010
--
-- version: 1.0
--
-- description: Generates the DDR L2P bus from SDR that is synchronous to the
-- core clock. Spartan6 FPGAs version.
--
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- last changes: 23-09-2010 (mcattin) Always active high reset for FFs.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity l2p_ser is
port
(
---------------------------------------------------------
-- Reset and clock
rst_n_i : in std_logic;
sys_clk_i : in std_logic;
io_clk_i : in std_logic;
serdes_strobe_i : in std_logic;
---------------------------------------------------------
-- L2P SDR inputs
l2p_valid_i : in std_logic;
l2p_dframe_i : in std_logic;
l2p_data_i : in std_logic_vector(31 downto 0);
---------------------------------------------------------
-- L2P DDR outputs
l2p_clk_p_o : out std_logic;
l2p_clk_n_o : out std_logic;
l2p_valid_o : out std_logic;
l2p_dframe_o : out std_logic;
l2p_data_o : out std_logic_vector(15 downto 0)
);
end l2p_ser;
architecture rtl of l2p_ser is
-----------------------------------------------------------------------------
-- Components declaration
-----------------------------------------------------------------------------
component serdes_n_to_1_s2_se
generic (
S : integer := 2; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
txioclk : in std_logic; -- IO Clock network
txserdesstrobe : in std_logic; -- Parallel data capture strobe
reset : in std_logic; -- Reset
gclk : in std_logic; -- Global clock
datain : in std_logic_vector((D*S)-1 downto 0); -- Data for output
dataout : out std_logic_vector(D-1 downto 0)) ; -- output
end component serdes_n_to_1_s2_se;
component serdes_n_to_1_s2_diff
generic (
S : integer := 2; -- Parameter to set the serdes factor 1..8
D : integer := 1) ; -- Set the number of inputs and outputs
port (
txioclk : in std_logic; -- IO Clock network
txserdesstrobe : in std_logic; -- Parallel data capture strobe
reset : in std_logic; -- Reset
gclk : in std_logic; -- Global clock
datain : in std_logic_vector((D*S)-1 downto 0); -- Data for output
dataout_p : out std_logic_vector(D-1 downto 0); -- output
dataout_n : out std_logic_vector(D-1 downto 0)) ; -- output
end component serdes_n_to_1_s2_diff;
-----------------------------------------------------------------------------
-- Comnstants declaration
-----------------------------------------------------------------------------
constant S : integer := 2; -- Set the serdes factor to 2
constant D : integer := 16; -- Set the number of outputs
constant c_TX_CLK : std_logic_vector(1 downto 0) := "01";
-----------------------------------------------------------------------------
-- Signals declaration
-----------------------------------------------------------------------------
-- Serdes reset
signal rst : std_logic;
-- SDR signals
signal l2p_dframe_t : std_logic_vector(1 downto 0);
signal l2p_valid_t : std_logic_vector(1 downto 0);
signal l2p_dframe_v : std_logic_vector(0 downto 0);
signal l2p_valid_v : std_logic_vector(0 downto 0);
signal l2p_clk_p_v : std_logic_vector(0 downto 0);
signal l2p_clk_n_v : std_logic_vector(0 downto 0);
begin
------------------------------------------------------------------------------
-- Active high reset for DDR FF
------------------------------------------------------------------------------
gen_fifo_rst_n : if c_RST_ACTIVE = '0' generate
rst <= not(rst_n_i);
end generate;
gen_fifo_rst : if c_RST_ACTIVE = '1' generate
rst <= rst_n_i;
end generate;
------------------------------------------------------------------------------
-- Instantiate serialiser to generate forwarded clock
------------------------------------------------------------------------------
cmp_clk_out : serdes_n_to_1_s2_diff
generic map(
S => S,
D => 1)
port map (
txioclk => io_clk_i,
txserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
reset => rst,
datain => c_TX_CLK, -- Transmit a constant to make the clock
dataout_p => l2p_clk_p_v,
dataout_n => l2p_clk_n_v);
-- Type conversion, std_logic_vector to std_logic
l2p_clk_p_o <= l2p_clk_p_v(0);
l2p_clk_n_o <= l2p_clk_n_v(0);
------------------------------------------------------------------------------
-- Instantiate serialisers for output data lines
------------------------------------------------------------------------------
cmp_data_out : serdes_n_to_1_s2_se
generic map(
S => S,
D => D)
port map (
txioclk => io_clk_i,
txserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
reset => rst,
datain => l2p_data_i,
dataout => l2p_data_o);
------------------------------------------------------------------------------
-- Instantiate serialisers for dframe
------------------------------------------------------------------------------
cmp_dframe_out : serdes_n_to_1_s2_se
generic map(
S => S,
D => 1)
port map (
txioclk => io_clk_i,
txserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
reset => rst,
datain => l2p_dframe_t,
dataout => l2p_dframe_v);
-- Serialize two times the same value
l2p_dframe_t <= l2p_dframe_i & l2p_dframe_i;
-- Type conversion, std_logic_vector to std_logic
l2p_dframe_o <= l2p_dframe_v(0);
------------------------------------------------------------------------------
-- Instantiate serialisers for valid
------------------------------------------------------------------------------
cmp_valid_out : serdes_n_to_1_s2_se
generic map(
S => S,
D => 1)
port map (
txioclk => io_clk_i,
txserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
reset => rst,
datain => l2p_valid_t,
dataout => l2p_valid_v);
-- Serialize two times the same value
l2p_valid_t <= l2p_valid_i & l2p_valid_i;
-- Type conversion, std_logic_vector to std_logic
l2p_valid_o <= l2p_valid_v(0);
end rtl;
hdl/spec/src/ip_cores/gnum_core/p2l_decode32.vhd
View file @ 14637348
......@@ -19,6 +19,18 @@
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: 27-09-2010 (mcattin) Rewrite a part of the decoder logic
--------------------------------------------------------------------------------
......
hdl/spec/src/ip_cores/gnum_core/p2l_des.vhd
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--------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core --
--------------------------------------------------------------------------------
--
-- unit name: P2L deserializer (p2l_des_s6.vhd)
--
-- authors: Simon Deprez (simon.deprez@cern.ch)
-- Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 31-08-2010
--
-- version: 1.0
--
-- description: Takes the DDR P2L bus and converts to SDR that is synchronous
-- to the core clock. Spartan6 FPGAs version.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- last changes: 23-09-2010 (mcattin) Always active high reset for FFs.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity p2l_des is
port
(
---------------------------------------------------------
-- Reset and clock
rst_n_i : in std_logic;
sys_clk_i : in std_logic;
io_clk_i : in std_logic;
serdes_strobe_i : in std_logic;
---------------------------------------------------------
-- P2L clock domain (DDR)
--
-- P2L inputs
p2l_valid_i : in std_logic;
p2l_dframe_i : in std_logic;
p2l_data_i : in std_logic_vector(15 downto 0);
---------------------------------------------------------
-- Core clock domain (SDR)
--
-- Deserialized output
p2l_valid_o : out std_logic;
p2l_dframe_o : out std_logic;
p2l_data_o : out std_logic_vector(31 downto 0)
);
end p2l_des;
architecture rtl of p2l_des is
-----------------------------------------------------------------------------
-- Components declaration
-----------------------------------------------------------------------------
component serdes_1_to_n_data_s2_se
generic (
USE_PD : boolean := false; -- Parameter to set generation of phase detector logic
S : integer := 2; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
use_phase_detector : in std_logic; -- Set generation of phase detector logic
datain : in std_logic_vector(D-1 downto 0); -- Input from se receiver pin
rxioclk : in std_logic; -- IO Clock network
rxserdesstrobe : in std_logic; -- Parallel data capture strobe
reset : in std_logic; -- Reset line
gclk : in std_logic; -- Global clock
bitslip : in std_logic; -- Bitslip control line
debug_in : in std_logic_vector(1 downto 0); -- input debug data
data_out : out std_logic_vector((D*S)-1 downto 0); -- Output data
-- Debug bus, 2D+6 = 2 lines per input (from mux and ce) + 7, leave nc if debug not required
debug : out std_logic_vector((2*D)+6 downto 0)) ;
end component serdes_1_to_n_data_s2_se;
-----------------------------------------------------------------------------
-- Comnstants declaration
-----------------------------------------------------------------------------
constant S : integer := 2; -- Set the serdes factor to 2
constant D : integer := 16; -- Set the number of inputs and outputs
-----------------------------------------------------------------------------
-- Signals declaration
-----------------------------------------------------------------------------
-- Serdes reset
signal rst : std_logic;
-- SDR signals
signal p2l_valid_v : std_logic_vector(0 downto 0);
signal p2l_dframe_v : std_logic_vector(0 downto 0);
signal p2l_valid_t : std_logic_vector(1 downto 0);
signal p2l_dframe_t : std_logic_vector(1 downto 0);
signal p2l_data_t : std_logic_vector(p2l_data_o'range);
signal p2l_valid_t2 : std_logic;
signal p2l_dframe_t2 : std_logic;
signal p2l_data_t2 : std_logic_vector(p2l_data_o'range);
signal p2l_data_bitslip : std_logic_vector(1 downto 0);
signal p2l_data_bitslip_p : std_logic;
--signal p2l_ctrl_v : std_logic_vector(1 downto 0);
--signal p2l_ctrl_t : std_logic_vector(3 downto 0);
begin
------------------------------------------------------------------------------
-- Active high reset
------------------------------------------------------------------------------
gen_rst_n : if c_RST_ACTIVE = '0' generate
rst <= not(rst_n_i);
end generate;
gen_rst : if c_RST_ACTIVE = '1' generate
rst <= rst_n_i;
end generate;
------------------------------------------------------------------------------
-- data input bit slip
------------------------------------------------------------------------------
p_din_bitslip : process (sys_clk_i, rst_n_i)
begin
if rst_n_i = c_RST_ACTIVE then
p2l_data_bitslip <= (others => '0');
elsif rising_edge(sys_clk_i) then
p2l_data_bitslip <= p2l_data_bitslip(0) & '1';
end if;
end process p_din_bitslip;
p2l_data_bitslip_p <= p2l_data_bitslip(0) and not(p2l_data_bitslip(1));
------------------------------------------------------------------------------
-- data inputs
------------------------------------------------------------------------------
cmp_data_in : serdes_1_to_n_data_s2_se
generic map(
USE_PD => false,
S => S,
D => D)
port map (
use_phase_detector => '0', -- '1' enables the phase detector logic
datain => p2l_data_i,
rxioclk => io_clk_i,
rxserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
bitslip => '0', --p2l_data_bitslip_p,
reset => rst,
data_out => p2l_data_t,
debug_in => "00",
debug => open);
------------------------------------------------------------------------------
-- dframe input
------------------------------------------------------------------------------
cmp_dframe_in : serdes_1_to_n_data_s2_se
generic map(
USE_PD => false,
S => S,
D => 1)
port map (
use_phase_detector => '0', -- '1' enables the phase detector logic
datain => p2l_dframe_v,
rxioclk => io_clk_i,
rxserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
bitslip => '0',
reset => rst,
data_out => p2l_dframe_t,
debug_in => "00",
debug => open);
-- Type conversion, std_logic to std_logic_vector
p2l_dframe_v(0) <= p2l_dframe_i;
------------------------------------------------------------------------------
-- valid input
------------------------------------------------------------------------------
cmp_valid_in : serdes_1_to_n_data_s2_se
generic map(
USE_PD => false,
S => S,
D => 1)
port map (
use_phase_detector => '0', -- '1' enables the phase detector logic
datain => p2l_valid_v,
rxioclk => io_clk_i,
rxserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
bitslip => '0',
reset => rst,
data_out => p2l_valid_t,
debug_in => "00",
debug => open);
-- Type conversion, std_logic to std_logic_vector
p2l_valid_v(0) <= p2l_valid_i;
p_in_sys_sync : process (sys_clk_i, rst_n_i)
begin
if rst_n_i = c_RST_ACTIVE then
p2l_data_o <= (others => '0');
p2l_dframe_o <= '0';
p2l_valid_o <= '0';
p2l_data_t2 <= (others => '0');
p2l_dframe_t2 <= '0';
p2l_valid_t2 <= '0';
elsif rising_edge(sys_clk_i) then
p2l_data_t2 <= p2l_data_t;
p2l_dframe_t2 <= p2l_dframe_t(0);
p2l_valid_t2 <= p2l_valid_t(0);
p2l_data_o <= p2l_data_t2;
p2l_dframe_o <= p2l_dframe_t2;
p2l_valid_o <= p2l_valid_t2;
end if;
end process p_in_sys_sync;
end rtl;
hdl/spec/src/ip_cores/gnum_core/p2l_dma_master.vhd
View file @ 14637348
......@@ -17,10 +17,23 @@
-- transfers from PCI express host to local application.
-- This entity is also used to catch the next item in chained DMA.
--
-- dependencies:
-- dependencies: general-cores library (genrams package)
--
--------------------------------------------------------------------------------
-- last changes: see svn log
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: 11-07-2011 (mcattin) Replaced Xilinx Coregen FIFOs with genrams
-- library cores from ohwr.org
--------------------------------------------------------------------------------
-- TODO: - byte enable support.
--------------------------------------------------------------------------------
......@@ -29,6 +42,7 @@ library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
use work.genram_pkg.all;
entity p2l_dma_master is
......@@ -123,8 +137,8 @@ architecture behaviour of p2l_dma_master is
-- c_MAX_READ_REQ_SIZE is the maximum size (in 32-bit words) of the payload of a packet.
-- Allowed c_MAX_READ_REQ_SIZE values are: 32, 64, 128, 256, 512, 1024.
-- This constant must be set according to the GN4124 and motherboard chipset capabilities.
constant c_MAX_READ_REQ_SIZE : unsigned(10 downto 0) := to_unsigned(1024, 11);
constant c_TO_WB_FIFO_FULL_THRES : std_logic_vector(8 downto 0) := std_logic_vector(to_unsigned(500, 9));
constant c_MAX_READ_REQ_SIZE : unsigned(10 downto 0) := to_unsigned(1024, 11);
constant c_TO_WB_FIFO_FULL_THRES : integer := 500;
-----------------------------------------------------------------------------
-- Signals declaration
......@@ -146,12 +160,13 @@ architecture behaviour of p2l_dma_master is
signal l2p_64b_address : std_logic;
signal s_l2p_header : std_logic_vector(31 downto 0);
signal l2p_last_packet : std_logic;
signal l2p_lbe_header : std_logic_vector(3 downto 0);
-- Target address counter
signal target_addr_cnt : unsigned(29 downto 0);
-- sync fifo
signal fifo_rst : std_logic;
signal fifo_rst_n : std_logic;
signal to_wb_fifo_empty : std_logic;
signal to_wb_fifo_full : std_logic;
......@@ -182,11 +197,11 @@ begin
------------------------------------------------------------------------------
-- Creates an active high reset for fifos regardless of c_RST_ACTIVE value
gen_fifo_rst_n : if c_RST_ACTIVE = '0' generate
fifo_rst <= not(rst_n_i);
fifo_rst_n <= rst_n_i;
end generate;
gen_fifo_rst : if c_RST_ACTIVE = '1' generate
fifo_rst <= rst_n_i;
fifo_rst_n <= not(rst_n_i);
end generate;
-- Errors to DMA controller
......@@ -253,10 +268,13 @@ begin
end if;
end process p_read_req;
-- Last Byte Enable must be "0000" when length = 1
l2p_lbe_header <= "0000" when l2p_len_header = 1 else "1111";
s_l2p_header <= "000" --> Traffic Class
& '0' --> Snoop
& "000" & l2p_64b_address --> Packet type = read request (32 or 64 bits)
& "1111" --> LBE (Last Byte Enable)
& l2p_lbe_header --> LBE (Last Byte Enable)
& "1111" --> FBE (First Byte Enable)
& "000" --> Reserved
& '0' --> VC (Virtual Channel)
......@@ -404,7 +422,8 @@ begin
p2l_data_cnt <= '0' & l2p_len_header;
end if;
elsif (p2l_dma_current_state = P2L_WAIT_READ_COMPLETION
and pd_pdm_data_valid_i = '1') then
and pd_pdm_data_valid_i = '1'
and pd_pdm_master_cpld_i = '1') then
-- decrement number of data to be received
p2l_data_cnt <= p2l_data_cnt - 1;
end if;
......@@ -490,21 +509,48 @@ begin
------------------------------------------------------------------------------
-- FIFOs for transition between GN4124 core and wishbone clock domain
------------------------------------------------------------------------------
cmp_to_wb_fifo : fifo_64x512
cmp_to_wb_fifo : generic_async_fifo
generic map (
g_data_width => 64,
g_size => 512,
g_show_ahead => false,
g_with_rd_empty => true,
g_with_rd_full => false,
g_with_rd_almost_empty => false,
g_with_rd_almost_full => false,
g_with_rd_count => false,
g_with_wr_empty => false,
g_with_wr_full => false,
g_with_wr_almost_empty => false,
g_with_wr_almost_full => true,
g_with_wr_count => false,
g_almost_empty_threshold => 0,
g_almost_full_threshold => c_TO_WB_FIFO_FULL_THRES)
port map (
rst => fifo_rst,
wr_clk => clk_i,
rd_clk => p2l_dma_clk_i,
din => to_wb_fifo_din,
wr_en => to_wb_fifo_wr,
rd_en => to_wb_fifo_rd,
prog_full_thresh_assert => c_TO_WB_FIFO_FULL_THRES,
prog_full_thresh_negate => c_TO_WB_FIFO_FULL_THRES,
dout => to_wb_fifo_dout,
full => open,
empty => to_wb_fifo_empty,
valid => to_wb_fifo_valid,
prog_full => to_wb_fifo_full);
rst_n_i => fifo_rst_n,
clk_wr_i => clk_i,
d_i => to_wb_fifo_din,
we_i => to_wb_fifo_wr,
wr_empty_o => open,
wr_full_o => open,
wr_almost_empty_o => open,
wr_almost_full_o => to_wb_fifo_full,
wr_count_o => open,
clk_rd_i => p2l_dma_clk_i,
q_o => to_wb_fifo_dout,
rd_i => to_wb_fifo_rd,
rd_empty_o => to_wb_fifo_empty,
rd_full_o => open,
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => open);
p_gen_fifo_valid : process(p2l_dma_clk_i)
begin
if rising_edge(p2l_dma_clk_i) then
to_wb_fifo_valid <= to_wb_fifo_rd and (not to_wb_fifo_empty);
end if;
end process;
-- pause transfer from GN4124 if fifo is (almost) full
p2l_rdy_o <= not(to_wb_fifo_full);
......
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files= ["i2c_master_bit_ctrl.vhd",
"i2c_master_byte_ctrl.vhd",
"i2c_master_top.vhd",
"wb_i2c_master.vhd",
"xwb_i2c_master.vhd"];
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library ieee;
use ieee.std_logic_1164.all;
use work.wishbone_pkg.all;
entity xwb_i2c_master is
generic(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
scl_pad_i : in std_logic; -- i2c clock line input
scl_pad_o : out std_logic; -- i2c clock line output
scl_padoen_o : out std_logic; -- i2c clock line output enable, active low
sda_pad_i : in std_logic; -- i2c data line input
sda_pad_o : out std_logic; -- i2c data line output
sda_padoen_o : out std_logic -- i2c data line output enable, active low
);
end xwb_i2c_master;
architecture rtl of xwb_i2c_master is
component wb_i2c_master
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
scl_pad_i : in std_logic;
scl_pad_o : out std_logic;
scl_padoen_o : out std_logic;
sda_pad_i : in std_logic;
sda_pad_o : out std_logic;
sda_padoen_o : out std_logic);
end component;
begin -- rtl
U_Wrapped_I2C : wb_i2c_master
generic map (
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
wb_adr_i => slave_i.adr(4 downto 0),
wb_dat_i => slave_i.dat,
wb_dat_o => slave_o.dat,
wb_sel_i => slave_i.sel,
wb_stb_i => slave_i.stb,
wb_cyc_i => slave_i.cyc,
wb_we_i => slave_i.we,
wb_ack_o => slave_o.ack,
wb_int_o => slave_o.int,
wb_stall_o => slave_o.stall,
scl_pad_i => scl_pad_i,
scl_pad_o => scl_pad_o,
scl_padoen_o => scl_padoen_o,
sda_pad_i => sda_pad_i,
sda_pad_o => sda_pad_o,
sda_padoen_o => sda_padoen_o);
end rtl;
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files = ["wb_onewire_master.vhd",
"xwb_onewire_master.vhd",
"sockit_owm.v"];
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