Commit 17667554 authored by penacoba's avatar penacoba

Most of the comments from the code review have been integrated


git-svn-id: http://svn.ohwr.org/fmc-tdc@72 85dfdc96-de2c-444c-878d-45b388be74a9
parent a86d35bc
......@@ -46,12 +46,14 @@ entity acam_databus_interface is
-- signals internal to the chip: interface with other modules
acam_ef1_o : out std_logic;
acam_ef1_meta_o : out std_logic;
acam_ef2_o : out std_logic;
acam_ef2_meta_o : out std_logic;
acam_lf1_o : out std_logic;
acam_lf2_o : out std_logic;
-- wishbone slave signals internal to the chip: interface with other modules
clk_i : in std_logic;
clk : in std_logic;
reset_i : in std_logic;
adr_i : in std_logic_vector(g_span-1 downto 0);
......@@ -70,16 +72,15 @@ end acam_databus_interface;
----------------------------------------------------------------------------------------------------
architecture rtl of acam_databus_interface is
type t_acam_interface is (idle, rd_start, read, rd_ack, wr_start, write, wr_ack);
type t_acam_interface is (IDLE, RD_START, RD_FETCH, RD_ACK, WR_START, WR_PUSH, WR_ACK);
signal acam_data_st, nxt_acam_data_st : t_acam_interface;
signal ef1 : std_logic;
signal ef2 : std_logic;
signal lf1 : std_logic;
signal lf2 : std_logic;
signal ef1_r : std_logic_vector(1 downto 0);
signal ef2_r : std_logic_vector(1 downto 0);
signal lf1_r : std_logic_vector(1 downto 0);
signal lf2_r : std_logic_vector(1 downto 0);
signal clk : std_logic;
signal reset : std_logic;
signal adr : std_logic_vector(g_span-1 downto 0);
signal cyc : std_logic;
......@@ -105,7 +106,7 @@ begin
databus_access_seq_fsm: process
begin
if reset ='1' then
acam_data_st <= idle;
acam_data_st <= IDLE;
else
acam_data_st <= nxt_acam_data_st;
end if;
......@@ -115,7 +116,7 @@ begin
databus_access_comb_fsm: process(acam_data_st, stb, cyc, we)
begin
case acam_data_st is
when idle =>
when IDLE =>
ack <= '0';
cs_extend <= '0';
rd_extend <= '0';
......@@ -123,67 +124,67 @@ begin
wr_remove <= '0';
if stb ='1' and cyc ='1' then
if we = '1' then
nxt_acam_data_st <= wr_start;
nxt_acam_data_st <= WR_START;
else
nxt_acam_data_st <= rd_start;
nxt_acam_data_st <= RD_START;
end if;
else
nxt_acam_data_st <= idle;
nxt_acam_data_st <= IDLE;
end if;
when rd_start =>
when RD_START =>
ack <= '0';
cs_extend <= '1';
rd_extend <= '1';
wr_extend <= '0';
wr_remove <= '0';
nxt_acam_data_st <= read;
nxt_acam_data_st <= RD_FETCH;
when read =>
when RD_FETCH =>
ack <= '0';
cs_extend <= '1';
rd_extend <= '1';
wr_extend <= '0';
wr_remove <= '0';
nxt_acam_data_st <= rd_ack;
nxt_acam_data_st <= RD_ACK;
when rd_ack =>
when RD_ACK =>
ack <= '1';
cs_extend <= '0';
rd_extend <= '0';
wr_extend <= '0';
wr_remove <= '0';
nxt_acam_data_st <= idle;
nxt_acam_data_st <= IDLE;
when wr_start =>
when WR_START =>
ack <= '0';
cs_extend <= '1';
rd_extend <= '0';
wr_extend <= '1';
wr_remove <= '0';
nxt_acam_data_st <= write;
nxt_acam_data_st <= WR_PUSH;
when write =>
when WR_PUSH =>
ack <= '0';
cs_extend <= '0';
rd_extend <= '0';
wr_extend <= '0';
wr_remove <= '1';
nxt_acam_data_st <= wr_ack;
nxt_acam_data_st <= WR_ACK;
when wr_ack =>
when WR_ACK =>
ack <= '1';
cs_extend <= '0';
rd_extend <= '0';
wr_extend <= '0';
wr_remove <= '0';
nxt_acam_data_st <= idle;
nxt_acam_data_st <= IDLE;
when others =>
ack <= '0';
......@@ -192,7 +193,7 @@ begin
wr_extend <= '0';
wr_remove <= '0';
nxt_acam_data_st <= idle;
nxt_acam_data_st <= IDLE;
end case;
end process;
......@@ -205,7 +206,6 @@ begin
-- Acam specs
-- inputs from other blocks
clk <= clk_i;
reset <= reset_i;
adr <= adr_i;
......@@ -215,27 +215,31 @@ begin
we <= we_i;
-- outputs to other blocks
acam_ef1_o <= ef1;
acam_ef2_o <= ef2;
acam_lf1_o <= lf1;
acam_lf2_o <= lf2;
acam_ef1_o <= ef1_r(0); -- this signal is perfectly synchronized
acam_ef1_meta_o <= ef1_r(1); -- this signal could be metastable but
-- not when we plan to use it...
acam_ef2_o <= ef2_r(0);
acam_ef2_meta_o <= ef2_r(1);
acam_lf1_o <= lf1_r(0);
acam_lf2_o <= lf2_r(0);
ack_o <= ack;
dat_o <= ef1 & ef2 & lf1 & lf2 & data_bus_io;
dat_o <= ef1_r(0) & ef2_r(0) & lf1_r(0) & lf2_r(0) & data_bus_io;
-- inputs from the ACAM
input_registers: process
begin
if reset ='1' then
ef1 <= '1';
ef2 <= '1';
lf1 <= '1';
lf2 <= '1';
ef1_r <= (others =>'1');
ef2_r <= (others =>'1');
lf1_r <= (others =>'0');
lf2_r <= (others =>'0');
else
ef1 <= ef1_i;
ef2 <= ef2_i;
lf1 <= lf1_i;
lf2 <= lf2_i;
ef1_r <= ef1_i & ef1_r(1);
ef2_r <= ef2_i & ef2_r(1);
lf1_r <= lf1_i & lf1_r(1);
lf2_r <= lf2_i & lf2_r(1);
end if;
wait until clk ='1';
end process;
......
......@@ -38,8 +38,8 @@ entity acam_timecontrol_interface is
stop_dis_o : out std_logic;
-- signals internal to the chip: interface with other modules
acam_refclk_i : in std_logic;
clk_i : in std_logic;
acam_refclk_edge_p_i : in std_logic;
clk : in std_logic;
start_trig_i : in std_logic;
reset_i : in std_logic;
window_delay_i : in std_logic_vector(g_width-1 downto 0);
......@@ -87,21 +87,23 @@ architecture rtl of acam_timecontrol_interface is
end component;
constant constant_delay : unsigned(g_width-1 downto 0):=x"00000004";
-- the delay between the referenc clock and the start window is the Total Delay
-- the Total delay is always obtained by adding the constant delay and the
-- window delay configured by the PCI-e
signal acam_refclk : std_logic;
signal clk : std_logic;
-- the start_from_fpga signal is generated in the middle of the start window
signal acam_refclk_edge_p : std_logic;
signal counter_reset : std_logic;
signal counter_value : std_logic_vector(g_width-1 downto 0);
signal refclk_edge : std_logic;
signal refclk_r : unsigned(3 downto 0);
signal reset : std_logic;
signal int_flag_r : unsigned(2 downto 0);
signal err_flag_r : unsigned(2 downto 0);
signal int_flag_r : std_logic_vector(2 downto 0);
signal err_flag_r : std_logic_vector(2 downto 0);
signal start_dis : std_logic;
signal start_from_fpga : std_logic;
signal start_trig : std_logic;
signal start_trig_r : unsigned(2 downto 0);
signal start_trig_r : std_logic_vector(2 downto 0);
signal start_trig_edge : std_logic;
signal start_trig_received : std_logic;
signal waitingfor_refclk : std_logic;
......@@ -116,14 +118,13 @@ signal window_start : std_logic;
-- architecture begins
----------------------------------------------------------------------------------------------------
begin
-- monitoring of the interrupt and error signals
sync_err_flag: process -- synchronisation registers for ERR external signal
begin
if reset ='1' then
err_flag_r <= (others=>'0');
else
err_flag_r <= shift_right(err_flag_r,1);
err_flag_r(2) <= err_flag_i;
err_flag_r <= err_flag_i & err_flag_r(2 downto 1);
end if;
wait until clk ='1';
end process;
......@@ -133,8 +134,7 @@ begin
if reset ='1' then
int_flag_r <= (others=>'0');
else
int_flag_r <= shift_right(int_flag_r,1);
int_flag_r(2) <= int_flag_i;
int_flag_r <= int_flag_i & int_flag_r(2 downto 1);
end if;
wait until clk ='1';
end process;
......@@ -219,7 +219,7 @@ begin
waitingfor_refclk <= '0';
elsif start_trig_edge ='1' then
waitingfor_refclk <= '1';
elsif refclk_edge ='1' then
elsif acam_refclk_edge_p ='1' then
waitingfor_refclk <= '0';
end if;
wait until clk ='1';
......@@ -240,36 +240,27 @@ begin
inputs_synchronizer: process
begin
if reset ='1' then
start_trig_r <= (others=>'0');
refclk_r <= (others=>'0');
start_trig_r <= (others=>'0');
else
start_trig_r <= shift_right(start_trig_r,1);
start_trig_r(2) <= start_trig;
refclk_r <= shift_right(refclk_r,1);
refclk_r(3) <= acam_refclk;
start_trig_r <= start_trig & start_trig_r(2 downto 1);
end if;
wait until clk ='1';
end process;
refclk_edge <= refclk_r(3) and
not(refclk_r(2)) and
not(refclk_r(1)) and
refclk_r(0);
start_trig_edge <= start_trig_r(2) and
not(start_trig_r(1)) and
not(start_trig_r(0));
window_prepulse <= waitingfor_refclk and refclk_edge;
counter_reset <= reset or window_start;
start_trig_edge <= start_trig_r(1) and not(start_trig_r(0));
window_prepulse <= waitingfor_refclk and acam_refclk_edge_p;
total_delay <= std_logic_vector(unsigned(window_delay)+constant_delay);
counter_reset <= reset or window_start;
-- inputs
clk <= clk_i;
reset <= reset_i;
start_trig <= start_trig_i;
acam_refclk <= acam_refclk_i;
acam_refclk_edge_p <= acam_refclk_edge_p_i;
window_delay <= window_delay_i;
-- outputs
......
......@@ -34,7 +34,7 @@ entity circular_buffer is
);
port(
-- wishbone classic slave signals to interface RAM with the internal modules providing the timestamps
class_clk_i : in std_logic;
clk : in std_logic;
class_reset_i : in std_logic;
class_adr_i : in std_logic_vector(g_span-1 downto 0);
......@@ -47,7 +47,6 @@ entity circular_buffer is
class_dat_o : out std_logic_vector(4*g_width-1 downto 0);
-- wishbone pipelined slave signals to interface RAM with gnum core for DMA access from PCI-e
pipe_clk_i : in std_logic;
pipe_reset_i : in std_logic;
pipe_adr_i : in std_logic_vector(g_span-1 downto 0);
......@@ -85,13 +84,13 @@ component blk_mem_circ_buff_v6_4
);
end component;
type t_wb_pipelined_mem_interface is (idle, mem_access, mem_access_and_acknowledge, acknowledge);
type t_wb_pipelined_mem_interface is (IDLE, MEM_ACCESS,
MEM_ACCESS_AND_ACKNOWLEDGE, ACKNOWLEDGE);
signal wb_pipelined_st, nxt_wb_pipelined_st : t_wb_pipelined_mem_interface;
signal class_ack : std_logic;
signal class_adr : std_logic_vector(7 downto 0);
signal class_clk : std_logic;
signal class_cyc : std_logic;
signal class_data_rd : std_logic_vector(4*g_width-1 downto 0);
signal class_data_wr : std_logic_vector(4*g_width-1 downto 0);
......@@ -102,7 +101,6 @@ signal class_we : std_logic_vector(0 downto 0);
signal pipe_ack : std_logic;
signal pipe_adr : std_logic_vector(9 downto 0);
signal pipe_clk : std_logic;
signal pipe_cyc : std_logic;
signal pipe_data_rd : std_logic_vector(g_width-1 downto 0);
signal pipe_data_wr : std_logic_vector(g_width-1 downto 0);
......@@ -126,76 +124,76 @@ begin
else
class_ack <= '0';
end if;
wait until class_clk ='1';
wait until clk ='1';
end process;
-- Wishbone pipelined interfacte compatible slave
pipelined_seq_fsm: process
begin
if pipe_reset ='1' then
wb_pipelined_st <= idle;
wb_pipelined_st <= IDLE;
else
wb_pipelined_st <= nxt_wb_pipelined_st;
end if;
wait until pipe_clk ='1';
wait until clk ='1';
end process;
pipelined_comb_fsm: process(wb_pipelined_st, pipe_stb, pipe_cyc)
begin
case wb_pipelined_st is
when idle =>
when IDLE =>
pipe_ack <= '0';
if pipe_stb ='1' and pipe_cyc ='1' then
nxt_wb_pipelined_st <= mem_access;
nxt_wb_pipelined_st <= MEM_ACCESS;
else
nxt_wb_pipelined_st <= idle;
nxt_wb_pipelined_st <= IDLE;
end if;
when mem_access =>
when MEM_ACCESS =>
pipe_ack <= '0';
if pipe_stb ='1' and pipe_cyc ='1' then
nxt_wb_pipelined_st <= mem_access_and_acknowledge;
nxt_wb_pipelined_st <= MEM_ACCESS_AND_ACKNOWLEDGE;
else
nxt_wb_pipelined_st <= acknowledge;
nxt_wb_pipelined_st <= ACKNOWLEDGE;
end if;
when mem_access_and_acknowledge =>
when MEM_ACCESS_AND_ACKNOWLEDGE =>
pipe_ack <= '1';
if pipe_stb ='1' and pipe_cyc ='1' then
nxt_wb_pipelined_st <= mem_access_and_acknowledge;
nxt_wb_pipelined_st <= MEM_ACCESS_AND_ACKNOWLEDGE;
else
nxt_wb_pipelined_st <= acknowledge;
nxt_wb_pipelined_st <= ACKNOWLEDGE;
end if;
when acknowledge =>
when ACKNOWLEDGE =>
pipe_ack <= '1';
if pipe_stb ='1' and pipe_cyc ='1' then
nxt_wb_pipelined_st <= mem_access;
nxt_wb_pipelined_st <= MEM_ACCESS;
else
nxt_wb_pipelined_st <= idle;
nxt_wb_pipelined_st <= IDLE;
end if;
when others =>
pipe_ack <= '0';
nxt_wb_pipelined_st <= idle;
nxt_wb_pipelined_st <= IDLE;
end case;
end process;
memory_block: blk_mem_circ_buff_v6_4
port map(
clka => class_clk,
clka => clk,
addra => class_adr,
dina => class_data_wr,
ena => class_en,
wea => class_we,
douta => class_data_rd,
clkb => pipe_clk,
clkb => clk,
addrb => pipe_adr,
dinb => pipe_data_wr,
enb => pipe_en,
......@@ -204,7 +202,6 @@ begin
);
-- inputs from other blocks
class_clk <= class_clk_i;
class_reset <= class_reset_i;
class_adr <= class_adr_i(7 downto 0);
......@@ -214,7 +211,6 @@ begin
class_stb <= class_stb_i;
class_we(0) <= class_we_i;
pipe_clk <= pipe_clk_i;
pipe_reset <= pipe_reset_i;
pipe_adr <= pipe_adr_i(9 downto 0);
......
......@@ -45,7 +45,7 @@ entity clk_rst_managr is
tdc_clk_p_i : in std_logic;
tdc_clk_n_i : in std_logic;
acam_refclk_o : out std_logic;
acam_refclk_edge_p_o : out std_logic;
general_reset_o : out std_logic;
pll_cs_o : out std_logic;
pll_dac_sync_o : out std_logic;
......@@ -176,11 +176,11 @@ signal nxt_pll_init_st : t_pll_init_st;
signal config_reg : t_stream;
signal address : t_instr;
signal acam_refclk_buf : std_logic;
signal spec_clk_buf : std_logic;
signal tdc_clk_buf : std_logic;
signal acam_refclk : std_logic;
signal acam_refclk_r : std_logic_vector(2 downto 0);
signal acam_refclk_edge_p : std_logic;
signal pll_sclk : std_logic;
signal spec_clk : std_logic;
signal tdc_clk : std_logic;
......@@ -195,7 +195,7 @@ signal gnum_reset : std_logic;
signal gral_incr : std_logic;
signal gral_reset_duration : std_logic_vector(31 downto 0);
signal inv_reset : std_logic;
signal cs : std_logic;
signal cs_n : std_logic;
----------------------------------------------------------------------------------------------------
-- architecture begins
......@@ -234,19 +234,6 @@ begin
I => spec_clk_buf
);
-- acam_refclk_ibuf : IBUFG
-- port map (
-- I => acam_refclk_i,
-- O => acam_refclk_buf
-- );
--
-- acam_refclk_gbuf : BUFG
-- port map (
-- O => acam_refclk,
-- I => acam_refclk_buf
-- );
acam_refclk <= acam_refclk_i;
-- The following processes generate a general internal reset signal for the whole core.
-- This internal reset is triggered by the reset signal coming from the GNUM chip.
-- The idea is to keep the internal reset asserted until the clock signal received
......@@ -306,7 +293,7 @@ begin
begin
case pll_init_st is
when start =>
cs <= '1';
cs_n <= '1';
if pll_sclk ='1' then
nxt_pll_init_st <= sending_instruction;
......@@ -315,7 +302,7 @@ begin
end if;
when sending_instruction =>
cs <= '0';
cs_n <= '0';
if bit_index = 0
and pll_sclk = '1' then
......@@ -325,7 +312,7 @@ begin
end if;
when sending_data =>
cs <= '0';
cs_n <= '0';
if bit_index = 0
and pll_sclk = '1' then
......@@ -335,7 +322,7 @@ begin
end if;
when rest =>
cs <= '1';
cs_n <= '1';
if pll_sclk = '1' then
if byte_index = 0 then
......@@ -348,12 +335,12 @@ begin
end if;
when done =>
cs <= '1';
cs_n <= '1';
nxt_pll_init_st <= done;
when others =>
cs <= '1';
cs_n <= '1';
nxt_pll_init_st <= start;
end case;
......@@ -363,7 +350,7 @@ begin
begin
if gnum_reset ='1' then
bit_index <= 15;
elsif cs ='1' then
elsif cs_n ='1' then
bit_index <= 15;
elsif pll_sclk ='1' then
if bit_index = 0 then
......@@ -561,18 +548,31 @@ begin
config_reg(66) <= reg_230;
config_reg(67) <= reg_231;
acam_refclk_synchronizer: process
begin
if inv_reset ='0' then
acam_refclk_r <= (others=>'0');
else
acam_refclk_r <= acam_refclk_i & acam_refclk_r(2 downto 1);
end if;
wait until tdc_clk ='1';
end process;
acam_refclk_edge_p <= acam_refclk_r(1) and not(acam_refclk_r(0));
-- Input and Output signals
---------------------------
gnum_reset <= gnum_reset_i;
gnum_reset <= gnum_reset_i;
acam_refclk_o <= acam_refclk;
general_reset_o <= not(inv_reset);
pll_cs_o <= cs;
pll_sdi_o <= bit_being_sent;
pll_sclk_o <= pll_sclk;
spec_clk_o <= spec_clk;
tdc_clk_o <= tdc_clk;
acam_refclk_edge_p_o <= acam_refclk_edge_p;
general_reset_o <= not(inv_reset);
pll_cs_o <= cs_n;
pll_sdi_o <= bit_being_sent;
pll_sclk_o <= pll_sclk;
spec_clk_o <= spec_clk;
tdc_clk_o <= tdc_clk;
end rtl;
----------------------------------------------------------------------------------------------------
......
This diff is collapsed.
......@@ -47,15 +47,15 @@ entity data_formatting is
acam_timestamp1_valid_i : in std_logic;
acam_timestamp2_i : in std_logic_vector(g_width-1 downto 0);
acam_timestamp2_valid_i : in std_logic;
clk_i : in std_logic;
clear_dacapo_flag_i : in std_logic;
clk : in std_logic;
clear_dacapo_counter_i : in std_logic;
reset_i : in std_logic;
clk_cycles_offset_i : in std_logic_vector(g_width-1 downto 0);
current_roll_over_i : in std_logic_vector(g_width-1 downto 0);
local_utc_i : in std_logic_vector(g_width-1 downto 0);
retrig_nb_offset_i : in std_logic_vector(g_width-1 downto 0);
wr_pointer_o : out std_logic_vector(g_width-1 downto 0)
wr_index_o : out std_logic_vector(g_width-1 downto 0)
);
end data_formatting;
......@@ -78,7 +78,6 @@ signal acam_fine_timestamp : std_logic_vector(16 downto 0);
signal acam_slope : std_logic;
signal acam_start_nb : std_logic_vector(7 downto 0);
signal clk : std_logic;
signal reset : std_logic;
signal clk_cycles_offset : std_logic_vector(g_width-1 downto 0);
signal current_roll_over : std_logic_vector(g_width-1 downto 0);
......@@ -98,9 +97,10 @@ signal local_utc : std_logic_vector(g_width-1 downto 0);
signal coarse_time : std_logic_vector(g_width-1 downto 0);
signal fine_time : std_logic_vector(g_width-1 downto 0);
signal clear_dacapo_flag : std_logic;
signal dacapo_flag : std_logic;
signal wr_pointer : unsigned(g_width-1 downto 0);
signal clear_dacapo_counter : std_logic;
signal dacapo_counter : unsigned(g_width-13 downto 0);
signal wr_pointer : unsigned(7 downto 0);
constant address_128bit_shift : std_logic_vector(3 downto 0):= x"0";
signal mem_ack : std_logic;
signal mem_data_rd : std_logic_vector(4*g_width-1 downto 0);
......@@ -151,16 +151,17 @@ begin
wait until clk ='1';
end process;
-- the Da Capo flag indicates if the circular buffer has been written completely
-- the Da Capo counter indicates the number of times the circular buffer has been written completely
-- it is cleared by the PCIe host.
dacapo_flag_update: process
dacapo_counter_update: process
begin
if reset ='1' then
dacapo_flag <= '0';
elsif clear_dacapo_flag ='1' then
dacapo_flag <= '0';
elsif wr_pointer = buff_size - 1 then
dacapo_flag <= '1';
dacapo_counter <= (others=>'0');
elsif clear_dacapo_counter ='1' then
dacapo_counter <= (others=>'0');
elsif mem_cyc ='1' and mem_stb ='1' and mem_we ='1' and mem_ack ='1'
and wr_pointer = buff_size - 1 then
dacapo_counter <= dacapo_counter + 1;
end if;
wait until clk ='1';
end process;
......@@ -194,7 +195,7 @@ begin
wait until clk ='1';
end process;
mem_adr <= std_logic_vector(wr_pointer);
mem_adr <= x"000000" & std_logic_vector(wr_pointer);
mem_data_wr <= full_timestamp;
-- the full timestamp is a 128-bits word divided in four 32-bits words
......@@ -262,8 +263,7 @@ begin
acam_timestamp2 <= acam_timestamp2_i;
acam_timestamp2_valid <= acam_timestamp2_valid_i;
clk <= clk_i;
clear_dacapo_flag <= clear_dacapo_flag_i;
clear_dacapo_counter <= clear_dacapo_counter_i;
reset <= reset_i;
clk_cycles_offset <= clk_cycles_offset_i;
retrig_nb_offset <= retrig_nb_offset_i;
......@@ -273,8 +273,9 @@ begin
mem_data_rd <= dat_i;
-- outputs
wr_pointer_o <= dacapo_flag & std_logic_vector(wr_pointer(g_width-6 downto 0)) & x"0";