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FMC TDC 1ns 5cha - Gateware
Commit 17667554 authored by penacoba's avatar penacoba
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Most of the comments from the code review have been integrated 


git-svn-id: http://svn.ohwr.org/fmc-tdc@72 85dfdc96-de2c-444c-878d-45b388be74a9
parent a86d35bc
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hdl/spec/src/rtl/acam_databus_interface.vhd
View file @ 17667554
......@@ -46,12 +46,14 @@ entity acam_databus_interface is
-- signals internal to the chip: interface with other modules
acam_ef1_o : out std_logic;
acam_ef1_meta_o : out std_logic;
acam_ef2_o : out std_logic;
acam_ef2_meta_o : out std_logic;
acam_lf1_o : out std_logic;
acam_lf2_o : out std_logic;
-- wishbone slave signals internal to the chip: interface with other modules
clk_i : in std_logic;
clk : in std_logic;
reset_i : in std_logic;
adr_i : in std_logic_vector(g_span-1 downto 0);
......@@ -70,16 +72,15 @@ end acam_databus_interface;
----------------------------------------------------------------------------------------------------
architecture rtl of acam_databus_interface is
type t_acam_interface is (idle, rd_start, read, rd_ack, wr_start, write, wr_ack);
type t_acam_interface is (IDLE, RD_START, RD_FETCH, RD_ACK, WR_START, WR_PUSH, WR_ACK);
signal acam_data_st, nxt_acam_data_st : t_acam_interface;
signal ef1 : std_logic;
signal ef2 : std_logic;
signal lf1 : std_logic;
signal lf2 : std_logic;
signal ef1_r : std_logic_vector(1 downto 0);
signal ef2_r : std_logic_vector(1 downto 0);
signal lf1_r : std_logic_vector(1 downto 0);
signal lf2_r : std_logic_vector(1 downto 0);
signal clk : std_logic;
signal reset : std_logic;
signal adr : std_logic_vector(g_span-1 downto 0);
signal cyc : std_logic;
......@@ -105,7 +106,7 @@ begin
databus_access_seq_fsm: process
begin
if reset ='1' then
acam_data_st <= idle;
acam_data_st <= IDLE;
else
acam_data_st <= nxt_acam_data_st;
end if;
......@@ -115,7 +116,7 @@ begin
databus_access_comb_fsm: process(acam_data_st, stb, cyc, we)
begin
case acam_data_st is
when idle =>
when IDLE =>
ack <= '0';
cs_extend <= '0';
rd_extend <= '0';
......@@ -123,67 +124,67 @@ begin
wr_remove <= '0';
if stb ='1' and cyc ='1' then
if we = '1' then
nxt_acam_data_st <= wr_start;
nxt_acam_data_st <= WR_START;
else
nxt_acam_data_st <= rd_start;
nxt_acam_data_st <= RD_START;
end if;
else
nxt_acam_data_st <= idle;
nxt_acam_data_st <= IDLE;
end if;
when rd_start =>
when RD_START =>
ack <= '0';
cs_extend <= '1';
rd_extend <= '1';
wr_extend <= '0';
wr_remove <= '0';
nxt_acam_data_st <= read;
nxt_acam_data_st <= RD_FETCH;
when read =>
when RD_FETCH =>
ack <= '0';
cs_extend <= '1';
rd_extend <= '1';
wr_extend <= '0';
wr_remove <= '0';
nxt_acam_data_st <= rd_ack;
nxt_acam_data_st <= RD_ACK;
when rd_ack =>
when RD_ACK =>
ack <= '1';
cs_extend <= '0';
rd_extend <= '0';
wr_extend <= '0';
wr_remove <= '0';
nxt_acam_data_st <= idle;
nxt_acam_data_st <= IDLE;
when wr_start =>
when WR_START =>
ack <= '0';
cs_extend <= '1';
rd_extend <= '0';
wr_extend <= '1';
wr_remove <= '0';
nxt_acam_data_st <= write;
nxt_acam_data_st <= WR_PUSH;
when write =>
when WR_PUSH =>
ack <= '0';
cs_extend <= '0';
rd_extend <= '0';
wr_extend <= '0';
wr_remove <= '1';
nxt_acam_data_st <= wr_ack;
nxt_acam_data_st <= WR_ACK;
when wr_ack =>
when WR_ACK =>
ack <= '1';
cs_extend <= '0';
rd_extend <= '0';
wr_extend <= '0';
wr_remove <= '0';
nxt_acam_data_st <= idle;
nxt_acam_data_st <= IDLE;
when others =>
ack <= '0';
......@@ -192,7 +193,7 @@ begin
wr_extend <= '0';
wr_remove <= '0';
nxt_acam_data_st <= idle;
nxt_acam_data_st <= IDLE;
end case;
end process;
......@@ -205,7 +206,6 @@ begin
-- Acam specs
-- inputs from other blocks
clk <= clk_i;
reset <= reset_i;
adr <= adr_i;
......@@ -215,27 +215,31 @@ begin
we <= we_i;
-- outputs to other blocks
acam_ef1_o <= ef1;
acam_ef2_o <= ef2;
acam_lf1_o <= lf1;
acam_lf2_o <= lf2;
acam_ef1_o <= ef1_r(0); -- this signal is perfectly synchronized
acam_ef1_meta_o <= ef1_r(1); -- this signal could be metastable but
-- not when we plan to use it...
acam_ef2_o <= ef2_r(0);
acam_ef2_meta_o <= ef2_r(1);
acam_lf1_o <= lf1_r(0);
acam_lf2_o <= lf2_r(0);
ack_o <= ack;
dat_o <= ef1 & ef2 & lf1 & lf2 & data_bus_io;
dat_o <= ef1_r(0) & ef2_r(0) & lf1_r(0) & lf2_r(0) & data_bus_io;
-- inputs from the ACAM
input_registers: process
begin
if reset ='1' then
ef1 <= '1';
ef2 <= '1';
lf1 <= '1';
lf2 <= '1';
ef1_r <= (others =>'1');
ef2_r <= (others =>'1');
lf1_r <= (others =>'0');
lf2_r <= (others =>'0');
else
ef1 <= ef1_i;
ef2 <= ef2_i;
lf1 <= lf1_i;
lf2 <= lf2_i;
ef1_r <= ef1_i & ef1_r(1);
ef2_r <= ef2_i & ef2_r(1);
lf1_r <= lf1_i & lf1_r(1);
lf2_r <= lf2_i & lf2_r(1);
end if;
wait until clk ='1';
end process;
......
hdl/spec/src/rtl/acam_timecontrol_interface.vhd
View file @ 17667554
......@@ -38,8 +38,8 @@ entity acam_timecontrol_interface is
stop_dis_o : out std_logic;
-- signals internal to the chip: interface with other modules
acam_refclk_i : in std_logic;
clk_i : in std_logic;
acam_refclk_edge_p_i : in std_logic;
clk : in std_logic;
start_trig_i : in std_logic;
reset_i : in std_logic;
window_delay_i : in std_logic_vector(g_width-1 downto 0);
......@@ -87,21 +87,23 @@ architecture rtl of acam_timecontrol_interface is
end component;
constant constant_delay : unsigned(g_width-1 downto 0):=x"00000004";
-- the delay between the referenc clock and the start window is the Total Delay
-- the Total delay is always obtained by adding the constant delay and the
-- window delay configured by the PCI-e
signal acam_refclk : std_logic;
signal clk : std_logic;
-- the start_from_fpga signal is generated in the middle of the start window
signal acam_refclk_edge_p : std_logic;
signal counter_reset : std_logic;
signal counter_value : std_logic_vector(g_width-1 downto 0);
signal refclk_edge : std_logic;
signal refclk_r : unsigned(3 downto 0);
signal reset : std_logic;
signal int_flag_r : unsigned(2 downto 0);
signal err_flag_r : unsigned(2 downto 0);
signal int_flag_r : std_logic_vector(2 downto 0);
signal err_flag_r : std_logic_vector(2 downto 0);
signal start_dis : std_logic;
signal start_from_fpga : std_logic;
signal start_trig : std_logic;
signal start_trig_r : unsigned(2 downto 0);
signal start_trig_r : std_logic_vector(2 downto 0);
signal start_trig_edge : std_logic;
signal start_trig_received : std_logic;
signal waitingfor_refclk : std_logic;
......@@ -116,14 +118,13 @@ signal window_start : std_logic;
-- architecture begins
----------------------------------------------------------------------------------------------------
begin
-- monitoring of the interrupt and error signals
sync_err_flag: process -- synchronisation registers for ERR external signal
begin
if reset ='1' then
err_flag_r <= (others=>'0');
else
err_flag_r <= shift_right(err_flag_r,1);
err_flag_r(2) <= err_flag_i;
err_flag_r <= err_flag_i & err_flag_r(2 downto 1);
end if;
wait until clk ='1';
end process;
......@@ -133,8 +134,7 @@ begin
if reset ='1' then
int_flag_r <= (others=>'0');
else
int_flag_r <= shift_right(int_flag_r,1);
int_flag_r(2) <= int_flag_i;
int_flag_r <= int_flag_i & int_flag_r(2 downto 1);
end if;
wait until clk ='1';
end process;
......@@ -219,7 +219,7 @@ begin
waitingfor_refclk <= '0';
elsif start_trig_edge ='1' then
waitingfor_refclk <= '1';
elsif refclk_edge ='1' then
elsif acam_refclk_edge_p ='1' then
waitingfor_refclk <= '0';
end if;
wait until clk ='1';
......@@ -240,36 +240,27 @@ begin
inputs_synchronizer: process
begin
if reset ='1' then
start_trig_r <= (others=>'0');
refclk_r <= (others=>'0');
start_trig_r <= (others=>'0');
else
start_trig_r <= shift_right(start_trig_r,1);
start_trig_r(2) <= start_trig;
refclk_r <= shift_right(refclk_r,1);
refclk_r(3) <= acam_refclk;
start_trig_r <= start_trig & start_trig_r(2 downto 1);
end if;
wait until clk ='1';
end process;
refclk_edge <= refclk_r(3) and
not(refclk_r(2)) and
not(refclk_r(1)) and
refclk_r(0);
start_trig_edge <= start_trig_r(2) and
not(start_trig_r(1)) and
not(start_trig_r(0));
window_prepulse <= waitingfor_refclk and refclk_edge;
counter_reset <= reset or window_start;
start_trig_edge <= start_trig_r(1) and not(start_trig_r(0));
window_prepulse <= waitingfor_refclk and acam_refclk_edge_p;
total_delay <= std_logic_vector(unsigned(window_delay)+constant_delay);
counter_reset <= reset or window_start;
-- inputs
clk <= clk_i;
reset <= reset_i;
start_trig <= start_trig_i;
acam_refclk <= acam_refclk_i;
acam_refclk_edge_p <= acam_refclk_edge_p_i;
window_delay <= window_delay_i;
-- outputs
......
hdl/spec/src/rtl/circular_buffer.vhd
View file @ 17667554
......@@ -34,7 +34,7 @@ entity circular_buffer is
);
port(
-- wishbone classic slave signals to interface RAM with the internal modules providing the timestamps
class_clk_i : in std_logic;
clk : in std_logic;
class_reset_i : in std_logic;
class_adr_i : in std_logic_vector(g_span-1 downto 0);
......@@ -47,7 +47,6 @@ entity circular_buffer is
class_dat_o : out std_logic_vector(4*g_width-1 downto 0);
-- wishbone pipelined slave signals to interface RAM with gnum core for DMA access from PCI-e
pipe_clk_i : in std_logic;
pipe_reset_i : in std_logic;
pipe_adr_i : in std_logic_vector(g_span-1 downto 0);
......@@ -85,13 +84,13 @@ component blk_mem_circ_buff_v6_4
);
end component;
type t_wb_pipelined_mem_interface is (idle, mem_access, mem_access_and_acknowledge, acknowledge);
type t_wb_pipelined_mem_interface is (IDLE, MEM_ACCESS,
MEM_ACCESS_AND_ACKNOWLEDGE, ACKNOWLEDGE);
signal wb_pipelined_st, nxt_wb_pipelined_st : t_wb_pipelined_mem_interface;
signal class_ack : std_logic;
signal class_adr : std_logic_vector(7 downto 0);
signal class_clk : std_logic;
signal class_cyc : std_logic;
signal class_data_rd : std_logic_vector(4*g_width-1 downto 0);
signal class_data_wr : std_logic_vector(4*g_width-1 downto 0);
......@@ -102,7 +101,6 @@ signal class_we : std_logic_vector(0 downto 0);
signal pipe_ack : std_logic;
signal pipe_adr : std_logic_vector(9 downto 0);
signal pipe_clk : std_logic;
signal pipe_cyc : std_logic;
signal pipe_data_rd : std_logic_vector(g_width-1 downto 0);
signal pipe_data_wr : std_logic_vector(g_width-1 downto 0);
......@@ -126,76 +124,76 @@ begin
else
class_ack <= '0';
end if;
wait until class_clk ='1';
wait until clk ='1';
end process;
-- Wishbone pipelined interfacte compatible slave
pipelined_seq_fsm: process
begin
if pipe_reset ='1' then
wb_pipelined_st <= idle;
wb_pipelined_st <= IDLE;
else
wb_pipelined_st <= nxt_wb_pipelined_st;
end if;
wait until pipe_clk ='1';
wait until clk ='1';
end process;
pipelined_comb_fsm: process(wb_pipelined_st, pipe_stb, pipe_cyc)
begin
case wb_pipelined_st is
when idle =>
when IDLE =>
pipe_ack <= '0';
if pipe_stb ='1' and pipe_cyc ='1' then
nxt_wb_pipelined_st <= mem_access;
nxt_wb_pipelined_st <= MEM_ACCESS;
else
nxt_wb_pipelined_st <= idle;
nxt_wb_pipelined_st <= IDLE;
end if;
when mem_access =>
when MEM_ACCESS =>
pipe_ack <= '0';
if pipe_stb ='1' and pipe_cyc ='1' then
nxt_wb_pipelined_st <= mem_access_and_acknowledge;
nxt_wb_pipelined_st <= MEM_ACCESS_AND_ACKNOWLEDGE;
else
nxt_wb_pipelined_st <= acknowledge;
nxt_wb_pipelined_st <= ACKNOWLEDGE;
end if;
when mem_access_and_acknowledge =>
when MEM_ACCESS_AND_ACKNOWLEDGE =>
pipe_ack <= '1';
if pipe_stb ='1' and pipe_cyc ='1' then
nxt_wb_pipelined_st <= mem_access_and_acknowledge;
nxt_wb_pipelined_st <= MEM_ACCESS_AND_ACKNOWLEDGE;
else
nxt_wb_pipelined_st <= acknowledge;
nxt_wb_pipelined_st <= ACKNOWLEDGE;
end if;
when acknowledge =>
when ACKNOWLEDGE =>
pipe_ack <= '1';
if pipe_stb ='1' and pipe_cyc ='1' then
nxt_wb_pipelined_st <= mem_access;
nxt_wb_pipelined_st <= MEM_ACCESS;
else
nxt_wb_pipelined_st <= idle;
nxt_wb_pipelined_st <= IDLE;
end if;
when others =>
pipe_ack <= '0';
nxt_wb_pipelined_st <= idle;
nxt_wb_pipelined_st <= IDLE;
end case;
end process;
memory_block: blk_mem_circ_buff_v6_4
port map(
clka => class_clk,
clka => clk,
addra => class_adr,
dina => class_data_wr,
ena => class_en,
wea => class_we,
douta => class_data_rd,
clkb => pipe_clk,
clkb => clk,
addrb => pipe_adr,
dinb => pipe_data_wr,
enb => pipe_en,
......@@ -204,7 +202,6 @@ begin
);
-- inputs from other blocks
class_clk <= class_clk_i;
class_reset <= class_reset_i;
class_adr <= class_adr_i(7 downto 0);
......@@ -214,7 +211,6 @@ begin
class_stb <= class_stb_i;
class_we(0) <= class_we_i;
pipe_clk <= pipe_clk_i;
pipe_reset <= pipe_reset_i;
pipe_adr <= pipe_adr_i(9 downto 0);
......
hdl/spec/src/rtl/clk_rst_managr.vhd
View file @ 17667554
......@@ -45,7 +45,7 @@ entity clk_rst_managr is
tdc_clk_p_i : in std_logic;
tdc_clk_n_i : in std_logic;
acam_refclk_o : out std_logic;
acam_refclk_edge_p_o : out std_logic;
general_reset_o : out std_logic;
pll_cs_o : out std_logic;
pll_dac_sync_o : out std_logic;
......@@ -176,11 +176,11 @@ signal nxt_pll_init_st : t_pll_init_st;
signal config_reg : t_stream;
signal address : t_instr;
signal acam_refclk_buf : std_logic;
signal spec_clk_buf : std_logic;
signal tdc_clk_buf : std_logic;
signal acam_refclk : std_logic;
signal acam_refclk_r : std_logic_vector(2 downto 0);
signal acam_refclk_edge_p : std_logic;
signal pll_sclk : std_logic;
signal spec_clk : std_logic;
signal tdc_clk : std_logic;
......@@ -195,7 +195,7 @@ signal gnum_reset : std_logic;
signal gral_incr : std_logic;
signal gral_reset_duration : std_logic_vector(31 downto 0);
signal inv_reset : std_logic;
signal cs : std_logic;
signal cs_n : std_logic;
----------------------------------------------------------------------------------------------------
-- architecture begins
......@@ -234,19 +234,6 @@ begin
I => spec_clk_buf
);
-- acam_refclk_ibuf : IBUFG
-- port map (
-- I => acam_refclk_i,
-- O => acam_refclk_buf
-- );
--
-- acam_refclk_gbuf : BUFG
-- port map (
-- O => acam_refclk,
-- I => acam_refclk_buf
-- );
acam_refclk <= acam_refclk_i;
-- The following processes generate a general internal reset signal for the whole core.
-- This internal reset is triggered by the reset signal coming from the GNUM chip.
-- The idea is to keep the internal reset asserted until the clock signal received
......@@ -306,7 +293,7 @@ begin
begin
case pll_init_st is
when start =>
cs <= '1';
cs_n <= '1';
if pll_sclk ='1' then
nxt_pll_init_st <= sending_instruction;
......@@ -315,7 +302,7 @@ begin
end if;
when sending_instruction =>
cs <= '0';
cs_n <= '0';
if bit_index = 0
and pll_sclk = '1' then
......@@ -325,7 +312,7 @@ begin
end if;
when sending_data =>
cs <= '0';
cs_n <= '0';
if bit_index = 0
and pll_sclk = '1' then
......@@ -335,7 +322,7 @@ begin
end if;
when rest =>
cs <= '1';
cs_n <= '1';
if pll_sclk = '1' then
if byte_index = 0 then
......@@ -348,12 +335,12 @@ begin
end if;
when done =>
cs <= '1';
cs_n <= '1';
nxt_pll_init_st <= done;
when others =>
cs <= '1';
cs_n <= '1';
nxt_pll_init_st <= start;
end case;
......@@ -363,7 +350,7 @@ begin
begin
if gnum_reset ='1' then
bit_index <= 15;
elsif cs ='1' then
elsif cs_n ='1' then
bit_index <= 15;
elsif pll_sclk ='1' then
if bit_index = 0 then
......@@ -561,18 +548,31 @@ begin
config_reg(66) <= reg_230;
config_reg(67) <= reg_231;
acam_refclk_synchronizer: process
begin
if inv_reset ='0' then
acam_refclk_r <= (others=>'0');
else
acam_refclk_r <= acam_refclk_i & acam_refclk_r(2 downto 1);
end if;
wait until tdc_clk ='1';
end process;
acam_refclk_edge_p <= acam_refclk_r(1) and not(acam_refclk_r(0));
-- Input and Output signals
---------------------------
gnum_reset <= gnum_reset_i;
gnum_reset <= gnum_reset_i;
acam_refclk_o <= acam_refclk;
general_reset_o <= not(inv_reset);
pll_cs_o <= cs;
pll_sdi_o <= bit_being_sent;
pll_sclk_o <= pll_sclk;
spec_clk_o <= spec_clk;
tdc_clk_o <= tdc_clk;
acam_refclk_edge_p_o <= acam_refclk_edge_p;
general_reset_o <= not(inv_reset);
pll_cs_o <= cs_n;
pll_sdi_o <= bit_being_sent;
pll_sclk_o <= pll_sclk;
spec_clk_o <= spec_clk;
tdc_clk_o <= tdc_clk;
end rtl;
----------------------------------------------------------------------------------------------------
......
hdl/spec/src/rtl/data_engine.vhd
View file @ 17667554
......@@ -11,7 +11,7 @@
-- and reads timestamps accordingly.
-- when acquisition mode is inactive: allows the configuration and readback of ACAM
-- registers.
-- Acts as a wishbone master.
-- Acts as a wishbone master to fetch the data from the ACAM interface
-- dependencies:
-- references :
-- modified by :
......@@ -47,10 +47,12 @@ entity data_engine is
we_o : out std_logic;
-- signals internal to the chip: interface with other modules
clk_i : in std_logic;
clk : in std_logic;
reset_i : in std_logic;
acam_ef1_i : in std_logic;
acam_ef1_meta_i : in std_logic;
acam_ef2_i : in std_logic;
acam_ef2_meta_i : in std_logic;
activate_acq_i : in std_logic;
deactivate_acq_i : in std_logic;
......@@ -80,12 +82,15 @@ end data_engine;
----------------------------------------------------------------------------------------------------
architecture rtl of data_engine is
type engine_state_ty is (active, inactive, get_stamp1, get_stamp2,
wr_config, rdbk_config, rd_status, rd_ififo1, rd_ififo2, rd_start01, wr_reset);
type engine_state_ty is (ACTIVE, INACTIVE, GET_STAMP1, GET_STAMP2,
WR_CONFIG, RDBK_CONFIG, RD_STATUS, RD_IFIFO1,
RD_IFIFO2, RD_START01, WR_RESET);
signal engine_st, nxt_engine_st : engine_state_ty;
signal acam_ef1 : std_logic;
signal acam_ef1_meta : std_logic;
signal acam_ef2 : std_logic;
signal acam_ef2_meta : std_logic;
signal acam_ack : std_logic;
signal acam_adr : std_logic_vector(7 downto 0);
......@@ -95,7 +100,6 @@ signal acam_we : std_logic;
signal acam_data_rd : std_logic_vector(g_width-1 downto 0);
signal acam_data_wr : std_logic_vector(g_width-1 downto 0);
signal clk : std_logic;
signal reset : std_logic;
signal activate_acq : std_logic;
......@@ -147,155 +151,155 @@ begin
acam_ack, acam_adr)
begin
case engine_st is
when inactive =>
acam_cyc <= '0';
when INACTIVE => -- the FSM acquisition needs to be inactive to
acam_cyc <= '0'; -- modify or read the ACAM config
acam_stb <= '0';
acam_we <= '0';
if activate_acq ='1' then
nxt_engine_st <= active;
nxt_engine_st <= ACTIVE;
elsif load_acam_config ='1' then
nxt_engine_st <= wr_config;
nxt_engine_st <= WR_CONFIG;
elsif read_acam_config ='1' then
nxt_engine_st <= rdbk_config;
nxt_engine_st <= RDBK_CONFIG;
elsif read_acam_status ='1' then
nxt_engine_st <= rd_status;
nxt_engine_st <= RD_STATUS;
elsif read_ififo1 ='1' then
nxt_engine_st <= rd_ififo1;
nxt_engine_st <= RD_IFIFO1;
elsif read_ififo2 ='1' then
nxt_engine_st <= rd_ififo2;
nxt_engine_st <= RD_IFIFO2;
elsif read_start01 ='1' then
nxt_engine_st <= rd_start01;
nxt_engine_st <= RD_START01;
elsif reset_acam ='1' then
nxt_engine_st <= wr_reset;
nxt_engine_st <= WR_RESET;
else
nxt_engine_st <= inactive;
nxt_engine_st <= INACTIVE;
end if;
when active =>
acam_cyc <= '0';
acam_stb <= '0';
acam_we <= '0';
when ACTIVE => -- when ACTIVE, the acquisition is intensive
acam_cyc <= '0'; -- the iFIFO of the ACAM is kept permanently
acam_stb <= '0'; -- empty
acam_we <= '0'; -- the core performs as fast as the ACAM
-- allows: one timestamp per refclk period
if deactivate_acq ='1' then
nxt_engine_st <= inactive;
nxt_engine_st <= INACTIVE;
elsif acam_ef1 ='0' then
nxt_engine_st <= get_stamp1;
nxt_engine_st <= GET_STAMP1;
elsif acam_ef2 ='0' then
nxt_engine_st <= get_stamp2;
nxt_engine_st <= GET_STAMP2;
else
nxt_engine_st <= active;
nxt_engine_st <= ACTIVE;
end if;
when get_stamp1 =>
when GET_STAMP1 =>
acam_cyc <= '1';
acam_stb <= '1';
acam_we <= '0';
if acam_ack ='1' then
if acam_ef2 ='0' then
nxt_engine_st <= get_stamp2;
elsif acam_ef1 ='0' then
nxt_engine_st <= get_stamp1;
else
nxt_engine_st <= active;
if acam_ack ='1' then -- the usage of a potentially metastable
if acam_ef2 ='0' then -- signal is allowed if to stay on the same
nxt_engine_st <= GET_STAMP2; -- state. Under those circumstances
elsif acam_ef1_meta ='0' then -- the arrival time of the rising edge
nxt_engine_st <= GET_STAMP1; -- would not be totally random, since
else -- it depends on the READ signal.
nxt_engine_st <= ACTIVE;
end if;
else
nxt_engine_st <= get_stamp1;
nxt_engine_st <= GET_STAMP1;
end if;
when get_stamp2 =>
when GET_STAMP2 =>
acam_cyc <= '1';
acam_stb <= '1';
acam_we <= '0';
if acam_ack ='1' then
if acam_ack ='1' then -- idem.
if acam_ef1 ='0' then
nxt_engine_st <= get_stamp1;
elsif acam_ef2 ='0' then
nxt_engine_st <= get_stamp2;
nxt_engine_st <= GET_STAMP1;
elsif acam_ef2_meta ='0' then
nxt_engine_st <= GET_STAMP2;
else
nxt_engine_st <= active;
nxt_engine_st <= ACTIVE;
end if;
else
nxt_engine_st <= get_stamp2;
nxt_engine_st <= GET_STAMP2;
end if;
when wr_config =>
when WR_CONFIG =>
acam_cyc <= '1';
acam_stb <= '1';
acam_we <= '1';
if acam_ack ='1' and acam_adr =x"0E" then
nxt_engine_st <= inactive;
nxt_engine_st <= INACTIVE;
else
nxt_engine_st <= wr_config;
nxt_engine_st <= WR_CONFIG;
end if;
when rdbk_config =>
when RDBK_CONFIG =>
acam_cyc <= '1';
acam_stb <= '1';
acam_we <= '0';
if acam_ack ='1' and acam_adr =x"0E" then
nxt_engine_st <= inactive;
nxt_engine_st <= INACTIVE;
else
nxt_engine_st <= rdbk_config;
nxt_engine_st <= RDBK_CONFIG;
end if;
when rd_status =>
when RD_STATUS =>
acam_cyc <= '1';
acam_stb <= '1';
acam_we <= '0';
if acam_ack ='1' then
nxt_engine_st <= inactive;
nxt_engine_st <= INACTIVE;
else
nxt_engine_st <= rd_status;
nxt_engine_st <= RD_STATUS;
end if;
when rd_ififo1 =>
when RD_IFIFO1 =>
acam_cyc <= '1';
acam_stb <= '1';
acam_we <= '0';
if acam_ack ='1' then
nxt_engine_st <= inactive;
nxt_engine_st <= INACTIVE;
else
nxt_engine_st <= rd_ififo1;
nxt_engine_st <= RD_IFIFO1;
end if;
when rd_ififo2 =>
when RD_IFIFO2 =>
acam_cyc <= '1';
acam_stb <= '1';
acam_we <= '0';
if acam_ack ='1' then
nxt_engine_st <= inactive;
nxt_engine_st <= INACTIVE;
else
nxt_engine_st <= rd_ififo2;
nxt_engine_st <= RD_IFIFO2;
end if;
when rd_start01 =>
when RD_START01 =>
acam_cyc <= '1';
acam_stb <= '1';
acam_we <= '0';
if acam_ack ='1' then
nxt_engine_st <= inactive;
nxt_engine_st <= INACTIVE;
else
nxt_engine_st <= rd_start01;
nxt_engine_st <= RD_START01;
end if;
when wr_reset =>
when WR_RESET =>
acam_cyc <= '1';
acam_stb <= '1';
acam_we <= '1';
if acam_ack ='1' then
nxt_engine_st <= inactive;
nxt_engine_st <= INACTIVE;
else
nxt_engine_st <= wr_reset;
nxt_engine_st <= WR_RESET;
end if;
when others =>
......@@ -303,35 +307,35 @@ begin
acam_stb <= '0';
acam_we <= '0';
nxt_engine_st <= inactive;
nxt_engine_st <= INACTIVE;
end case;
end process;
address_generation: process(engine_st, config_adr_counter)
begin
case engine_st is
when inactive =>
when INACTIVE =>
acam_adr <= x"00";
when active =>
when ACTIVE =>
acam_adr <= x"00";
when get_stamp1 =>
acam_adr <= x"08";
when get_stamp2 =>
acam_adr <= x"09";
when wr_config =>
acam_adr <= std_logic_vector(config_adr_counter);
when rdbk_config =>
acam_adr <= std_logic_vector(config_adr_counter);
when rd_status =>
acam_adr <= x"0C";
when rd_ififo1 =>
acam_adr <= x"08";
when rd_ififo2 =>
acam_adr <= x"09";
when rd_start01 =>
acam_adr <= x"0A";
when wr_reset =>
acam_adr <= x"04";
when GET_STAMP1 =>
acam_adr <= std_logic_vector(c_acam_adr_reg8);
when GET_STAMP2 =>
acam_adr <= std_logic_vector(c_acam_adr_reg9);
when WR_CONFIG =>
acam_adr <= std_logic_vector(config_adr_counter); -- sweeps through
when RDBK_CONFIG => -- the addresses
acam_adr <= std_logic_vector(config_adr_counter); -- of the ACAM
when RD_STATUS => -- config registers
acam_adr <= std_logic_vector(c_acam_adr_reg12);
when RD_IFIFO1 =>
acam_adr <= std_logic_vector(c_acam_adr_reg8);
when RD_IFIFO2 =>
acam_adr <= std_logic_vector(c_acam_adr_reg9);
when RD_START01 =>
acam_adr <= std_logic_vector(c_acam_adr_reg10);
when WR_RESET =>
acam_adr <= std_logic_vector(c_acam_adr_reg4);
when others =>
acam_adr <= x"00";
end case;
......@@ -340,18 +344,18 @@ begin
config_adr: process -- process to generate the valid addresses
begin -- for the ACAM config registers
if reset ='1' then
config_adr_counter <= x"00";
config_adr_counter <= unsigned(c_acam_adr_reg0);
elsif load_acam_config ='1' or read_acam_config ='1' then
config_adr_counter <= x"00";
config_adr_counter <= unsigned(c_acam_adr_reg0);
elsif acam_ack ='1' then
if config_adr_counter= x"0E" then
config_adr_counter <= x"0E";
elsif config_adr_counter= x"0C" then
config_adr_counter <= x"0E";
elsif config_adr_counter= x"07" then
config_adr_counter <= x"0B";
if config_adr_counter= unsigned(c_acam_adr_reg14) then
config_adr_counter <= unsigned(c_acam_adr_reg14);
elsif config_adr_counter= unsigned(c_acam_adr_reg12) then
config_adr_counter <= unsigned(c_acam_adr_reg14);
elsif config_adr_counter= unsigned(c_acam_adr_reg7) then
config_adr_counter <= unsigned(c_acam_adr_reg11);
else
config_adr_counter <= config_adr_counter + 1;
end if;
......@@ -361,41 +365,41 @@ begin
data_config_decoding: process(acam_adr, engine_st, acam_config, reset_word)
begin
case acam_adr is
when x"00" =>
case acam_adr is -- the values for the ACAM config registers are multiplexed
when c_acam_adr_reg0 => -- into the data bus according to the register addresses
acam_data_wr <= acam_config(0);
when x"01" =>
when c_acam_adr_reg1 =>
acam_data_wr <= acam_config(1);
when x"02" =>
when c_acam_adr_reg2 =>
acam_data_wr <= acam_config(2);
when x"03" =>
when c_acam_adr_reg3 =>
acam_data_wr <= acam_config(3);
when x"04" =>
when c_acam_adr_reg4 =>
if engine_st = wr_reset then
acam_data_wr <= reset_word;
else
acam_data_wr <= acam_config(4);
end if;
when x"05" =>
when c_acam_adr_reg5 =>
acam_data_wr <= acam_config(5);
when x"06" =>
when c_acam_adr_reg6 =>
acam_data_wr <= acam_config(6);
when x"07" =>
when c_acam_adr_reg7 =>
acam_data_wr <= acam_config(7);
when x"0B" =>
when c_acam_adr_reg11 =>
acam_data_wr <= acam_config(8);
when x"0C" =>
when c_acam_adr_reg12 =>
acam_data_wr <= acam_config(9);
when x"0E" =>
when c_acam_adr_reg14 =>
acam_data_wr <= acam_config(10);
when others =>
acam_data_wr <= (others =>'0');
end case;
end process;
data_readback_decoding: process
begin
if reset ='1' then
data_readback_decoding: process -- the values from the ACAM config registers are demultiplexed
begin -- from the data bus into dedicated registers according
if reset ='1' then -- the register addresses
acam_config_rdbk(0) <= (others =>'0');
acam_config_rdbk(1) <= (others =>'0');
acam_config_rdbk(2) <= (others =>'0');
......@@ -412,55 +416,55 @@ begin
acam_ififo2 <= (others =>'0');
acam_start01 <= (others =>'0');
elsif acam_cyc ='1' and acam_stb ='1' and acam_ack ='1' and acam_we ='0' then
if acam_adr= x"00" then
if acam_adr= c_acam_adr_reg0 then
acam_config_rdbk(0) <= acam_data_rd;
end if;
if acam_adr= x"01" then
if acam_adr= c_acam_adr_reg1 then
acam_config_rdbk(1) <= acam_data_rd;
end if;
if acam_adr= x"02" then
if acam_adr= c_acam_adr_reg2 then
acam_config_rdbk(2) <= acam_data_rd;
end if;
if acam_adr= x"03" then
if acam_adr= c_acam_adr_reg3 then
acam_config_rdbk(3) <= acam_data_rd;
end if;
if acam_adr= x"04" then
if acam_adr= c_acam_adr_reg4 then
acam_config_rdbk(4) <= acam_data_rd;
end if;
if acam_adr= x"05" then
if acam_adr= c_acam_adr_reg5 then
acam_config_rdbk(5) <= acam_data_rd;
end if;
if acam_adr= x"06" then
if acam_adr= c_acam_adr_reg6 then
acam_config_rdbk(6) <= acam_data_rd;
end if;
if acam_adr= x"07" then
if acam_adr= c_acam_adr_reg7 then
acam_config_rdbk(7) <= acam_data_rd;
end if;
if acam_adr= x"0B" then
if acam_adr= c_acam_adr_reg11 then
acam_config_rdbk(8) <= acam_data_rd;
end if;
if acam_adr= x"0C" then
if acam_adr= c_acam_adr_reg12 then
acam_config_rdbk(9) <= acam_data_rd;
end if;
if acam_adr= x"0E" then
if acam_adr= c_acam_adr_reg14 then
acam_config_rdbk(10) <= acam_data_rd;
end if;
if acam_adr= x"08" then
if acam_adr= c_acam_adr_reg8 then
acam_ififo1 <= acam_data_rd;
end if;
if acam_adr= x"09" then
if acam_adr= c_acam_adr_reg9 then
acam_ififo2 <= acam_data_rd;
end if;
if acam_adr= x"0A" then
if acam_adr= c_acam_adr_reg10 then
acam_start01 <= acam_data_rd;
end if;
end if;
wait until clk ='1';
end process;
acam_timestamp1 <= acam_data_rd;
acam_timestamp2 <= acam_data_rd;
acam_timestamp1 <= acam_data_rd; -- timestamps can come from iFIFO1
acam_timestamp2 <= acam_data_rd; -- or iFIFO2
acam_timestamp1_valid <= '1' when (acam_ack ='1' and engine_st = get_stamp1)
else '0';
......@@ -472,12 +476,13 @@ begin
reset_word <= reg4(31 downto 24) & "01" & reg4(21 downto 0);
-- inputs
clk <= clk_i;
reset <= reset_i;
acam_ack <= ack_i;
acam_data_rd <= dat_i;
acam_ef1 <= acam_ef1_i;
acam_ef1_meta <= acam_ef1_meta_i;
acam_ef2 <= acam_ef2_i;
acam_ef2_meta <= acam_ef2_meta_i;
activate_acq <= activate_acq_i;
deactivate_acq <= deactivate_acq_i;
......
hdl/spec/src/rtl/data_formatting.vhd
View file @ 17667554
......@@ -47,15 +47,15 @@ entity data_formatting is
acam_timestamp1_valid_i : in std_logic;
acam_timestamp2_i : in std_logic_vector(g_width-1 downto 0);
acam_timestamp2_valid_i : in std_logic;
clk_i : in std_logic;
clear_dacapo_flag_i : in std_logic;
clk : in std_logic;
clear_dacapo_counter_i : in std_logic;
reset_i : in std_logic;
clk_cycles_offset_i : in std_logic_vector(g_width-1 downto 0);
current_roll_over_i : in std_logic_vector(g_width-1 downto 0);
local_utc_i : in std_logic_vector(g_width-1 downto 0);
retrig_nb_offset_i : in std_logic_vector(g_width-1 downto 0);
wr_pointer_o : out std_logic_vector(g_width-1 downto 0)
wr_index_o : out std_logic_vector(g_width-1 downto 0)
);
end data_formatting;
......@@ -78,7 +78,6 @@ signal acam_fine_timestamp : std_logic_vector(16 downto 0);
signal acam_slope : std_logic;
signal acam_start_nb : std_logic_vector(7 downto 0);
signal clk : std_logic;
signal reset : std_logic;
signal clk_cycles_offset : std_logic_vector(g_width-1 downto 0);
signal current_roll_over : std_logic_vector(g_width-1 downto 0);
......@@ -98,9 +97,10 @@ signal local_utc : std_logic_vector(g_width-1 downto 0);
signal coarse_time : std_logic_vector(g_width-1 downto 0);
signal fine_time : std_logic_vector(g_width-1 downto 0);
signal clear_dacapo_flag : std_logic;
signal dacapo_flag : std_logic;
signal wr_pointer : unsigned(g_width-1 downto 0);
signal clear_dacapo_counter : std_logic;
signal dacapo_counter : unsigned(g_width-13 downto 0);
signal wr_pointer : unsigned(7 downto 0);
constant address_128bit_shift : std_logic_vector(3 downto 0):= x"0";
signal mem_ack : std_logic;
signal mem_data_rd : std_logic_vector(4*g_width-1 downto 0);
......@@ -151,16 +151,17 @@ begin
wait until clk ='1';
end process;
-- the Da Capo flag indicates if the circular buffer has been written completely
-- the Da Capo counter indicates the number of times the circular buffer has been written completely
-- it is cleared by the PCIe host.
dacapo_flag_update: process
dacapo_counter_update: process
begin
if reset ='1' then
dacapo_flag <= '0';
elsif clear_dacapo_flag ='1' then
dacapo_flag <= '0';
elsif wr_pointer = buff_size - 1 then
dacapo_flag <= '1';
dacapo_counter <= (others=>'0');
elsif clear_dacapo_counter ='1' then
dacapo_counter <= (others=>'0');
elsif mem_cyc ='1' and mem_stb ='1' and mem_we ='1' and mem_ack ='1'
and wr_pointer = buff_size - 1 then
dacapo_counter <= dacapo_counter + 1;
end if;
wait until clk ='1';
end process;
......@@ -194,7 +195,7 @@ begin
wait until clk ='1';
end process;
mem_adr <= std_logic_vector(wr_pointer);
mem_adr <= x"000000" & std_logic_vector(wr_pointer);
mem_data_wr <= full_timestamp;
-- the full timestamp is a 128-bits word divided in four 32-bits words
......@@ -262,8 +263,7 @@ begin
acam_timestamp2 <= acam_timestamp2_i;
acam_timestamp2_valid <= acam_timestamp2_valid_i;
clk <= clk_i;
clear_dacapo_flag <= clear_dacapo_flag_i;
clear_dacapo_counter <= clear_dacapo_counter_i;
reset <= reset_i;
clk_cycles_offset <= clk_cycles_offset_i;
retrig_nb_offset <= retrig_nb_offset_i;
......@@ -273,8 +273,9 @@ begin
mem_data_rd <= dat_i;
-- outputs
wr_pointer_o <= dacapo_flag & std_logic_vector(wr_pointer(g_width-6 downto 0)) & x"0";
-- wr_pointer_o <= dacapo_flag & std_logic_vector(wr_pointer(g_width-6 downto 0)) & x"0";
wr_index_o <= std_logic_vector(dacapo_counter) & std_logic_vector(wr_pointer) & address_128bit_shift;
adr_o <= mem_adr;
cyc_o <= mem_cyc;
dat_o <= mem_data_wr;
......
hdl/spec/src/rtl/one_hz_gen.vhd
View file @ 17667554
......@@ -29,19 +29,19 @@ use work.tdc_core_pkg.all;
----------------------------------------------------------------------------------------------------
entity one_hz_gen is
generic(
g_width : integer :=32
g_width : integer :=32
);
port(
acam_refclk_i : in std_logic;
clk_i : in std_logic;
clock_period_i : in std_logic_vector(g_width-1 downto 0); -- nb of clock periods for 1s
load_utc_i : in std_logic;
pulse_delay_i : in std_logic_vector(g_width-1 downto 0); -- nb of clock periods phase delay
reset_i : in std_logic; -- with respect to reference clock
starting_utc_i : in std_logic_vector(g_width-1 downto 0);
local_utc_o : out std_logic_vector(g_width-1 downto 0);
one_hz_p_o : out std_logic
acam_refclk_edge_p_i : in std_logic;
clk : in std_logic;
clock_period_i : in std_logic_vector(g_width-1 downto 0); -- nb of clock periods for 1s
load_utc_i : in std_logic;
pulse_delay_i : in std_logic_vector(g_width-1 downto 0); -- nb of clock periods phase delay
reset_i : in std_logic; -- with respect to reference clock
starting_utc_i : in std_logic_vector(g_width-1 downto 0);
local_utc_o : out std_logic_vector(g_width-1 downto 0);
one_hz_p_o : out std_logic
);
end one_hz_gen;
......@@ -52,47 +52,45 @@ architecture rtl of one_hz_gen is
component free_counter
generic(
width : integer :=32
width : integer :=32
);
port(
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
start_value : in std_logic_vector(width-1 downto 0);
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
start_value : in std_logic_vector(width-1 downto 0);
count_done : out std_logic;
current_value : out std_logic_vector(width-1 downto 0)
count_done : out std_logic;
current_value : out std_logic_vector(width-1 downto 0)
);
end component;
component countdown_counter
generic(
width : integer :=32
width : integer :=32
);
port(
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
start_value : in std_logic_vector(width-1 downto 0);
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
start_value : in std_logic_vector(width-1 downto 0);
count_done : out std_logic;
current_value : out std_logic_vector(width-1 downto 0)
count_done : out std_logic;
current_value : out std_logic_vector(width-1 downto 0)
);
end component;
constant constant_delay : unsigned(g_width-1 downto 0):=x"00000004";
constant constant_delay : unsigned(g_width-1 downto 0):=x"00000004";
signal clk : std_logic;
signal local_utc : unsigned(g_width-1 downto 0);
signal load_utc : std_logic;
signal one_hz_p_pre : std_logic;
signal one_hz_p_post : std_logic;
signal onesec_counter_en : std_logic;
signal refclk_edge : std_logic;
signal reset : std_logic;
signal s_acam_refclk : unsigned(3 downto 0);
signal starting_utc : std_logic_vector(g_width-1 downto 0);
signal total_delay : std_logic_vector(g_width-1 downto 0);
signal local_utc : unsigned(g_width-1 downto 0);
signal load_utc : std_logic;
signal one_hz_p_pre : std_logic;
signal one_hz_p_post : std_logic;
signal onesec_counter_en : std_logic;
signal acam_refclk_edge_p : std_logic;
signal reset : std_logic;
signal starting_utc : std_logic_vector(g_width-1 downto 0);
signal total_delay : std_logic_vector(g_width-1 downto 0);
----------------------------------------------------------------------------------------------------
......@@ -102,37 +100,37 @@ begin
clock_periods_counter: free_counter
generic map(
width => g_width
width => g_width
)
port map(
clk => clk_i,
enable => onesec_counter_en,
reset => reset_i,
start_value => clock_period_i,
clk => clk,
enable => onesec_counter_en,
reset => reset_i,
start_value => clock_period_i,
count_done => one_hz_p_pre,
current_value => open
count_done => one_hz_p_pre,
current_value => open
);
pulse_delayer_counter: countdown_counter
generic map(
width => g_width
width => g_width
)
port map(
clk => clk_i,
reset => reset_i,
start => one_hz_p_pre,
start_value => total_delay,
clk => clk,
reset => reset_i,
start => one_hz_p_pre,
start_value => total_delay,
count_done => one_hz_p_post,
current_value => open
count_done => one_hz_p_post,
current_value => open
);
onesec_trigger: process
begin
if reset ='1' then
onesec_counter_en <= '0';
elsif refclk_edge ='1' then
elsif acam_refclk_edge_p ='1' then
onesec_counter_en <= '1';
end if;
wait until clk ='1';
......@@ -141,42 +139,26 @@ begin
utc_counter: process
begin
if reset ='1' then
local_utc <= (others=>'0');
local_utc <= (others=>'0');
elsif load_utc ='1' then
local_utc <= unsigned(starting_utc);
local_utc <= unsigned(starting_utc);
elsif one_hz_p_post ='1' then
local_utc <= local_utc + 1;
local_utc <= local_utc + 1;
end if;
wait until clk ='1';
end process;
refclk_edge <= not(s_acam_refclk(3)) and
s_acam_refclk(2) and
s_acam_refclk(1) and
not(s_acam_refclk(0));
total_delay <= std_logic_vector(unsigned(pulse_delay_i)+constant_delay);
total_delay <= std_logic_vector(unsigned(pulse_delay_i)+constant_delay);
-- inputs
sync_acam_refclk: process
begin
if reset ='1' then
s_acam_refclk <= (others=>'0');
else
s_acam_refclk <= shift_right(s_acam_refclk,1);
s_acam_refclk(3) <= acam_refclk_i;
end if;
wait until clk ='1';
end process;
acam_refclk_edge_p <= acam_refclk_edge_p_i;
reset <= reset_i;
load_utc <= load_utc_i;
starting_utc <= starting_utc_i;
clk <= clk_i;
reset <= reset_i;
load_utc <= load_utc_i;
starting_utc <= starting_utc_i;
-- output
local_utc_o <= std_logic_vector(local_utc);
one_hz_p_o <= one_hz_p_post;
local_utc_o <= std_logic_vector(local_utc);
one_hz_p_o <= one_hz_p_post;
end rtl;
----------------------------------------------------------------------------------------------------
......
hdl/spec/src/rtl/reg_ctrl.vhd
View file @ 17667554
......@@ -28,52 +28,52 @@ use work.tdc_core_pkg.all;
----------------------------------------------------------------------------------------------------
entity reg_ctrl is
generic(
g_span : integer :=32;
g_width : integer :=32
g_span : integer :=32;
g_width : integer :=32
);
port(
-- wishbone classic slave signals to interface with the host through the gnum core and the gnum chip
reg_clk_i : in std_logic;
reg_reset_i : in std_logic;
clk : in std_logic;
reg_reset_i : in std_logic;
reg_adr_i : in std_logic_vector(g_span-1 downto 0);
reg_cyc_i : in std_logic;
reg_dat_i : in std_logic_vector(g_width-1 downto 0);
reg_stb_i : in std_logic;
reg_we_i : in std_logic;
reg_adr_i : in std_logic_vector(g_span-1 downto 0);
reg_cyc_i : in std_logic;
reg_dat_i : in std_logic_vector(g_width-1 downto 0);
reg_stb_i : in std_logic;
reg_we_i : in std_logic;
reg_ack_o : out std_logic;
reg_dat_o : out std_logic_vector(g_width-1 downto 0);
reg_ack_o : out std_logic;
reg_dat_o : out std_logic_vector(g_width-1 downto 0);
-- control signals for interface with other internal modules
activate_acq_o : out std_logic;
deactivate_acq_o : out std_logic;
load_acam_config_o : out std_logic;
read_acam_config_o : out std_logic;
read_acam_status_o : out std_logic;
read_ififo1_o : out std_logic;
read_ififo2_o : out std_logic;
read_start01_o : out std_logic;
reset_acam_o : out std_logic;
load_utc_o : out std_logic;
clear_dacapo_flag_o : out std_logic;
activate_acq_o : out std_logic;
deactivate_acq_o : out std_logic;
load_acam_config_o : out std_logic;
read_acam_config_o : out std_logic;
read_acam_status_o : out std_logic;
read_ififo1_o : out std_logic;
read_ififo2_o : out std_logic;
read_start01_o : out std_logic;
reset_acam_o : out std_logic;
load_utc_o : out std_logic;
clear_dacapo_counter_o : out std_logic;
-- configuration registers from and for the ACAM and the modules of the TDC core
acam_config_rdbk_i : in config_vector;
acam_status_i : in std_logic_vector(g_width-1 downto 0);
acam_ififo1_i : in std_logic_vector(g_width-1 downto 0);
acam_ififo2_i : in std_logic_vector(g_width-1 downto 0);
acam_start01_i : in std_logic_vector(g_width-1 downto 0);
local_utc_i : in std_logic_vector(g_width-1 downto 0);
irq_code_i : in std_logic_vector(g_width-1 downto 0);
core_status_i : in std_logic_vector(g_width-1 downto 0);
wr_pointer_i : in std_logic_vector(g_width-1 downto 0);
acam_config_o : out config_vector;
starting_utc_o : out std_logic_vector(g_width-1 downto 0);
in_en_ctrl_o : out std_logic_vector(g_width-1 downto 0);
start_phase_o : out std_logic_vector(g_width-1 downto 0);
one_hz_phase_o : out std_logic_vector(g_width-1 downto 0)
acam_config_rdbk_i : in config_vector;
acam_status_i : in std_logic_vector(g_width-1 downto 0);
acam_ififo1_i : in std_logic_vector(g_width-1 downto 0);
acam_ififo2_i : in std_logic_vector(g_width-1 downto 0);
acam_start01_i : in std_logic_vector(g_width-1 downto 0);
local_utc_i : in std_logic_vector(g_width-1 downto 0);
irq_code_i : in std_logic_vector(g_width-1 downto 0);
wr_index_i : in std_logic_vector(g_width-1 downto 0);
core_status_i : in std_logic_vector(g_width-1 downto 0);
acam_config_o : out config_vector;
starting_utc_o : out std_logic_vector(g_width-1 downto 0);
in_en_ctrl_o : out std_logic_vector(g_width-1 downto 0);
start_phase_o : out std_logic_vector(g_width-1 downto 0);
one_hz_phase_o : out std_logic_vector(g_width-1 downto 0)
);
end reg_ctrl;
......@@ -82,35 +82,34 @@ end reg_ctrl;
----------------------------------------------------------------------------------------------------
architecture rtl of reg_ctrl is
signal reg_ack : std_logic;
signal reg_adr : std_logic_vector(7 downto 0);
signal reg_clk : std_logic;
signal reg_cyc : std_logic;
signal reg_data_rd : std_logic_vector(g_width-1 downto 0);
signal reg_data_wr : std_logic_vector(g_width-1 downto 0);
signal reg_en : std_logic;
signal reg_reset : std_logic;
signal reg_stb : std_logic;
signal reg_we : std_logic;
signal acam_config_rdbk : config_vector;
signal acam_status : std_logic_vector(g_width-1 downto 0);
signal acam_ififo1 : std_logic_vector(g_width-1 downto 0);
signal acam_ififo2 : std_logic_vector(g_width-1 downto 0);
signal acam_start01 : std_logic_vector(g_width-1 downto 0);
signal core_status : std_logic_vector(g_width-1 downto 0);
signal irq_code : std_logic_vector(g_width-1 downto 0);
signal local_utc : std_logic_vector(g_width-1 downto 0);
signal wr_pointer : std_logic_vector(g_width-1 downto 0);
signal acam_config : config_vector;
signal starting_utc : std_logic_vector(g_width-1 downto 0);
signal in_en_ctrl : std_logic_vector(g_width-1 downto 0);
signal start_phase : std_logic_vector(g_width-1 downto 0);
signal one_hz_phase : std_logic_vector(g_width-1 downto 0);
signal control_register : std_logic_vector(g_width-1 downto 0);
signal clear_ctrl_reg : std_logic;
signal reg_ack : std_logic;
signal reg_adr : std_logic_vector(7 downto 0);
signal reg_cyc : std_logic;
signal reg_data_rd : std_logic_vector(g_width-1 downto 0);
signal reg_data_wr : std_logic_vector(g_width-1 downto 0);
signal reg_en : std_logic;
signal reg_reset : std_logic;
signal reg_stb : std_logic;
signal reg_we : std_logic;
signal acam_config_rdbk : config_vector;
signal acam_status : std_logic_vector(g_width-1 downto 0);
signal acam_ififo1 : std_logic_vector(g_width-1 downto 0);
signal acam_ififo2 : std_logic_vector(g_width-1 downto 0);
signal acam_start01 : std_logic_vector(g_width-1 downto 0);
signal core_status : std_logic_vector(g_width-1 downto 0);
signal irq_code : std_logic_vector(g_width-1 downto 0);
signal local_utc : std_logic_vector(g_width-1 downto 0);
signal wr_index : std_logic_vector(g_width-1 downto 0);
signal acam_config : config_vector;
signal starting_utc : std_logic_vector(g_width-1 downto 0);
signal in_en_ctrl : std_logic_vector(g_width-1 downto 0);
signal start_phase : std_logic_vector(g_width-1 downto 0);
signal one_hz_phase : std_logic_vector(g_width-1 downto 0);
signal control_register : std_logic_vector(g_width-1 downto 0);
signal clear_ctrl_reg : std_logic;
----------------------------------------------------------------------------------------------------
-- architecture begins
......@@ -121,105 +120,105 @@ begin
csr_interface: process
begin
if reg_reset ='1' then
reg_ack <= '0';
reg_ack <= '0';
else
reg_ack <= reg_stb and reg_cyc;
reg_ack <= reg_stb and reg_cyc;
end if;
wait until reg_clk ='1';
wait until clk ='1';
end process;
-- config registers for ACAM
acam_config_reg: process
begin
if reg_reset ='1' then
acam_config(0) <= (others =>'0');
acam_config(1) <= (others =>'0');
acam_config(2) <= (others =>'0');
acam_config(3) <= (others =>'0');
acam_config(4) <= (others =>'0');
acam_config(5) <= (others =>'0');
acam_config(6) <= (others =>'0');
acam_config(7) <= (others =>'0');
acam_config(8) <= (others =>'0');
acam_config(9) <= (others =>'0');
acam_config(10) <= (others =>'0');
acam_config(0) <= (others =>'0');
acam_config(1) <= (others =>'0');
acam_config(2) <= (others =>'0');
acam_config(3) <= (others =>'0');
acam_config(4) <= (others =>'0');
acam_config(5) <= (others =>'0');
acam_config(6) <= (others =>'0');
acam_config(7) <= (others =>'0');
acam_config(8) <= (others =>'0');
acam_config(9) <= (others =>'0');
acam_config(10) <= (others =>'0');
elsif reg_cyc ='1' and reg_stb ='1' and reg_we ='1' then
if reg_adr = x"00" then -- corresponds to address 80000 of the gnum BAR 0
acam_config(0) <= reg_data_wr;
if reg_adr = c_acam_adr_reg0 then
acam_config(0) <= reg_data_wr;
end if;
if reg_adr = x"01" then -- corresponds to address 80004 of the gnum BAR 00
acam_config(1) <= reg_data_wr;
if reg_adr = c_acam_adr_reg1 then
acam_config(1) <= reg_data_wr;
end if;
if reg_adr = x"02" then -- corresponds to address 80008 of the gnum BAR 0
acam_config(2) <= reg_data_wr;
if reg_adr = c_acam_adr_reg2 then
acam_config(2) <= reg_data_wr;
end if;
if reg_adr = x"03" then -- corresponds to address 8000C of the gnum BAR 0
acam_config(3) <= reg_data_wr;
if reg_adr = c_acam_adr_reg3 then
acam_config(3) <= reg_data_wr;
end if;
if reg_adr = x"04" then -- corresponds to address 80010 of the gnum BAR 0
acam_config(4) <= reg_data_wr;
if reg_adr = c_acam_adr_reg4 then
acam_config(4) <= reg_data_wr;
end if;
if reg_adr = x"05" then -- corresponds to address 80014 of the gnum BAR 0
acam_config(5) <= reg_data_wr;
if reg_adr = c_acam_adr_reg5 then
acam_config(5) <= reg_data_wr;
end if;
if reg_adr = x"06" then -- corresponds to address 80018 of the gnum BAR 0
acam_config(6) <= reg_data_wr;
if reg_adr = c_acam_adr_reg6 then
acam_config(6) <= reg_data_wr;
end if;
if reg_adr = x"07" then -- corresponds to address 8001C of the gnum BAR 0
acam_config(7) <= reg_data_wr;
if reg_adr = c_acam_adr_reg7 then
acam_config(7) <= reg_data_wr;
end if;
if reg_adr = x"0B" then -- corresponds to address 8002C of the gnum BAR 0
acam_config(8) <= reg_data_wr;
if reg_adr = c_acam_adr_reg11 then
acam_config(8) <= reg_data_wr;
end if;
if reg_adr = x"0C" then -- corresponds to address 80030 of the gnum BAR 0
acam_config(9) <= reg_data_wr;
if reg_adr = c_acam_adr_reg12 then
acam_config(9) <= reg_data_wr;
end if;
if reg_adr = x"0E" then -- corresponds to address 80038 of the gnum BAR 0
acam_config(10) <= reg_data_wr;
if reg_adr = c_acam_adr_reg14 then
acam_config(10) <= reg_data_wr;
end if;
end if;
wait until reg_clk ='1';
wait until clk ='1';
end process;
-- config registers for TDC core
core_config_reg: process
begin
if reg_reset ='1' then
starting_utc <= (others =>'0');
in_en_ctrl <= (others =>'0');
start_phase <= (others =>'0');
one_hz_phase <= (others =>'0');
starting_utc <= (others =>'0');
in_en_ctrl <= (others =>'0');
start_phase <= (others =>'0');
one_hz_phase <= (others =>'0');
elsif reg_cyc ='1' and reg_stb ='1' and reg_we ='1' then
if reg_adr = x"20" then -- corresponds to address 80080 of the gnum BAR 0
if reg_adr = c_starting_utc_adr then
starting_utc <= reg_data_wr;
end if;
if reg_adr = x"21" then -- corresponds to address 80084 of the gnum BAR 0
if reg_adr = c_in_en_ctrl_adr then
in_en_ctrl <= reg_data_wr;
end if;
if reg_adr = x"22" then -- corresponds to address 80088 of the gnum BAR 0
if reg_adr = c_start_phase_adr then
start_phase <= reg_data_wr;
end if;
if reg_adr = x"23" then -- corresponds to address 8008C of the gnum BAR 0
if reg_adr = c_one_hz_phase_adr then
one_hz_phase <= reg_data_wr;
end if;
end if;
wait until reg_clk ='1';
wait until clk ='1';
end process;
-- control register for TDC core:
......@@ -238,62 +237,61 @@ begin
clear_ctrl_reg <= '0';
elsif reg_cyc ='1' and reg_stb ='1' and reg_we ='1' then
if reg_adr = x"3F" then -- corresponds to address 800FC of the gnum BAR 0
if reg_adr = c_control_register_adr then
control_register <= reg_data_wr;
clear_ctrl_reg <= '1';
end if;
end if;
wait until reg_clk ='1';
wait until clk ='1';
end process;
-- All control and status registers read back
with reg_adr select
reg_data_rd <= acam_config(0) when x"00",
acam_config(1) when x"01",
acam_config(2) when x"02",
acam_config(3) when x"03",
acam_config(4) when x"04",
acam_config(5) when x"05",
acam_config(6) when x"06",
acam_config(7) when x"07",
acam_config(8) when x"0B",
acam_config(9) when x"0C",
acam_config(10) when x"0E",
reg_data_rd <= acam_config(0) when c_acam_adr_reg0,
acam_config(1) when c_acam_adr_reg1,
acam_config(2) when c_acam_adr_reg2,
acam_config(3) when c_acam_adr_reg3,
acam_config(4) when c_acam_adr_reg4,
acam_config(5) when c_acam_adr_reg5,
acam_config(6) when c_acam_adr_reg6,
acam_config(7) when c_acam_adr_reg7,
acam_config(8) when c_acam_adr_reg11,
acam_config(9) when c_acam_adr_reg12,
acam_config(10) when c_acam_adr_reg14,
acam_config_rdbk(0) when x"10",
acam_config_rdbk(1) when x"11",
acam_config_rdbk(2) when x"12",
acam_config_rdbk(3) when x"13",
acam_config_rdbk(4) when x"14",
acam_config_rdbk(5) when x"15",
acam_config_rdbk(6) when x"16",
acam_config_rdbk(7) when x"17",
acam_ififo1 when x"18",
acam_ififo2 when x"19",
acam_start01 when x"1A",
acam_config_rdbk(8) when x"1B",
acam_config_rdbk(9) when x"1C",
acam_config_rdbk(10) when x"1E",
acam_config_rdbk(0) when c_acam_adr_reg0_rdbk,
acam_config_rdbk(1) when c_acam_adr_reg1_rdbk,
acam_config_rdbk(2) when c_acam_adr_reg2_rdbk,
acam_config_rdbk(3) when c_acam_adr_reg3_rdbk,
acam_config_rdbk(4) when c_acam_adr_reg4_rdbk,
acam_config_rdbk(5) when c_acam_adr_reg5_rdbk,
acam_config_rdbk(6) when c_acam_adr_reg6_rdbk,
acam_config_rdbk(7) when c_acam_adr_reg7_rdbk,
acam_ififo1 when c_acam_adr_reg8_rdbk,
acam_ififo2 when c_acam_adr_reg9_rdbk,
acam_start01 when c_acam_adr_reg10_rdbk,
acam_config_rdbk(8) when c_acam_adr_reg11_rdbk,
acam_config_rdbk(9) when c_acam_adr_reg12_rdbk,
acam_config_rdbk(10) when c_acam_adr_reg14_rdbk,
starting_utc when x"20",
in_en_ctrl when x"21",
start_phase when x"22",
one_hz_phase when x"23",
starting_utc when c_starting_utc_adr,
in_en_ctrl when c_in_en_ctrl_adr,
start_phase when c_start_phase_adr,
one_hz_phase when c_one_hz_phase_adr,
-- RESERVED when x"24",
local_utc when x"25",
irq_code when x"26",
wr_pointer when x"27",
core_status when x"28",
local_utc when c_local_utc_adr,
irq_code when c_irq_code_adr,
wr_index when c_wr_index_adr,
core_status when c_core_status_adr,
x"FFFFFFFF" when others;
-- inputs
reg_clk <= reg_clk_i;
reg_reset <= reg_reset_i;
reg_adr <= reg_adr_i(7 downto 0);
......@@ -311,7 +309,7 @@ begin
local_utc <= local_utc_i;
irq_code <= irq_code_i;
wr_pointer <= wr_pointer_i;
wr_index <= wr_index_i;
core_status <= core_status_i;
-- outputs
......@@ -329,7 +327,7 @@ begin
read_start01_o <= control_register(7);
reset_acam_o <= control_register(8);
load_utc_o <= control_register(9);
clear_dacapo_flag_o <= control_register(10);
clear_dacapo_counter_o <= control_register(10);
starting_utc_o <= starting_utc;
in_en_ctrl_o <= in_en_ctrl;
......
hdl/spec/src/rtl/start_retrigger_control.vhd
View file @ 17667554
......@@ -36,7 +36,7 @@ entity start_retrigger_control is
port(
acam_rise_intflag_p_i : in std_logic;
acam_fall_intflag_p_i : in std_logic;
clk_i : in std_logic;
clk : in std_logic;
one_hz_p_i : in std_logic;
reset_i : in std_logic;
retrig_period_i : in std_logic_vector(g_width-1 downto 0);
......@@ -85,7 +85,6 @@ architecture rtl of start_retrigger_control is
signal acam_fall_intflag_p : std_logic;
signal acam_rise_intflag_p : std_logic;
signal add_roll_over : std_logic;
signal clk : std_logic;
signal clk_cycles_offset : std_logic_vector(g_width-1 downto 0);
signal current_cycles : std_logic_vector(g_width-1 downto 0);
signal current_retrig_nb : std_logic_vector(g_width-1 downto 0);
......@@ -99,9 +98,6 @@ signal retrig_period_reset : std_logic;
signal roll_over_reset : std_logic;
signal roll_over_value : std_logic_vector(g_width-1 downto 0);
signal acam_halfcounter_gone : std_logic;
----------------------------------------------------------------------------------------------------
-- architecture begins
----------------------------------------------------------------------------------------------------
......@@ -176,7 +172,6 @@ begin
-- inputs
acam_fall_intflag_p <= acam_fall_intflag_p_i;
acam_rise_intflag_p <= acam_rise_intflag_p_i;
clk <= clk_i;
one_hz_p <= one_hz_p_i;
reset <= reset_i;
retrig_period <= retrig_period_i;
......
hdl/spec/src/rtl/tdc_core_pkg.vhd
View file @ 17667554
......@@ -70,17 +70,72 @@ package tdc_core_pkg is
current_value : out std_logic_vector(width-1 downto 0)
);
end component;
constant data_width : integer:=32;
constant tdc_led_period_sim : std_logic_vector(data_width-1 downto 0):=x"0000F424"; -- 500 us at 125 MHz
constant tdc_led_period_syn : std_logic_vector(data_width-1 downto 0):=x"03B9ACA0"; -- 500 ms at 125 MHz
constant spec_led_period_sim : std_logic_vector(data_width-1 downto 0):=x"00004E20"; -- 1 ms at 20 MHz
constant spec_led_period_syn : std_logic_vector(data_width-1 downto 0):=x"01312D00"; -- 1 s at 20 MHz
constant blink_length_syn : std_logic_vector(data_width-1 downto 0):=x"00BEBC20"; -- 100 ms at 125 MHz
constant blink_length_sim : std_logic_vector(data_width-1 downto 0):=x"000004E2"; -- 10 us at 125 MHz
subtype config_register is std_logic_vector(data_width-1 downto 0);
type config_vector is array (10 downto 0) of config_register;
constant data_width : integer:=32;
constant tdc_led_period_sim : std_logic_vector(data_width-1 downto 0):=x"0000F424"; -- 500 us at 125 MHz
constant tdc_led_period_syn : std_logic_vector(data_width-1 downto 0):=x"03B9ACA0"; -- 500 ms at 125 MHz
constant spec_led_period_sim : std_logic_vector(data_width-1 downto 0):=x"00004E20"; -- 1 ms at 20 MHz
constant spec_led_period_syn : std_logic_vector(data_width-1 downto 0):=x"01312D00"; -- 1 s at 20 MHz
constant blink_length_syn : std_logic_vector(data_width-1 downto 0):=x"00BEBC20"; -- 100 ms at 125 MHz
constant blink_length_sim : std_logic_vector(data_width-1 downto 0):=x"000004E2"; -- 10 us at 125 MHz
subtype config_register is std_logic_vector(data_width-1 downto 0);
type config_vector is array (10 downto 0) of config_register;
-- Addresses of ACAM registers to be written from the PCI-e host for configuration
constant c_acam_adr_reg0 : std_logic_vector(7 downto 0):= x"00"; -- corresponds to address 80000 of the gnum BAR 0
constant c_acam_adr_reg1 : std_logic_vector(7 downto 0):= x"01"; -- corresponds to address 80004 of the gnum BAR 0
constant c_acam_adr_reg2 : std_logic_vector(7 downto 0):= x"02"; -- corresponds to address 80008 of the gnum BAR 0
constant c_acam_adr_reg3 : std_logic_vector(7 downto 0):= x"03"; -- corresponds to address 8000C of the gnum BAR 0
constant c_acam_adr_reg4 : std_logic_vector(7 downto 0):= x"04"; -- corresponds to address 80010 of the gnum BAR 0
constant c_acam_adr_reg5 : std_logic_vector(7 downto 0):= x"05"; -- corresponds to address 80014 of the gnum BAR 0
constant c_acam_adr_reg6 : std_logic_vector(7 downto 0):= x"06"; -- corresponds to address 80018 of the gnum BAR 0
constant c_acam_adr_reg7 : std_logic_vector(7 downto 0):= x"07"; -- corresponds to address 8001C of the gnum BAR 0
constant c_acam_adr_reg11 : std_logic_vector(7 downto 0):= x"0B"; -- corresponds to address 8002C of the gnum BAR 0
constant c_acam_adr_reg12 : std_logic_vector(7 downto 0):= x"0C"; -- corresponds to address 80030 of the gnum BAR 0
constant c_acam_adr_reg14 : std_logic_vector(7 downto 0):= x"0E"; -- corresponds to address 80038 of the gnum BAR 0
-- Addresses of ACAM read-only register (used within the core to access ACAM timestamps)
constant c_acam_adr_reg8 : std_logic_vector(7 downto 0):= x"08"; -- not accessible for writing from PCI-e
constant c_acam_adr_reg9 : std_logic_vector(7 downto 0):= x"09"; -- not accessible for writing from PCI-e
constant c_acam_adr_reg10 : std_logic_vector(7 downto 0):= x"0A"; -- not accessible for writing from PCI-e
-- Addresses of ACAM registers readback
constant c_acam_adr_reg0_rdbk : std_logic_vector(7 downto 0):= x"10"; -- corresponds to address 80040 of the gnum BAR 0
constant c_acam_adr_reg1_rdbk : std_logic_vector(7 downto 0):= x"11"; -- corresponds to address 80044 of the gnum BAR 0
constant c_acam_adr_reg2_rdbk : std_logic_vector(7 downto 0):= x"12"; -- corresponds to address 80048 of the gnum BAR 0
constant c_acam_adr_reg3_rdbk : std_logic_vector(7 downto 0):= x"13"; -- corresponds to address 8004C of the gnum BAR 0
constant c_acam_adr_reg4_rdbk : std_logic_vector(7 downto 0):= x"14"; -- corresponds to address 80050 of the gnum BAR 0
constant c_acam_adr_reg5_rdbk : std_logic_vector(7 downto 0):= x"15"; -- corresponds to address 80054 of the gnum BAR 0
constant c_acam_adr_reg6_rdbk : std_logic_vector(7 downto 0):= x"16"; -- corresponds to address 80058 of the gnum BAR 0
constant c_acam_adr_reg7_rdbk : std_logic_vector(7 downto 0):= x"17"; -- corresponds to address 8005C of the gnum BAR 0
constant c_acam_adr_reg8_rdbk : std_logic_vector(7 downto 0):= x"18"; -- corresponds to address 80060 of the gnum BAR 0
constant c_acam_adr_reg9_rdbk : std_logic_vector(7 downto 0):= x"19"; -- corresponds to address 80064 of the gnum BAR 0
constant c_acam_adr_reg10_rdbk : std_logic_vector(7 downto 0):= x"1A"; -- corresponds to address 80068 of the gnum BAR 0
constant c_acam_adr_reg11_rdbk : std_logic_vector(7 downto 0):= x"1B"; -- corresponds to address 8006C of the gnum BAR 0
constant c_acam_adr_reg12_rdbk : std_logic_vector(7 downto 0):= x"1C"; -- corresponds to address 80070 of the gnum BAR 0
constant c_acam_adr_reg14_rdbk : std_logic_vector(7 downto 0):= x"1E"; -- corresponds to address 80078 of the gnum BAR 0
-- Addresses of TDC core configuration registers
constant c_starting_utc_adr : std_logic_vector(7 downto 0):= x"20"; -- corresponds to address 80080 of the gnum BAR 0
constant c_in_en_ctrl_adr : std_logic_vector(7 downto 0):= x"21"; -- corresponds to address 80084 of the gnum BAR 0
constant c_start_phase_adr : std_logic_vector(7 downto 0):= x"22"; -- corresponds to address 80088 of the gnum BAR 0
constant c_one_hz_phase_adr : std_logic_vector(7 downto 0):= x"23"; -- corresponds to address 8008C of the gnum BAR 0
--constant c_irq_config_adr : std_logic_vector(7 downto 0):= x"24";
-- Addresses of TDC core status registers
constant c_local_utc_adr : std_logic_vector(7 downto 0):= x"25"; -- corresponds to address 80094 of the gnum BAR 0
constant c_irq_code_adr : std_logic_vector(7 downto 0):= x"26"; -- corresponds to address 80098 of the gnum BAR 0
constant c_wr_index_adr : std_logic_vector(7 downto 0):= x"27"; -- corresponds to address 8009C of the gnum BAR 0
constant c_core_status_adr : std_logic_vector(7 downto 0):= x"28"; -- corresponds to address 800A0 of the gnum BAR 0
-- Address of TDC core control register
constant c_control_register_adr : std_logic_vector(7 downto 0):= x"3F"; -- corresponds to address 800FC of the gnum BAR 0
end tdc_core_pkg;
......
hdl/spec/src/rtl/top_tdc.vhd
View file @ 17667554
......@@ -28,99 +28,99 @@ use work.gn4124_core_pkg.all;
----------------------------------------------------------------------------------------------------
entity top_tdc is
generic(
g_span : integer :=32;
g_width : integer :=32;
values_for_simulation : boolean :=FALSE
);
g_span : integer :=32; -- address span in bus interfaces
g_width : integer :=32; -- data width in bus interfaces
values_for_simulation : boolean :=FALSE -- this generic is set to TRUE
); -- when instantiated in a test-bench
port(
-- interface with GNUM
rst_n_a_i : in std_logic;
rst_n_a_i : in std_logic;
-- P2L Direction
p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
p2l_dframe_i: in std_logic; -- Receive Frame
p2l_valid_i : in std_logic; -- Receive Data Valid
p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
rx_error_o : out std_logic; -- Receive Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Virtual channel ready
p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_data_i : in std_logic_vector(15 downto 0);-- Parallel receive data
p2l_dframe_i : in std_logic; -- Receive Frame
p2l_valid_i : in std_logic; -- Receive Data Valid
p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
rx_error_o : out std_logic; -- Receive Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Virtual channel ready
-- L2P Direction
l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
l2p_dframe_o: out std_logic; -- Transmit Data Frame
l2p_valid_o : out std_logic; -- Transmit Data Valid
l2p_edb_o : out std_logic; -- Packet termination and discard
l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i: in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
spare_o : out std_logic;
l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
l2p_data_o : out std_logic_vector(15 downto 0);-- Parallel transmit data
l2p_dframe_o : out std_logic; -- Transmit Data Frame
l2p_valid_o : out std_logic; -- Transmit Data Valid
l2p_edb_o : out std_logic; -- Packet termination and discard
l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
spare_o : out std_logic;
-- interface signals with PLL circuit on TDC mezzanine
acam_refclk_i : in std_logic;
pll_ld_i : in std_logic;
pll_refmon_i : in std_logic;
pll_sdo_i : in std_logic;
pll_status_i : in std_logic;
tdc_clk_p_i : in std_logic;
tdc_clk_n_i : in std_logic;
acam_refclk_i : in std_logic; -- 31.25 MHz clock that is also received by ACAM
pll_ld_i : in std_logic; -- PLL AD9516 interface signals
pll_refmon_i : in std_logic; --
pll_sdo_i : in std_logic; --
pll_status_i : in std_logic; --
tdc_clk_p_i : in std_logic; -- 125 MHz differential clock : system clock
tdc_clk_n_i : in std_logic; --
pll_cs_o : out std_logic;
pll_dac_sync_o : out std_logic;
pll_sdi_o : out std_logic;
pll_sclk_o : out std_logic;
pll_cs_o : out std_logic; -- PLL AD9516 interface signals
pll_dac_sync_o : out std_logic; --
pll_sdi_o : out std_logic; --
pll_sclk_o : out std_logic; --
-- interface signals with acam (timing) on TDC mezzanine
err_flag_i : in std_logic;
int_flag_i : in std_logic;
err_flag_i : in std_logic; -- error flag signal coming from ACAM
int_flag_i : in std_logic; -- interrupt flag signal coming from ACAM
start_dis_o : out std_logic;
start_from_fpga_o : out std_logic;
stop_dis_o : out std_logic;
start_dis_o : out std_logic; -- start disable signal for ACAM
start_from_fpga_o : out std_logic; -- start signal for ACAM
stop_dis_o : out std_logic; -- stop disable signal for ACAM
-- interface signals with acam (data) on TDC mezzanine
data_bus_io : inout std_logic_vector(27 downto 0);
ef1_i : in std_logic;
ef2_i : in std_logic;
lf1_i : in std_logic;
lf2_i : in std_logic;
ef1_i : in std_logic; -- empty flag iFIFO1 signal from ACAM
ef2_i : in std_logic; -- empty flag iFIFO2 signal from ACAM
lf1_i : in std_logic; -- load flag iFIFO1 signal from ACAM
lf2_i : in std_logic; -- load flag iFIFO2 signal from ACAM
address_o : out std_logic_vector(3 downto 0);
cs_n_o : out std_logic;
oe_n_o : out std_logic;
rd_n_o : out std_logic;
wr_n_o : out std_logic;
cs_n_o : out std_logic; -- chip select for ACAM
oe_n_o : out std_logic; -- output enable for ACAM
rd_n_o : out std_logic; -- read signal for ACAM
wr_n_o : out std_logic; -- write signal for ACAM
-- other signals on the TDC mezzanine
tdc_in_fpga_5_i : in std_logic;
mute_inputs_o : out std_logic;
tdc_led_status_o : out std_logic;
tdc_led_trig1_o : out std_logic;
tdc_led_trig2_o : out std_logic;
tdc_led_trig3_o : out std_logic;
tdc_led_trig4_o : out std_logic;
tdc_led_trig5_o : out std_logic;
term_en_1_o : out std_logic;
term_en_2_o : out std_logic;
term_en_3_o : out std_logic;
term_en_4_o : out std_logic;
term_en_5_o : out std_logic;
tdc_in_fpga_5_i : in std_logic; -- input 5 for ACAM is also received by FPGA
-- all 4 other stop inputs are miss-routed on PCB
mute_inputs_o : out std_logic; -- controls all 5 inputs (actual function: ENABLE)
tdc_led_status_o : out std_logic; -- amber led on front pannel
tdc_led_trig1_o : out std_logic; -- amber leds on front pannel
tdc_led_trig2_o : out std_logic; --
tdc_led_trig3_o : out std_logic; --
tdc_led_trig4_o : out std_logic; --
tdc_led_trig5_o : out std_logic; --
term_en_1_o : out std_logic; -- enable of 50 Ohm termination inputs
term_en_2_o : out std_logic; --
term_en_3_o : out std_logic; --
term_en_4_o : out std_logic; --
term_en_5_o : out std_logic; --
-- other signals on the SPEC carrier
spec_aux0_i : in std_logic;
spec_aux1_i : in std_logic;
spec_aux2_o : out std_logic;
spec_aux3_o : out std_logic;
spec_aux4_o : out std_logic;
spec_aux5_o : out std_logic;
spec_led_green_o : out std_logic;
spec_led_red_o : out std_logic;
spec_clk_i : in std_logic
spec_aux0_i : in std_logic; -- buttons on spec card
spec_aux1_i : in std_logic; --
spec_aux2_o : out std_logic; -- red leds on spec PCB
spec_aux3_o : out std_logic; --
spec_aux4_o : out std_logic; --
spec_aux5_o : out std_logic; --
spec_led_green_o : out std_logic; -- green led on spec front pannel
spec_led_red_o : out std_logic; -- red led on spec front pannel
spec_clk_i : in std_logic -- 20 MHz clock from VCXO on spec card
);
end top_tdc;
......@@ -134,8 +134,8 @@ architecture rtl of top_tdc is
g_width : integer :=32
);
port(
acam_refclk_i : in std_logic;
clk_i : in std_logic;
acam_refclk_edge_p_i : in std_logic;
clk : in std_logic;
clock_period_i : in std_logic_vector(g_width-1 downto 0);
load_utc_i : in std_logic;
pulse_delay_i : in std_logic_vector(g_width-1 downto 0);
......@@ -161,8 +161,8 @@ architecture rtl of top_tdc is
stop_dis_o : out std_logic;
-- signals internal to the chip: interface with other modules
acam_refclk_i : in std_logic;
clk_i : in std_logic;
acam_refclk_edge_p_i : in std_logic;
clk : in std_logic;
start_trig_i : in std_logic;
reset_i : in std_logic;
window_delay_i : in std_logic_vector(g_width-1 downto 0);
......@@ -193,11 +193,13 @@ architecture rtl of top_tdc is
wr_n_o : out std_logic;
acam_ef1_o : out std_logic;
acam_ef1_meta_o : out std_logic;
acam_ef2_o : out std_logic;
acam_ef2_meta_o : out std_logic;
acam_lf1_o : out std_logic;
acam_lf2_o : out std_logic;
clk_i : in std_logic;
clk : in std_logic;
reset_i : in std_logic;
adr_i : in std_logic_vector(g_span-1 downto 0);
......@@ -218,7 +220,7 @@ architecture rtl of top_tdc is
port(
acam_rise_intflag_p_i : in std_logic;
acam_fall_intflag_p_i : in std_logic;
clk_i : in std_logic;
clk : in std_logic;
one_hz_p_i : in std_logic;
reset_i : in std_logic;
retrig_period_i : in std_logic_vector(g_width-1 downto 0);
......@@ -246,10 +248,12 @@ architecture rtl of top_tdc is
we_o : out std_logic;
-- signals internal to the chip: interface with other modules
clk_i : in std_logic;
clk : in std_logic;
reset_i : in std_logic;
acam_ef1_i : in std_logic;
acam_ef1_meta_i : in std_logic;
acam_ef2_i : in std_logic;
acam_ef2_meta_i : in std_logic;
activate_acq_i : in std_logic;
deactivate_acq_i : in std_logic;
......@@ -296,15 +300,15 @@ architecture rtl of top_tdc is
acam_timestamp1_valid_i : in std_logic;
acam_timestamp2_i : in std_logic_vector(g_width-1 downto 0);
acam_timestamp2_valid_i : in std_logic;
clk_i : in std_logic;
clear_dacapo_flag_i : in std_logic;
clk : in std_logic;
clear_dacapo_counter_i : in std_logic;
reset_i : in std_logic;
clk_cycles_offset_i : in std_logic_vector(g_width-1 downto 0);
current_roll_over_i : in std_logic_vector(g_width-1 downto 0);
local_utc_i : in std_logic_vector(g_width-1 downto 0);
retrig_nb_offset_i : in std_logic_vector(g_width-1 downto 0);
wr_pointer_o : out std_logic_vector(g_width-1 downto 0)
wr_index_o : out std_logic_vector(g_width-1 downto 0)
);
end component;
......@@ -315,7 +319,7 @@ architecture rtl of top_tdc is
);
port(
-- wishbone classic slave signals to interface RAM with the modules providing the timestamps
class_clk_i : in std_logic;
clk : in std_logic;
class_reset_i : in std_logic;
class_adr_i : in std_logic_vector(g_span-1 downto 0);
......@@ -328,7 +332,6 @@ architecture rtl of top_tdc is
class_dat_o : out std_logic_vector(4*g_width-1 downto 0);
-- wishbone pipelined slave signals to interface RAM with gnum core for DMA access from PCI-e
pipe_clk_i : in std_logic;
pipe_reset_i : in std_logic;
pipe_adr_i : in std_logic_vector(g_span-1 downto 0);
......@@ -350,47 +353,47 @@ architecture rtl of top_tdc is
);
port(
-- wishbone classic slave signals to interface with the host through the gnum core and the gnum chip
reg_clk_i : in std_logic;
reg_reset_i : in std_logic;
clk : in std_logic;
reg_reset_i : in std_logic;
reg_adr_i : in std_logic_vector(g_span-1 downto 0);
reg_cyc_i : in std_logic;
reg_dat_i : in std_logic_vector(g_width-1 downto 0);
reg_stb_i : in std_logic;
reg_we_i : in std_logic;
reg_adr_i : in std_logic_vector(g_span-1 downto 0);
reg_cyc_i : in std_logic;
reg_dat_i : in std_logic_vector(g_width-1 downto 0);
reg_stb_i : in std_logic;
reg_we_i : in std_logic;
reg_ack_o : out std_logic;
reg_dat_o : out std_logic_vector(g_width-1 downto 0);
reg_ack_o : out std_logic;
reg_dat_o : out std_logic_vector(g_width-1 downto 0);
-- control signals for interface with other internal modules
activate_acq_o : out std_logic;
deactivate_acq_o : out std_logic;
load_acam_config_o : out std_logic;
read_acam_config_o : out std_logic;
read_acam_status_o : out std_logic;
read_ififo1_o : out std_logic;
read_ififo2_o : out std_logic;
read_start01_o : out std_logic;
reset_acam_o : out std_logic;
load_utc_o : out std_logic;
clear_dacapo_flag_o : out std_logic;
activate_acq_o : out std_logic;
deactivate_acq_o : out std_logic;
load_acam_config_o : out std_logic;
read_acam_config_o : out std_logic;
read_acam_status_o : out std_logic;
read_ififo1_o : out std_logic;
read_ififo2_o : out std_logic;
read_start01_o : out std_logic;
reset_acam_o : out std_logic;
load_utc_o : out std_logic;
clear_dacapo_counter_o : out std_logic;
-- configuration registers from and for the ACAM and the modules of the TDC core
acam_config_rdbk_i : in config_vector;
acam_status_i : in std_logic_vector(g_width-1 downto 0);
acam_ififo1_i : in std_logic_vector(g_width-1 downto 0);
acam_ififo2_i : in std_logic_vector(g_width-1 downto 0);
acam_start01_i : in std_logic_vector(g_width-1 downto 0);
local_utc_i : in std_logic_vector(g_width-1 downto 0);
irq_code_i : in std_logic_vector(g_width-1 downto 0);
core_status_i : in std_logic_vector(g_width-1 downto 0);
wr_pointer_i : in std_logic_vector(g_width-1 downto 0);
acam_config_o : out config_vector;
starting_utc_o : out std_logic_vector(g_width-1 downto 0);
in_en_ctrl_o : out std_logic_vector(g_width-1 downto 0);
start_phase_o : out std_logic_vector(g_width-1 downto 0);
one_hz_phase_o : out std_logic_vector(g_width-1 downto 0)
acam_config_rdbk_i : in config_vector;
acam_status_i : in std_logic_vector(g_width-1 downto 0);
acam_ififo1_i : in std_logic_vector(g_width-1 downto 0);
acam_ififo2_i : in std_logic_vector(g_width-1 downto 0);
acam_start01_i : in std_logic_vector(g_width-1 downto 0);
local_utc_i : in std_logic_vector(g_width-1 downto 0);
irq_code_i : in std_logic_vector(g_width-1 downto 0);
core_status_i : in std_logic_vector(g_width-1 downto 0);
wr_index_i : in std_logic_vector(g_width-1 downto 0);
acam_config_o : out config_vector;
starting_utc_o : out std_logic_vector(g_width-1 downto 0);
in_en_ctrl_o : out std_logic_vector(g_width-1 downto 0);
start_phase_o : out std_logic_vector(g_width-1 downto 0);
one_hz_phase_o : out std_logic_vector(g_width-1 downto 0)
);
end component;
......@@ -410,7 +413,7 @@ architecture rtl of top_tdc is
tdc_clk_p_i : in std_logic;
tdc_clk_n_i : in std_logic;
acam_refclk_o : out std_logic;
acam_refclk_edge_p_o : out std_logic;
general_reset_o : out std_logic;
pll_cs_o : out std_logic;
pll_dac_sync_o : out std_logic;
......@@ -423,11 +426,11 @@ architecture rtl of top_tdc is
component gn4124_core
generic(
g_BAR0_APERTURE : integer := 20; -- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
g_BAR0_APERTURE : integer := 20; -- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
-- => number of bits to address periph on the board
g_CSR_WB_SLAVES_NB : integer := 1; -- Number of CSR wishbone slaves
g_DMA_WB_SLAVES_NB : integer := 1; -- Number of DMA wishbone slaves
g_DMA_WB_ADDR_WIDTH : integer := 26 -- DMA wishbone address bus width
g_CSR_WB_SLAVES_NB : integer := 1; -- Number of CSR wishbone slaves
g_DMA_WB_SLAVES_NB : integer := 1; -- Number of DMA wishbone slaves
g_DMA_WB_ADDR_WIDTH : integer := 26 -- DMA wishbone address bus width
);
port
(
......@@ -435,84 +438,87 @@ architecture rtl of top_tdc is
-- Control and status
--
-- Asynchronous reset from GN4124
rst_n_a_i : in std_logic;
rst_n_a_i : in std_logic;
-- P2L clock PLL locked
p2l_pll_locked : out std_logic;
p2l_pll_locked : out std_logic;
-- Debug ouputs
debug_o : out std_logic_vector(7 downto 0);
debug_o : out std_logic_vector(7 downto 0);
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
p2l_dframe_i : in std_logic; -- Receive Frame
p2l_valid_i : in std_logic; -- Receive Data Valid
p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
p2l_dframe_i : in std_logic; -- Receive Frame
p2l_valid_i : in std_logic; -- Receive Data Valid
-- P2L Control
p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
rx_error_o : out std_logic; -- Receive Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Virtual channel ready
p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
rx_error_o : out std_logic; -- Receive Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Virtual channel ready
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
l2p_dframe_o : out std_logic; -- Transmit Data Frame
l2p_valid_o : out std_logic; -- Transmit Data Valid
l2p_edb_o : out std_logic; -- Packet termination and discard
l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
l2p_dframe_o : out std_logic; -- Transmit Data Frame
l2p_valid_o : out std_logic; -- Transmit Data Valid
l2p_edb_o : out std_logic; -- Packet termination and discard
-- L2P Control
l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
---------------------------------------------------------
-- Interrupt interface
dma_irq_o : out std_logic_vector(1 downto 0); -- Interrupts sources to IRQ manager
irq_p_i : in std_logic; -- Interrupt request pulse from IRQ manager
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
dma_irq_o : out std_logic_vector(1 downto 0); -- Interrupts sources to IRQ manager
irq_p_i : in std_logic; -- Interrupt request pulse from IRQ manager
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
---------------------------------------------------------
-- Target interface (CSR wishbone master)
wb_clk_i : in std_logic;
wb_adr_o : out std_logic_vector(g_BAR0_APERTURE-log2_ceil(g_CSR_WB_SLAVES_NB+1)-1 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic;
wb_we_o : out std_logic;
wb_cyc_o : out std_logic_vector(g_CSR_WB_SLAVES_NB-1 downto 0);
wb_dat_i : in std_logic_vector((32*g_CSR_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_CSR_WB_SLAVES_NB-1 downto 0);
wb_clk_i : in std_logic;
wb_adr_o : out std_logic_vector(g_BAR0_APERTURE-log2_ceil(g_CSR_WB_SLAVES_NB+1)-1 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic;
wb_we_o : out std_logic;
wb_cyc_o : out std_logic_vector(g_CSR_WB_SLAVES_NB-1 downto 0);
wb_dat_i : in std_logic_vector((32*g_CSR_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_CSR_WB_SLAVES_NB-1 downto 0);
---------------------------------------------------------
-- DMA interface (Pipelined wishbone master)
dma_clk_i : in std_logic;
dma_adr_o : out std_logic_vector(31 downto 0);
dma_dat_o : out std_logic_vector(31 downto 0); -- Data out
dma_sel_o : out std_logic_vector(3 downto 0); -- Byte select
dma_stb_o : out std_logic;
dma_we_o : out std_logic;
dma_cyc_o : out std_logic; --_vector(g_DMA_WB_SLAVES_NB-1 downto 0);
dma_dat_i : in std_logic_vector((32*g_DMA_WB_SLAVES_NB)-1 downto 0); -- Data in
dma_ack_i : in std_logic; --_vector(g_DMA_WB_SLAVES_NB-1 downto 0);
dma_stall_i : in std_logic--_vector(g_DMA_WB_SLAVES_NB-1 downto 0) -- for pipelined Wishbone
dma_clk_i : in std_logic;
dma_adr_o : out std_logic_vector(31 downto 0);
dma_dat_o : out std_logic_vector(31 downto 0); -- Data out
dma_sel_o : out std_logic_vector(3 downto 0); -- Byte select
dma_stb_o : out std_logic;
dma_we_o : out std_logic;
dma_cyc_o : out std_logic; --_vector(g_DMA_WB_SLAVES_NB-1 downto 0);
dma_dat_i : in std_logic_vector((32*g_DMA_WB_SLAVES_NB)-1 downto 0); -- Data in
dma_ack_i : in std_logic; --_vector(g_DMA_WB_SLAVES_NB-1 downto 0);
dma_stall_i : in std_logic--_vector(g_DMA_WB_SLAVES_NB-1 downto 0) -- for pipelined Wishbone
);
end component;
--used to generate the one_hz_p pulse
--constant sim_clock_period : std_logic_vector(g_width-1 downto 0):=x"0000F424"; -- 500 us at 125 MHz (tdc board clock)
constant sim_clock_period : std_logic_vector(g_width-1 downto 0):=x"0001E848"; -- 1 ms at 125 MHz (tdc board clock)
constant syn_clock_period : std_logic_vector(g_width-1 downto 0):=x"07735940"; -- 1 s at 125 MHz (tdc board clock)
constant c_sim_clock_period : std_logic_vector(g_width-1 downto 0):=x"0001E848"; -- 1 ms at 125 MHz (tdc board clock)
constant c_syn_clock_period : std_logic_vector(g_width-1 downto 0):=x"07735940"; -- 1 s at 125 MHz (tdc board clock)
constant c_retrig_period : std_logic_vector(g_width-1 downto 0):= x"00000040";
constant c_retrig_period_shift : integer:=6;
constant retrig_period : std_logic_vector(g_width-1 downto 0):= x"00000040";
constant retrig_period_shift : integer:=6;
constant c_dma_userspace_baseadr: std_logic_vector(31 downto 0):= x"00000000";
constant c_csr_userspace_baseadr: std_logic_vector(18 downto 0):= "010" & x"0000";
signal spec_led_blink_done : std_logic;
signal spec_led_period_done : std_logic;
......@@ -525,6 +531,7 @@ signal window_delay : std_logic_vector(g_width-1 downto 0);
signal clock_period : std_logic_vector(g_width-1 downto 0);
signal gnum_reset : std_logic;
signal gnum_reset_r : std_logic;
signal spec_led_green : std_logic;
signal spec_led_red : std_logic;
......@@ -536,27 +543,25 @@ signal tdc_led_trig4 : std_logic;
signal tdc_led_trig5 : std_logic;
signal acam_ef1 : std_logic;
signal acam_ef1_meta : std_logic;
signal acam_ef2 : std_logic;
signal acam_ef2_meta : std_logic;
signal acam_lf1 : std_logic;
signal acam_lf2 : std_logic;
signal acam_fall_errflag_p : std_logic;
signal acam_rise_errflag_p : std_logic;
signal acam_fall_intflag_p : std_logic;
signal acam_rise_intflag_p : std_logic;
signal acam_refclk_edge_p : std_logic;
signal acam_timestamp1 : std_logic_vector(g_width-1 downto 0);
signal acam_timestamp1_valid : std_logic;
signal acam_timestamp2 : std_logic_vector(g_width-1 downto 0);
signal acam_timestamp2_valid : std_logic;
signal clear_dacapo_flag : std_logic;
signal core_status : std_logic_vector(g_width-1 downto 0);
signal clk_cycles_offset : std_logic_vector(g_width-1 downto 0);
signal current_roll_over : std_logic_vector(g_width-1 downto 0);
signal general_reset : std_logic;
signal one_hz_p : std_logic;
signal retrig_nb_offset : std_logic_vector(g_width-1 downto 0);
signal start_trig : std_logic;
signal local_utc : std_logic_vector(g_width-1 downto 0);
signal wr_pointer : std_logic_vector(g_width-1 downto 0);
signal acm_adr : std_logic_vector(g_span-1 downto 0);
signal acm_cyc : std_logic;
......@@ -615,29 +620,32 @@ signal reg_data_rd : std_logic_vector(g_width-1 downto 0);
signal activate_acq : std_logic;
signal deactivate_acq : std_logic;
signal load_utc : std_logic;
signal load_tdc_config : std_logic;
signal load_acam_config : std_logic;
signal read_acam_config : std_logic;
signal reset_acam : std_logic;
signal read_acam_status : std_logic;
signal read_ififo1 : std_logic;
signal read_ififo2 : std_logic;
signal read_start01 : std_logic;
signal reset_acam : std_logic;
signal load_utc : std_logic;
signal clear_dacapo_counter : std_logic;
signal starting_utc : std_logic_vector(g_width-1 downto 0);
signal in_en_ctrl : std_logic_vector(g_width-1 downto 0);
signal start_phase : std_logic_vector(g_width-1 downto 0);
signal one_hz_phase : std_logic_vector(g_width-1 downto 0);
signal acam_config : config_vector;
signal acam_config_rdbk : config_vector;
signal acam_status : std_logic_vector(g_width-1 downto 0);
signal acam_ififo1 : std_logic_vector(g_width-1 downto 0);
signal acam_ififo2 : std_logic_vector(g_width-1 downto 0);
signal acam_start01 : std_logic_vector(g_width-1 downto 0);
signal local_utc : std_logic_vector(g_width-1 downto 0);
signal irq_code : std_logic_vector(g_width-1 downto 0);
signal acam_config : config_vector;
signal wr_index : std_logic_vector(g_width-1 downto 0);
signal core_status : std_logic_vector(g_width-1 downto 0);
signal acam_refclk : std_logic;
signal clk : std_logic;
signal spec_clk : std_logic;
......@@ -648,19 +656,19 @@ begin
one_second_block: one_hz_gen
generic map(
g_width => g_width
g_width => g_width
)
port map(
acam_refclk_i => acam_refclk,
clk_i => clk,
clock_period_i => clock_period,
load_utc_i => load_utc,
pulse_delay_i => pulse_delay,
reset_i => general_reset,
starting_utc_i => starting_utc,
acam_refclk_edge_p_i => acam_refclk_edge_p,
clk => clk,
clock_period_i => clock_period,
load_utc_i => load_utc,
pulse_delay_i => pulse_delay,
reset_i => general_reset,
starting_utc_i => starting_utc,
local_utc_o => local_utc,
one_hz_p_o => one_hz_p
local_utc_o => local_utc,
one_hz_p_o => one_hz_p
);
acam_timing_block: acam_timecontrol_interface
......@@ -672,15 +680,15 @@ begin
err_flag_i => err_flag_i,
int_flag_i => int_flag_i,
-- this is the config for acam test, in normal application connect the outputs
-- At the end the disable signals are not used in the current application
start_dis_o => start_dis_o,
start_from_fpga_o => start_from_fpga_o,
stop_dis_o => stop_dis_o,
-- signals internal to the chip: interface with other modules
acam_refclk_i => acam_refclk,
clk_i => clk,
start_trig_i => start_trig,
acam_refclk_edge_p_i => acam_refclk_edge_p,
clk => clk,
start_trig_i => activate_acq,
reset_i => general_reset,
window_delay_i => window_delay,
......@@ -710,12 +718,14 @@ begin
wr_n_o => wr_n_o,
acam_ef1_o => acam_ef1,
acam_ef1_meta_o => acam_ef1_meta,
acam_ef2_o => acam_ef2,
acam_ef2_meta_o => acam_ef2_meta,
acam_lf1_o => acam_lf1,
acam_lf2_o => acam_lf2,
-- signals internal to the chip: interface with other modules
clk_i => clk,
clk => clk,
reset_i => general_reset,
adr_i => acm_adr,
......@@ -735,10 +745,10 @@ begin
port map(
acam_fall_intflag_p_i => acam_fall_intflag_p,
acam_rise_intflag_p_i => acam_rise_intflag_p,
clk_i => clk,
clk => clk,
one_hz_p_i => one_hz_p,
reset_i => general_reset,
retrig_period_i => retrig_period,
retrig_period_i => c_retrig_period,
clk_cycles_offset_o => clk_cycles_offset,
current_roll_over_o => current_roll_over,
......@@ -762,10 +772,12 @@ begin
we_o => acm_we,
-- signals internal to the chip: interface with other modules
clk_i => clk,
clk => clk,
reset_i => general_reset,
acam_ef1_i => acam_ef1,
acam_ef1_meta_i => acam_ef1_meta,
acam_ef2_i => acam_ef2,
acam_ef2_meta_i => acam_ef2_meta,
activate_acq_i => activate_acq,
deactivate_acq_i => deactivate_acq,
......@@ -791,11 +803,12 @@ begin
data_formatting_block: data_formatting
generic map(
g_retrig_period_shift => retrig_period_shift,
g_retrig_period_shift => c_retrig_period_shift,
g_span => g_span,
g_width => g_width
)
port map(
-- wishbone master signals internal to the chip: interface with the circular buffer
ack_i => mem_class_ack,
dat_i => mem_class_data_rd,
......@@ -805,19 +818,20 @@ begin
stb_o => mem_class_stb,
we_o => mem_class_we,
-- signals internal to the chip: interface with other modules
acam_timestamp1_i => acam_timestamp1,
acam_timestamp1_valid_i => acam_timestamp1_valid,
acam_timestamp2_i => acam_timestamp2,
acam_timestamp2_valid_i => acam_timestamp2_valid,
clk_i => clk,
clear_dacapo_flag_i => clear_dacapo_flag,
clk => clk,
clear_dacapo_counter_i => clear_dacapo_counter,
reset_i => general_reset,
clk_cycles_offset_i => clk_cycles_offset,
current_roll_over_i => current_roll_over,
retrig_nb_offset_i => retrig_nb_offset,
local_utc_i => local_utc,
wr_pointer_o => wr_pointer
wr_index_o => wr_index
);
circular_buffer_block: circular_buffer
......@@ -827,7 +841,7 @@ begin
)
port map(
-- wishbone classic slave signals to interface RAM with the internal modules providing the timestamps
class_clk_i => clk,
clk => clk,
class_reset_i => general_reset,
class_adr_i => mem_class_adr,
......@@ -840,7 +854,6 @@ begin
class_dat_o => mem_class_data_rd,
-- wishbone pipelined slave signals to interface RAM with gnum core for DMA access from PCI-e
pipe_clk_i => clk,
pipe_reset_i => general_reset,
pipe_adr_i => mem_pipe_adr,
......@@ -861,7 +874,7 @@ begin
)
port map(
-- wishbone classic slave signals to interface with the host through the gnum core and the gnum chip
reg_clk_i => clk,
clk => clk,
reg_reset_i => general_reset,
reg_adr_i => reg_adr,
......@@ -884,9 +897,9 @@ begin
read_start01_o => read_start01,
reset_acam_o => reset_acam,
load_utc_o => load_utc,
clear_dacapo_flag_o => clear_dacapo_flag,
clear_dacapo_counter_o => clear_dacapo_counter,
-- configuration registers for the ACAM and the modules of the TDC core
-- configuration and status registers for the ACAM and the modules of the TDC core
acam_config_rdbk_i => acam_config_rdbk,
acam_status_i => acam_status,
acam_ififo1_i => acam_ififo1,
......@@ -895,7 +908,7 @@ begin
local_utc_i => local_utc,
irq_code_i => irq_code,
core_status_i => core_status,
wr_pointer_i => wr_pointer,
wr_index_i => wr_index,
acam_config_o => acam_config,
starting_utc_o => starting_utc,
......@@ -910,24 +923,24 @@ begin
values_for_simulation => values_for_simulation
)
port map(
acam_refclk_i => acam_refclk_i,
pll_ld_i => pll_ld_i,
pll_refmon_i => pll_refmon_i,
pll_sdo_i => pll_sdo_i,
pll_status_i => pll_status_i,
gnum_reset_i => gnum_reset,
spec_clk_i => spec_clk_i,
tdc_clk_p_i => tdc_clk_p_i,
tdc_clk_n_i => tdc_clk_n_i,
acam_refclk_i => acam_refclk_i,
pll_ld_i => pll_ld_i,
pll_refmon_i => pll_refmon_i,
pll_sdo_i => pll_sdo_i,
pll_status_i => pll_status_i,
gnum_reset_i => gnum_reset,
spec_clk_i => spec_clk_i,
tdc_clk_p_i => tdc_clk_p_i,
tdc_clk_n_i => tdc_clk_n_i,
acam_refclk_o => acam_refclk,
general_reset_o => general_reset,
pll_cs_o => pll_cs_o,
pll_dac_sync_o => pll_dac_sync_o,
pll_sdi_o => pll_sdi_o,
pll_sclk_o => pll_sclk_o,
spec_clk_o => spec_clk,
tdc_clk_o => clk
acam_refclk_edge_p_o => acam_refclk_edge_p,
general_reset_o => general_reset,
pll_cs_o => pll_cs_o,
pll_dac_sync_o => pll_dac_sync_o,
pll_sdi_o => pll_sdi_o,
pll_sclk_o => pll_sclk_o,
spec_clk_o => spec_clk,
tdc_clk_o => clk
);
gnum_interface_block: gn4124_core
......@@ -988,71 +1001,79 @@ begin
spec_led_period_counter: free_counter
port map(
clk => spec_clk,
enable => '1',
reset => gnum_reset,
start_value => spec_led_period,
clk => spec_clk,
enable => '1',
reset => gnum_reset,
start_value => spec_led_period,
count_done => spec_led_period_done,
current_value => open
count_done => spec_led_period_done,
current_value => open
);
spec_led_blink_counter: countdown_counter
port map(
clk => spec_clk,
reset => gnum_reset,
start => spec_led_period_done,
start_value => visible_blink_length,
clk => spec_clk,
reset => gnum_reset,
start => spec_led_period_done,
start_value => visible_blink_length,
count_done => spec_led_blink_done,
current_value => open
count_done => spec_led_blink_done,
current_value => open
);
tdc_led_blink_counter: countdown_counter
port map(
clk => clk,
reset => general_reset,
start => one_hz_p,
start_value => visible_blink_length,
clk => clk,
reset => general_reset,
start => one_hz_p,
start_value => visible_blink_length,
count_done => tdc_led_blink_done,
current_value => open
count_done => tdc_led_blink_done,
current_value => open
);
-- connection of the DMA master port from the GNUM core to the circular buffer slave
------------------------------------------------------------------------------------
-- (address decoding: memory used has 1024 bytes depth)
mem_pipe_cyc <= '1' when dma_cyc='1' and dma_adr(31 downto 10)=x"00000" & "00" else '0';
mem_pipe_adr <= dma_adr;
mem_pipe_stb <= dma_stb;
mem_pipe_we <= dma_we;
mem_pipe_data_wr <= dma_dat_w;
dma_ack <= mem_pipe_ack;
dma_dat_r <= mem_pipe_data_rd;
dma_stall <= mem_pipe_stall;
-- address decoding: memory used has 1024 bytes depth
-- (the DMA port of the GNUM core manages address for 8-bit words)
mem_pipe_cyc <= '1' when dma_cyc='1' and dma_adr(31 downto 10)= c_dma_userspace_baseadr(31 downto 10)
else '0';
-- mem_pipe_cyc <= '1' when dma_cyc='1' and dma_adr(31 downto 10)=x"00000" & "00" else '0';
mem_pipe_adr <= dma_adr;
mem_pipe_stb <= dma_stb;
mem_pipe_we <= dma_we;
mem_pipe_data_wr <= dma_dat_w;
dma_ack <= mem_pipe_ack;
dma_dat_r <= mem_pipe_data_rd;
dma_stall <= mem_pipe_stall;
-- CSR master connected to the register control slave
------------------------------------------------------
-- address decoding: first 512 kB for GNUM core, second 512 kB for TDC application (of which only 256 bytes are reserved)
reg_cyc <= '1' when csr_cyc(0)='1' and csr_adr(18 downto 8)="010" & x"00" else '0';
reg_adr(31 downto 19) <= (others=>'0');
reg_adr(18 downto 0) <= csr_adr;
reg_stb <= csr_stb;
reg_we <= csr_we;
reg_data_wr <= csr_dat_w;
csr_ack(0) <= reg_ack;
csr_dat_r <= reg_data_rd;
-- (the CSR port of the GNUM core already treats addresses for 32-bit words)
reg_cyc <= '1' when csr_cyc(0)='1' and csr_adr(18 downto 8)= c_csr_userspace_baseadr(18 downto 8)
else '0';
-- reg_cyc <= '1' when csr_cyc(0)='1' and csr_adr(18 downto 8)="010" & x"00" else '0';
reg_adr(31 downto 19) <= (others=>'0');
reg_adr(18 downto 0) <= csr_adr;
reg_stb <= csr_stb;
reg_we <= csr_we;
reg_data_wr <= csr_dat_w;
csr_ack(0) <= reg_ack;
csr_dat_r <= reg_data_rd;
spec_led: process
begin
if gnum_reset ='1' then
spec_led_red <= '0';
spec_led_red <= '0';
elsif spec_led_period_done ='1' then
spec_led_red <= '1';
spec_led_red <= '1';
elsif spec_led_blink_done ='1' then
spec_led_red <= '0';
spec_led_red <= '0';
end if;
wait until spec_clk ='1';
end process;
......@@ -1060,31 +1081,35 @@ begin
tdc_led: process
begin
if general_reset ='1' then
tdc_led_status <= '0';
tdc_led_status <= '0';
elsif one_hz_p ='1' then
tdc_led_status <= '1';
tdc_led_status <= '1';
elsif tdc_led_blink_done = '1' then
tdc_led_status <= '0';
tdc_led_status <= '0';
end if;
wait until clk ='1';
end process;
spec_led_period <= spec_led_period_sim when values_for_simulation
else spec_led_period_syn;
spec_led_period <= spec_led_period_sim when values_for_simulation
else spec_led_period_syn;
visible_blink_length <= blink_length_sim when values_for_simulation
else blink_length_syn;
visible_blink_length <= blink_length_sim when values_for_simulation
else blink_length_syn;
clock_period <= sim_clock_period when values_for_simulation
else syn_clock_period;
clock_period <= c_sim_clock_period when values_for_simulation
else c_syn_clock_period;
-- internal signals
irq_p <= dma_irq(0) or dma_irq(1);
spec_led_green <= pll_ld_i;
start_trig <= activate_acq;
irq_p <= dma_irq(0) or dma_irq(1);
spec_led_green <= pll_ld_i;
-- inputs
gnum_reset <= not(rst_n_a_i);
sync_gnum_reset: process
begin
gnum_reset_r <= not(rst_n_a_i);
gnum_reset <= gnum_reset_r;
wait until spec_clk ='1';
end process;
-- outputs
process
......
hdl/spec/src/test_bench/tb_tdc.vhd
View file @ 17667554
......@@ -486,7 +486,8 @@ begin
tstop2_i => tstop2,
tstop3_i => tstop3,
tstop4_i => tstop4,
tstop5_i => dummy_tstop5,
tstop5_i => tstop5,
-- tstop5_i => dummy_tstop5,
startdis_i => start_dis_o,
stopdis_i => stop_dis_o,
......
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