Commit 17667554 authored by penacoba's avatar penacoba

Most of the comments from the code review have been integrated


git-svn-id: http://svn.ohwr.org/fmc-tdc@72 85dfdc96-de2c-444c-878d-45b388be74a9
parent a86d35bc
...@@ -46,12 +46,14 @@ entity acam_databus_interface is ...@@ -46,12 +46,14 @@ entity acam_databus_interface is
-- signals internal to the chip: interface with other modules -- signals internal to the chip: interface with other modules
acam_ef1_o : out std_logic; acam_ef1_o : out std_logic;
acam_ef1_meta_o : out std_logic;
acam_ef2_o : out std_logic; acam_ef2_o : out std_logic;
acam_ef2_meta_o : out std_logic;
acam_lf1_o : out std_logic; acam_lf1_o : out std_logic;
acam_lf2_o : out std_logic; acam_lf2_o : out std_logic;
-- wishbone slave signals internal to the chip: interface with other modules -- wishbone slave signals internal to the chip: interface with other modules
clk_i : in std_logic; clk : in std_logic;
reset_i : in std_logic; reset_i : in std_logic;
adr_i : in std_logic_vector(g_span-1 downto 0); adr_i : in std_logic_vector(g_span-1 downto 0);
...@@ -70,16 +72,15 @@ end acam_databus_interface; ...@@ -70,16 +72,15 @@ end acam_databus_interface;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
architecture rtl of acam_databus_interface is architecture rtl of acam_databus_interface is
type t_acam_interface is (idle, rd_start, read, rd_ack, wr_start, write, wr_ack); type t_acam_interface is (IDLE, RD_START, RD_FETCH, RD_ACK, WR_START, WR_PUSH, WR_ACK);
signal acam_data_st, nxt_acam_data_st : t_acam_interface; signal acam_data_st, nxt_acam_data_st : t_acam_interface;
signal ef1 : std_logic; signal ef1_r : std_logic_vector(1 downto 0);
signal ef2 : std_logic; signal ef2_r : std_logic_vector(1 downto 0);
signal lf1 : std_logic; signal lf1_r : std_logic_vector(1 downto 0);
signal lf2 : std_logic; signal lf2_r : std_logic_vector(1 downto 0);
signal clk : std_logic;
signal reset : std_logic; signal reset : std_logic;
signal adr : std_logic_vector(g_span-1 downto 0); signal adr : std_logic_vector(g_span-1 downto 0);
signal cyc : std_logic; signal cyc : std_logic;
...@@ -105,7 +106,7 @@ begin ...@@ -105,7 +106,7 @@ begin
databus_access_seq_fsm: process databus_access_seq_fsm: process
begin begin
if reset ='1' then if reset ='1' then
acam_data_st <= idle; acam_data_st <= IDLE;
else else
acam_data_st <= nxt_acam_data_st; acam_data_st <= nxt_acam_data_st;
end if; end if;
...@@ -115,7 +116,7 @@ begin ...@@ -115,7 +116,7 @@ begin
databus_access_comb_fsm: process(acam_data_st, stb, cyc, we) databus_access_comb_fsm: process(acam_data_st, stb, cyc, we)
begin begin
case acam_data_st is case acam_data_st is
when idle => when IDLE =>
ack <= '0'; ack <= '0';
cs_extend <= '0'; cs_extend <= '0';
rd_extend <= '0'; rd_extend <= '0';
...@@ -123,67 +124,67 @@ begin ...@@ -123,67 +124,67 @@ begin
wr_remove <= '0'; wr_remove <= '0';
if stb ='1' and cyc ='1' then if stb ='1' and cyc ='1' then
if we = '1' then if we = '1' then
nxt_acam_data_st <= wr_start; nxt_acam_data_st <= WR_START;
else else
nxt_acam_data_st <= rd_start; nxt_acam_data_st <= RD_START;
end if; end if;
else else
nxt_acam_data_st <= idle; nxt_acam_data_st <= IDLE;
end if; end if;
when rd_start => when RD_START =>
ack <= '0'; ack <= '0';
cs_extend <= '1'; cs_extend <= '1';
rd_extend <= '1'; rd_extend <= '1';
wr_extend <= '0'; wr_extend <= '0';
wr_remove <= '0'; wr_remove <= '0';
nxt_acam_data_st <= read; nxt_acam_data_st <= RD_FETCH;
when read => when RD_FETCH =>
ack <= '0'; ack <= '0';
cs_extend <= '1'; cs_extend <= '1';
rd_extend <= '1'; rd_extend <= '1';
wr_extend <= '0'; wr_extend <= '0';
wr_remove <= '0'; wr_remove <= '0';
nxt_acam_data_st <= rd_ack; nxt_acam_data_st <= RD_ACK;
when rd_ack => when RD_ACK =>
ack <= '1'; ack <= '1';
cs_extend <= '0'; cs_extend <= '0';
rd_extend <= '0'; rd_extend <= '0';
wr_extend <= '0'; wr_extend <= '0';
wr_remove <= '0'; wr_remove <= '0';
nxt_acam_data_st <= idle; nxt_acam_data_st <= IDLE;
when wr_start => when WR_START =>
ack <= '0'; ack <= '0';
cs_extend <= '1'; cs_extend <= '1';
rd_extend <= '0'; rd_extend <= '0';
wr_extend <= '1'; wr_extend <= '1';
wr_remove <= '0'; wr_remove <= '0';
nxt_acam_data_st <= write; nxt_acam_data_st <= WR_PUSH;
when write => when WR_PUSH =>
ack <= '0'; ack <= '0';
cs_extend <= '0'; cs_extend <= '0';
rd_extend <= '0'; rd_extend <= '0';
wr_extend <= '0'; wr_extend <= '0';
wr_remove <= '1'; wr_remove <= '1';
nxt_acam_data_st <= wr_ack; nxt_acam_data_st <= WR_ACK;
when wr_ack => when WR_ACK =>
ack <= '1'; ack <= '1';
cs_extend <= '0'; cs_extend <= '0';
rd_extend <= '0'; rd_extend <= '0';
wr_extend <= '0'; wr_extend <= '0';
wr_remove <= '0'; wr_remove <= '0';
nxt_acam_data_st <= idle; nxt_acam_data_st <= IDLE;
when others => when others =>
ack <= '0'; ack <= '0';
...@@ -192,7 +193,7 @@ begin ...@@ -192,7 +193,7 @@ begin
wr_extend <= '0'; wr_extend <= '0';
wr_remove <= '0'; wr_remove <= '0';
nxt_acam_data_st <= idle; nxt_acam_data_st <= IDLE;
end case; end case;
end process; end process;
...@@ -205,7 +206,6 @@ begin ...@@ -205,7 +206,6 @@ begin
-- Acam specs -- Acam specs
-- inputs from other blocks -- inputs from other blocks
clk <= clk_i;
reset <= reset_i; reset <= reset_i;
adr <= adr_i; adr <= adr_i;
...@@ -215,27 +215,31 @@ begin ...@@ -215,27 +215,31 @@ begin
we <= we_i; we <= we_i;
-- outputs to other blocks -- outputs to other blocks
acam_ef1_o <= ef1; acam_ef1_o <= ef1_r(0); -- this signal is perfectly synchronized
acam_ef2_o <= ef2; acam_ef1_meta_o <= ef1_r(1); -- this signal could be metastable but
acam_lf1_o <= lf1; -- not when we plan to use it...
acam_lf2_o <= lf2; acam_ef2_o <= ef2_r(0);
acam_ef2_meta_o <= ef2_r(1);
acam_lf1_o <= lf1_r(0);
acam_lf2_o <= lf2_r(0);
ack_o <= ack; ack_o <= ack;
dat_o <= ef1 & ef2 & lf1 & lf2 & data_bus_io; dat_o <= ef1_r(0) & ef2_r(0) & lf1_r(0) & lf2_r(0) & data_bus_io;
-- inputs from the ACAM -- inputs from the ACAM
input_registers: process input_registers: process
begin begin
if reset ='1' then if reset ='1' then
ef1 <= '1'; ef1_r <= (others =>'1');
ef2 <= '1'; ef2_r <= (others =>'1');
lf1 <= '1'; lf1_r <= (others =>'0');
lf2 <= '1'; lf2_r <= (others =>'0');
else else
ef1 <= ef1_i; ef1_r <= ef1_i & ef1_r(1);
ef2 <= ef2_i; ef2_r <= ef2_i & ef2_r(1);
lf1 <= lf1_i; lf1_r <= lf1_i & lf1_r(1);
lf2 <= lf2_i; lf2_r <= lf2_i & lf2_r(1);
end if; end if;
wait until clk ='1'; wait until clk ='1';
end process; end process;
......
...@@ -38,8 +38,8 @@ entity acam_timecontrol_interface is ...@@ -38,8 +38,8 @@ entity acam_timecontrol_interface is
stop_dis_o : out std_logic; stop_dis_o : out std_logic;
-- signals internal to the chip: interface with other modules -- signals internal to the chip: interface with other modules
acam_refclk_i : in std_logic; acam_refclk_edge_p_i : in std_logic;
clk_i : in std_logic; clk : in std_logic;
start_trig_i : in std_logic; start_trig_i : in std_logic;
reset_i : in std_logic; reset_i : in std_logic;
window_delay_i : in std_logic_vector(g_width-1 downto 0); window_delay_i : in std_logic_vector(g_width-1 downto 0);
...@@ -87,21 +87,23 @@ architecture rtl of acam_timecontrol_interface is ...@@ -87,21 +87,23 @@ architecture rtl of acam_timecontrol_interface is
end component; end component;
constant constant_delay : unsigned(g_width-1 downto 0):=x"00000004"; constant constant_delay : unsigned(g_width-1 downto 0):=x"00000004";
-- the delay between the referenc clock and the start window is the Total Delay
-- the Total delay is always obtained by adding the constant delay and the
-- window delay configured by the PCI-e
signal acam_refclk : std_logic; -- the start_from_fpga signal is generated in the middle of the start window
signal clk : std_logic;
signal acam_refclk_edge_p : std_logic;
signal counter_reset : std_logic; signal counter_reset : std_logic;
signal counter_value : std_logic_vector(g_width-1 downto 0); signal counter_value : std_logic_vector(g_width-1 downto 0);
signal refclk_edge : std_logic;
signal refclk_r : unsigned(3 downto 0);
signal reset : std_logic; signal reset : std_logic;
signal int_flag_r : unsigned(2 downto 0); signal int_flag_r : std_logic_vector(2 downto 0);
signal err_flag_r : unsigned(2 downto 0); signal err_flag_r : std_logic_vector(2 downto 0);
signal start_dis : std_logic; signal start_dis : std_logic;
signal start_from_fpga : std_logic; signal start_from_fpga : std_logic;
signal start_trig : std_logic; signal start_trig : std_logic;
signal start_trig_r : unsigned(2 downto 0); signal start_trig_r : std_logic_vector(2 downto 0);
signal start_trig_edge : std_logic; signal start_trig_edge : std_logic;
signal start_trig_received : std_logic; signal start_trig_received : std_logic;
signal waitingfor_refclk : std_logic; signal waitingfor_refclk : std_logic;
...@@ -116,14 +118,13 @@ signal window_start : std_logic; ...@@ -116,14 +118,13 @@ signal window_start : std_logic;
-- architecture begins -- architecture begins
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
begin begin
-- monitoring of the interrupt and error signals
sync_err_flag: process -- synchronisation registers for ERR external signal sync_err_flag: process -- synchronisation registers for ERR external signal
begin begin
if reset ='1' then if reset ='1' then
err_flag_r <= (others=>'0'); err_flag_r <= (others=>'0');
else else
err_flag_r <= shift_right(err_flag_r,1); err_flag_r <= err_flag_i & err_flag_r(2 downto 1);
err_flag_r(2) <= err_flag_i;
end if; end if;
wait until clk ='1'; wait until clk ='1';
end process; end process;
...@@ -133,8 +134,7 @@ begin ...@@ -133,8 +134,7 @@ begin
if reset ='1' then if reset ='1' then
int_flag_r <= (others=>'0'); int_flag_r <= (others=>'0');
else else
int_flag_r <= shift_right(int_flag_r,1); int_flag_r <= int_flag_i & int_flag_r(2 downto 1);
int_flag_r(2) <= int_flag_i;
end if; end if;
wait until clk ='1'; wait until clk ='1';
end process; end process;
...@@ -219,7 +219,7 @@ begin ...@@ -219,7 +219,7 @@ begin
waitingfor_refclk <= '0'; waitingfor_refclk <= '0';
elsif start_trig_edge ='1' then elsif start_trig_edge ='1' then
waitingfor_refclk <= '1'; waitingfor_refclk <= '1';
elsif refclk_edge ='1' then elsif acam_refclk_edge_p ='1' then
waitingfor_refclk <= '0'; waitingfor_refclk <= '0';
end if; end if;
wait until clk ='1'; wait until clk ='1';
...@@ -240,36 +240,27 @@ begin ...@@ -240,36 +240,27 @@ begin
inputs_synchronizer: process inputs_synchronizer: process
begin begin
if reset ='1' then if reset ='1' then
start_trig_r <= (others=>'0'); start_trig_r <= (others=>'0');
refclk_r <= (others=>'0');
else else
start_trig_r <= shift_right(start_trig_r,1); start_trig_r <= start_trig & start_trig_r(2 downto 1);
start_trig_r(2) <= start_trig;
refclk_r <= shift_right(refclk_r,1);
refclk_r(3) <= acam_refclk;
end if; end if;
wait until clk ='1'; wait until clk ='1';
end process; end process;
refclk_edge <= refclk_r(3) and
not(refclk_r(2)) and
not(refclk_r(1)) and
refclk_r(0);
start_trig_edge <= start_trig_r(2) and
not(start_trig_r(1)) and
not(start_trig_r(0));
window_prepulse <= waitingfor_refclk and refclk_edge;
counter_reset <= reset or window_start; counter_reset <= reset or window_start;
start_trig_edge <= start_trig_r(1) and not(start_trig_r(0));
window_prepulse <= waitingfor_refclk and acam_refclk_edge_p;
total_delay <= std_logic_vector(unsigned(window_delay)+constant_delay); total_delay <= std_logic_vector(unsigned(window_delay)+constant_delay);
counter_reset <= reset or window_start;
-- inputs -- inputs
clk <= clk_i;
reset <= reset_i; reset <= reset_i;
start_trig <= start_trig_i; start_trig <= start_trig_i;
acam_refclk <= acam_refclk_i; acam_refclk_edge_p <= acam_refclk_edge_p_i;
window_delay <= window_delay_i; window_delay <= window_delay_i;
-- outputs -- outputs
......
...@@ -34,7 +34,7 @@ entity circular_buffer is ...@@ -34,7 +34,7 @@ entity circular_buffer is
); );
port( port(
-- wishbone classic slave signals to interface RAM with the internal modules providing the timestamps -- wishbone classic slave signals to interface RAM with the internal modules providing the timestamps
class_clk_i : in std_logic; clk : in std_logic;
class_reset_i : in std_logic; class_reset_i : in std_logic;
class_adr_i : in std_logic_vector(g_span-1 downto 0); class_adr_i : in std_logic_vector(g_span-1 downto 0);
...@@ -47,7 +47,6 @@ entity circular_buffer is ...@@ -47,7 +47,6 @@ entity circular_buffer is
class_dat_o : out std_logic_vector(4*g_width-1 downto 0); class_dat_o : out std_logic_vector(4*g_width-1 downto 0);
-- wishbone pipelined slave signals to interface RAM with gnum core for DMA access from PCI-e -- wishbone pipelined slave signals to interface RAM with gnum core for DMA access from PCI-e
pipe_clk_i : in std_logic;
pipe_reset_i : in std_logic; pipe_reset_i : in std_logic;
pipe_adr_i : in std_logic_vector(g_span-1 downto 0); pipe_adr_i : in std_logic_vector(g_span-1 downto 0);
...@@ -85,13 +84,13 @@ component blk_mem_circ_buff_v6_4 ...@@ -85,13 +84,13 @@ component blk_mem_circ_buff_v6_4
); );
end component; end component;
type t_wb_pipelined_mem_interface is (idle, mem_access, mem_access_and_acknowledge, acknowledge); type t_wb_pipelined_mem_interface is (IDLE, MEM_ACCESS,
MEM_ACCESS_AND_ACKNOWLEDGE, ACKNOWLEDGE);
signal wb_pipelined_st, nxt_wb_pipelined_st : t_wb_pipelined_mem_interface; signal wb_pipelined_st, nxt_wb_pipelined_st : t_wb_pipelined_mem_interface;
signal class_ack : std_logic; signal class_ack : std_logic;
signal class_adr : std_logic_vector(7 downto 0); signal class_adr : std_logic_vector(7 downto 0);
signal class_clk : std_logic;
signal class_cyc : std_logic; signal class_cyc : std_logic;
signal class_data_rd : std_logic_vector(4*g_width-1 downto 0); signal class_data_rd : std_logic_vector(4*g_width-1 downto 0);
signal class_data_wr : std_logic_vector(4*g_width-1 downto 0); signal class_data_wr : std_logic_vector(4*g_width-1 downto 0);
...@@ -102,7 +101,6 @@ signal class_we : std_logic_vector(0 downto 0); ...@@ -102,7 +101,6 @@ signal class_we : std_logic_vector(0 downto 0);
signal pipe_ack : std_logic; signal pipe_ack : std_logic;
signal pipe_adr : std_logic_vector(9 downto 0); signal pipe_adr : std_logic_vector(9 downto 0);
signal pipe_clk : std_logic;
signal pipe_cyc : std_logic; signal pipe_cyc : std_logic;
signal pipe_data_rd : std_logic_vector(g_width-1 downto 0); signal pipe_data_rd : std_logic_vector(g_width-1 downto 0);
signal pipe_data_wr : std_logic_vector(g_width-1 downto 0); signal pipe_data_wr : std_logic_vector(g_width-1 downto 0);
...@@ -126,76 +124,76 @@ begin ...@@ -126,76 +124,76 @@ begin
else else
class_ack <= '0'; class_ack <= '0';
end if; end if;
wait until class_clk ='1'; wait until clk ='1';
end process; end process;
-- Wishbone pipelined interfacte compatible slave -- Wishbone pipelined interfacte compatible slave
pipelined_seq_fsm: process pipelined_seq_fsm: process
begin begin
if pipe_reset ='1' then if pipe_reset ='1' then
wb_pipelined_st <= idle; wb_pipelined_st <= IDLE;
else else
wb_pipelined_st <= nxt_wb_pipelined_st; wb_pipelined_st <= nxt_wb_pipelined_st;
end if; end if;
wait until pipe_clk ='1'; wait until clk ='1';
end process; end process;
pipelined_comb_fsm: process(wb_pipelined_st, pipe_stb, pipe_cyc) pipelined_comb_fsm: process(wb_pipelined_st, pipe_stb, pipe_cyc)
begin begin
case wb_pipelined_st is case wb_pipelined_st is
when idle => when IDLE =>
pipe_ack <= '0'; pipe_ack <= '0';
if pipe_stb ='1' and pipe_cyc ='1' then if pipe_stb ='1' and pipe_cyc ='1' then
nxt_wb_pipelined_st <= mem_access; nxt_wb_pipelined_st <= MEM_ACCESS;
else else
nxt_wb_pipelined_st <= idle; nxt_wb_pipelined_st <= IDLE;
end if; end if;
when mem_access => when MEM_ACCESS =>
pipe_ack <= '0'; pipe_ack <= '0';
if pipe_stb ='1' and pipe_cyc ='1' then if pipe_stb ='1' and pipe_cyc ='1' then
nxt_wb_pipelined_st <= mem_access_and_acknowledge; nxt_wb_pipelined_st <= MEM_ACCESS_AND_ACKNOWLEDGE;
else else
nxt_wb_pipelined_st <= acknowledge; nxt_wb_pipelined_st <= ACKNOWLEDGE;
end if; end if;
when mem_access_and_acknowledge => when MEM_ACCESS_AND_ACKNOWLEDGE =>
pipe_ack <= '1'; pipe_ack <= '1';
if pipe_stb ='1' and pipe_cyc ='1' then if pipe_stb ='1' and pipe_cyc ='1' then
nxt_wb_pipelined_st <= mem_access_and_acknowledge; nxt_wb_pipelined_st <= MEM_ACCESS_AND_ACKNOWLEDGE;
else else
nxt_wb_pipelined_st <= acknowledge; nxt_wb_pipelined_st <= ACKNOWLEDGE;
end if; end if;
when acknowledge => when ACKNOWLEDGE =>
pipe_ack <= '1'; pipe_ack <= '1';
if pipe_stb ='1' and pipe_cyc ='1' then if pipe_stb ='1' and pipe_cyc ='1' then
nxt_wb_pipelined_st <= mem_access; nxt_wb_pipelined_st <= MEM_ACCESS;
else else
nxt_wb_pipelined_st <= idle; nxt_wb_pipelined_st <= IDLE;
end if; end if;
when others => when others =>
pipe_ack <= '0'; pipe_ack <= '0';
nxt_wb_pipelined_st <= idle; nxt_wb_pipelined_st <= IDLE;
end case; end case;
end process; end process;
memory_block: blk_mem_circ_buff_v6_4 memory_block: blk_mem_circ_buff_v6_4
port map( port map(
clka => class_clk, clka => clk,
addra => class_adr, addra => class_adr,
dina => class_data_wr, dina => class_data_wr,
ena => class_en, ena => class_en,
wea => class_we, wea => class_we,
douta => class_data_rd, douta => class_data_rd,
clkb => pipe_clk, clkb => clk,
addrb => pipe_adr, addrb => pipe_adr,
dinb => pipe_data_wr, dinb => pipe_data_wr,
enb => pipe_en, enb => pipe_en,
...@@ -204,7 +202,6 @@ begin ...@@ -204,7 +202,6 @@ begin
); );
-- inputs from other blocks -- inputs from other blocks
class_clk <= class_clk_i;
class_reset <= class_reset_i; class_reset <= class_reset_i;
class_adr <= class_adr_i(7 downto 0); class_adr <= class_adr_i(7 downto 0);
...@@ -214,7 +211,6 @@ begin ...@@ -214,7 +211,6 @@ begin
class_stb <= class_stb_i; class_stb <= class_stb_i;
class_we(0) <= class_we_i; class_we(0) <= class_we_i;
pipe_clk <= pipe_clk_i;
pipe_reset <= pipe_reset_i; pipe_reset <= pipe_reset_i;
pipe_adr <= pipe_adr_i(9 downto 0); pipe_adr <= pipe_adr_i(9 downto 0);
......
...@@ -45,7 +45,7 @@ entity clk_rst_managr is ...@@ -45,7 +45,7 @@ entity clk_rst_managr is
tdc_clk_p_i : in std_logic; tdc_clk_p_i : in std_logic;
tdc_clk_n_i : in std_logic; tdc_clk_n_i : in std_logic;
acam_refclk_o : out std_logic; acam_refclk_edge_p_o : out std_logic;
general_reset_o : out std_logic; general_reset_o : out std_logic;
pll_cs_o : out std_logic; pll_cs_o : out std_logic;
pll_dac_sync_o : out std_logic; pll_dac_sync_o : out std_logic;
...@@ -176,11 +176,11 @@ signal nxt_pll_init_st : t_pll_init_st; ...@@ -176,11 +176,11 @@ signal nxt_pll_init_st : t_pll_init_st;
signal config_reg : t_stream; signal config_reg : t_stream;
signal address : t_instr; signal address : t_instr;
signal acam_refclk_buf : std_logic;
signal spec_clk_buf : std_logic; signal spec_clk_buf : std_logic;
signal tdc_clk_buf : std_logic; signal tdc_clk_buf : std_logic;
signal acam_refclk : std_logic; signal acam_refclk_r : std_logic_vector(2 downto 0);
signal acam_refclk_edge_p : std_logic;
signal pll_sclk : std_logic; signal pll_sclk : std_logic;
signal spec_clk : std_logic; signal spec_clk : std_logic;
signal tdc_clk : std_logic; signal tdc_clk : std_logic;
...@@ -195,7 +195,7 @@ signal gnum_reset : std_logic; ...@@ -195,7 +195,7 @@ signal gnum_reset : std_logic;
signal gral_incr : std_logic; signal gral_incr : std_logic;
signal gral_reset_duration : std_logic_vector(31 downto 0); signal gral_reset_duration : std_logic_vector(31 downto 0);
signal inv_reset : std_logic; signal inv_reset : std_logic;
signal cs : std_logic; signal cs_n : std_logic;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- architecture begins -- architecture begins
...@@ -234,19 +234,6 @@ begin ...@@ -234,19 +234,6 @@ begin
I => spec_clk_buf I => spec_clk_buf
); );
-- acam_refclk_ibuf : IBUFG
-- port map (
-- I => acam_refclk_i,
-- O => acam_refclk_buf
-- );
--
-- acam_refclk_gbuf : BUFG
-- port map (
-- O => acam_refclk,
-- I => acam_refclk_buf
-- );
acam_refclk <= acam_refclk_i;
-- The following processes generate a general internal reset signal for the whole core. -- The following processes generate a general internal reset signal for the whole core.
-- This internal reset is triggered by the reset signal coming from the GNUM chip. -- This internal reset is triggered by the reset signal coming from the GNUM chip.
-- The idea is to keep the internal reset asserted until the clock signal received -- The idea is to keep the internal reset asserted until the clock signal received
...@@ -306,7 +293,7 @@ begin ...@@ -306,7 +293,7 @@ begin
begin begin
case pll_init_st is case pll_init_st is
when start => when start =>
cs <= '1'; cs_n <= '1';
if pll_sclk ='1' then if pll_sclk ='1' then
nxt_pll_init_st <= sending_instruction; nxt_pll_init_st <= sending_instruction;
...@@ -315,7 +302,7 @@ begin ...@@ -315,7 +302,7 @@ begin
end if; end if;
when sending_instruction => when sending_instruction =>
cs <= '0'; cs_n <= '0';
if bit_index = 0 if bit_index = 0
and pll_sclk = '1' then and pll_sclk = '1' then
...@@ -325,7 +312,7 @@ begin ...@@ -325,7 +312,7 @@ begin
end if; end if;
when sending_data => when sending_data =>
cs <= '0'; cs_n <= '0';
if bit_index = 0 if bit_index = 0
and pll_sclk = '1' then and pll_sclk = '1' then
...@@ -335,7 +322,7 @@ begin ...@@ -335,7 +322,7 @@ begin
end if; end if;
when rest => when rest =>
cs <= '1'; cs_n <= '1';
if pll_sclk = '1' then if pll_sclk = '1' then
if byte_index = 0 then if byte_index = 0 then
...@@ -348,12 +335,12 @@ begin ...@@ -348,12 +335,12 @@ begin
end if; end if;
when done => when done =>
cs <= '1'; cs_n <= '1';
nxt_pll_init_st <= done; nxt_pll_init_st <= done;
when others => when others =>
cs <= '1'; cs_n <= '1';
nxt_pll_init_st <= start; nxt_pll_init_st <= start;
end case; end case;
...@@ -363,7 +350,7 @@ begin ...@@ -363,7 +350,7 @@ begin
begin begin
if gnum_reset ='1' then if gnum_reset ='1' then
bit_index <= 15; bit_index <= 15;
elsif cs ='1' then elsif cs_n ='1' then
bit_index <= 15; bit_index <= 15;
elsif pll_sclk ='1' then elsif pll_sclk ='1' then
if bit_index = 0 then if bit_index = 0 then
...@@ -561,18 +548,31 @@ begin ...@@ -561,18 +548,31 @@ begin
config_reg(66) <= reg_230; config_reg(66) <= reg_230;
config_reg(67) <= reg_231; config_reg(67) <= reg_231;
acam_refclk_synchronizer: process
begin
if inv_reset ='0' then
acam_refclk_r <= (others=>'0');
else
acam_refclk_r <= acam_refclk_i & acam_refclk_r(2 downto 1);
end if;
wait until tdc_clk ='1';
end process;
acam_refclk_edge_p <= acam_refclk_r(1) and not(acam_refclk_r(0));
-- Input and Output signals -- Input and Output signals
--------------------------- ---------------------------
gnum_reset <= gnum_reset_i; gnum_reset <= gnum_reset_i;
acam_refclk_o <= acam_refclk; acam_refclk_edge_p_o <= acam_refclk_edge_p;
general_reset_o <= not(inv_reset); general_reset_o <= not(inv_reset);
pll_cs_o <= cs; pll_cs_o <= cs_n;
pll_sdi_o <= bit_being_sent; pll_sdi_o <= bit_being_sent;
pll_sclk_o <= pll_sclk; pll_sclk_o <= pll_sclk;
spec_clk_o <= spec_clk; spec_clk_o <= spec_clk;
tdc_clk_o <= tdc_clk; tdc_clk_o <= tdc_clk;
end rtl; end rtl;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
......
This diff is collapsed.
...@@ -47,15 +47,15 @@ entity data_formatting is ...@@ -47,15 +47,15 @@ entity data_formatting is
acam_timestamp1_valid_i : in std_logic; acam_timestamp1_valid_i : in std_logic;
acam_timestamp2_i : in std_logic_vector(g_width-1 downto 0); acam_timestamp2_i : in std_logic_vector(g_width-1 downto 0);
acam_timestamp2_valid_i : in std_logic; acam_timestamp2_valid_i : in std_logic;
clk_i : in std_logic; clk : in std_logic;
clear_dacapo_flag_i : in std_logic; clear_dacapo_counter_i : in std_logic;
reset_i : in std_logic; reset_i : in std_logic;
clk_cycles_offset_i : in std_logic_vector(g_width-1 downto 0); clk_cycles_offset_i : in std_logic_vector(g_width-1 downto 0);
current_roll_over_i : in std_logic_vector(g_width-1 downto 0); current_roll_over_i : in std_logic_vector(g_width-1 downto 0);
local_utc_i : in std_logic_vector(g_width-1 downto 0); local_utc_i : in std_logic_vector(g_width-1 downto 0);
retrig_nb_offset_i : in std_logic_vector(g_width-1 downto 0); retrig_nb_offset_i : in std_logic_vector(g_width-1 downto 0);
wr_pointer_o : out std_logic_vector(g_width-1 downto 0) wr_index_o : out std_logic_vector(g_width-1 downto 0)
); );
end data_formatting; end data_formatting;
...@@ -78,7 +78,6 @@ signal acam_fine_timestamp : std_logic_vector(16 downto 0); ...@@ -78,7 +78,6 @@ signal acam_fine_timestamp : std_logic_vector(16 downto 0);
signal acam_slope : std_logic; signal acam_slope : std_logic;
signal acam_start_nb : std_logic_vector(7 downto 0); signal acam_start_nb : std_logic_vector(7 downto 0);
signal clk : std_logic;
signal reset : std_logic; signal reset : std_logic;
signal clk_cycles_offset : std_logic_vector(g_width-1 downto 0); signal clk_cycles_offset : std_logic_vector(g_width-1 downto 0);
signal current_roll_over : std_logic_vector(g_width-1 downto 0); signal current_roll_over : std_logic_vector(g_width-1 downto 0);
...@@ -98,9 +97,10 @@ signal local_utc : std_logic_vector(g_width-1 downto 0); ...@@ -98,9 +97,10 @@ signal local_utc : std_logic_vector(g_width-1 downto 0);
signal coarse_time : std_logic_vector(g_width-1 downto 0); signal coarse_time : std_logic_vector(g_width-1 downto 0);
signal fine_time : std_logic_vector(g_width-1 downto 0); signal fine_time : std_logic_vector(g_width-1 downto 0);
signal clear_dacapo_flag : std_logic; signal clear_dacapo_counter : std_logic;
signal dacapo_flag : std_logic; signal dacapo_counter : unsigned(g_width-13 downto 0);
signal wr_pointer : unsigned(g_width-1 downto 0); signal wr_pointer : unsigned(7 downto 0);
constant address_128bit_shift : std_logic_vector(3 downto 0):= x"0";
signal mem_ack : std_logic; signal mem_ack : std_logic;
signal mem_data_rd : std_logic_vector(4*g_width-1 downto 0); signal mem_data_rd : std_logic_vector(4*g_width-1 downto 0);
...@@ -151,16 +151,17 @@ begin ...@@ -151,16 +151,17 @@ begin
wait until clk ='1'; wait until clk ='1';
end process; end process;
-- the Da Capo flag indicates if the circular buffer has been written completely -- the Da Capo counter indicates the number of times the circular buffer has been written completely
-- it is cleared by the PCIe host. -- it is cleared by the PCIe host.
dacapo_flag_update: process dacapo_counter_update: process
begin begin
if reset ='1' then if reset ='1' then
dacapo_flag <= '0'; dacapo_counter <= (others=>'0');
elsif clear_dacapo_flag ='1' then elsif clear_dacapo_counter ='1' then
dacapo_flag <= '0'; dacapo_counter <= (others=>'0');
elsif wr_pointer = buff_size - 1 then elsif mem_cyc ='1' and mem_stb ='1' and mem_we ='1' and mem_ack ='1'
dacapo_flag <= '1'; and wr_pointer = buff_size - 1 then
dacapo_counter <= dacapo_counter + 1;
end if; end if;
wait until clk ='1'; wait until clk ='1';
end process; end process;
...@@ -194,7 +195,7 @@ begin ...@@ -194,7 +195,7 @@ begin
wait until clk ='1'; wait until clk ='1';
end process; end process;
mem_adr <= std_logic_vector(wr_pointer); mem_adr <= x"000000" & std_logic_vector(wr_pointer);
mem_data_wr <= full_timestamp; mem_data_wr <= full_timestamp;
-- the full timestamp is a 128-bits word divided in four 32-bits words -- the full timestamp is a 128-bits word divided in four 32-bits words
...@@ -262,8 +263,7 @@ begin ...@@ -262,8 +263,7 @@ begin
acam_timestamp2 <= acam_timestamp2_i; acam_timestamp2 <= acam_timestamp2_i;
acam_timestamp2_valid <= acam_timestamp2_valid_i; acam_timestamp2_valid <= acam_timestamp2_valid_i;
clk <= clk_i; clear_dacapo_counter <= clear_dacapo_counter_i;
clear_dacapo_flag <= clear_dacapo_flag_i;
reset <= reset_i; reset <= reset_i;
clk_cycles_offset <= clk_cycles_offset_i; clk_cycles_offset <= clk_cycles_offset_i;
retrig_nb_offset <= retrig_nb_offset_i; retrig_nb_offset <= retrig_nb_offset_i;
...@@ -273,8 +273,9 @@ begin ...@@ -273,8 +273,9 @@ begin
mem_data_rd <= dat_i; mem_data_rd <= dat_i;
-- outputs -- outputs
wr_pointer_o <= dacapo_flag & std_logic_vector(wr_pointer(g_width-6 downto 0)) & x"0"; -- wr_pointer_o <= dacapo_flag & std_logic_vector(wr_pointer(g_width-6 downto 0)) & x"0";
wr_index_o <= std_logic_vector(dacapo_counter) & std_logic_vector(wr_pointer) & address_128bit_shift;
adr_o <= mem_adr; adr_o <= mem_adr;
cyc_o <= mem_cyc; cyc_o <= mem_cyc;
dat_o <= mem_data_wr; dat_o <= mem_data_wr;
......
...@@ -29,19 +29,19 @@ use work.tdc_core_pkg.all; ...@@ -29,19 +29,19 @@ use work.tdc_core_pkg.all;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
entity one_hz_gen is entity one_hz_gen is
generic( generic(
g_width : integer :=32 g_width : integer :=32
); );
port( port(
acam_refclk_i : in std_logic; acam_refclk_edge_p_i : in std_logic;
clk_i : in std_logic; clk : in std_logic;
clock_period_i : in std_logic_vector(g_width-1 downto 0); -- nb of clock periods for 1s clock_period_i : in std_logic_vector(g_width-1 downto 0); -- nb of clock periods for 1s
load_utc_i : in std_logic; load_utc_i : in std_logic;
pulse_delay_i : in std_logic_vector(g_width-1 downto 0); -- nb of clock periods phase delay pulse_delay_i : in std_logic_vector(g_width-1 downto 0); -- nb of clock periods phase delay
reset_i : in std_logic; -- with respect to reference clock reset_i : in std_logic; -- with respect to reference clock
starting_utc_i : in std_logic_vector(g_width-1 downto 0); starting_utc_i : in std_logic_vector(g_width-1 downto 0);
local_utc_o : out std_logic_vector(g_width-1 downto 0); local_utc_o : out std_logic_vector(g_width-1 downto 0);
one_hz_p_o : out std_logic one_hz_p_o : out std_logic
); );
end one_hz_gen; end one_hz_gen;
...@@ -52,47 +52,45 @@ architecture rtl of one_hz_gen is ...@@ -52,47 +52,45 @@ architecture rtl of one_hz_gen is
component free_counter component free_counter
generic( generic(
width : integer :=32 width : integer :=32
); );
port( port(
clk : in std_logic; clk : in std_logic;
enable : in std_logic; enable : in std_logic;
reset : in std_logic; reset : in std_logic;
start_value : in std_logic_vector(width-1 downto 0); start_value : in std_logic_vector(width-1 downto 0);
count_done : out std_logic; count_done : out std_logic;
current_value : out std_logic_vector(width-1 downto 0) current_value : out std_logic_vector(width-1 downto 0)
); );
end component; end component;
component countdown_counter component countdown_counter
generic( generic(
width : integer :=32 width : integer :=32
); );
port( port(
clk : in std_logic; clk : in std_logic;
reset : in std_logic; reset : in std_logic;
start : in std_logic; start : in std_logic;
start_value : in std_logic_vector(width-1 downto 0); start_value : in std_logic_vector(width-1 downto 0);
count_done : out std_logic; count_done : out std_logic;
current_value : out std_logic_vector(width-1 downto 0) current_value : out std_logic_vector(width-1 downto 0)
); );
end component; end component;
constant constant_delay : unsigned(g_width-1 downto 0):=x"00000004"; constant constant_delay : unsigned(g_width-1 downto 0):=x"00000004";
signal clk : std_logic; signal local_utc : unsigned(g_width-1 downto 0);
signal local_utc : unsigned(g_width-1 downto 0); signal load_utc : std_logic;
signal load_utc : std_logic; signal one_hz_p_pre : std_logic;
signal one_hz_p_pre : std_logic; signal one_hz_p_post : std_logic;
signal one_hz_p_post : std_logic; signal onesec_counter_en : std_logic;
signal onesec_counter_en : std_logic; signal acam_refclk_edge_p : std_logic;
signal refclk_edge : std_logic; signal reset : std_logic;
signal reset : std_logic; signal starting_utc : std_logic_vector(g_width-1 downto 0);
signal s_acam_refclk : unsigned(3 downto 0); signal total_delay : std_logic_vector(g_width-1 downto 0);
signal starting_utc : std_logic_vector(g_width-1 downto 0);
signal total_delay : std_logic_vector(g_width-1 downto 0);
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
...@@ -102,37 +100,37 @@ begin ...@@ -102,37 +100,37 @@ begin
clock_periods_counter: free_counter clock_periods_counter: free_counter
generic map( generic map(
width => g_width width => g_width
) )
port map( port map(
clk => clk_i, clk => clk,
enable => onesec_counter_en, enable => onesec_counter_en,
reset => reset_i, reset => reset_i,
start_value => clock_period_i, start_value => clock_period_i,
count_done => one_hz_p_pre, count_done => one_hz_p_pre,
current_value => open current_value => open
); );
pulse_delayer_counter: countdown_counter pulse_delayer_counter: countdown_counter
generic map( generic map(
width => g_width width => g_width
) )
port map( port map(
clk => clk_i, clk => clk,
reset => reset_i, reset => reset_i,
start => one_hz_p_pre, start => one_hz_p_pre,
start_value => total_delay, start_value => total_delay,
count_done => one_hz_p_post, count_done => one_hz_p_post,
current_value => open current_value => open
); );
onesec_trigger: process onesec_trigger: process
begin begin
if reset ='1' then if reset ='1' then
onesec_counter_en <= '0'; onesec_counter_en <= '0';
elsif refclk_edge ='1' then elsif acam_refclk_edge_p ='1' then
onesec_counter_en <= '1'; onesec_counter_en <= '1';
end if; end if;
wait until clk ='1'; wait until clk ='1';
...@@ -141,42 +139,26 @@ begin ...@@ -141,42 +139,26 @@ begin
utc_counter: process utc_counter: process
begin begin
if reset ='1' then if reset ='1' then
local_utc <= (others=>'0'); local_utc <= (others=>'0');
elsif load_utc ='1' then elsif load_utc ='1' then
local_utc <= unsigned(starting_utc); local_utc <= unsigned(starting_utc);
elsif one_hz_p_post ='1' then elsif one_hz_p_post ='1' then
local_utc <= local_utc + 1; local_utc <= local_utc + 1;
end if; end if;
wait until clk ='1'; wait until clk ='1';
end process; end process;
refclk_edge <= not(s_acam_refclk(3)) and total_delay <= std_logic_vector(unsigned(pulse_delay_i)+constant_delay);
s_acam_refclk(2) and
s_acam_refclk(1) and
not(s_acam_refclk(0));
total_delay <= std_logic_vector(unsigned(pulse_delay_i)+constant_delay);
-- inputs -- inputs
sync_acam_refclk: process acam_refclk_edge_p <= acam_refclk_edge_p_i;
begin reset <= reset_i;
if reset ='1' then load_utc <= load_utc_i;
s_acam_refclk <= (others=>'0'); starting_utc <= starting_utc_i;
else
s_acam_refclk <= shift_right(s_acam_refclk,1);
s_acam_refclk(3) <= acam_refclk_i;
end if;
wait until clk ='1';
end process;
clk <= clk_i;
reset <= reset_i;
load_utc <= load_utc_i;
starting_utc <= starting_utc_i;
-- output -- output
local_utc_o <= std_logic_vector(local_utc); local_utc_o <= std_logic_vector(local_utc);
one_hz_p_o <= one_hz_p_post; one_hz_p_o <= one_hz_p_post;
end rtl; end rtl;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
......
This diff is collapsed.
...@@ -36,7 +36,7 @@ entity start_retrigger_control is ...@@ -36,7 +36,7 @@ entity start_retrigger_control is
port( port(
acam_rise_intflag_p_i : in std_logic; acam_rise_intflag_p_i : in std_logic;
acam_fall_intflag_p_i : in std_logic; acam_fall_intflag_p_i : in std_logic;
clk_i : in std_logic; clk : in std_logic;
one_hz_p_i : in std_logic; one_hz_p_i : in std_logic;
reset_i : in std_logic; reset_i : in std_logic;
retrig_period_i : in std_logic_vector(g_width-1 downto 0); retrig_period_i : in std_logic_vector(g_width-1 downto 0);
...@@ -85,7 +85,6 @@ architecture rtl of start_retrigger_control is ...@@ -85,7 +85,6 @@ architecture rtl of start_retrigger_control is
signal acam_fall_intflag_p : std_logic; signal acam_fall_intflag_p : std_logic;
signal acam_rise_intflag_p : std_logic; signal acam_rise_intflag_p : std_logic;
signal add_roll_over : std_logic; signal add_roll_over : std_logic;
signal clk : std_logic;
signal clk_cycles_offset : std_logic_vector(g_width-1 downto 0); signal clk_cycles_offset : std_logic_vector(g_width-1 downto 0);
signal current_cycles : std_logic_vector(g_width-1 downto 0); signal current_cycles : std_logic_vector(g_width-1 downto 0);
signal current_retrig_nb : std_logic_vector(g_width-1 downto 0); signal current_retrig_nb : std_logic_vector(g_width-1 downto 0);
...@@ -99,9 +98,6 @@ signal retrig_period_reset : std_logic; ...@@ -99,9 +98,6 @@ signal retrig_period_reset : std_logic;
signal roll_over_reset : std_logic; signal roll_over_reset : std_logic;
signal roll_over_value : std_logic_vector(g_width-1 downto 0); signal roll_over_value : std_logic_vector(g_width-1 downto 0);
signal acam_halfcounter_gone : std_logic;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- architecture begins -- architecture begins
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
...@@ -176,7 +172,6 @@ begin ...@@ -176,7 +172,6 @@ begin
-- inputs -- inputs
acam_fall_intflag_p <= acam_fall_intflag_p_i; acam_fall_intflag_p <= acam_fall_intflag_p_i;
acam_rise_intflag_p <= acam_rise_intflag_p_i; acam_rise_intflag_p <= acam_rise_intflag_p_i;
clk <= clk_i;
one_hz_p <= one_hz_p_i; one_hz_p <= one_hz_p_i;
reset <= reset_i; reset <= reset_i;
retrig_period <= retrig_period_i; retrig_period <= retrig_period_i;
......
...@@ -70,17 +70,72 @@ package tdc_core_pkg is ...@@ -70,17 +70,72 @@ package tdc_core_pkg is
current_value : out std_logic_vector(width-1 downto 0) current_value : out std_logic_vector(width-1 downto 0)
); );
end component; end component;
constant data_width : integer:=32;
constant tdc_led_period_sim : std_logic_vector(data_width-1 downto 0):=x"0000F424"; -- 500 us at 125 MHz
constant tdc_led_period_syn : std_logic_vector(data_width-1 downto 0):=x"03B9ACA0"; -- 500 ms at 125 MHz
constant spec_led_period_sim : std_logic_vector(data_width-1 downto 0):=x"00004E20"; -- 1 ms at 20 MHz
constant spec_led_period_syn : std_logic_vector(data_width-1 downto 0):=x"01312D00"; -- 1 s at 20 MHz
constant blink_length_syn : std_logic_vector(data_width-1 downto 0):=x"00BEBC20"; -- 100 ms at 125 MHz
constant blink_length_sim : std_logic_vector(data_width-1 downto 0):=x"000004E2"; -- 10 us at 125 MHz
subtype config_register is std_logic_vector(data_width-1 downto 0); constant data_width : integer:=32;
type config_vector is array (10 downto 0) of config_register; constant tdc_led_period_sim : std_logic_vector(data_width-1 downto 0):=x"0000F424"; -- 500 us at 125 MHz
constant tdc_led_period_syn : std_logic_vector(data_width-1 downto 0):=x"03B9ACA0"; -- 500 ms at 125 MHz
constant spec_led_period_sim : std_logic_vector(data_width-1 downto 0):=x"00004E20"; -- 1 ms at 20 MHz
constant spec_led_period_syn : std_logic_vector(data_width-1 downto 0):=x"01312D00"; -- 1 s at 20 MHz
constant blink_length_syn : std_logic_vector(data_width-1 downto 0):=x"00BEBC20"; -- 100 ms at 125 MHz
constant blink_length_sim : std_logic_vector(data_width-1 downto 0):=x"000004E2"; -- 10 us at 125 MHz
subtype config_register is std_logic_vector(data_width-1 downto 0);
type config_vector is array (10 downto 0) of config_register;
-- Addresses of ACAM registers to be written from the PCI-e host for configuration
constant c_acam_adr_reg0 : std_logic_vector(7 downto 0):= x"00"; -- corresponds to address 80000 of the gnum BAR 0
constant c_acam_adr_reg1 : std_logic_vector(7 downto 0):= x"01"; -- corresponds to address 80004 of the gnum BAR 0
constant c_acam_adr_reg2 : std_logic_vector(7 downto 0):= x"02"; -- corresponds to address 80008 of the gnum BAR 0
constant c_acam_adr_reg3 : std_logic_vector(7 downto 0):= x"03"; -- corresponds to address 8000C of the gnum BAR 0
constant c_acam_adr_reg4 : std_logic_vector(7 downto 0):= x"04"; -- corresponds to address 80010 of the gnum BAR 0
constant c_acam_adr_reg5 : std_logic_vector(7 downto 0):= x"05"; -- corresponds to address 80014 of the gnum BAR 0
constant c_acam_adr_reg6 : std_logic_vector(7 downto 0):= x"06"; -- corresponds to address 80018 of the gnum BAR 0
constant c_acam_adr_reg7 : std_logic_vector(7 downto 0):= x"07"; -- corresponds to address 8001C of the gnum BAR 0
constant c_acam_adr_reg11 : std_logic_vector(7 downto 0):= x"0B"; -- corresponds to address 8002C of the gnum BAR 0
constant c_acam_adr_reg12 : std_logic_vector(7 downto 0):= x"0C"; -- corresponds to address 80030 of the gnum BAR 0
constant c_acam_adr_reg14 : std_logic_vector(7 downto 0):= x"0E"; -- corresponds to address 80038 of the gnum BAR 0
-- Addresses of ACAM read-only register (used within the core to access ACAM timestamps)
constant c_acam_adr_reg8 : std_logic_vector(7 downto 0):= x"08"; -- not accessible for writing from PCI-e
constant c_acam_adr_reg9 : std_logic_vector(7 downto 0):= x"09"; -- not accessible for writing from PCI-e
constant c_acam_adr_reg10 : std_logic_vector(7 downto 0):= x"0A"; -- not accessible for writing from PCI-e
-- Addresses of ACAM registers readback
constant c_acam_adr_reg0_rdbk : std_logic_vector(7 downto 0):= x"10"; -- corresponds to address 80040 of the gnum BAR 0
constant c_acam_adr_reg1_rdbk : std_logic_vector(7 downto 0):= x"11"; -- corresponds to address 80044 of the gnum BAR 0
constant c_acam_adr_reg2_rdbk : std_logic_vector(7 downto 0):= x"12"; -- corresponds to address 80048 of the gnum BAR 0
constant c_acam_adr_reg3_rdbk : std_logic_vector(7 downto 0):= x"13"; -- corresponds to address 8004C of the gnum BAR 0
constant c_acam_adr_reg4_rdbk : std_logic_vector(7 downto 0):= x"14"; -- corresponds to address 80050 of the gnum BAR 0
constant c_acam_adr_reg5_rdbk : std_logic_vector(7 downto 0):= x"15"; -- corresponds to address 80054 of the gnum BAR 0
constant c_acam_adr_reg6_rdbk : std_logic_vector(7 downto 0):= x"16"; -- corresponds to address 80058 of the gnum BAR 0
constant c_acam_adr_reg7_rdbk : std_logic_vector(7 downto 0):= x"17"; -- corresponds to address 8005C of the gnum BAR 0
constant c_acam_adr_reg8_rdbk : std_logic_vector(7 downto 0):= x"18"; -- corresponds to address 80060 of the gnum BAR 0
constant c_acam_adr_reg9_rdbk : std_logic_vector(7 downto 0):= x"19"; -- corresponds to address 80064 of the gnum BAR 0
constant c_acam_adr_reg10_rdbk : std_logic_vector(7 downto 0):= x"1A"; -- corresponds to address 80068 of the gnum BAR 0
constant c_acam_adr_reg11_rdbk : std_logic_vector(7 downto 0):= x"1B"; -- corresponds to address 8006C of the gnum BAR 0
constant c_acam_adr_reg12_rdbk : std_logic_vector(7 downto 0):= x"1C"; -- corresponds to address 80070 of the gnum BAR 0
constant c_acam_adr_reg14_rdbk : std_logic_vector(7 downto 0):= x"1E"; -- corresponds to address 80078 of the gnum BAR 0
-- Addresses of TDC core configuration registers
constant c_starting_utc_adr : std_logic_vector(7 downto 0):= x"20"; -- corresponds to address 80080 of the gnum BAR 0
constant c_in_en_ctrl_adr : std_logic_vector(7 downto 0):= x"21"; -- corresponds to address 80084 of the gnum BAR 0
constant c_start_phase_adr : std_logic_vector(7 downto 0):= x"22"; -- corresponds to address 80088 of the gnum BAR 0
constant c_one_hz_phase_adr : std_logic_vector(7 downto 0):= x"23"; -- corresponds to address 8008C of the gnum BAR 0
--constant c_irq_config_adr : std_logic_vector(7 downto 0):= x"24";
-- Addresses of TDC core status registers
constant c_local_utc_adr : std_logic_vector(7 downto 0):= x"25"; -- corresponds to address 80094 of the gnum BAR 0
constant c_irq_code_adr : std_logic_vector(7 downto 0):= x"26"; -- corresponds to address 80098 of the gnum BAR 0
constant c_wr_index_adr : std_logic_vector(7 downto 0):= x"27"; -- corresponds to address 8009C of the gnum BAR 0
constant c_core_status_adr : std_logic_vector(7 downto 0):= x"28"; -- corresponds to address 800A0 of the gnum BAR 0
-- Address of TDC core control register
constant c_control_register_adr : std_logic_vector(7 downto 0):= x"3F"; -- corresponds to address 800FC of the gnum BAR 0
end tdc_core_pkg; end tdc_core_pkg;
......
This diff is collapsed.
...@@ -486,7 +486,8 @@ begin ...@@ -486,7 +486,8 @@ begin
tstop2_i => tstop2, tstop2_i => tstop2,
tstop3_i => tstop3, tstop3_i => tstop3,
tstop4_i => tstop4, tstop4_i => tstop4,
tstop5_i => dummy_tstop5, tstop5_i => tstop5,
-- tstop5_i => dummy_tstop5,
startdis_i => start_dis_o, startdis_i => start_dis_o,
stopdis_i => stop_dis_o, stopdis_i => stop_dis_o,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment