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FMC TDC 1ns 5cha - Gateware
Commits
1b4e6b54
Commit
1b4e6b54
authored
Mar 18, 2015
by
Tomasz Wlostowski
Browse files
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Plain Diff
TDC core wisbhone now synchronous to system clock
parent
1f8235d9
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Showing
6 changed files
with
862 additions
and
881 deletions
+862
-881
circular_buffer.vhd
hdl/wr_spec_tdc/hdl/rtl/circular_buffer.vhd
+8
-7
fmc_tdc_core.vhd
hdl/wr_spec_tdc/hdl/rtl/fmc_tdc_core.vhd
+124
-121
fmc_tdc_mezzanine.vhd
hdl/wr_spec_tdc/hdl/rtl/fmc_tdc_mezzanine.vhd
+528
-548
reg_ctrl.vhd
hdl/wr_spec_tdc/hdl/rtl/reg_ctrl.vhd
+77
-65
fmc_tdc_wrapper.vhd
hdl/wr_spec_tdc/hdl/top/spec/fmc_tdc_wrapper.vhd
+13
-34
tdc_core_pkg.vhd
hdl/wr_spec_tdc/hdl/top/spec/tdc_core_pkg.vhd
+112
-106
No files found.
hdl/wr_spec_tdc/hdl/rtl/circular_buffer.vhd
View file @
1b4e6b54
...
...
@@ -105,7 +105,8 @@ entity circular_buffer is
port
-- INPUTS
-- Signal from the clk_rst_manager
(
clk_i
:
in
std_logic
;
-- 125 MHz clock; same for both ports
(
clk_tdc_i
:
in
std_logic
;
-- 125 MHz clock; same for both ports
clk_sys_i
:
in
std_logic
;
-- Signals from the data_formatting unit (WISHBONE classic): timestamps writing
tstamp_wr_rst_i
:
in
std_logic
;
-- timestamp writing WISHBONE reset
...
...
@@ -155,9 +156,9 @@ begin
-- TIMESTAMP WRITINGS WISHBONE CLASSIC ACK --
---------------------------------------------------------------------------------------------------
-- WISHBONE classic interface compatible slave
classic_interface
:
process
(
clk_i
)
classic_interface
:
process
(
clk_
tdc_
i
)
begin
if
rising_edge
(
clk_i
)
then
if
rising_edge
(
clk_
tdc_
i
)
then
if
tstamp_wr_rst_i
=
'1'
then
tstamp_wr_ack_p
<=
'0'
;
...
...
@@ -186,9 +187,9 @@ begin
-- ACK : _________________|-----------------------------------|_____
-- DATO: <DAT0><DAT1><DAT2><DAT3><DAT4><DAT5>
WB_pipe_ack_fsm_seq
:
process
(
clk_i
)
WB_pipe_ack_fsm_seq
:
process
(
clk_
sys_
i
)
begin
if
rising_edge
(
clk_i
)
then
if
rising_edge
(
clk_
sys_
i
)
then
if
tdc_mem_wb_rst_i
=
'1'
then
tstamp_rd_wb_st
<=
IDLE
;
else
...
...
@@ -275,7 +276,7 @@ begin
memory_block
:
blk_mem_circ_buff_v6_4
port
map
(
-- Port A: attached to the data_formatting unit
clka
=>
clk_i
,
clka
=>
clk_
tdc_
i
,
addra
=>
tstamp_wr_adr_i
(
7
downto
0
),
-- 2^8 = 256 addresses
dina
=>
tstamp_wr_dat_i
,
-- 128-bit long timestamps
ena
=>
tstamp_wr_cyc_i
,
...
...
@@ -283,7 +284,7 @@ begin
douta
=>
tstamp_wr_dat_o
,
-- not used
-- Port B: attached to the GN4124/VME_core unit
clkb
=>
clk_i
,
clkb
=>
clk_
sys_
i
,
addrb
=>
tdc_mem_wb_adr_i
(
9
downto
0
),
-- 2^10 = 1024 addresses
dinb
=>
tdc_mem_wb_dat_i
,
-- not used
enb
=>
tdc_mem_wb_cyc_i
,
...
...
hdl/wr_spec_tdc/hdl/rtl/fmc_tdc_core.vhd
View file @
1b4e6b54
...
...
@@ -161,79 +161,76 @@ entity fmc_tdc_core is
values_for_simul
:
boolean
:
=
FALSE
);
-- this generic is set to TRUE
-- when instantiated in a test-bench
port
(
-- Clock and reset
clk_125m_i
:
in
std_logic
;
-- 125 MHz clk from the PLL on the TDC mezz
rst_i
:
in
std_logic
;
-- global reset, synched to clk_125m_i
acam_refclk_r_edge_p_i
:
in
std_logic
;
-- rising edge on 31.25MHz ACAM reference clock
send_dac_word_p_o
:
out
std_logic
;
-- command from GN4124/VME to reconfigure the TDC mezz DAC with dac_word_o
dac_word_o
:
out
std_logic_vector
(
23
downto
0
);
-- new DAC configuration word from GN4124/VME
-- Signals for the timing interface with the ACAM on TDC mezzanine
start_from_fpga_o
:
out
std_logic
;
-- start pulse
err_flag_i
:
in
std_logic
;
-- error flag
int_flag_i
:
in
std_logic
;
-- interrupt flag
start_dis_o
:
out
std_logic
;
-- start disable, not used
stop_dis_o
:
out
std_logic
;
-- disables all acam channels
-- Signals for the data interface with the ACAM on TDC mezzanine
data_bus_io
:
inout
std_logic_vector
(
27
downto
0
);
address_o
:
out
std_logic_vector
(
3
downto
0
);
cs_n_o
:
out
std_logic
;
-- chip select for ACAM
oe_n_o
:
out
std_logic
;
-- output enable for ACAM
rd_n_o
:
out
std_logic
;
-- read signal for ACAM
wr_n_o
:
out
std_logic
;
-- write signal for ACAM
ef1_i
:
in
std_logic
;
-- empty flag of ACAM iFIFO1
ef2_i
:
in
std_logic
;
-- empty flag of ACAM iFIFO2
-- Signals for the Input Logic on TDC mezzanine
enable_inputs_o
:
out
std_logic
;
-- enables all 5 inputs
term_en_1_o
:
out
std_logic
;
-- Ch.1 termination enable of 50 Ohm termination
term_en_2_o
:
out
std_logic
;
-- Ch.2 termination enable of 50 Ohm termination
term_en_3_o
:
out
std_logic
;
-- Ch.3 termination enable of 50 Ohm termination
term_en_4_o
:
out
std_logic
;
-- Ch.4 termination enable of 50 Ohm termination
term_en_5_o
:
out
std_logic
;
-- Ch.5 termination enable of 50 Ohm termination
-- LEDs on TDC mezzanine
tdc_led_status_o
:
out
std_logic
;
-- amber led on front pannel, division of clk_125m_i
tdc_led_trig1_o
:
out
std_logic
;
-- amber led on front pannel, Ch.1 termination
tdc_led_trig2_o
:
out
std_logic
;
-- amber led on front pannel, Ch.2 termination
tdc_led_trig3_o
:
out
std_logic
;
-- amber led on front pannel, Ch.3 termination
tdc_led_trig4_o
:
out
std_logic
;
-- amber led on front pannel, Ch.4 termination
tdc_led_trig5_o
:
out
std_logic
;
-- amber led on front pannel, Ch.5 termination
-- TDC input signals, also arriving to the FPGA; not used currently
tdc_in_fpga_1_i
:
in
std_logic
;
-- TDC input Ch.1, not used
tdc_in_fpga_2_i
:
in
std_logic
;
-- TDC input Ch.2, not used
tdc_in_fpga_3_i
:
in
std_logic
;
-- TDC input Ch.3, not used
tdc_in_fpga_4_i
:
in
std_logic
;
-- TDC input Ch.4, not used
tdc_in_fpga_5_i
:
in
std_logic
;
-- TDC input Ch.5, not used
-- Interrupts
irq_tstamp_p_o
:
out
std_logic
;
-- if amount of tstamps > tstamps_threshold
irq_time_p_o
:
out
std_logic
;
-- if 0 < amount of tstamps < tstamps_threshold and time > time_threshold
irq_acam_err_p_o
:
out
std_logic
;
-- if ACAM err_flag_i is activated
-- White Rabbit control and status registers
wrabbit_status_reg_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
wrabbit_ctrl_reg_o
:
out
std_logic_vector
(
g_width
-1
downto
0
);
-- White Rabbit timing
wrabbit_synched_i
:
in
std_logic
;
wrabbit_tai_p_i
:
in
std_logic
;
wrabbit_tai_i
:
in
std_logic_vector
(
31
downto
0
);
-- WISHBONE bus interface with the GN4124/VME core for the configuration of the TDC core
tdc_config_wb_adr_i
:
in
std_logic_vector
(
g_span
-1
downto
0
);
-- WISHBONE classic address
tdc_config_wb_dat_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
-- WISHBONE classic data in
tdc_config_wb_stb_i
:
in
std_logic
;
-- WISHBONE classic strobe
tdc_config_wb_we_i
:
in
std_logic
;
-- WISHBONE classic write enable
tdc_config_wb_cyc_i
:
in
std_logic
;
-- WISHBONE classic cycle
tdc_config_wb_ack_o
:
out
std_logic
;
-- WISHBONE classic acknowledge
tdc_config_wb_dat_o
:
out
std_logic_vector
(
g_width
-1
downto
0
);
-- WISHBONE classic data out
-- WISHBONE bus interface with the GN4124/VME core for the retrieval of the timestamps from the TDC core memory
tdc_mem_wb_adr_i
:
in
std_logic_vector
(
31
downto
0
);
-- WISHBONE pipelined address
tdc_mem_wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
-- WISHBONE pipelined data in
tdc_mem_wb_stb_i
:
in
std_logic
;
-- WISHBONE pipelined strobe
tdc_mem_wb_we_i
:
in
std_logic
;
-- WISHBONE pipelined write enable
tdc_mem_wb_cyc_i
:
in
std_logic
;
-- WISHBONE pipelined cycle
tdc_mem_wb_ack_o
:
out
std_logic
;
-- WISHBONE pipelined acknowledge
tdc_mem_wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
-- WISHBONE pipelined data out
tdc_mem_wb_stall_o
:
out
std_logic
;
-- WISHBONE pipelined stall
direct_timestamp_o
:
out
std_logic_vector
(
127
downto
0
);
direct_timestamp_stb_o
:
out
std_logic
);
(
clk_sys_i
:
in
std_logic
;
rst_n_sys_i
:
in
std_logic
;
clk_tdc_i
:
in
std_logic
;
-- 125 MHz reference from the PLL
rst_tdc_i
:
in
std_logic
;
-- global reset, synched to clk_tdc_i
acam_refclk_r_edge_p_i
:
in
std_logic
;
-- rising edge on 31.25MHz ACAM reference clock
send_dac_word_p_o
:
out
std_logic
;
-- command from GN4124/VME to reconfigure the TDC mezz DAC with dac_word_o
dac_word_o
:
out
std_logic_vector
(
23
downto
0
);
-- new DAC configuration word from GN4124/VME
-- Signals for the timing interface with the ACAM on TDC mezzanine
start_from_fpga_o
:
out
std_logic
;
-- start pulse
err_flag_i
:
in
std_logic
;
-- error flag
int_flag_i
:
in
std_logic
;
-- interrupt flag
start_dis_o
:
out
std_logic
;
-- start disable, not used
stop_dis_o
:
out
std_logic
;
-- disables all acam channels
-- Signals for the data interface with the ACAM on TDC mezzanine
data_bus_io
:
inout
std_logic_vector
(
27
downto
0
);
address_o
:
out
std_logic_vector
(
3
downto
0
);
cs_n_o
:
out
std_logic
;
-- chip select for ACAM
oe_n_o
:
out
std_logic
;
-- output enable for ACAM
rd_n_o
:
out
std_logic
;
-- read signal for ACAM
wr_n_o
:
out
std_logic
;
-- write signal for ACAM
ef1_i
:
in
std_logic
;
-- empty flag of ACAM iFIFO1
ef2_i
:
in
std_logic
;
-- empty flag of ACAM iFIFO2
-- Signals for the Input Logic on TDC mezzanine
enable_inputs_o
:
out
std_logic
;
-- enables all 5 inputs
term_en_1_o
:
out
std_logic
;
-- Ch.1 termination enable of 50 Ohm termination
term_en_2_o
:
out
std_logic
;
-- Ch.2 termination enable of 50 Ohm termination
term_en_3_o
:
out
std_logic
;
-- Ch.3 termination enable of 50 Ohm termination
term_en_4_o
:
out
std_logic
;
-- Ch.4 termination enable of 50 Ohm termination
term_en_5_o
:
out
std_logic
;
-- Ch.5 termination enable of 50 Ohm termination
-- LEDs on TDC mezzanine
tdc_led_status_o
:
out
std_logic
;
-- amber led on front pannel, division of clk_tdc_i
tdc_led_trig1_o
:
out
std_logic
;
-- amber led on front pannel, Ch.1 termination
tdc_led_trig2_o
:
out
std_logic
;
-- amber led on front pannel, Ch.2 termination
tdc_led_trig3_o
:
out
std_logic
;
-- amber led on front pannel, Ch.3 termination
tdc_led_trig4_o
:
out
std_logic
;
-- amber led on front pannel, Ch.4 termination
tdc_led_trig5_o
:
out
std_logic
;
-- amber led on front pannel, Ch.5 termination
-- TDC input signals, also arriving to the FPGA; not used currently
tdc_in_fpga_1_i
:
in
std_logic
;
-- TDC input Ch.1, not used
tdc_in_fpga_2_i
:
in
std_logic
;
-- TDC input Ch.2, not used
tdc_in_fpga_3_i
:
in
std_logic
;
-- TDC input Ch.3, not used
tdc_in_fpga_4_i
:
in
std_logic
;
-- TDC input Ch.4, not used
tdc_in_fpga_5_i
:
in
std_logic
;
-- TDC input Ch.5, not used
-- Interrupts
irq_tstamp_p_o
:
out
std_logic
;
-- if amount of tstamps > tstamps_threshold
irq_time_p_o
:
out
std_logic
;
-- if 0 < amount of tstamps < tstamps_threshold and time > time_threshold
irq_acam_err_p_o
:
out
std_logic
;
-- if ACAM err_flag_i is activated
-- White Rabbit control and status registers
wrabbit_status_reg_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
wrabbit_ctrl_reg_o
:
out
std_logic_vector
(
g_width
-1
downto
0
);
-- White Rabbit timing
wrabbit_synched_i
:
in
std_logic
;
wrabbit_tai_p_i
:
in
std_logic
;
wrabbit_tai_i
:
in
std_logic_vector
(
31
downto
0
);
-- WISHBONE bus interface with the GN4124/VME core for the configuration
-- of the TDC core (clk_sys)
cfg_slave_i
:
in
t_wishbone_slave_in
;
cfg_slave_o
:
out
t_wishbone_slave_out
;
-- WISHBONE bus interface with the GN4124/VME core for the retrieval
-- of the timestamps from the TDC core memory (clk_sys)
mem_slave_i
:
in
t_wishbone_slave_in
;
mem_slave_o
:
out
t_wishbone_slave_out
;
direct_timestamp_o
:
out
std_logic_vector
(
127
downto
0
);
direct_timestamp_stb_o
:
out
std_logic
);
end
fmc_tdc_core
;
...
...
@@ -281,7 +278,10 @@ architecture rtl of fmc_tdc_core is
signal
tdc_in_fpga_1
,
tdc_in_fpga_2
,
tdc_in_fpga_3
:
std_logic_vector
(
1
downto
0
);
signal
tdc_in_fpga_4
,
tdc_in_fpga_5
:
std_logic_vector
(
1
downto
0
);
signal
acam_tstamp_channel
:
std_logic_vector
(
2
downto
0
);
-- Chipscope
signal
rst_sys
:
std_logic
;
-- Chipscope
component
chipscope_ila
port
(
CONTROL
:
inout
std_logic_vector
(
35
downto
0
);
...
...
@@ -308,6 +308,8 @@ architecture rtl of fmc_tdc_core is
--=================================================================================================
begin
rst_sys
<=
not
rst_n_sys_i
;
---------------------------------------------------------------------------------------------------
-- TDC REGISTERS CONTROLLER --
---------------------------------------------------------------------------------------------------
...
...
@@ -316,15 +318,15 @@ begin
(
g_span
=>
g_span
,
g_width
=>
g_width
)
port
map
(
clk_
i
=>
clk_125m
_i
,
rst_
i
=>
rst
_i
,
tdc_config_wb_adr_i
=>
tdc_config_wb_adr
_i
,
tdc_config_wb_dat_i
=>
tdc_config_wb_dat
_i
,
tdc_config_wb_stb_i
=>
tdc_config_wb_stb_i
,
tdc_config_wb_we_i
=>
tdc_config_wb_we_i
,
tdc_config_wb_cyc_i
=>
tdc_config_wb_cyc
_i
,
tdc_config_wb_ack_o
=>
tdc_config_wb_ack
_o
,
tdc_config_wb_dat_o
=>
tdc_config_wb_dat_o
,
(
clk_
tdc_i
=>
clk_tdc
_i
,
rst_
tdc_i
=>
rst_tdc
_i
,
clk_sys_i
=>
clk_sys
_i
,
rst_n_sys_i
=>
rst_n_sys
_i
,
slave_i
=>
cfg_slave
_i
,
slave_o
=>
cfg_slave
_o
,
activate_acq_p_o
=>
activate_acq_p
,
deactivate_acq_p_o
=>
deactivate_acq_p
,
acam_wr_config_p_o
=>
load_acam_config
,
...
...
@@ -336,7 +338,7 @@ begin
acam_rst_p_o
=>
reset_acam
,
load_utc_p_o
=>
load_utc
,
dacapo_c_rst_p_o
=>
clear_dacapo_counter
,
deactivate_chan_o
=>
deactivate_chan
,
deactivate_chan_o
=>
deactivate_chan
,
acam_config_rdbk_i
=>
acam_config_rdbk
,
acam_ififo1_i
=>
acam_ififo1
,
acam_ififo2_i
=>
acam_ififo2
,
...
...
@@ -362,10 +364,10 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- termination enable registers
term_enable_regs
:
process
(
clk_
125m
_i
)
term_enable_regs
:
process
(
clk_
tdc
_i
)
begin
if
rising_edge
(
clk_
125m
_i
)
then
if
rst_i
=
'1'
then
if
rising_edge
(
clk_
tdc
_i
)
then
if
rst_
tdc_
i
=
'1'
then
enable_inputs_o
<=
'0'
;
term_en_5_o
<=
'0'
;
term_en_4_o
<=
'0'
;
...
...
@@ -392,11 +394,11 @@ begin
(
g_width
=>
g_width
)
port
map
(
acam_refclk_r_edge_p_i
=>
acam_refclk_r_edge_p_i
,
clk_i
=>
clk_
125m
_i
,
clk_i
=>
clk_
tdc
_i
,
clk_period_i
=>
clk_period
,
load_utc_p_i
=>
load_utc
,
pulse_delay_i
=>
pulse_delay
,
rst_i
=>
rst_i
,
rst_i
=>
rst_
tdc_
i
,
starting_utc_i
=>
starting_utc
,
local_utc_o
=>
local_utc
,
local_utc_p_o
=>
local_utc_p
);
...
...
@@ -408,18 +410,18 @@ begin
-- ACAM TIMECONTROL INTERFACE --
---------------------------------------------------------------------------------------------------
acam_timing_block
:
acam_timecontrol_interface
port
map
port
map
(
err_flag_i
=>
err_flag_i
,
int_flag_i
=>
int_flag_i
,
start_from_fpga_o
=>
start_from_fpga
,
stop_dis_o
=>
stop_dis_o
,
stop_dis_o
=>
stop_dis_o
,
acam_refclk_r_edge_p_i
=>
acam_refclk_r_edge_p_i
,
utc_p_i
=>
utc_p
,
clk_i
=>
clk_
125m
_i
,
clk_i
=>
clk_
tdc
_i
,
activate_acq_p_i
=>
activate_acq_p
,
state_active_p_i
=>
state_active_p
,
deactivate_acq_p_i
=>
deactivate_acq_p
,
rst_i
=>
rst_i
,
state_active_p_i
=>
state_active_p
,
deactivate_acq_p_i
=>
deactivate_acq_p
,
rst_i
=>
rst_
tdc_
i
,
acam_errflag_f_edge_p_o
=>
acam_errflag_f_edge_p
,
acam_errflag_r_edge_p_o
=>
acam_errflag_r_edge_p
,
acam_intflag_f_edge_p_o
=>
acam_intflag_f_edge_p
);
...
...
@@ -444,8 +446,8 @@ begin
ef1_meta_o
=>
acam_ef1_meta
,
ef2_o
=>
acam_ef2
,
ef2_meta_o
=>
acam_ef2_meta
,
clk_i
=>
clk_
125m
_i
,
rst_i
=>
rst_i
,
clk_i
=>
clk_
tdc
_i
,
rst_i
=>
rst_
tdc_
i
,
adr_i
=>
acm_adr
,
cyc_i
=>
acm_cyc
,
dat_i
=>
acm_dat_w
,
...
...
@@ -463,10 +465,10 @@ begin
(
g_width
=>
g_width
)
port
map
(
acam_intflag_f_edge_p_i
=>
acam_intflag_f_edge_p
,
clk_i
=>
clk_
125m
_i
,
clk_i
=>
clk_
tdc
_i
,
utc_p_i
=>
utc_p
,
rst_i
=>
rst_i
,
current_retrig_nb_o
=>
current_retrig_nb
,
-- for debug
rst_i
=>
rst_
tdc_
i
,
current_retrig_nb_o
=>
current_retrig_nb
,
-- for debug
roll_over_incr_recent_o
=>
roll_over_incr_recent
,
clk_i_cycles_offset_o
=>
clk_i_cycles_offset
,
roll_over_nb_o
=>
roll_over_nb
,
...
...
@@ -485,8 +487,8 @@ begin
acam_dat_o
=>
acm_dat_w
,
acam_stb_o
=>
acm_stb
,
acam_we_o
=>
acm_we
,
clk_i
=>
clk_
125m
_i
,
rst_i
=>
rst_i
,
clk_i
=>
clk_
tdc
_i
,
rst_i
=>
rst_
tdc_
i
,
acam_ef1_i
=>
acam_ef1
,
acam_ef1_meta_i
=>
acam_ef1_meta
,
acam_ef2_i
=>
acam_ef2
,
...
...
@@ -518,8 +520,8 @@ begin
---------------------------------------------------------------------------------------------------
data_formatting_block
:
data_formatting
port
map
(
clk_i
=>
clk_
125m
_i
,
rst_i
=>
rst_i
,
(
clk_i
=>
clk_
tdc
_i
,
rst_i
=>
rst_
tdc_
i
,
tstamp_wr_wb_ack_i
=>
circ_buff_class_ack
,
tstamp_wr_dat_i
=>
circ_buff_class_data_rd
,
tstamp_wr_wb_adr_o
=>
circ_buff_class_adr
,
...
...
@@ -560,8 +562,8 @@ begin
generic
map
(
g_width
=>
32
)
port
map
(
clk_i
=>
clk_
125m
_i
,
rst_i
=>
rst_i
,
(
clk_i
=>
clk_
tdc
_i
,
rst_i
=>
rst_
tdc_
i
,
irq_tstamp_threshold_i
=>
irq_tstamp_threshold
,
irq_time_threshold_i
=>
irq_time_threshold
,
acam_errflag_r_edge_p_i
=>
acam_errflag_r_edge_p
,
...
...
@@ -578,8 +580,9 @@ begin
---------------------------------------------------------------------------------------------------
circular_buffer_block
:
circular_buffer
port
map
(
clk_i
=>
clk_125m_i
,
tstamp_wr_rst_i
=>
rst_i
,
(
clk_tdc_i
=>
clk_tdc_i
,
clk_sys_i
=>
clk_sys_i
,
tstamp_wr_rst_i
=>
rst_tdc_i
,
tstamp_wr_adr_i
=>
circ_buff_class_adr
,
tstamp_wr_cyc_i
=>
circ_buff_class_cyc
,
tstamp_wr_dat_i
=>
circ_buff_class_data_wr
,
...
...
@@ -587,15 +590,15 @@ begin
tstamp_wr_we_i
=>
circ_buff_class_we
,
tstamp_wr_ack_p_o
=>
circ_buff_class_ack
,
tstamp_wr_dat_o
=>
circ_buff_class_data_rd
,
tdc_mem_wb_rst_i
=>
rst_
i
,
tdc_mem_wb_adr_i
=>
tdc_mem_wb_adr_i
,
tdc_mem_wb_cyc_i
=>
tdc_mem_wb_cyc_i
,
tdc_mem_wb_dat_i
=>
tdc_mem_wb_dat_i
,
tdc_mem_wb_stb_i
=>
tdc_mem_wb_stb_i
,
tdc_mem_wb_we_i
=>
tdc_mem_wb_we_i
,
tdc_mem_wb_ack_o
=>
tdc_mem_wb_ack_o
,
tdc_mem_wb_dat_o
=>
tdc_mem_wb_dat_o
,
tdc_mem_wb_stall_o
=>
tdc_mem_wb_stall_o
);
tdc_mem_wb_rst_i
=>
rst_
sys
,
tdc_mem_wb_adr_i
=>
mem_slave_i
.
adr
,
tdc_mem_wb_cyc_i
=>
mem_slave_i
.
cyc
,
tdc_mem_wb_dat_i
=>
mem_slave_i
.
dat
,
tdc_mem_wb_stb_i
=>
mem_slave_i
.
stb
,
tdc_mem_wb_we_i
=>
mem_slave_i
.
we
,
tdc_mem_wb_ack_o
=>
mem_slave_o
.
ack
,
tdc_mem_wb_dat_o
=>
mem_slave_o
.
dat
,
tdc_mem_wb_stall_o
=>
mem_slave_o
.
stall
);
---------------------------------------------------------------------------------------------------
...
...
@@ -606,8 +609,8 @@ begin
(
g_width
=>
32
,
values_for_simul
=>
values_for_simul
)
port
map
(
clk_i
=>
clk_
125m
_i
,
rst_i
=>
rst_i
,
(
clk_i
=>
clk_
tdc
_i
,
rst_i
=>
rst_
tdc_
i
,
utc_p_i
=>
local_utc_p
,
acam_inputs_en_i
=>
acam_inputs_en
,
acam_channel_i
=>
acam_channel
,
...
...
@@ -633,7 +636,7 @@ begin
-- chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
-- CLK => clk_
125m
_i,
-- CLK => clk_
tdc
_i,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
...
...
@@ -664,4 +667,4 @@ begin
end
rtl
;
----------------------------------------------------------------------------------------------------
-- architecture ends
----------------------------------------------------------------------------------------------------
\ No newline at end of file
----------------------------------------------------------------------------------------------------
hdl/wr_spec_tdc/hdl/rtl/fmc_tdc_mezzanine.vhd
View file @
1b4e6b54
--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- fmc_tdc_mezzanine |
-- |
---------------------------------------------------------------------------------------------------
-- File fmc_tdc_mezzanine.vhd |
-- |
-- Description The unit combines |
-- o the TDC core |
-- o the wrabbit_sync unit that is managing the White Rabbit synchronization and |
-- control signals |
-- o the I2C core for the communication with the TDC board EEPROM |
-- o the OneWire core for the communication with the TDC board UniqueID&Thermeter |
-- o the Embedded Interrupt Controller core that concentrates several interrupt |
-- sources into one WISHBONE interrupt request line. |
-- |
-- For the interconnection between the GN4124/VME core and the different cores (TDC, |
-- I2C, 1W, EIC, timestamps memory) the unit instantiates an SDB crossbar. |
-- |
-- Note that the TDC core uses word addressing, whereas the GN4124/VME cores use byte|
-- addressing |
-- _______________________________ |
-- | FMC TDC mezzanine | |
-- | | |
-- | ________________ | |
-- | |--| WRabbit_sync | | |
-- | | |________________| | |
-- | | ________________ ___ | |
-- | |->| | | | | |
-- ACAM chip <--> | | TDC core | | | | <--> |
-- | |--|________________| | S | | |
-- | | ________________ | | | |
-- | | | | | | | |
-- EEPROM chip <--> | | | I2C core | | | | <--> |
-- | | |________________| | | | |
-- | | ________________ | D | | GN4124/VME core |
-- | | | | | | | |
-- 1W chip <--> | | | 1W core | | | | <--> |
-- | | |________________| | | | |
-- | | ________________ | | | |
-- | | | | | B | | |
-- | |->| EIC | | | | <--> |
-- | |________________| |___| | |
-- | | |
-- |________________________________| |
-- ^ ^ |
-- | 125 MHz rst | |
-- __|________________________|___ |
-- | | |
-- DAC chip <--> | clks_rsts_manager | |
-- PLL chip |_______________________________| |
-- |
-- Figure 1: FMC TDC mezzanine architecture and |
-- connection with the clks_rsts_manager unit |
-- |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 01/2014 |
-- Version v2 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 07/2013 v1 EG First version |
-- 01/2014 v2 EG Different output for the timestamp data |
-- 01/2014 v3 EG Removed option for timestamps retrieval through DMA |
-- 08/2014 v4 EG Corrected missalignement between wrabbit_tai and wrabbit_tai_p (line 444) |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
library
IEEE
;
use
IEEE
.
std_logic_1164
.
all
;
use
IEEE
.
numeric_std
.
all
;
use
work
.
tdc_core_pkg
.
all
;
use
work
.
gencores_pkg
.
all
;
use
work
.
wishbone_pkg
.
all
;
--=================================================================================================
-- Entity declaration for fmc_tdc_mezzanine
--=================================================================================================
entity
fmc_tdc_mezzanine
is
generic
(
g_with_wrabbit_core
:
boolean
:
=
FALSE
;
g_span
:
integer
:
=
32
;
g_width
:
integer
:
=
32
;
values_for_simul
:
boolean
:
=
FALSE
);
port
-- TDC core
(
-- Clock & reset 62M5
clk_sys_i
:
in
std_logic
;
-- 62.5 MHz clock
rst_sys_n_i
:
in
std_logic
;
-- reset for 62.5 MHz logic
-- Signals from the clks_rsts_manager unit
clk_ref_0_i
:
in
std_logic
;
-- 125 MHz clock
rst_ref_0_i
:
in
std_logic
;
-- reset for 125 MHz logic
acam_refclk_r_edge_p_i
:
in
std_logic
;
send_dac_word_p_o
:
out
std_logic
;
dac_word_o
:
out
std_logic_vector
(
23
downto
0
);
-- Interface with ACAM
start_from_fpga_o
:
out
std_logic
;
err_flag_i
:
in
std_logic
;
int_flag_i
:
in
std_logic
;
start_dis_o
:
out
std_logic
;
stop_dis_o
:
out
std_logic
;
data_bus_io
:
inout
std_logic_vector
(
27
downto
0
);
address_o
:
out
std_logic_vector
(
3
downto
0
);
cs_n_o
:
out
std_logic
;
oe_n_o
:
out
std_logic
;
rd_n_o
:
out
std_logic
;
wr_n_o
:
out
std_logic
;
ef1_i
:
in
std_logic
;
ef2_i
:
in
std_logic
;
-- Channels termination
enable_inputs_o
:
out
std_logic
;
term_en_1_o
:
out
std_logic
;
term_en_2_o
:
out
std_logic
;
term_en_3_o
:
out
std_logic
;
term_en_4_o
:
out
std_logic
;
term_en_5_o
:
out
std_logic
;
-- TDC board LEDs
tdc_led_status_o
:
out
std_logic
;
tdc_led_trig1_o
:
out
std_logic
;
tdc_led_trig2_o
:
out
std_logic
;
tdc_led_trig3_o
:
out
std_logic
;
tdc_led_trig4_o
:
out
std_logic
;
tdc_led_trig5_o
:
out
std_logic
;
-- Input pulses arriving also to the FPGA, currently not treated
tdc_in_fpga_1_i
:
in
std_logic
;
tdc_in_fpga_2_i
:
in
std_logic
;
tdc_in_fpga_3_i
:
in
std_logic
;
tdc_in_fpga_4_i
:
in
std_logic
;
tdc_in_fpga_5_i
:
in
std_logic
;
-- White Rabbit core
wrabbit_link_up_i
:
in
std_logic
;
wrabbit_time_valid_i
:
in
std_logic
;
wrabbit_cycles_i
:
in
std_logic_vector
(
27
downto
0
);
wrabbit_utc_i
:
in
std_logic_vector
(
31
downto
0
);
wrabbit_clk_aux_lock_en_o
:
out
std_logic
;
wrabbit_clk_aux_locked_i
:
in
std_logic
;
wrabbit_clk_dmtd_locked_i
:
in
std_logic
;
wrabbit_dac_value_i
:
in
std_logic_vector
(
23
downto
0
);
wrabbit_dac_wr_p_i
:
in
std_logic
;
-- WISHBONE interface with the GN4124/VME_core
-- for the core configuration | timestamps retrieval | core interrupts | 1Wire | I2C
wb_tdc_csr_adr_i
:
in
std_logic_vector
(
31
downto
0
);
wb_tdc_csr_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_tdc_csr_cyc_i
:
in
std_logic
;
wb_tdc_csr_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_tdc_csr_stb_i
:
in
std_logic
;
wb_tdc_csr_we_i
:
in
std_logic
;
wb_tdc_csr_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_tdc_csr_ack_o
:
out
std_logic
;
wb_tdc_csr_stall_o
:
out
std_logic
;
wb_irq_o
:
out
std_logic
;
-- I2C EEPROM interface
i2c_scl_o
:
out
std_logic
;
i2c_scl_oen_o
:
out
std_logic
;
i2c_scl_i
:
in
std_logic
;
i2c_sda_oen_o
:
out
std_logic
;
i2c_sda_o
:
out
std_logic
;
i2c_sda_i
:
in
std_logic
;
-- 1-Wire interface
onewire_b
:
inout
std_logic
;
direct_timestamp_o
:
out
std_logic_vector
(
127
downto
0
);
direct_timestamp_stb_o
:
out
std_logic
);
end
fmc_tdc_mezzanine
;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture
rtl
of
fmc_tdc_mezzanine
is
---------------------------------------------------------------------------------------------------
-- SDB CONSTANTS --
---------------------------------------------------------------------------------------------------
-- Note: All address in sdb and crossbar are BYTE addresses!
-- Master ports on the wishbone crossbar
constant
c_NUM_WB_MASTERS
:
integer
:
=
5
;
constant
c_WB_SLAVE_TDC_ONEWIRE
:
integer
:
=
0
;
-- TDC mezzanine board UnidueID&Thermometer 1-wire
constant
c_WB_SLAVE_TDC_CORE_CONFIG
:
integer
:
=
1
;
-- TDC core configuration registers
constant
c_WB_SLAVE_TDC_EIC
:
integer
:
=
2
;
-- TDC interrupts
constant
c_WB_SLAVE_TDC_I2C
:
integer
:
=
3
;
-- TDC mezzanine board system EEPROM I2C
constant
c_WB_SLAVE_TSTAMP_MEM
:
integer
:
=
4
;
-- Access to TDC core memory for timestamps retrieval
-- Slave port on the wishbone crossbar
constant
c_NUM_WB_SLAVES
:
integer
:
=
1
;
-- Wishbone master(s)
constant
c_WB_MASTER
:
integer
:
=
0
;
-- sdb header address
constant
c_SDB_ADDRESS
:
t_wishbone_address
:
=
x"00000000"
;
-- WISHBONE crossbar layout
constant
c_INTERCONNECT_LAYOUT
:
t_sdb_record_array
(
4
downto
0
)
:
=
(
0
=>
f_sdb_embed_device
(
c_ONEWIRE_SDB_DEVICE
,
x"00010000"
),
1
=>
f_sdb_embed_device
(
c_TDC_CONFIG_SDB_DEVICE
,
x"00011000"
),
2
=>
f_sdb_embed_device
(
c_TDC_EIC_DEVICE
,
x"00012000"
),
3
=>
f_sdb_embed_device
(
c_I2C_SDB_DEVICE
,
x"00013000"
),
4
=>
f_sdb_embed_device
(
c_TDC_MEM_SDB_DEVICE
,
x"00014000"
));
---------------------------------------------------------------------------------------------------
-- Signals --
---------------------------------------------------------------------------------------------------
-- resets
signal
general_rst_n
,
rst_ref_0_n
:
std_logic
;
-- Wishbone buse(s) from crossbar master port(s)
signal
cnx_master_out
:
t_wishbone_master_out_array
(
c_NUM_WB_MASTERS
-1
downto
0
);
signal
cnx_master_in
:
t_wishbone_master_in_array
(
c_NUM_WB_MASTERS
-1
downto
0
);
-- Wishbone buse(s) to crossbar slave port(s)
signal
cnx_slave_out
:
t_wishbone_slave_out_array
(
c_NUM_WB_SLAVES
-1
downto
0
);
signal
cnx_slave_in
:
t_wishbone_slave_in_array
(
c_NUM_WB_SLAVES
-1
downto
0
);
-- Wishbone bus from additional registers
signal
xreg_slave_out
:
t_wishbone_slave_out
;
signal
xreg_slave_in
:
t_wishbone_slave_in
;
-- WISHBONE addresses
signal
tdc_core_wb_adr
:
std_logic_vector
(
31
downto
0
);
signal
tdc_mem_wb_adr
:
std_logic_vector
(
31
downto
0
);
-- 1-wire
signal
mezz_owr_en
,
mezz_owr_i
:
std_logic_vector
(
0
downto
0
);
-- I2C
signal
sys_scl_in
,
sys_scl_out
:
std_logic
;
signal
sys_scl_oe_n
,
sys_sda_in
:
std_logic
;
signal
sys_sda_out
,
sys_sda_oe_n
:
std_logic
;
-- IRQ
signal
irq_tstamp_p
,
irq_time_p
:
std_logic
;
signal
irq_acam_err_p
:
std_logic
;
-- WRabbit
signal
reg_to_wr
,
reg_from_wr
:
std_logic_vector
(
31
downto
0
);
signal
wrabbit_utc_p
:
std_logic
;
signal
wrabbit_synched
:
std_logic
;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
rst_ref_0_n
<=
not
(
rst_ref_0_i
);
---------------------------------------------------------------------------------------------------
-- CSR WISHBONE CROSSBAR --
---------------------------------------------------------------------------------------------------
-- CSR wishbone address decoder
-- 0x10000 -> TDC core configuration
-- 0x11000 -> TDC mezzanine board 1-Wire
-- 0x12000 -> EIC for TDC core
-- 0x13000 -> TDC mezzanine board EEPROM I2C
-- 0x14000 -> TDC core timestamps retrieval
-- Additional register to help timing
cmp_xwb_reg
:
xwb_register_link
port
map
(
clk_sys_i
=>
clk_ref_0_i
,
rst_n_i
=>
rst_ref_0_n
,
slave_i
=>
xreg_slave_in
,
slave_o
=>
xreg_slave_out
,
master_i
=>
cnx_slave_out
(
c_WB_MASTER
),
master_o
=>
cnx_slave_in
(
c_WB_MASTER
));
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
wb_tdc_csr_dat_o
<=
xreg_slave_out
.
dat
;
wb_tdc_csr_ack_o
<=
xreg_slave_out
.
ack
;
wb_tdc_csr_stall_o
<=
xreg_slave_out
.
stall
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Connect crossbar slave port to entity port
xreg_slave_in
.
adr
<=
wb_tdc_csr_adr_i
;
xreg_slave_in
.
dat
<=
wb_tdc_csr_dat_i
;
xreg_slave_in
.
sel
<=
wb_tdc_csr_sel_i
;
xreg_slave_in
.
stb
<=
wb_tdc_csr_stb_i
;
xreg_slave_in
.
we
<=
wb_tdc_csr_we_i
;
xreg_slave_in
.
cyc
<=
wb_tdc_csr_cyc_i
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_sdb_crossbar
:
xwb_sdb_crossbar
generic
map
(
g_num_masters
=>
c_NUM_WB_SLAVES
,
g_num_slaves
=>
c_NUM_WB_MASTERS
,
g_registered
=>
true
,
g_wraparound
=>
true
,
g_layout
=>
c_INTERCONNECT_LAYOUT
,
g_sdb_addr
=>
c_SDB_ADDRESS
)
port
map
(
clk_sys_i
=>
clk_ref_0_i
,
rst_n_i
=>
rst_ref_0_n
,
slave_i
=>
cnx_slave_in
,
slave_o
=>
cnx_slave_out
,
master_i
=>
cnx_master_in
,
master_o
=>
cnx_master_out
);
---------------------------------------------------------------------------------------------------
-- TDC CORE --
---------------------------------------------------------------------------------------------------
cmp_tdc_core
:
fmc_tdc_core
generic
map
(
g_span
=>
g_span
,
g_width
=>
g_width
,
values_for_simul
=>
FALSE
)
port
map
(
-- clks, rst
clk_125m_i
=>
clk_ref_0_i
,
rst_i
=>
rst_ref_0_i
,
acam_refclk_r_edge_p_i
=>
acam_refclk_r_edge_p_i
,
-- DAC configuration
send_dac_word_p_o
=>
send_dac_word_p_o
,
dac_word_o
=>
dac_word_o
,
-- ACAM
start_from_fpga_o
=>
start_from_fpga_o
,
err_flag_i
=>
err_flag_i
,
int_flag_i
=>
int_flag_i
,
start_dis_o
=>
start_dis_o
,
stop_dis_o
=>
stop_dis_o
,
data_bus_io
=>
data_bus_io
,
address_o
=>
address_o
,
cs_n_o
=>
cs_n_o
,
oe_n_o
=>
oe_n_o
,
rd_n_o
=>
rd_n_o
,
wr_n_o
=>
wr_n_o
,
ef1_i
=>
ef1_i
,
ef2_i
=>
ef2_i
,
-- Input channels enable
enable_inputs_o
=>
enable_inputs_o
,
term_en_1_o
=>
term_en_1_o
,
term_en_2_o
=>
term_en_2_o
,
term_en_3_o
=>
term_en_3_o
,
term_en_4_o
=>
term_en_4_o
,
term_en_5_o
=>
term_en_5_o
,
-- Input channels to FPGA (not used currently)
tdc_in_fpga_1_i
=>
tdc_in_fpga_1_i
,
tdc_in_fpga_2_i
=>
tdc_in_fpga_2_i
,
tdc_in_fpga_3_i
=>
tdc_in_fpga_3_i
,
tdc_in_fpga_4_i
=>
tdc_in_fpga_4_i
,
tdc_in_fpga_5_i
=>
tdc_in_fpga_5_i
,
-- TDC board LEDs
tdc_led_status_o
=>
tdc_led_status_o
,
tdc_led_trig1_o
=>
tdc_led_trig1_o
,
tdc_led_trig2_o
=>
tdc_led_trig2_o
,
tdc_led_trig3_o
=>
tdc_led_trig3_o
,
tdc_led_trig4_o
=>
tdc_led_trig4_o
,
tdc_led_trig5_o
=>
tdc_led_trig5_o
,
-- Interrupts
irq_tstamp_p_o
=>
irq_tstamp_p
,
irq_time_p_o
=>
irq_time_p
,
irq_acam_err_p_o
=>
irq_acam_err_p
,
-- WR stuff
wrabbit_tai_i
=>
wrabbit_utc_i
,
wrabbit_tai_p_i
=>
wrabbit_utc_p
,
wrabbit_synched_i
=>
wrabbit_synched
,
wrabbit_status_reg_i
=>
reg_from_wr
,
wrabbit_ctrl_reg_o
=>
reg_to_wr
,
-- WISHBONE CSR for core configuration
tdc_config_wb_adr_i
=>
tdc_core_wb_adr
,
tdc_config_wb_dat_i
=>
cnx_master_out
(
c_WB_SLAVE_TDC_CORE_CONFIG
)
.
dat
,
tdc_config_wb_stb_i
=>
cnx_master_out
(
c_WB_SLAVE_TDC_CORE_CONFIG
)
.
stb
,
tdc_config_wb_we_i
=>
cnx_master_out
(
c_WB_SLAVE_TDC_CORE_CONFIG
)
.
we
,
tdc_config_wb_cyc_i
=>
cnx_master_out
(
c_WB_SLAVE_TDC_CORE_CONFIG
)
.
cyc
,
tdc_config_wb_dat_o
=>
cnx_master_in
(
c_WB_SLAVE_TDC_CORE_CONFIG
)
.
dat
,
tdc_config_wb_ack_o
=>
cnx_master_in
(
c_WB_SLAVE_TDC_CORE_CONFIG
)
.
ack
,
-- WISHBONE for timestamps transfer
tdc_mem_wb_adr_i
=>
tdc_mem_wb_adr
,
--wb_tdc_mem_adr_i,
tdc_mem_wb_dat_i
=>
cnx_master_out
(
c_WB_SLAVE_TSTAMP_MEM
)
.
dat
,
tdc_mem_wb_stb_i
=>
cnx_master_out
(
c_WB_SLAVE_TSTAMP_MEM
)
.
stb
,
tdc_mem_wb_we_i
=>
cnx_master_out
(
c_WB_SLAVE_TSTAMP_MEM
)
.
we
,
tdc_mem_wb_cyc_i
=>
cnx_master_out
(
c_WB_SLAVE_TSTAMP_MEM
)
.
cyc
,
tdc_mem_wb_ack_o
=>
cnx_master_in
(
c_WB_SLAVE_TSTAMP_MEM
)
.
ack
,
tdc_mem_wb_dat_o
=>
cnx_master_in
(
c_WB_SLAVE_TSTAMP_MEM
)
.
dat
,
tdc_mem_wb_stall_o
=>
cnx_master_in
(
c_WB_SLAVE_TSTAMP_MEM
)
.
stall
,
direct_timestamp_o
=>
direct_timestamp_o
,
direct_timestamp_stb_o
=>
direct_timestamp_stb_o
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Convert byte address into word address
tdc_core_wb_adr
<=
"00"
&
cnx_master_out
(
c_WB_SLAVE_TDC_CORE_CONFIG
)
.
adr
(
31
downto
2
);
tdc_mem_wb_adr
<=
"00"
&
cnx_master_out
(
c_WB_SLAVE_TSTAMP_MEM
)
.
adr
(
31
downto
2
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
cnx_master_in
(
c_WB_SLAVE_TDC_CORE_CONFIG
)
.
err
<=
'0'
;
cnx_master_in
(
c_WB_SLAVE_TDC_CORE_CONFIG
)
.
rty
<=
'0'
;
cnx_master_in
(
c_WB_SLAVE_TDC_CORE_CONFIG
)
.
stall
<=
'0'
;
cnx_master_in
(
c_WB_SLAVE_TDC_CORE_CONFIG
)
.
int
<=
'0'
;
cnx_master_in
(
c_WB_SLAVE_TSTAMP_MEM
)
.
err
<=
'0'
;
cnx_master_in
(
c_WB_SLAVE_TSTAMP_MEM
)
.
rty
<=
'0'
;
cnx_master_in
(
c_WB_SLAVE_TSTAMP_MEM
)
.
int
<=
'0'
;
---------------------------------------------------------------------------------------------------
-- WHITE RABBIT STUFF --
-- only synthesized if g_with_wrabbit_core is TRUE --
---------------------------------------------------------------------------------------------------
cmp_wrabbit_synch
:
wrabbit_sync
generic
map
(
g_simulation
=>
false
,
g_with_wrabbit_core
=>
g_with_wrabbit_core
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_sys_i
=>
rst_sys_n_i
,
clk_ref_i
=>
clk_ref_0_i
,
rst_n_ref_i
=>
rst_ref_0_n
,
wrabbit_dac_value_i
=>
wrabbit_dac_value_i
,
wrabbit_dac_wr_p_i
=>
wrabbit_dac_wr_p_i
,
wrabbit_link_up_i
=>
wrabbit_link_up_i
,
wrabbit_time_valid_i
=>
wrabbit_time_valid_i
,
wrabbit_clk_aux_lock_en_o
=>
wrabbit_clk_aux_lock_en_o
,
wrabbit_clk_aux_locked_i
=>
wrabbit_clk_aux_locked_i
,
wrabbit_clk_dmtd_locked_i
=>
'1'
,
-- FIXME
wrabbit_synched_o
=>
wrabbit_synched
,
wrabbit_reg_i
=>
reg_to_wr
,
-- synced to 125MHz mezzanine
wrabbit_reg_o
=>
reg_from_wr
);
-- synced to 125MHz mezzanine
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
wrabbit_one_hz_pulse
:
process
(
clk_ref_0_i
)
begin
if
rising_edge
(
clk_ref_0_i
)
then
if
rst_ref_0_n
=
'0'
then
wrabbit_utc_p
<=
'0'
;
else
if
wrabbit_clk_aux_locked_i
=
'1'
and
g_with_wrabbit_core
then
if
unsigned
(
wrabbit_cycles_i
)
=
(
unsigned
(
c_SYN_CLK_PERIOD
)
-3
)
then
-- so that the end of the pulse
-- comes exactly upon the UTC change
wrabbit_utc_p
<=
'1'
;
else
wrabbit_utc_p
<=
'0'
;
end
if
;
else
wrabbit_utc_p
<=
'0'
;
end
if
;
end
if
;
end
if
;
end
process
;
---------------------------------------------------------------------------------------------------
-- TDC Mezzanine Board UniqueID&Thermometer OneWire --
---------------------------------------------------------------------------------------------------
cmp_fmc_onewire
:
xwb_onewire_master
generic
map
(
g_interface_mode
=>
PIPELINED
,
g_address_granularity
=>
BYTE
,
g_num_ports
=>
1
,
g_ow_btp_normal
=>
"5.0"
,
g_ow_btp_overdrive
=>
"1.0"
)
port
map
(
clk_sys_i
=>
clk_ref_0_i
,
rst_n_i
=>
rst_ref_0_n
,
slave_i
=>
cnx_master_out
(
c_WB_SLAVE_TDC_ONEWIRE
),
slave_o
=>
cnx_master_in
(
c_WB_SLAVE_TDC_ONEWIRE
),
desc_o
=>
open
,
owr_pwren_o
=>
open
,
owr_en_o
=>
mezz_owr_en
,
owr_i
=>
mezz_owr_i
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
onewire_b
<=
'0'
when
mezz_owr_en
(
0
)
=
'1'
else
'Z'
;
mezz_owr_i
(
0
)
<=
onewire_b
;
---------------------------------------------------------------------------------------------------
-- WBGEN2 EMBEDDED INTERRUPTS CONTROLLER --
---------------------------------------------------------------------------------------------------
-- IRQ sources
-- 0 -> number of accumulated timestamps reached threshold
-- 1 -> number of seconds passed reached threshold and number of accumulated tstamps > 0
-- 2 -> ACAM error
cmp_tdc_eic
:
tdc_eic
port
map
(
clk_sys_i
=>
clk_ref_0_i
,
rst_n_i
=>
rst_ref_0_n
,
wb_adr_i
=>
cnx_master_out
(
c_WB_SLAVE_TDC_EIC
)
.
adr
(
3
downto
2
),
wb_dat_i
=>
cnx_master_out
(
c_WB_SLAVE_TDC_EIC
)
.
dat
,
wb_dat_o
=>
cnx_master_in
(
c_WB_SLAVE_TDC_EIC
)
.
dat
,
wb_cyc_i
=>
cnx_master_out
(
c_WB_SLAVE_TDC_EIC
)
.
cyc
,
wb_sel_i
=>
cnx_master_out
(
c_WB_SLAVE_TDC_EIC
)
.
sel
,
wb_stb_i
=>
cnx_master_out
(
c_WB_SLAVE_TDC_EIC
)
.
stb
,
wb_we_i
=>
cnx_master_out
(
c_WB_SLAVE_TDC_EIC
)
.
we
,
wb_ack_o
=>
cnx_master_in
(
c_WB_SLAVE_TDC_EIC
)
.
ack
,
wb_stall_o
=>
cnx_master_in
(
c_WB_SLAVE_TDC_EIC
)
.
stall
,
wb_int_o
=>
wb_irq_o
,
irq_tdc_tstamps_i
=>
irq_tstamp_p
,
irq_tdc_time_i
=>
irq_time_p
,
irq_tdc_acam_err_i
=>
irq_acam_err_p
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
cnx_master_in
(
c_WB_SLAVE_TDC_EIC
)
.
err
<=
'0'
;
cnx_master_in
(
c_WB_SLAVE_TDC_EIC
)
.
rty
<=
'0'
;
cnx_master_in
(
c_WB_SLAVE_TDC_EIC
)
.
int
<=
'0'
;
---------------------------------------------------------------------------------------------------
-- TDC Mezzanine Board EEPROM I2C --
---------------------------------------------------------------------------------------------------
cmp_I2C_master
:
xwb_i2c_master
generic
map
(
g_interface_mode
=>
PIPELINED
,
g_address_granularity
=>
BYTE
)
port
map
(
clk_sys_i
=>
clk_ref_0_i
,
rst_n_i
=>
rst_ref_0_n
,
slave_i
=>
cnx_master_out
(
c_WB_SLAVE_TDC_I2C
),
slave_o
=>
cnx_master_in
(
c_WB_SLAVE_TDC_I2C
),
desc_o
=>
open
,
scl_pad_i
(
0
)
=>
i2c_scl_i
,
scl_pad_o
(
0
)
=>
sys_scl_out
,
scl_padoen_o
(
0
)
=>
sys_scl_oe_n
,
sda_pad_i
(
0
)
=>
i2c_sda_i
,
sda_pad_o
(
0
)
=>
sys_sda_out
,
sda_padoen_o
(
0
)
=>
sys_sda_oe_n
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
i2c_sda_oen_o
<=
sys_sda_oe_n
;
i2c_sda_o
<=
sys_sda_out
;
i2c_scl_oen_o
<=
sys_scl_oe_n
;
i2c_scl_o
<=
sys_scl_out
;
end
rtl
;
----------------------------------------------------------------------------------------------------
-- architecture ends
--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- fmc_tdc_mezzanine |
-- |
---------------------------------------------------------------------------------------------------
-- File fmc_tdc_mezzanine.vhd |
-- |
-- Description The unit combines |
-- o the TDC core |
-- o the wrabbit_sync unit that is managing the White Rabbit synchronization and |
-- control signals |
-- o the I2C core for the communication with the TDC board EEPROM |
-- o the OneWire core for the communication with the TDC board UniqueID&Thermeter |
-- o the Embedded Interrupt Controller core that concentrates several interrupt |
-- sources into one WISHBONE interrupt request line. |
-- |
-- For the interconnection between the GN4124/VME core and the different cores (TDC, |
-- I2C, 1W, EIC, timestamps memory) the unit instantiates an SDB crossbar. |
-- |
-- Note that the TDC core uses word addressing, whereas the GN4124/VME cores use byte|
-- addressing |
-- _______________________________ |
-- | FMC TDC mezzanine | |
-- | | |
-- | ________________ | |
-- | |--| WRabbit_sync | | |
-- | | |________________| | |
-- | | ________________ ___ | |
-- | |->| | | | | |
-- ACAM chip <--> | | TDC core | | | | <--> |
-- | |--|________________| | S | | |
-- | | ________________ | | | |
-- | | | | | | | |
-- EEPROM chip <--> | | | I2C core | | | | <--> |
-- | | |________________| | | | |
-- | | ________________ | D | | GN4124/VME core |
-- | | | | | | | |
-- 1W chip <--> | | | 1W core | | | | <--> |
-- | | |________________| | | | |
-- | | ________________ | | | |
-- | | | | | B | | |
-- | |->| EIC | | | | <--> |
-- | |________________| |___| | |
-- | | |
-- |________________________________| |
-- ^ ^ |
-- | 125 MHz rst | |
-- __|________________________|___ |
-- | | |
-- DAC chip <--> | clks_rsts_manager | |
-- PLL chip |_______________________________| |
-- |
-- Figure 1: FMC TDC mezzanine architecture and |
-- connection with the clks_rsts_manager unit |
-- |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 01/2014 |
-- Version v2 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 07/2013 v1 EG First version |
-- 01/2014 v2 EG Different output for the timestamp data |
-- 01/2014 v3 EG Removed option for timestamps retrieval through DMA |
-- 08/2014 v4 EG Corrected missalignement between wrabbit_tai and wrabbit_tai_p (line 444) |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
library
IEEE
;
use
IEEE
.
std_logic_1164
.
all
;
use
IEEE
.
numeric_std
.
all
;
use
work
.
tdc_core_pkg
.
all
;
use
work
.
gencores_pkg
.
all
;
use
work
.
wishbone_pkg
.
all
;
--=================================================================================================
-- Entity declaration for fmc_tdc_mezzanine
--=================================================================================================
entity
fmc_tdc_mezzanine
is
generic
(
g_with_wrabbit_core
:
boolean
:
=
FALSE
;
g_span
:
integer
:
=
32
;
g_width
:
integer
:
=
32
;
values_for_simul
:
boolean
:
=
FALSE
);
port
-- TDC core
(
-- System clock & reset (Wishbone)
clk_sys_i
:
in
std_logic
;
-- 62.5 MHz clock
rst_sys_n_i
:
in
std_logic
;
-- reset for 62.5 MHz logic
-- TDC 125 MHz reference & Reset (FMC)
clk_tdc_i
:
in
std_logic
;
-- 125 MHz clock
rst_tdc_i
:
in
std_logic
;
-- reset for 125 MHz logic
acam_refclk_r_edge_p_i
:
in
std_logic
;
send_dac_word_p_o
:
out
std_logic
;
dac_word_o
:
out
std_logic_vector
(
23
downto
0
);
-- Interface with ACAM
start_from_fpga_o
:
out
std_logic
;
err_flag_i
:
in
std_logic
;
int_flag_i
:
in
std_logic
;
start_dis_o
:
out
std_logic
;
stop_dis_o
:
out
std_logic
;
data_bus_io
:
inout
std_logic_vector
(
27
downto
0
);
address_o
:
out
std_logic_vector
(
3
downto
0
);
cs_n_o
:
out
std_logic
;
oe_n_o
:
out
std_logic
;
rd_n_o
:
out
std_logic
;
wr_n_o
:
out
std_logic
;
ef1_i
:
in
std_logic
;
ef2_i
:
in
std_logic
;
-- Channels termination
enable_inputs_o
:
out
std_logic
;
term_en_1_o
:
out
std_logic
;
term_en_2_o
:
out
std_logic
;
term_en_3_o
:
out
std_logic
;
term_en_4_o
:
out
std_logic
;
term_en_5_o
:
out
std_logic
;
-- TDC board LEDs
tdc_led_status_o
:
out
std_logic
;
tdc_led_trig1_o
:
out
std_logic
;
tdc_led_trig2_o
:
out
std_logic
;
tdc_led_trig3_o
:
out
std_logic
;
tdc_led_trig4_o
:
out
std_logic
;
tdc_led_trig5_o
:
out
std_logic
;
-- Input pulses arriving also to the FPGA, currently not treated
tdc_in_fpga_1_i
:
in
std_logic
;
tdc_in_fpga_2_i
:
in
std_logic
;
tdc_in_fpga_3_i
:
in
std_logic
;
tdc_in_fpga_4_i
:
in
std_logic
;
tdc_in_fpga_5_i
:
in
std_logic
;
-- White Rabbit core
wrabbit_link_up_i
:
in
std_logic
;
wrabbit_time_valid_i
:
in
std_logic
;
wrabbit_cycles_i
:
in
std_logic_vector
(
27
downto
0
);
wrabbit_utc_i
:
in
std_logic_vector
(
31
downto
0
);
wrabbit_clk_aux_lock_en_o
:
out
std_logic
;
wrabbit_clk_aux_locked_i
:
in
std_logic
;
wrabbit_clk_dmtd_locked_i
:
in
std_logic
;
wrabbit_dac_value_i
:
in
std_logic_vector
(
23
downto
0
);
wrabbit_dac_wr_p_i
:
in
std_logic
;
-- WISHBONE interface with the GN4124/VME_core (clk_sys)
-- for the core configuration | timestamps retrieval | core interrupts | 1Wire | I2C
slave_i
:
in
t_wishbone_slave_in
;
slave_o
:
out
t_wishbone_slave_out
;
wb_irq_o
:
out
std_logic
;
-- I2C EEPROM interface
i2c_scl_o
:
out
std_logic
;
i2c_scl_oen_o
:
out
std_logic
;
i2c_scl_i
:
in
std_logic
;
i2c_sda_oen_o
:
out
std_logic
;
i2c_sda_o
:
out
std_logic
;
i2c_sda_i
:
in
std_logic
;
-- 1-Wire interface
onewire_b
:
inout
std_logic
;
direct_timestamp_o
:
out
std_logic_vector
(
127
downto
0
);
direct_timestamp_stb_o
:
out
std_logic
);
end
fmc_tdc_mezzanine
;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture
rtl
of
fmc_tdc_mezzanine
is
---------------------------------------------------------------------------------------------------
-- SDB CONSTANTS --
---------------------------------------------------------------------------------------------------
-- Note: All address in sdb and crossbar are BYTE addresses!
-- Master ports on the wishbone crossbar
constant
c_NUM_WB_MASTERS
:
integer
:
=
5
;
constant
c_WB_SLAVE_TDC_ONEWIRE
:
integer
:
=
0
;
-- TDC mezzanine board UnidueID&Thermometer 1-wire
constant
c_WB_SLAVE_TDC_CORE_CONFIG
:
integer
:
=
1
;
-- TDC core configuration registers
constant
c_WB_SLAVE_TDC_EIC
:
integer
:
=
2
;
-- TDC interrupts
constant
c_WB_SLAVE_TDC_I2C
:
integer
:
=
3
;
-- TDC mezzanine board system EEPROM I2C
constant
c_WB_SLAVE_TSTAMP_MEM
:
integer
:
=
4
;
-- Access to TDC core memory for timestamps retrieval
-- Slave port on the wishbone crossbar
constant
c_NUM_WB_SLAVES
:
integer
:
=
1
;
-- Wishbone master(s)
constant
c_WB_MASTER
:
integer
:
=
0
;
-- sdb header address
constant
c_SDB_ADDRESS
:
t_wishbone_address
:
=
x"00000000"
;
-- WISHBONE crossbar layout
constant
c_INTERCONNECT_LAYOUT
:
t_sdb_record_array
(
4
downto
0
)
:
=
(
0
=>
f_sdb_embed_device
(
c_ONEWIRE_SDB_DEVICE
,
x"00010000"
),
1
=>
f_sdb_embed_device
(
c_TDC_CONFIG_SDB_DEVICE
,
x"00011000"
),
2
=>
f_sdb_embed_device
(
c_TDC_EIC_DEVICE
,
x"00012000"
),
3
=>
f_sdb_embed_device
(
c_I2C_SDB_DEVICE
,
x"00013000"
),
4
=>
f_sdb_embed_device
(
c_TDC_MEM_SDB_DEVICE
,
x"00014000"
));
---------------------------------------------------------------------------------------------------
-- Signals --
---------------------------------------------------------------------------------------------------
-- resets
signal
general_rst_n
,
rst_ref_0_n
:
std_logic
;
-- Wishbone buse(s) from crossbar master port(s)
signal
cnx_master_out
:
t_wishbone_master_out_array
(
c_NUM_WB_MASTERS
-1
downto
0
);
signal
cnx_master_in
:
t_wishbone_master_in_array
(
c_NUM_WB_MASTERS
-1
downto
0
);
-- WISHBONE addresses
signal
tdc_core_wb_adr
:
std_logic_vector
(
31
downto
0
);
signal
tdc_mem_wb_adr
:
std_logic_vector
(
31
downto
0
);
-- 1-wire
signal
mezz_owr_en
,
mezz_owr_i
:
std_logic_vector
(
0
downto
0
);
-- I2C
signal
sys_scl_in
,
sys_scl_out
:
std_logic
;
signal
sys_scl_oe_n
,
sys_sda_in
:
std_logic
;
signal
sys_sda_out
,
sys_sda_oe_n
:
std_logic
;
-- IRQ
signal
irq_tstamp_p
,
irq_time_p
:
std_logic
;
signal
irq_acam_err_p
:
std_logic
;
signal
irq_tstamp_p_sys
,
irq_time_p_sys
:
std_logic
;
signal
irq_acam_err_p_sys
:
std_logic
;
-- WRabbit
signal
reg_to_wr
,
reg_from_wr
:
std_logic_vector
(
31
downto
0
);
signal
wrabbit_utc_p
:
std_logic
;
signal
wrabbit_synched
:
std_logic
;
function
f_wb_shift_address_word
(
w
:
t_wishbone_master_out
)
return
t_wishbone_master_out
is
variable
r
:
t_wishbone_master_out
;
begin
r
.
adr
:
=
"00"
&
w
.
adr
(
31
downto
2
);
r
.
dat
:
=
w
.
dat
;
r
.
cyc
:
=
w
.
cyc
;
r
.
stb
:
=
w
.
stb
;
r
.
we
:
=
w
.
we
;
r
.
sel
:
=
w
.
sel
;
return
r
;
end
f_wb_shift_address_word
;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
rst_ref_0_n
<=
not
(
rst_tdc_i
);
---------------------------------------------------------------------------------------------------
-- CSR WISHBONE CROSSBAR --
---------------------------------------------------------------------------------------------------
-- CSR wishbone address decoder
-- 0x10000 -> TDC core configuration
-- 0x11000 -> TDC mezzanine board 1-Wire
-- 0x12000 -> EIC for TDC core
-- 0x13000 -> TDC mezzanine board EEPROM I2C
-- 0x14000 -> TDC core timestamps retrieval
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_sdb_crossbar
:
xwb_sdb_crossbar
generic
map
(
g_num_masters
=>
c_NUM_WB_SLAVES
,
g_num_slaves
=>
c_NUM_WB_MASTERS
,
g_registered
=>
true
,
g_wraparound
=>
true
,
g_layout
=>
c_INTERCONNECT_LAYOUT
,
g_sdb_addr
=>
c_SDB_ADDRESS
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_sys_n_i
,
slave_i
(
0
)
=>
slave_i
,
slave_o
(
0
)
=>
slave_o
,
master_i
=>
cnx_master_in
,
master_o
=>
cnx_master_out
);
---------------------------------------------------------------------------------------------------
-- TDC CORE --
---------------------------------------------------------------------------------------------------
cmp_tdc_core
:
fmc_tdc_core
generic
map
(
g_span
=>
g_span
,
g_width
=>
g_width
,
values_for_simul
=>
FALSE
)
port
map
(
-- clks, rst
clk_tdc_i
=>
clk_tdc_i
,
rst_tdc_i
=>
rst_tdc_i
,
clk_sys_i
=>
clk_sys_i
,
rst_n_sys_i
=>
rst_sys_n_i
,
acam_refclk_r_edge_p_i
=>
acam_refclk_r_edge_p_i
,
-- DAC configuration
send_dac_word_p_o
=>
send_dac_word_p_o
,
dac_word_o
=>
dac_word_o
,
-- ACAM
start_from_fpga_o
=>
start_from_fpga_o
,
err_flag_i
=>
err_flag_i
,
int_flag_i
=>
int_flag_i
,
start_dis_o
=>
start_dis_o
,
stop_dis_o
=>
stop_dis_o
,
data_bus_io
=>
data_bus_io
,
address_o
=>
address_o
,
cs_n_o
=>
cs_n_o
,
oe_n_o
=>
oe_n_o
,
rd_n_o
=>
rd_n_o
,
wr_n_o
=>
wr_n_o
,
ef1_i
=>
ef1_i
,
ef2_i
=>
ef2_i
,
-- Input channels enable
enable_inputs_o
=>
enable_inputs_o
,
term_en_1_o
=>
term_en_1_o
,
term_en_2_o
=>
term_en_2_o
,
term_en_3_o
=>
term_en_3_o
,
term_en_4_o
=>
term_en_4_o
,
term_en_5_o
=>
term_en_5_o
,
-- Input channels to FPGA (not used currently)
tdc_in_fpga_1_i
=>
tdc_in_fpga_1_i
,
tdc_in_fpga_2_i
=>
tdc_in_fpga_2_i
,
tdc_in_fpga_3_i
=>
tdc_in_fpga_3_i
,
tdc_in_fpga_4_i
=>
tdc_in_fpga_4_i
,
tdc_in_fpga_5_i
=>
tdc_in_fpga_5_i
,
-- TDC board LEDs
tdc_led_status_o
=>
tdc_led_status_o
,
tdc_led_trig1_o
=>
tdc_led_trig1_o
,
tdc_led_trig2_o
=>
tdc_led_trig2_o
,
tdc_led_trig3_o
=>
tdc_led_trig3_o
,
tdc_led_trig4_o
=>
tdc_led_trig4_o
,
tdc_led_trig5_o
=>
tdc_led_trig5_o
,
-- Interrupts
irq_tstamp_p_o
=>
irq_tstamp_p
,
irq_time_p_o
=>
irq_time_p
,
irq_acam_err_p_o
=>
irq_acam_err_p
,
-- WR stuff
wrabbit_tai_i
=>
wrabbit_utc_i
,
wrabbit_tai_p_i
=>
wrabbit_utc_p
,
wrabbit_synched_i
=>
wrabbit_synched
,
wrabbit_status_reg_i
=>
reg_from_wr
,
wrabbit_ctrl_reg_o
=>
reg_to_wr
,
-- WISHBONE CSR for core configuration
cfg_slave_i
=>
f_wb_shift_address_word
(
cnx_master_out
(
c_WB_SLAVE_TDC_CORE_CONFIG
)),
cfg_slave_o
=>
cnx_master_in
(
c_WB_SLAVE_TDC_CORE_CONFIG
),
mem_slave_i
=>
f_wb_shift_address_word
(
cnx_master_out
(
c_WB_SLAVE_TSTAMP_MEM
)),
mem_slave_o
=>
cnx_master_in
(
c_WB_SLAVE_TSTAMP_MEM
),
direct_timestamp_o
=>
direct_timestamp_o
,
direct_timestamp_stb_o
=>
direct_timestamp_stb_o
);
---------------------------------------------------------------------------------------------------
-- WHITE RABBIT STUFF --
-- only synthesized if g_with_wrabbit_core is TRUE --
---------------------------------------------------------------------------------------------------
cmp_wrabbit_synch
:
wrabbit_sync
generic
map
(
g_simulation
=>
false
,
g_with_wrabbit_core
=>
g_with_wrabbit_core
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_sys_i
=>
rst_sys_n_i
,
clk_ref_i
=>
clk_tdc_i
,
rst_n_ref_i
=>
rst_ref_0_n
,
wrabbit_dac_value_i
=>
wrabbit_dac_value_i
,
wrabbit_dac_wr_p_i
=>
wrabbit_dac_wr_p_i
,
wrabbit_link_up_i
=>
wrabbit_link_up_i
,
wrabbit_time_valid_i
=>
wrabbit_time_valid_i
,
wrabbit_clk_aux_lock_en_o
=>
wrabbit_clk_aux_lock_en_o
,
wrabbit_clk_aux_locked_i
=>
wrabbit_clk_aux_locked_i
,
wrabbit_clk_dmtd_locked_i
=>
'1'
,
-- FIXME
wrabbit_synched_o
=>
wrabbit_synched
,
wrabbit_reg_i
=>
reg_to_wr
,
-- synced to 125MHz mezzanine
wrabbit_reg_o
=>
reg_from_wr
);
-- synced to 125MHz mezzanine
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
wrabbit_one_hz_pulse
:
process
(
clk_tdc_i
)
begin
if
rising_edge
(
clk_tdc_i
)
then
if
rst_ref_0_n
=
'0'
then
wrabbit_utc_p
<=
'0'
;
else
if
wrabbit_clk_aux_locked_i
=
'1'
and
g_with_wrabbit_core
then
if
unsigned
(
wrabbit_cycles_i
)
=
(
unsigned
(
c_SYN_CLK_PERIOD
)
-3
)
then
-- so that the end of the pulse
-- comes exactly upon the UTC change
wrabbit_utc_p
<=
'1'
;
else
wrabbit_utc_p
<=
'0'
;
end
if
;
else
wrabbit_utc_p
<=
'0'
;
end
if
;
end
if
;
end
if
;
end
process
;
---------------------------------------------------------------------------------------------------
-- TDC Mezzanine Board UniqueID&Thermometer OneWire --
---------------------------------------------------------------------------------------------------
cmp_fmc_onewire
:
xwb_onewire_master
generic
map
(
g_interface_mode
=>
PIPELINED
,
g_address_granularity
=>
BYTE
,
g_num_ports
=>
1
,
g_ow_btp_normal
=>
"5.0"
,
g_ow_btp_overdrive
=>
"1.0"
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_sys_n_i
,
slave_i
=>
cnx_master_out
(
c_WB_SLAVE_TDC_ONEWIRE
),
slave_o
=>
cnx_master_in
(
c_WB_SLAVE_TDC_ONEWIRE
),
desc_o
=>
open
,
owr_pwren_o
=>
open
,
owr_en_o
=>
mezz_owr_en
,
owr_i
=>
mezz_owr_i
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
onewire_b
<=
'0'
when
mezz_owr_en
(
0
)
=
'1'
else
'Z'
;
mezz_owr_i
(
0
)
<=
onewire_b
;
---------------------------------------------------------------------------------------------------
-- WBGEN2 EMBEDDED INTERRUPTS CONTROLLER --
---------------------------------------------------------------------------------------------------
-- IRQ sources
-- 0 -> number of accumulated timestamps reached threshold
-- 1 -> number of seconds passed reached threshold and number of accumulated tstamps > 0
-- 2 -> ACAM error
cmp_tdc_eic
:
tdc_eic
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_sys_n_i
,
wb_adr_i
=>
cnx_master_out
(
c_WB_SLAVE_TDC_EIC
)
.
adr
(
3
downto
2
),
wb_dat_i
=>
cnx_master_out
(
c_WB_SLAVE_TDC_EIC
)
.
dat
,
wb_dat_o
=>
cnx_master_in
(
c_WB_SLAVE_TDC_EIC
)
.
dat
,
wb_cyc_i
=>
cnx_master_out
(
c_WB_SLAVE_TDC_EIC
)
.
cyc
,
wb_sel_i
=>
cnx_master_out
(
c_WB_SLAVE_TDC_EIC
)
.
sel
,
wb_stb_i
=>
cnx_master_out
(
c_WB_SLAVE_TDC_EIC
)
.
stb
,
wb_we_i
=>
cnx_master_out
(
c_WB_SLAVE_TDC_EIC
)
.
we
,
wb_ack_o
=>
cnx_master_in
(
c_WB_SLAVE_TDC_EIC
)
.
ack
,
wb_stall_o
=>
cnx_master_in
(
c_WB_SLAVE_TDC_EIC
)
.
stall
,
wb_int_o
=>
wb_irq_o
,
irq_tdc_tstamps_i
=>
irq_tstamp_p_sys
,
irq_tdc_time_i
=>
irq_time_p_sys
,
irq_tdc_acam_err_i
=>
irq_acam_err_p_sys
);
cmp_sync_irq_tstamp
:
gc_pulse_synchronizer2
port
map
(
clk_in_i
=>
clk_tdc_i
,
rst_in_n_i
=>
rst_ref_0_n
,
clk_out_i
=>
clk_sys_i
,
rst_out_n_i
=>
rst_sys_n_i
,
d_p_i
=>
irq_tstamp_p
,
q_p_o
=>
irq_tstamp_p_sys
);
irq_time_p_sys
<=
'0'
;
-- we don't need these in the driver
irq_acam_err_p_sys
<=
'0'
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
cnx_master_in
(
c_WB_SLAVE_TDC_EIC
)
.
err
<=
'0'
;
cnx_master_in
(
c_WB_SLAVE_TDC_EIC
)
.
rty
<=
'0'
;
cnx_master_in
(
c_WB_SLAVE_TDC_EIC
)
.
int
<=
'0'
;
---------------------------------------------------------------------------------------------------
-- TDC Mezzanine Board EEPROM I2C --
---------------------------------------------------------------------------------------------------
cmp_I2C_master
:
xwb_i2c_master
generic
map
(
g_interface_mode
=>
PIPELINED
,
g_address_granularity
=>
BYTE
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_sys_n_i
,
slave_i
=>
cnx_master_out
(
c_WB_SLAVE_TDC_I2C
),
slave_o
=>
cnx_master_in
(
c_WB_SLAVE_TDC_I2C
),
desc_o
=>
open
,
scl_pad_i
(
0
)
=>
i2c_scl_i
,
scl_pad_o
(
0
)
=>
sys_scl_out
,
scl_padoen_o
(
0
)
=>
sys_scl_oe_n
,
sda_pad_i
(
0
)
=>
i2c_sda_i
,
sda_pad_o
(
0
)
=>
sys_sda_out
,
sda_padoen_o
(
0
)
=>
sys_sda_oe_n
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
i2c_sda_oen_o
<=
sys_sda_oe_n
;
i2c_sda_o
<=
sys_sda_out
;
i2c_scl_oen_o
<=
sys_scl_oe_n
;
i2c_scl_o
<=
sys_scl_out
;
end
rtl
;
----------------------------------------------------------------------------------------------------
-- architecture ends
----------------------------------------------------------------------------------------------------
hdl/wr_spec_tdc/hdl/rtl/reg_ctrl.vhd
View file @
1b4e6b54
...
...
@@ -72,7 +72,7 @@ use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library
work
;
use
work
.
tdc_core_pkg
.
all
;
-- definitions of types, constants, entities
use
work
.
wishbone_pkg
.
all
;
--=================================================================================================
-- Entity declaration for reg_ctrl
...
...
@@ -85,16 +85,15 @@ entity reg_ctrl is
port
-- INPUTS
-- Signals from the clks_rsts_manager unit
(
clk_
i
:
in
std_logic
;
-- 125 MHz
rst_
i
:
in
std_logic
;
-- global reset, synched to clk_i
(
clk_
sys_i
:
in
std_logic
;
rst_
n_sys_i
:
in
std_logic
;
-- global reset, synched to clk_sys
-- Signals from the GN4124/VME_core unit: WISHBONE for regs transfer
tdc_config_wb_adr_i
:
in
std_logic_vector
(
g_span
-1
downto
0
);
-- WISHBONE address
tdc_config_wb_cyc_i
:
in
std_logic
;
-- WISHBONE cycle
tdc_config_wb_dat_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
-- WISHBONE data in
tdc_config_wb_stb_i
:
in
std_logic
;
-- WISHBONE strobe
tdc_config_wb_we_i
:
in
std_logic
;
-- WISHBONE write enable
clk_tdc_i
:
in
std_logic
;
rst_tdc_i
:
in
std_logic
;
slave_i
:
in
t_wishbone_slave_in
;
-- WB interface (clk_sys domain)
slave_o
:
out
t_wishbone_slave_out
;
-- Signals from the data_engine unit: configuration regs read back from the ACAM
acam_config_rdbk_i
:
in
config_vector
;
-- array keeping values read back from ACAM regs 0-7, 11, 12, 14
acam_ififo1_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
-- keeps value read back from ACAM reg 8; for debug reasons only
...
...
@@ -114,11 +113,7 @@ entity reg_ctrl is
-- White Rabbit status
wrabbit_status_reg_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
--
-- OUTPUTS
-- Signals to the GN4124/VME_core unit: WISHBONE for regs transfer
tdc_config_wb_ack_o
:
out
std_logic
;
-- WISHBONE acknowledge
tdc_config_wb_dat_o
:
out
std_logic_vector
(
g_width
-1
downto
0
);
-- WISHBONE data out
-- Signals to the data_engine unit: config regs for the ACAM
acam_config_o
:
out
config_vector
;
...
...
@@ -136,7 +131,7 @@ entity reg_ctrl is
-- Signal to the data_formatting unit
dacapo_c_rst_p_o
:
out
std_logic
;
-- clears the dacapo counter
deactivate_chan_o
:
out
std_logic_vector
(
4
downto
0
);
-- stops registering timestamps from a specific channel
deactivate_chan_o
:
out
std_logic_vector
(
4
downto
0
);
-- stops registering timestamps from a specific channel
-- Signals to the clks_resets_manager unit
send_dac_word_p_o
:
out
std_logic
;
-- initiates the reconfiguration of the DAC
...
...
@@ -187,13 +182,33 @@ architecture rtl of reg_ctrl is
signal
cyc_in_progress
:
std_logic
;
signal
wb_in
:
t_wishbone_slave_in
;
signal
wb_out
:
t_wishbone_slave_out
;
signal
rst_n_tdc
:
std_logic
;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
reg_adr
<=
tdc_config_wb_adr_i
(
7
downto
0
);
-- we are interested in addresses 0:5000 to 0:50FC
rst_n_tdc
<=
not
rst_tdc_i
;
wb_out
.
stall
<=
'0'
;
wb_out
.
err
<=
'0'
;
wb_out
.
rty
<=
'0'
;
cmp_clks_crossing
:
xwb_clock_crossing
port
map
(
slave_clk_i
=>
clk_sys_i
,
-- Slave control port: VME interface at 62.5 MHz
slave_rst_n_i
=>
rst_n_sys_i
,
slave_i
=>
slave_i
,
slave_o
=>
slave_o
,
master_clk_i
=>
clk_tdc_i
,
master_rst_n_i
=>
rst_n_tdc
,
master_i
=>
wb_out
,
master_o
=>
wb_in
);
reg_adr
<=
wb_in
.
adr
(
7
downto
0
);
-- we are interested in addresses 0:5000 to 0:50FC
---------------------------------------------------------------------------------------------------
-- WISHBONE ACK to GN4124/VME_core --
...
...
@@ -202,23 +217,23 @@ begin
-- TDCconfig_ack_generator: generation of the WISHBONE acknowledge signal for the
-- interactions with the GN4124/VME_core.
TDCconfig_ack_generator
:
process
(
clk_i
)
TDCconfig_ack_generator
:
process
(
clk_
tdc_
i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_
i
=
'1
'
then
tdc_config_wb_ack_o
<=
'0'
;
if
rising_edge
(
clk_
tdc_
i
)
then
if
rst_
n_tdc
=
'0
'
then
wb_out
.
ack
<=
'0'
;
ack_out_pipe1
<=
'0'
;
ack_out_pipe0
<=
'0'
;
cyc_in_progress
<=
'0'
;
elsif
(
tdc_config_wb_cyc_i
=
'0
'
)
then
elsif
(
wb_in
.
cyc
/=
'1
'
)
then
ack_out_pipe1
<=
'0'
;
ack_out_pipe0
<=
'0'
;
cyc_in_progress
<=
'0'
;
else
cyc_in_progress
<=
'1'
;
tdc_config_wb_ack_o
<=
ack_out_pipe1
;
wb_out
.
ack
<=
ack_out_pipe1
;
ack_out_pipe1
<=
ack_out_pipe0
;
ack_out_pipe0
<=
tdc_config_wb_stb_i
and
tdc_config_wb_cyc_i
and
not
cyc_in_progress
;
ack_out_pipe0
<=
wb_in
.
stb
and
wb_in
.
cyc
and
not
cyc_in_progress
;
end
if
;
end
if
;
end
process
;
...
...
@@ -233,10 +248,10 @@ begin
-- input to the data_engine and the acam_databus_interface units for the further transfer to the
-- ACAM chip.
ACAM_config_reg_reception
:
process
(
clk
_i
)
ACAM_config_reg_reception
:
process
(
clk_tdc
_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_i
=
'1'
then
if
rising_edge
(
clk_
tdc_
i
)
then
if
rst_
tdc_
i
=
'1'
then
acam_config
(
0
)
<=
(
others
=>
'0'
);
acam_config
(
1
)
<=
(
others
=>
'0'
);
acam_config
(
2
)
<=
(
others
=>
'0'
);
...
...
@@ -249,50 +264,50 @@ begin
acam_config
(
9
)
<=
(
others
=>
'0'
);
acam_config
(
10
)
<=
(
others
=>
'0'
);
elsif
tdc_config_wb_cyc_i
=
'1'
and
tdc_config_wb_stb_i
=
'1'
and
tdc_config_wb_we_i
=
'1'
then
-- WISHBONE writes
elsif
wb_in
.
cyc
=
'1'
and
wb_in
.
stb
=
'1'
and
wb_in
.
we
=
'1'
then
-- WISHBONE writes
if
reg_adr
=
c_ACAM_REG0_ADR
then
acam_config
(
0
)
<=
tdc_config_wb_dat_i
;
acam_config
(
0
)
<=
wb_in
.
dat
;
end
if
;
if
reg_adr
=
c_ACAM_REG1_ADR
then
acam_config
(
1
)
<=
tdc_config_wb_dat_i
;
if
reg_adr
=
c_ACAM_REG1_ADR
then
acam_config
(
1
)
<=
wb_in
.
dat
;
end
if
;
if
reg_adr
=
c_ACAM_REG2_ADR
then
acam_config
(
2
)
<=
tdc_config_wb_dat_i
;
acam_config
(
2
)
<=
wb_in
.
dat
;
end
if
;
if
reg_adr
=
c_ACAM_REG3_ADR
then
acam_config
(
3
)
<=
tdc_config_wb_dat_i
;
acam_config
(
3
)
<=
wb_in
.
dat
;
end
if
;
if
reg_adr
=
c_ACAM_REG4_ADR
then
acam_config
(
4
)
<=
tdc_config_wb_dat_i
;
acam_config
(
4
)
<=
wb_in
.
dat
;
end
if
;
if
reg_adr
=
c_ACAM_REG5_ADR
then
acam_config
(
5
)
<=
tdc_config_wb_dat_i
;
acam_config
(
5
)
<=
wb_in
.
dat
;
end
if
;
if
reg_adr
=
c_ACAM_REG6_ADR
then
acam_config
(
6
)
<=
tdc_config_wb_dat_i
;
acam_config
(
6
)
<=
wb_in
.
dat
;
end
if
;
if
reg_adr
=
c_ACAM_REG7_ADR
then
acam_config
(
7
)
<=
tdc_config_wb_dat_i
;
acam_config
(
7
)
<=
wb_in
.
dat
;
end
if
;
if
reg_adr
=
c_ACAM_REG11_ADR
then
acam_config
(
8
)
<=
tdc_config_wb_dat_i
;
acam_config
(
8
)
<=
wb_in
.
dat
;
end
if
;
if
reg_adr
=
c_ACAM_REG12_ADR
then
acam_config
(
9
)
<=
tdc_config_wb_dat_i
;
acam_config
(
9
)
<=
wb_in
.
dat
;
end
if
;
if
reg_adr
=
c_ACAM_REG14_ADR
then
acam_config
(
10
)
<=
tdc_config_wb_dat_i
;
acam_config
(
10
)
<=
wb_in
.
dat
;
end
if
;
end
if
;
end
if
;
...
...
@@ -316,10 +331,10 @@ begin
-- o one_hz_phase : eva: think it s not used
-- o start_phase : eva: think it s not used
TDCcore_config_reg_reception
:
process
(
clk_i
)
TDCcore_config_reg_reception
:
process
(
clk_
tdc_
i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_i
=
'1'
then
if
rising_edge
(
clk_
tdc_
i
)
then
if
rst_
tdc_
i
=
'1'
then
acam_inputs_en
<=
(
others
=>
'0'
);
starting_utc
<=
(
others
=>
'0'
);
start_phase
<=
(
others
=>
'0'
);
...
...
@@ -330,43 +345,42 @@ begin
irq_time_threshold
<=
x"000000C8"
;
-- default 200 ms
dac_word
<=
c_DEFAULT_DAC_WORD
;
-- default DAC Vout = 1.65
elsif
wb_in
.
cyc
=
'1'
and
wb_in
.
stb
=
'1'
and
wb_in
.
we
=
'1'
then
elsif
tdc_config_wb_cyc_i
=
'1'
and
tdc_config_wb_stb_i
=
'1'
and
tdc_config_wb_we_i
=
'1'
then
-- WISHBONE writes
if
reg_adr
=
c_STARTING_UTC_ADR
then
starting_utc
<=
tdc_config_wb_dat_i
;
if
reg_adr
=
c_STARTING_UTC_ADR
then
starting_utc
<=
wb_in
.
dat
;
end
if
;
if
reg_adr
=
c_ACAM_INPUTS_EN_ADR
then
acam_inputs_en
<=
tdc_config_wb_dat_i
;
acam_inputs_en
<=
wb_in
.
dat
;
end
if
;
if
reg_adr
=
c_START_PHASE_ADR
then
start_phase
<=
tdc_config_wb_dat_i
;
start_phase
<=
wb_in
.
dat
;
end
if
;
if
reg_adr
=
c_ONE_HZ_PHASE_ADR
then
one_hz_phase
<=
tdc_config_wb_dat_i
;
one_hz_phase
<=
wb_in
.
dat
;
end
if
;
if
reg_adr
=
c_IRQ_TSTAMP_THRESH_ADR
then
irq_tstamp_threshold
<=
tdc_config_wb_dat_i
;
irq_tstamp_threshold
<=
wb_in
.
dat
;
end
if
;
if
reg_adr
=
c_IRQ_TIME_THRESH_ADR
then
irq_time_threshold
<=
tdc_config_wb_dat_i
;
irq_time_threshold
<=
wb_in
.
dat
;
end
if
;
if
reg_adr
=
c_DAC_WORD_ADR
then
dac_word
<=
tdc_config_wb_dat_i
(
23
downto
0
);
dac_word
<=
wb_in
.
dat
(
23
downto
0
);
end
if
;
if
reg_adr
=
c_WRABBIT_CTRL_ADR
then
wrabbit_ctrl_reg
<=
tdc_config_wb_dat_i
;
wrabbit_ctrl_reg
<=
wb_in
.
dat
;
end
if
;
if
reg_adr
=
c_DEACT_CHAN_ADR
then
deactivate_chan
<=
tdc_config_wb_dat_i
;
deactivate_chan
<=
wb_in
.
dat
;
end
if
;
end
if
;
...
...
@@ -392,10 +406,10 @@ begin
-- Note that only one bit of the register should be written at a time. The process receives
-- the register, defines the action to be taken and after 1 clk cycle clears the register.
TDCcore_ctrl_reg_reception
:
process
(
clk
_i
)
TDCcore_ctrl_reg_reception
:
process
(
clk_tdc
_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_i
=
'1'
then
if
rising_edge
(
clk_
tdc_
i
)
then
if
rst_
tdc_
i
=
'1'
then
ctrl_reg
<=
(
others
=>
'0'
);
clear_ctrl_reg
<=
'0'
;
...
...
@@ -403,9 +417,9 @@ begin
ctrl_reg
<=
(
others
=>
'0'
);
clear_ctrl_reg
<=
'0'
;
elsif
tdc_config_wb_cyc_i
=
'1'
and
tdc_config_wb_stb_i
=
'1'
and
tdc_config_wb_we_i
=
'1'
then
-- WISHBONE writes
elsif
wb_in
.
cyc
=
'1'
and
wb_in
.
stb
=
'1'
and
wb_in
.
we
=
'1'
then
if
reg_adr
=
c_CTRL_REG_ADR
then
ctrl_reg
<=
tdc_config_wb_dat_i
;
ctrl_reg
<=
wb_in
.
dat
;
clear_ctrl_reg
<=
'1'
;
end
if
;
...
...
@@ -435,7 +449,7 @@ begin
generic
map
(
width
=>
3
)
port
map
(
clk_i
=>
clk_i
,
(
clk_i
=>
clk_
tdc_
i
,
rst_i
=>
send_dac_word_p
,
counter_top_i
=>
"111"
,
counter_incr_en_i
=>
pulse_extender_en
,
...
...
@@ -453,17 +467,15 @@ begin
-- including those of the ACAM and the TDC core.
-- Note: pipelining of the address for timing/slack reasons
WISHBONEreads
:
process
(
clk
_i
)
WISHBONEreads
:
process
(
clk_tdc
_i
)
begin
if
rising_edge
(
clk_i
)
then
--if tdc_config_wb_cyc_i = '1' and tdc_config_wb_stb_i = '1' and tdc_config_wb_we_i = '0' then -- WISHBONE reads
-- tdc_config_wb_dat_o <= dat_out;
if
rising_edge
(
clk_tdc_i
)
then
reg_adr_pipe0
<=
reg_adr
;
dat_out_pipe0
<=
dat_out_comb0
;
dat_out_pipe1
<=
dat_out_comb1
;
dat_out_pipe2
<=
dat_out_comb2
;
dat_out_pipe3
<=
dat_out_comb3
;
tdc_config_wb_dat_o
<=
dat_out_pipe0
or
dat_out_pipe1
or
dat_out_pipe2
or
dat_out_pipe3
;
wb_out
.
dat
<=
dat_out_pipe0
or
dat_out_pipe1
or
dat_out_pipe2
or
dat_out_pipe3
;
--end if;
end
if
;
end
process
;
...
...
@@ -532,4 +544,4 @@ end architecture rtl;
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
---------------------------------------------------------------------------------------------------
hdl/wr_spec_tdc/hdl/top/spec/fmc_tdc_wrapper.vhd
View file @
1b4e6b54
...
...
@@ -71,7 +71,7 @@
-- Date 01/2014 |
-- Version v5 (see sdb_meta_pkg) |
-- Depends on |
--
|
--
---------------- |
-- Last changes |
-- 05/2011 v1 GP First version |
...
...
@@ -251,9 +251,6 @@ architecture rtl of fmc_tdc_wrapper is
signal
pll_sclk
,
pll_sdi
,
pll_dac_sync
:
std_logic
;
signal
tdc_slave_in
:
t_wishbone_slave_in
;
signal
tdc_slave_out
:
t_wishbone_slave_out
;
signal
fmc_eic_irq
:
std_logic
;
signal
fmc_eic_irq_synch
:
std_logic_vector
(
1
downto
0
);
...
...
@@ -352,8 +349,16 @@ begin
(
clk_sys_i
=>
clk_sys_i
,
rst_sys_n_i
=>
rst_sys_n_i
,
-- 125M clk and reset
clk_ref_0_i
=>
clk_125m_mezz
,
rst_ref_0_i
=>
rst_125m_mezz
,
clk_tdc_i
=>
clk_125m_mezz
,
rst_tdc_i
=>
rst_125m_mezz
,
-- Wishbone
slave_i
=>
cnx_master_out
(
c_slave_regs
),
slave_o
=>
cnx_master_in
(
c_slave_regs
),
-- Interrupt line from EIC
wb_irq_o
=>
fmc_eic_irq
,
-- Configuration of the DAC on the TDC mezzanine, non White Rabbit
acam_refclk_r_edge_p_i
=>
acam_refclk_r_edge_p
,
send_dac_word_p_o
=>
send_dac_word_p
,
...
...
@@ -393,15 +398,7 @@ begin
tdc_in_fpga_4_i
=>
tdc_in_fpga_4_i
,
tdc_in_fpga_5_i
=>
tdc_in_fpga_5_i
,
-- WISHBONE interface with the GN4124 core
wb_tdc_csr_adr_i
=>
tdc_slave_in
.
adr
,
wb_tdc_csr_dat_i
=>
tdc_slave_in
.
dat
,
wb_tdc_csr_stb_i
=>
tdc_slave_in
.
stb
,
wb_tdc_csr_we_i
=>
tdc_slave_in
.
we
,
wb_tdc_csr_cyc_i
=>
tdc_slave_in
.
cyc
,
wb_tdc_csr_sel_i
=>
tdc_slave_in
.
sel
,
wb_tdc_csr_dat_o
=>
tdc_slave_out
.
dat
,
wb_tdc_csr_ack_o
=>
tdc_slave_out
.
ack
,
wb_tdc_csr_stall_o
=>
tdc_slave_out
.
stall
,
-- White Rabbit
wrabbit_link_up_i
=>
tm_link_up_i
,
wrabbit_time_valid_i
=>
tm_time_valid_i
,
...
...
@@ -412,8 +409,7 @@ begin
wrabbit_clk_dmtd_locked_i
=>
'1'
,
-- FIXME: fan out real signal from the WRCore
wrabbit_dac_value_i
=>
tm_dac_value_i
,
wrabbit_dac_wr_p_i
=>
tm_dac_wr_i
,
-- Interrupt line from EIC
wb_irq_o
=>
fmc_eic_irq
,
-- EEPROM I2C on TDC mezzanine
i2c_scl_oen_o
=>
tdc_scl_oen
,
i2c_scl_i
=>
mezz_scl_b
,
...
...
@@ -426,23 +422,6 @@ begin
direct_timestamp_o
=>
direct_timestamp
,
direct_timestamp_stb_o
=>
direct_timestamp_wr
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Domains crossing: clk_125m_mezz <-> clk_62m5_sys
cmp_tdc_clk_crossing
:
xwb_clock_crossing
port
map
(
slave_clk_i
=>
clk_sys_i
,
slave_rst_n_i
=>
rst_sys_n_i
,
slave_i
=>
cnx_master_out
(
c_slave_regs
),
slave_o
=>
cnx_master_in
(
c_slave_regs
),
master_clk_i
=>
clk_125m_mezz
,
-- Master reader port: TDC core at 125 MHz
master_rst_n_i
=>
rst_125m_mezz_n
,
master_i
=>
tdc_slave_out
,
master_o
=>
tdc_slave_in
);
tdc_slave_out
.
err
<=
'0'
;
tdc_slave_out
.
rty
<=
'0'
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Domains crossing: synchronization of the wb_ird_o from 125MHz to 62.5MHz
irq_pulse_synchronizer
:
process
(
clk_sys_i
)
...
...
hdl/wr_spec_tdc/hdl/top/spec/tdc_core_pkg.vhd
View file @
1b4e6b54
...
...
@@ -337,23 +337,38 @@ package tdc_core_pkg is
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
component
fmc_tdc_mezzanine
is
generic
(
g_with_wrabbit_core
:
boolean
:
=
TRUE
;
g_span
:
integer
:
=
32
;
g_width
:
integer
:
=
32
;
values_for_simul
:
boolean
:
=
FALSE
);
port
-- 62.5MHz clock and synchronous reset
(
clk_sys_i
:
in
std_logic
;
rst_sys_n_i
:
in
std_logic
;
-- Signals from the clks_rsts_manager unit
clk_ref_0_i
:
in
std_logic
;
rst_ref_0_i
:
in
std_logic
;
-- TDC core
port
-- TDC core
(
-- System clock & reset (Wishbone)
clk_sys_i
:
in
std_logic
;
-- 62.5 MHz clock
rst_sys_n_i
:
in
std_logic
;
-- reset for 62.5 MHz logic
-- TDC 125 MHz reference & Reset (FMC)
clk_tdc_i
:
in
std_logic
;
-- 125 MHz clock
rst_tdc_i
:
in
std_logic
;
-- reset for 125 MHz logic
-- WISHBONE interface with the GN4124/VME_core (clk_sys)
-- for the core configuration | timestamps retrieval | core interrupts | 1Wire | I2C
slave_i
:
in
t_wishbone_slave_in
;
slave_o
:
out
t_wishbone_slave_out
;
wb_irq_o
:
out
std_logic
;
acam_refclk_r_edge_p_i
:
in
std_logic
;
send_dac_word_p_o
:
out
std_logic
;
dac_word_o
:
out
std_logic_vector
(
23
downto
0
);
-- Interface with ACAM
start_from_fpga_o
:
out
std_logic
;
err_flag_i
:
in
std_logic
;
int_flag_i
:
in
std_logic
;
...
...
@@ -367,23 +382,26 @@ package tdc_core_pkg is
wr_n_o
:
out
std_logic
;
ef1_i
:
in
std_logic
;
ef2_i
:
in
std_logic
;
tdc_in_fpga_1_i
:
in
std_logic
;
tdc_in_fpga_2_i
:
in
std_logic
;
tdc_in_fpga_3_i
:
in
std_logic
;
tdc_in_fpga_4_i
:
in
std_logic
;
tdc_in_fpga_5_i
:
in
std_logic
;
-- Channels termination
enable_inputs_o
:
out
std_logic
;
term_en_1_o
:
out
std_logic
;
term_en_2_o
:
out
std_logic
;
term_en_3_o
:
out
std_logic
;
term_en_4_o
:
out
std_logic
;
term_en_5_o
:
out
std_logic
;
-- TDC board LEDs
tdc_led_status_o
:
out
std_logic
;
tdc_led_trig1_o
:
out
std_logic
;
tdc_led_trig2_o
:
out
std_logic
;
tdc_led_trig3_o
:
out
std_logic
;
tdc_led_trig4_o
:
out
std_logic
;
tdc_led_trig5_o
:
out
std_logic
;
-- Input pulses arriving also to the FPGA, currently not treated
tdc_in_fpga_1_i
:
in
std_logic
;
tdc_in_fpga_2_i
:
in
std_logic
;
tdc_in_fpga_3_i
:
in
std_logic
;
tdc_in_fpga_4_i
:
in
std_logic
;
tdc_in_fpga_5_i
:
in
std_logic
;
-- White Rabbit core
wrabbit_link_up_i
:
in
std_logic
;
wrabbit_time_valid_i
:
in
std_logic
;
...
...
@@ -394,104 +412,86 @@ package tdc_core_pkg is
wrabbit_clk_dmtd_locked_i
:
in
std_logic
;
wrabbit_dac_value_i
:
in
std_logic_vector
(
23
downto
0
);
wrabbit_dac_wr_p_i
:
in
std_logic
;
-- WISHBONE interface with the GN4124/VME_core
-- for the core configuration | timestamps retrieval | core interrupts | 1Wire | I2C
wb_tdc_csr_adr_i
:
in
std_logic_vector
(
31
downto
0
);
wb_tdc_csr_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_tdc_csr_cyc_i
:
in
std_logic
;
wb_tdc_csr_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_tdc_csr_stb_i
:
in
std_logic
;
wb_tdc_csr_we_i
:
in
std_logic
;
wb_tdc_csr_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_tdc_csr_ack_o
:
out
std_logic
;
wb_tdc_csr_stall_o
:
out
std_logic
;
wb_irq_o
:
out
std_logic
;
-- I2C EEPROM interface
i2c_scl_o
:
out
std_logic
;
i2c_scl_oen_o
:
out
std_logic
;
i2c_scl_i
:
in
std_logic
;
i2c_sda_o
:
out
std_logic
;
i2c_sda_oen_o
:
out
std_logic
;
i2c_sda_o
:
out
std_logic
;
i2c_sda_i
:
in
std_logic
;
-- 1-wire UniqueID&Thermometer
interface
-- 1-Wire
interface
onewire_b
:
inout
std_logic
;
direct_timestamp_o
:
out
std_logic_vector
(
127
downto
0
);
direct_timestamp_stb_o
:
out
std_logic
);
direct_timestamp_o
:
out
std_logic_vector
(
127
downto
0
);
direct_timestamp_stb_o
:
out
std_logic
);
end
component
;
---------------------------------------------------------------------------------------------------
component
fmc_tdc_core
component
fmc_tdc_core
is
generic
(
g_span
:
integer
:
=
32
;
g_width
:
integer
:
=
32
;
values_for_simul
:
boolean
:
=
FALSE
);
port
(
clk_125m_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
acam_refclk_r_edge_p_i
:
in
std_logic
;
send_dac_word_p_o
:
out
std_logic
;
dac_word_o
:
out
std_logic_vector
(
23
downto
0
);
start_from_fpga_o
:
out
std_logic
;
err_flag_i
:
in
std_logic
;
int_flag_i
:
in
std_logic
;
start_dis_o
:
out
std_logic
;
stop_dis_o
:
out
std_logic
;
data_bus_io
:
inout
std_logic_vector
(
27
downto
0
);
address_o
:
out
std_logic_vector
(
3
downto
0
);
cs_n_o
:
out
std_logic
;
oe_n_o
:
out
std_logic
;
rd_n_o
:
out
std_logic
;
wr_n_o
:
out
std_logic
;
ef1_i
:
in
std_logic
;
ef2_i
:
in
std_logic
;
tdc_in_fpga_1_i
:
in
std_logic
;
tdc_in_fpga_2_i
:
in
std_logic
;
tdc_in_fpga_3_i
:
in
std_logic
;
tdc_in_fpga_4_i
:
in
std_logic
;
tdc_in_fpga_5_i
:
in
std_logic
;
enable_inputs_o
:
out
std_logic
;
term_en_1_o
:
out
std_logic
;
term_en_2_o
:
out
std_logic
;
term_en_3_o
:
out
std_logic
;
term_en_4_o
:
out
std_logic
;
term_en_5_o
:
out
std_logic
;
tdc_led_status_o
:
out
std_logic
;
tdc_led_trig1_o
:
out
std_logic
;
tdc_led_trig2_o
:
out
std_logic
;
tdc_led_trig3_o
:
out
std_logic
;
tdc_led_trig4_o
:
out
std_logic
;
tdc_led_trig5_o
:
out
std_logic
;
wrabbit_status_reg_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
wrabbit_ctrl_reg_o
:
out
std_logic_vector
(
g_width
-1
downto
0
);
wrabbit_synched_i
:
in
std_logic
;
wrabbit_tai_p_i
:
in
std_logic
;
wrabbit_tai_i
:
in
std_logic_vector
(
31
downto
0
);
irq_tstamp_p_o
:
out
std_logic
;
irq_time_p_o
:
out
std_logic
;
irq_acam_err_p_o
:
out
std_logic
;
tdc_config_wb_adr_i
:
in
std_logic_vector
(
g_span
-1
downto
0
);
tdc_config_wb_dat_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
tdc_config_wb_stb_i
:
in
std_logic
;
tdc_config_wb_we_i
:
in
std_logic
;
tdc_config_wb_cyc_i
:
in
std_logic
;
tdc_config_wb_dat_o
:
out
std_logic_vector
(
g_width
-1
downto
0
);
tdc_config_wb_ack_o
:
out
std_logic
;
tdc_mem_wb_adr_i
:
in
std_logic_vector
(
31
downto
0
);
tdc_mem_wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
tdc_mem_wb_stb_i
:
in
std_logic
;
tdc_mem_wb_we_i
:
in
std_logic
;
tdc_mem_wb_cyc_i
:
in
std_logic
;
tdc_mem_wb_ack_o
:
out
std_logic
;
tdc_mem_wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
tdc_mem_wb_stall_o
:
out
std_logic
;
direct_timestamp_o
:
out
std_logic_vector
(
127
downto
0
);
direct_timestamp_stb_o
:
out
std_logic
);
end
component
;
port
(
clk_sys_i
:
in
std_logic
;
rst_n_sys_i
:
in
std_logic
;
clk_tdc_i
:
in
std_logic
;
rst_tdc_i
:
in
std_logic
;
acam_refclk_r_edge_p_i
:
in
std_logic
;
send_dac_word_p_o
:
out
std_logic
;
dac_word_o
:
out
std_logic_vector
(
23
downto
0
);
start_from_fpga_o
:
out
std_logic
;
err_flag_i
:
in
std_logic
;
int_flag_i
:
in
std_logic
;
start_dis_o
:
out
std_logic
;
stop_dis_o
:
out
std_logic
;
data_bus_io
:
inout
std_logic_vector
(
27
downto
0
);
address_o
:
out
std_logic_vector
(
3
downto
0
);
cs_n_o
:
out
std_logic
;
oe_n_o
:
out
std_logic
;
rd_n_o
:
out
std_logic
;
wr_n_o
:
out
std_logic
;
ef1_i
:
in
std_logic
;
ef2_i
:
in
std_logic
;
enable_inputs_o
:
out
std_logic
;
term_en_1_o
:
out
std_logic
;
term_en_2_o
:
out
std_logic
;
term_en_3_o
:
out
std_logic
;
term_en_4_o
:
out
std_logic
;
term_en_5_o
:
out
std_logic
;
tdc_led_status_o
:
out
std_logic
;
tdc_led_trig1_o
:
out
std_logic
;
tdc_led_trig2_o
:
out
std_logic
;
tdc_led_trig3_o
:
out
std_logic
;
tdc_led_trig4_o
:
out
std_logic
;
tdc_led_trig5_o
:
out
std_logic
;
tdc_in_fpga_1_i
:
in
std_logic
;
tdc_in_fpga_2_i
:
in
std_logic
;
tdc_in_fpga_3_i
:
in
std_logic
;
tdc_in_fpga_4_i
:
in
std_logic
;
tdc_in_fpga_5_i
:
in
std_logic
;
irq_tstamp_p_o
:
out
std_logic
;
irq_time_p_o
:
out
std_logic
;
irq_acam_err_p_o
:
out
std_logic
;
wrabbit_status_reg_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
wrabbit_ctrl_reg_o
:
out
std_logic_vector
(
g_width
-1
downto
0
);
wrabbit_synched_i
:
in
std_logic
;
wrabbit_tai_p_i
:
in
std_logic
;
wrabbit_tai_i
:
in
std_logic_vector
(
31
downto
0
);
cfg_slave_i
:
in
t_wishbone_slave_in
;
cfg_slave_o
:
out
t_wishbone_slave_out
;
mem_slave_i
:
in
t_wishbone_slave_in
;
mem_slave_o
:
out
t_wishbone_slave_out
;
direct_timestamp_o
:
out
std_logic_vector
(
127
downto
0
);
direct_timestamp_stb_o
:
out
std_logic
);
end
component
fmc_tdc_core
;
---------------------------------------------------------------------------------------------------
component
wrabbit_sync
is
generic
...
...
@@ -645,18 +645,23 @@ package tdc_core_pkg is
---------------------------------------------------------------------------------------------------
component
reg_ctrl
generic
(
g_span
:
integer
:
=
32
;
g_width
:
integer
:
=
32
);
port
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
tdc_config_wb_adr_i
:
in
std_logic_vector
(
g_span
-1
downto
0
);
tdc_config_wb_cyc_i
:
in
std_logic
;
tdc_config_wb_dat_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
tdc_config_wb_stb_i
:
in
std_logic
;
tdc_config_wb_we_i
:
in
std_logic
;
(
clk_sys_i
:
in
std_logic
;
rst_n_sys_i
:
in
std_logic
;
-- global reset, synched to clk_sys_i
clk_tdc_i
:
in
std_logic
;
rst_tdc_i
:
in
std_logic
;
slave_i
:
in
t_wishbone_slave_in
;
-- WB interface (clk_sys domain)
slave_o
:
out
t_wishbone_slave_out
;
acam_config_rdbk_i
:
in
config_vector
;
acam_ififo1_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
acam_ififo2_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
...
...
@@ -667,8 +672,7 @@ package tdc_core_pkg is
core_status_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
wrabbit_status_reg_i
:
in
std_logic_vector
(
g_width
-1
downto
0
);
----------------------------------------------------------------------
tdc_config_wb_ack_o
:
out
std_logic
;
tdc_config_wb_dat_o
:
out
std_logic_vector
(
g_width
-1
downto
0
);
activate_acq_p_o
:
out
std_logic
;
deactivate_acq_p_o
:
out
std_logic
;
deactivate_chan_o
:
out
std_logic_vector
(
4
downto
0
);
...
...
@@ -909,7 +913,9 @@ package tdc_core_pkg is
---------------------------------------------------------------------------------------------------
component
circular_buffer
port
(
clk_i
:
in
std_logic
;
(
clk_tdc_i
:
in
std_logic
;
-- 125 MHz clock; same for both port
clk_sys_i
:
in
std_logic
;
tstamp_wr_rst_i
:
in
std_logic
;
tstamp_wr_stb_i
:
in
std_logic
;
tstamp_wr_cyc_i
:
in
std_logic
;
...
...
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