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FMC TDC 1ns 5cha - Gateware
Commit 22139218 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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rtl: rewrote circular_buffer to use generic RAM instead of an NGC

parent 9e39ab1f
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hdl/rtl/circular_buffer.vhd
View file @ 22139218
......@@ -90,12 +90,12 @@
-- Standard library
library IEEE;
use IEEE.std_logic_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
use IEEE.std_logic_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.tdc_core_pkg.all; -- definitions of types, constants, entities
use work.tdc_core_pkg.all; -- definitions of types, constants, entities
use work.genram_pkg.all; -- for the RAM
--=================================================================================================
-- Entity declaration for circular_buffer
......@@ -103,36 +103,38 @@ use work.tdc_core_pkg.all; -- definitions of types, constants, entities
entity circular_buffer is
port
-- INPUTS
-- Signal from the clk_rst_manager
(clk_tdc_i : in std_logic; -- 125 MHz clock; same for both ports
-- INPUTS
-- Signal from the clk_rst_manager
(clk_tdc_i : in std_logic; -- 125 MHz clock; same for both ports
clk_sys_i : in std_logic;
rst_n_sys_i : in std_logic;
-- Signals from the data_formatting unit (WISHBONE classic): timestamps writing
tstamp_wr_rst_i : in std_logic; -- timestamp writing WISHBONE reset
tstamp_wr_stb_i : in std_logic; -- timestamp writing WISHBONE strobe
tstamp_wr_cyc_i : in std_logic; -- timestamp writing WISHBONE cycle
tstamp_wr_we_i : in std_logic; -- timestamp writing WISHBONE write enable
tstamp_wr_adr_i : in std_logic_vector(7 downto 0); -- adr 8 bits long 2^8 = 255
tstamp_wr_dat_i : in std_logic_vector(127 downto 0); -- timestamp 128 bits long
tstamp_wr_rst_i : in std_logic; -- timestamp writing WISHBONE reset
tstamp_wr_stb_i : in std_logic; -- timestamp writing WISHBONE strobe
tstamp_wr_cyc_i : in std_logic; -- timestamp writing WISHBONE cycle
tstamp_wr_we_i : in std_logic; -- timestamp writing WISHBONE write enable
tstamp_wr_adr_i : in std_logic_vector(7 downto 0); -- adr 8 bits long 2^8 = 255
tstamp_wr_dat_i : in std_logic_vector(127 downto 0); -- timestamp 128 bits long
-- Signals from the GN4124/VME core unit (WISHBONE pipelined): timestamps reading
tdc_mem_wb_rst_i : in std_logic; -- timestamp reading WISHBONE reset
tdc_mem_wb_stb_i : in std_logic; -- timestamp reading WISHBONE strobe
tdc_mem_wb_cyc_i : in std_logic; -- timestamp reading WISHBONE cycle
tdc_mem_wb_we_i : in std_logic; -- timestamp reading WISHBONE write enable; not used
tdc_mem_wb_adr_i : in std_logic_vector(31 downto 0); -- adr 10 bits long 2^10 = 1024
tdc_mem_wb_dat_i : in std_logic_vector(31 downto 0); -- not used
-- OUTPUTS
tdc_mem_wb_rst_i : in std_logic; -- timestamp reading WISHBONE reset
tdc_mem_wb_stb_i : in std_logic; -- timestamp reading WISHBONE strobe
tdc_mem_wb_cyc_i : in std_logic; -- timestamp reading WISHBONE cycle
tdc_mem_wb_we_i : in std_logic; -- timestamp reading WISHBONE write enable; not used
tdc_mem_wb_adr_i : in std_logic_vector(31 downto 0); -- adr 10 bits long 2^10 = 1024
tdc_mem_wb_dat_i : in std_logic_vector(31 downto 0); -- not used
-- OUTPUTS
-- Signals to the data_formatting unit (WISHBONE classic): timestamps writing
tstamp_wr_ack_p_o : out std_logic; -- timestamp writing WISHBONE classic acknowledge
tstamp_wr_dat_o : out std_logic_vector(127 downto 0); -- not used
tstamp_wr_ack_p_o : out std_logic; -- timestamp writing WISHBONE classic acknowledge
tstamp_wr_dat_o : out std_logic_vector(127 downto 0); -- not used
-- Signals to the GN4124/VME core unit (WISHBONE pipelined): timestamps reading
tdc_mem_wb_ack_o : out std_logic; -- timestamp reading WISHBONE pipelined acknowledge
tdc_mem_wb_dat_o : out std_logic_vector(31 downto 0); -- 32 bit words
tdc_mem_wb_stall_o : out std_logic); -- timestamp reading WISHBONE pipelined stall
tdc_mem_wb_ack_o : out std_logic; -- timestamp reading WISHBONE pipelined acknowledge
tdc_mem_wb_dat_o : out std_logic_vector(31 downto 0); -- 32 bit words
tdc_mem_wb_stall_o : out std_logic); -- timestamp reading WISHBONE pipelined stall
end circular_buffer;
......@@ -142,10 +144,13 @@ end circular_buffer;
architecture rtl of circular_buffer is
type t_wb_wr is (IDLE, MEM_ACCESS, MEM_ACCESS_AND_ACKNOWLEDGE, ACKNOWLEDGE);
type t_rd_data_array is array(0 to 3) of std_logic_vector(31 downto 0);
signal tstamp_rd_wb_st, nxt_tstamp_rd_wb_st : t_wb_wr;
signal tstamp_wr_ack_p : std_logic;
signal tstamp_rd_we, tstamp_wr_we : std_logic_vector(0 downto 0);
signal tstamp_rd_we, tstamp_wr_we : std_logic_vector(3 downto 0);
signal mb_data : t_rd_data_array;
signal adr_d0 : std_logic_vector(1 downto 0);
--=================================================================================================
-- architecture begin
......@@ -156,14 +161,14 @@ begin
-- TIMESTAMP WRITINGS WISHBONE CLASSIC ACK --
---------------------------------------------------------------------------------------------------
-- WISHBONE classic interface compatible slave
classic_interface: process (clk_tdc_i)
classic_interface : process (clk_tdc_i)
begin
if rising_edge (clk_tdc_i) then
if tstamp_wr_rst_i ='1' then
if tstamp_wr_rst_i = '1' then
tstamp_wr_ack_p <= '0';
elsif tstamp_wr_stb_i = '1' and tstamp_wr_cyc_i = '1' and tstamp_wr_ack_p = '0' then
tstamp_wr_ack_p <= '1'; -- a new 1 clk-wide ack is given for each stb
tstamp_wr_ack_p <= '1'; -- a new 1 clk-wide ack is given for each stb
else
tstamp_wr_ack_p <= '0';
end if;
......@@ -171,7 +176,7 @@ begin
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
tstamp_wr_ack_p_o <= tstamp_wr_ack_p;
tstamp_wr_ack_p_o <= tstamp_wr_ack_p;
---------------------------------------------------------------------------------------------------
......@@ -187,10 +192,10 @@ begin
-- ACK : _________________|-----------------------------------|_____
-- DATO: <DAT0><DAT1><DAT2><DAT3><DAT4><DAT5>
WB_pipe_ack_fsm_seq: process (clk_sys_i)
WB_pipe_ack_fsm_seq : process (clk_sys_i)
begin
if rising_edge (clk_sys_i) then
if tdc_mem_wb_rst_i ='1' then
if tdc_mem_wb_rst_i = '1' then
tstamp_rd_wb_st <= IDLE;
else
tstamp_rd_wb_st <= nxt_tstamp_rd_wb_st;
......@@ -199,70 +204,70 @@ begin
end process;
---------------------------------------------------------------------------------------------------
WB_pipe_ack_fsm_comb: process (tstamp_rd_wb_st, tdc_mem_wb_stb_i, tdc_mem_wb_cyc_i)
WB_pipe_ack_fsm_comb : process (tstamp_rd_wb_st, tdc_mem_wb_stb_i, tdc_mem_wb_cyc_i)
begin
case tstamp_rd_wb_st is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when IDLE =>
-----------------------------------------------
tdc_mem_wb_ack_o <= '0';
-----------------------------------------------
-----------------------------------------------
tdc_mem_wb_ack_o <= '0';
-----------------------------------------------
if tdc_mem_wb_stb_i = '1' and tdc_mem_wb_cyc_i = '1' then
nxt_tstamp_rd_wb_st <= MEM_ACCESS;
else
nxt_tstamp_rd_wb_st <= IDLE;
end if;
if tdc_mem_wb_stb_i = '1' and tdc_mem_wb_cyc_i = '1' then
nxt_tstamp_rd_wb_st <= MEM_ACCESS;
else
nxt_tstamp_rd_wb_st <= IDLE;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when MEM_ACCESS =>
-----------------------------------------------
tdc_mem_wb_ack_o <= '0';
-----------------------------------------------
-----------------------------------------------
tdc_mem_wb_ack_o <= '0';
-----------------------------------------------
if tdc_mem_wb_stb_i = '1' and tdc_mem_wb_cyc_i = '1' then
nxt_tstamp_rd_wb_st <= MEM_ACCESS_AND_ACKNOWLEDGE;
else
nxt_tstamp_rd_wb_st <= ACKNOWLEDGE;
end if;
if tdc_mem_wb_stb_i = '1' and tdc_mem_wb_cyc_i = '1' then
nxt_tstamp_rd_wb_st <= MEM_ACCESS_AND_ACKNOWLEDGE;
else
nxt_tstamp_rd_wb_st <= ACKNOWLEDGE;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when MEM_ACCESS_AND_ACKNOWLEDGE =>
-----------------------------------------------
tdc_mem_wb_ack_o <= '1';
-----------------------------------------------
-----------------------------------------------
tdc_mem_wb_ack_o <= '1';
-----------------------------------------------
if tdc_mem_wb_stb_i = '1' and tdc_mem_wb_cyc_i = '1' then
nxt_tstamp_rd_wb_st <= MEM_ACCESS_AND_ACKNOWLEDGE;
else
nxt_tstamp_rd_wb_st <= ACKNOWLEDGE;
end if;
if tdc_mem_wb_stb_i = '1' and tdc_mem_wb_cyc_i = '1' then
nxt_tstamp_rd_wb_st <= MEM_ACCESS_AND_ACKNOWLEDGE;
else
nxt_tstamp_rd_wb_st <= ACKNOWLEDGE;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when ACKNOWLEDGE =>
-----------------------------------------------
tdc_mem_wb_ack_o <= '1';
-----------------------------------------------
-----------------------------------------------
tdc_mem_wb_ack_o <= '1';
-----------------------------------------------
if tdc_mem_wb_stb_i = '1' and tdc_mem_wb_cyc_i = '1' then
nxt_tstamp_rd_wb_st <= MEM_ACCESS;
else
nxt_tstamp_rd_wb_st <= IDLE;
end if;
if tdc_mem_wb_stb_i = '1' and tdc_mem_wb_cyc_i = '1' then
nxt_tstamp_rd_wb_st <= MEM_ACCESS;
else
nxt_tstamp_rd_wb_st <= IDLE;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when others =>
-----------------------------------------------
tdc_mem_wb_ack_o <= '0';
-----------------------------------------------
-----------------------------------------------
tdc_mem_wb_ack_o <= '0';
-----------------------------------------------
nxt_tstamp_rd_wb_st <= IDLE;
nxt_tstamp_rd_wb_st <= IDLE;
end case;
end process;
......@@ -270,32 +275,41 @@ begin
tdc_mem_wb_stall_o <= '0';
---------------------------------------------------------------------------------------------------
-- DUAL PORT BLOCK RAM --
---------------------------------------------------------------------------------------------------
memory_block: blk_mem_circ_buff_v6_4
port map(
-- Port A: attached to the data_formatting unit
clka => clk_tdc_i,
addra => tstamp_wr_adr_i(7 downto 0), -- 2^8 = 256 addresses
dina => tstamp_wr_dat_i, -- 128-bit long timestamps
ena => tstamp_wr_cyc_i,
wea => tstamp_wr_we,
douta => tstamp_wr_dat_o, -- not used
-- Port B: attached to the GN4124/VME_core unit
clkb => clk_sys_i,
addrb => tdc_mem_wb_adr_i(9 downto 0),-- 2^10 = 1024 addresses
dinb => tdc_mem_wb_dat_i, -- not used
enb => tdc_mem_wb_cyc_i,
web => tstamp_rd_we, -- not used
--------------------------------------------------
doutb => tdc_mem_wb_dat_o); -- 32-bit long words
--------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
tstamp_wr_we(0) <= tstamp_wr_we_i;
tstamp_rd_we(0) <= tdc_mem_wb_we_i;
gen_mem_blocks : for i in 0 to 3 generate
memory_block : generic_dpram
generic map (
g_data_width => 32,
g_size => 256,
g_with_byte_enable => false,
g_addr_conflict_resolution => "dont_care",
g_dual_clock => true)
port map (
rst_n_i => rst_n_sys_i,
clka_i => clk_tdc_i,
wea_i => tstamp_wr_we(0),
aa_i => tstamp_wr_adr_i(7 downto 0),
da_i => tstamp_wr_dat_i(32*i + 31 downto 32*i),
clkb_i => clk_sys_i,
web_i => tstamp_rd_we(i),
ab_i => tdc_mem_wb_adr_i(9 downto 2),
db_i => tdc_mem_wb_dat_i,
qb_o => mb_data(i));
tstamp_rd_we(i) <= '1' when unsigned(tdc_mem_wb_adr_i(1 downto 0) = i) else '0';
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
adr_d0 <= tdc_mem_wb_adr_i(1 downto 0);
end if;
end process;
tdc_mem_wb_dat_o <= mb_data(to_integer(unsigned(adr_d0)));
end generate gen_mem_blocks;
tstamp_wr_we(0) <= tstamp_wr_we_i and tstamp_wr_cyc_i and tstamp_wr_stb_i;
end architecture rtl;
......
hdl/rtl/data_formatting.vhd
View file @ 22139218
......@@ -80,7 +80,6 @@ entity data_formatting is
-- Signals from the circular_buffer unit: WISHBONE classic
tstamp_wr_wb_ack_i : in std_logic; -- tstamp writing WISHBONE acknowledge
tstamp_wr_dat_i : in std_logic_vector(127 downto 0); -- not used
-- Signals from the data_engine unit
acam_tstamp1_ok_p_i : in std_logic; -- tstamp1 valid indicator
......
hdl/rtl/fmc_tdc_core.vhd
View file @ 22139218
......@@ -523,7 +523,6 @@ begin
(clk_i => clk_tdc_i,
rst_i => rst_tdc_i,
tstamp_wr_wb_ack_i => circ_buff_class_ack,
tstamp_wr_dat_i => circ_buff_class_data_rd,
tstamp_wr_wb_adr_o => circ_buff_class_adr,
tstamp_wr_wb_cyc_o => circ_buff_class_cyc,
tstamp_wr_dat_o => circ_buff_class_data_wr,
......
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