testbench: sample top level testbench for SVEC

389734e7 · Tomasz Wlostowski · b358b1ed · 389734e7 · 389734e7 · 389734e7
Commit 389734e7 authored Mar 26, 2015 by Tomasz Wlostowski
10 changed files
--- a/hdl/testbench/include/cpu_csr_driver.svh
+++ b/hdl/testbench/include/cpu_csr_driver.svh
+`include "wrn_cpu_csr_regs.vh"
+
+typedef class NodeCPUDbgQueue;
+   
+
+class NodeCPUControl;
+   protected CBusAccessor bus;
+   protected uint32_t base;
+
+   protected uint32_t core_count ,app_id;
+
+//   NodeCPUDbgQueue dbgq [$];
+   NodeCPUDbgQueue dbgq [$];
+   
+   function new ( CBusAccessor bus_, input uint32_t base_);
+      base = base_;
+      bus = bus_;
+   endfunction // new
+
+   task writel ( uint32_t r, uint32_t v );
+      bus.write ( base + r, v );
+   endtask // _write
+
+   task readl (  uint32_t r, ref uint32_t v );
+      uint64_t tmp;
+      bus.read (base + r, tmp );
+      v= tmp;
+   endtask // readl
+   
+   task init();
+      int i;
+      
+      
+      readl(`ADDR_WRN_CPU_CSR_APP_ID, app_id);
+      readl(`ADDR_WRN_CPU_CSR_CORE_COUNT, core_count);
+
+      core_count&='hf;
+
+      for(i=0;i<core_count;i++)
+	begin
+	   NodeCPUDbgQueue q = new ( this, i );
+	   
+	   dbgq.push_back (q);
+	end
+      
+      $display("App ID: %x", app_id);
+      $display("Core count: %d", core_count);
+      for(i=0;i<core_count;i++)
+      begin
+         uint32_t memsize;
+         writel(`ADDR_WRN_CPU_CSR_CORE_SEL, i);
+         readl(`ADDR_WRN_CPU_CSR_CORE_MEMSIZE, memsize);
+         $display("Core %d: %d kB private memory", i, memsize/1024);
+ 
+      end
+      
+      
+      
+      
+   endtask // init
+
+   task reset_core(int core, int reset);
+      uint32_t rstr;
+      readl(`ADDR_WRN_CPU_CSR_RESET, rstr);
+
+      if(reset)
+        rstr |= (1<<core);
+      else
+        rstr &= ~(1<<core);
+      writel(`ADDR_WRN_CPU_CSR_RESET, rstr);
+   endtask // enable_cpu
+
+
+   task debug_int_enable(int core, int enable);
+      uint32_t imsk;
+
+      readl(`ADDR_WRN_CPU_CSR_DBG_IMSK, imsk);
+      if(enable)
+	imsk |= (1<<core);
+      else
+	imsk &= ~(1<<core);
+      writel(`ADDR_WRN_CPU_CSR_DBG_IMSK, imsk);
+   endtask // debug_int_enable
+
+
+   
+   task load_firmware(int core, string filename);
+      integer f = $fopen(filename,"r");
+      uint32_t q[$];
+      int     n, i;
+      
+      reset_core(core, 1);
+
+      writel(`ADDR_WRN_CPU_CSR_CORE_SEL, core);
+
+      
+      
+      while(!$feof(f))
+        begin
+           int addr, data;
+           string cmd;
+           
+           $fscanf(f,"%s %08x %08x", cmd,addr,data);
+           if(cmd == "write")
+             begin
+                writel(`ADDR_WRN_CPU_CSR_UADDR, addr);
+                writel(`ADDR_WRN_CPU_CSR_UDATA, data);
+		q.push_back(data);
+		n++;
+		
+             end
+        end
+
+      for(i=0;i<n;i++)
+	begin
+	   uint32_t rv;
+           writel(`ADDR_WRN_CPU_CSR_UADDR, i);
+           readl(`ADDR_WRN_CPU_CSR_UDATA, rv);
+	   $display("readback: addr %x d %x", i, rv);
+	   if(rv != q[i])
+	     $display("verification error\n");
+	   
+	end
+      
+      
+   endtask
+        
+      
+ 
+   task update();
+      int i;
+
+      for(i=0;i<core_count;i++)
+	dbgq[i].update();
+
+   endtask // update
+   
+   
+   
+endclass 
+
+
+class NodeCPUDbgQueue;
+   protected NodeCPUControl cctl;
+   protected int core_id;
+
+   int 		 queue[$];
+   
+   function new ( NodeCPUControl cctl_, int core_id_);
+      cctl = cctl_;
+      core_id = core_id_;
+   endfunction // new
+   
+
+   task update();
+      uint32_t rval;
+      
+      forever begin
+		 cctl.readl(`ADDR_WRN_CPU_CSR_DBG_POLL , rval);
+	 if(! (rval & (1<<core_id)))
+	   break;
+	 cctl.writel(`ADDR_WRN_CPU_CSR_CORE_SEL, core_id);
+	 cctl.readl(`ADDR_WRN_CPU_CSR_DBG_MSG, rval);
+	 queue.push_back(rval);
+	 $display("dbg rx '%c'", rval);
+      end
+	   
+   endtask // update
+   
+
+   
+   
+endclass // NodeCPUDbgQueue
--- a/hdl/testbench/include/mqueue_host.svh
+++ b/hdl/testbench/include/mqueue_host.svh
+`define MQUEUE_BASE_IN(x) ('h4000 + (x) * 'h400)
+`define MQUEUE_BASE_OUT(x) ('h8000 + (x) * 'h400)
+
+`define MQUEUE_CMD_CLAIM (1<<24)
+`define MQUEUE_CMD_PURGE (1<<25)
+`define MQUEUE_CMD_READY (1<<26)
+`define MQUEUE_CMD_DISCARD (1<<27)
+
+`define MQUEUE_SLOT_COMMAND 0
+`define MQUEUE_SLOT_STATUS 4
+
+`define MQUEUE_GCR_INCOMING_STATUS_MASK (32'h0000ffff)
+
+`define MQUEUE_GCR_SLOT_COUNT 0
+`define MQUEUE_GCR_SLOT_STATUS 4
+`define MQUEUE_GCR_IRQ_MASK 8
+`define MQUEUE_GCR_IRQ_COALESCE 12
+
+
+class MQueueCB;
+   protected CBusAccessor bus;
+   protected uint32_t base;
+   
+   function new ( CBusAccessor bus_, input uint32_t base_);
+      base = base_;
+      bus = bus_;
+   endfunction // new
+
+   task outgoing_write ( int slot, uint32_t r, uint32_t v );
+      
+      bus.write ( base + `MQUEUE_BASE_OUT(slot) + r, v);
+   endtask // slot_write
+   
+   
+   task send(int slot, uint32_t data[] );
+      int i;
+      
+      outgoing_write( slot, `MQUEUE_SLOT_COMMAND, `MQUEUE_CMD_CLAIM);
+      for(i=0;i<data.size(); i++)
+        outgoing_write( slot, 8 + i * 4, data[i]);
+      outgoing_write( slot, `MQUEUE_SLOT_COMMAND, `MQUEUE_CMD_READY | data.size());
+   endtask // send
+   
+endclass 
+
+class MQueueHost;
+   protected CBusAccessor bus;
+   protected uint32_t base;
+   protected bit initialized;
+
+   protected int n_in, n_out;
+
+   typedef struct {
+      uint32_t data[$];
+   } mqueue_message_t;
+     
+   typedef mqueue_message_t slot_queue_t[$];
+      
+   slot_queue_t slots_in[16], slots_out[16];
+   
+   function bit poll(int slot);
+      return slots_in[slot].size() != 0;
+   endfunction // poll
+
+   function mqueue_message_t recv (int slot);
+      mqueue_message_t tmp = slots_in[slot][$];
+      slots_in[slot].pop_back();
+      return tmp;
+   endfunction
+
+   task send (int slot, uint32_t data[$]);
+      mqueue_message_t msg;
+      msg.data = data;
+      slots_out[slot].push_back(msg);
+   endtask // send
+
+   function int idle();
+      int i;
+      for(i=0;i<n_out;i++)
+        if(slots_out[i].size())
+          return 0;
+      return 1;
+   endfunction // idle
+   
+        
+      
+     
+   
+   function new( CBusAccessor bus_, input uint32_t base_);
+      base = base_;
+      bus = bus_;
+      initialized = 0;
+      
+   endfunction // new
+   
+   task incoming_write ( int slot, uint32_t r, uint32_t v );
+      
+      bus.write ( base + `MQUEUE_BASE_IN(slot) + r, v );
+   endtask // slot_write
+
+   task incoming_read ( int slot, uint32_t r, ref uint32_t v );
+      uint64_t tmp;
+      
+      bus.read ( base + `MQUEUE_BASE_IN(slot) + r, tmp );
+      v= tmp;
+      
+   endtask // slot_write
+
+   task outgoing_read ( int slot, uint32_t r, ref uint32_t v );
+      uint64_t tmp;
+      
+      bus.read ( base + `MQUEUE_BASE_OUT(slot) + r, tmp );
+      v= tmp;
+   endtask // slot_write
+
+   task outgoing_write ( int slot, uint32_t r, uint32_t v );
+      bus.write ( base + `MQUEUE_BASE_OUT(slot) + r, v);
+   endtask // slot_write
+
+   
+   task gcr_read ( uint32_t r, output uint32_t rv );
+      uint64_t tmp;
+      
+      bus.read ( base + r, tmp );
+      rv = tmp;
+      
+   endtask // gcr_read
+
+   task outgoing_check_full( int slot, output int full );
+      uint32_t rv;
+      outgoing_read( slot, `MQUEUE_SLOT_STATUS, rv);
+      full = (rv & 1) ? 1:  0;
+   endtask // outgoing_full
+
+
+   task incoming_send(int slot, uint32_t data[$] );
+      int i;
+      
+      incoming_write( slot, `MQUEUE_SLOT_COMMAND, `MQUEUE_CMD_CLAIM);
+      for(i=0;i<data.size(); i++)
+        incoming_write( slot, 8 + i * 4, data[i]);
+      incoming_write( slot, `MQUEUE_SLOT_COMMAND, `MQUEUE_CMD_READY | data.size());
+
+      $display("in%d tx size=%d ", slot, data.size());
+
+   endtask // send
+
+   task init();
+      uint32_t slot_count, slot_status;
+      int i, entries, size;
+      
+      gcr_read(`MQUEUE_GCR_SLOT_COUNT, slot_count);
+
+      n_in = slot_count & 'hff;
+      n_out = (slot_count >> 8) & 'hff;
+
+      $display("HMQ init: CPU->Host (outgoing) slots: %d Host->CPU (incoming) slots: %d", n_out, n_in);
+      for(i =0 ; i<n_out; i++)begin
+         outgoing_read(i, `MQUEUE_SLOT_STATUS, slot_status);
+         size = 1 << (( slot_status >> 28) & 'hf);
+         entries = 1 << (( slot_status >> 2) & 'h3f);
+         
+         $display(" - out%d: size=%d, entries=%d", i, size, entries);
+
+      end
+
+      for(i =0 ; i<n_in; i++)
+        begin
+         incoming_read(i, `MQUEUE_SLOT_STATUS, slot_status);
+         size = 1 << (( slot_status >> 28) & 'hf);
+         entries = 1 << (( slot_status >> 2) & 'h3f);
+         
+         $display(" - in%d: size=%d, entries=%d", i, size, entries);
+
+      end
+      
+      initialized = 1;
+      
+   endtask // init
+
+   task outgoing_input(int slot);
+      uint32_t stat;
+      int count, i;
+      
+      outgoing_read ( slot, `MQUEUE_SLOT_STATUS, stat );
+
+      
+      count = (stat >> 16) & 'hff;
+
+      $display("slot stat %x", stat);
+      
+      
+      $display("out%d rx size=%d ", slot, count);
+      for(i=0;i<count;i++)begin
+         uint32_t d;
+         
+         outgoing_read ( slot, 8 + i * 4, d );
+         $display("data: %x '%c'", d, d);
+      end
+
+      outgoing_write( slot, `MQUEUE_SLOT_COMMAND, `MQUEUE_CMD_DISCARD );
+      
+      
+   endtask // read_incoming
+   
+   task update();
+      uint32_t in_stat, irq_mask;
+      int i;
+      
+      
+      if(!initialized)
+        init();
+
+      gcr_read( `MQUEUE_GCR_SLOT_STATUS, in_stat);
+
+      $display("GCR stat %x", in_stat);
+
+      gcr_read( `MQUEUE_GCR_IRQ_MASK, irq_mask);
+
+      $display("GCR irq_mask %x", irq_mask);
+      
+
+      if(in_stat & `MQUEUE_GCR_INCOMING_STATUS_MASK)
+        begin
+           for(i = 0; i < n_in ;i++)
+             if(in_stat & (1<<i))
+                  outgoing_input (i);
+           
+        end
+      
+      for(i = 0; i < n_out ;i++)
+        begin
+           if ( slots_out[i].size() )
+             begin
+                incoming_send(i, slots_out[i][$].data);
+                slots_out[i].pop_back();
+             end
+        end
+      
+      
+      
+      
+   endtask // update
+   
+
+      
+   
+endclass
+
+  
+
--- a/hdl/testbench/include/vhd_wishbone_master.svh
+++ b/hdl/testbench/include/vhd_wishbone_master.svh
+`include "simdrv_defs.svh"
+`include "if_wb_master.svh"
+
+interface IVHDWishboneMaster
+  (
+   input clk_i,
+   input rst_n_i
+   );
+
+   parameter g_addr_width 	   = 32;
+   parameter g_data_width 	   = 32;
+
+   typedef virtual IWishboneMaster VIWishboneMaster;
+   
+   IWishboneMaster #(g_addr_width, g_data_width) TheMaster (clk_i, rst_n_i);
+
+   t_wishbone_master_in in;
+   t_wishbone_master_out out;
+
+   modport master
+     (
+      input  in,
+      output out
+      );
+   
+   assign out.cyc = TheMaster.cyc;
+   assign out.stb = TheMaster.stb;
+   assign out.we = TheMaster.we;
+   assign out.sel = TheMaster.sel;
+   assign out.adr = TheMaster.adr;
+   assign out.dat = TheMaster.dat_o;
+   
+   assign TheMaster.ack = in.ack;
+   assign TheMaster.stall = in.stall;
+   assign TheMaster.rty = in.rty;
+   assign TheMaster.err = in.err;
+   assign TheMaster.dat_i = in.dat;
+
+   
+   function CBusAccessor get_accessor();
+      return TheMaster.get_accessor();
+   endfunction // get_accessor
+
+   initial begin
+      CWishboneAccessor acc;
+      
+      @(posedge rst_n_i);
+      @(posedge clk_i);
+
+      TheMaster.settings.addr_gran = BYTE;
+      TheMaster.settings.cyc_on_stall = 1;
+      
+      acc = TheMaster.get_accessor();
+      acc.set_mode( PIPELINED );
+      
+   end
+   
+      
+endinterface // IVHDWishboneMaster
--- a/hdl/testbench/include/vme64x_bfm/components/sn74vmeh22501.v
+++ b/hdl/testbench/include/vme64x_bfm/components/sn74vmeh22501.v
+`timescale 1ns/1ns 
+
+module sn74vmeh22501 (
+    input   oeab1,
+            oeby1_n,
+            a1,
+    output  y1,
+    inout   b1,
+
+    input   oeab2,
+            oeby2_n,
+            a2,
+    output  y2,
+    inout   b2,
+
+    input   oe_n,
+    input   dir,    
+            clkab,
+            le,
+            clkba,
+    inout   [1:8] a3,
+    inout   [1:8] b3);
+
+assign b1   = oeab1   ? a1      : 1'bz;
+assign y1   = oeby1_n ? 1'bz    : b1;
+
+assign b2   = oeab2   ? a2      : 1'bz;
+assign y2   = oeby2_n ? 1'bz    : b2;
+
+reg [1:8] b3LFF;
+always @(posedge clkab) if (~le) b3LFF <= #1 a3;
+always @* if (le) b3LFF = a3;
+assign b3   = (~oe_n && dir) ? b3LFF : 8'hz;
+
+reg [1:8] a3LFF;
+always @(posedge clkba) if (~le) a3LFF <= #1 b3;
+always @* if (le) a3LFF = b3;
+assign a3   = (~oe_n && ~dir) ? a3LFF : 8'hz;
+
+endmodule
+
--- a/hdl/testbench/include/vme64x_bfm/svec_vme_buffers.svh
+++ b/hdl/testbench/include/vme64x_bfm/svec_vme_buffers.svh
+`include "components/sn74vmeh22501.v"
+
+`include "vme64x_bfm.svh"
+
+module bidir_buf(
+    a,
+    b,
+    dir, /* 0: a->b, 1: b->a */
+    oe_n );
+
+   parameter g_width = 1;
+   
+   inout [g_width-1:0] a,b;
+   input               dir, oe_n;
+   
+   assign b = (!dir && !oe_n) ? a : 'bz;
+   assign a = (dir && !oe_n) ? b : 'bz;
+endmodule // bidir_buf
+
+
+
+
+module svec_vme_buffers (
+    output       VME_AS_n_o,
+    output       VME_RST_n_o,
+    output       VME_WRITE_n_o,
+    output [5:0] VME_AM_o,
+    output [1:0] VME_DS_n_o,
+    output [5:0] VME_GA_o,
+    input        VME_BERR_i,
+    input        VME_DTACK_n_i,
+    input        VME_RETRY_n_i,
+    input        VME_RETRY_OE_i,
+    inout        VME_LWORD_n_b,
+    inout [31:1] VME_ADDR_b,
+    inout [31:0] VME_DATA_b,
+    output       VME_BBSY_n_o,
+    input [6:0]  VME_IRQ_n_i,
+    output       VME_IACKIN_n_o,
+    input        VME_IACKOUT_n_i,
+    output        VME_IACK_n_o,
+    input        VME_DTACK_OE_i,
+    input        VME_DATA_DIR_i,
+    input        VME_DATA_OE_N_i,
+    input        VME_ADDR_DIR_i,
+    input        VME_ADDR_OE_N_i,
+                 
+    IVME64X.slave slave
+    );
+
+   pullup(slave.as_n);
+   pullup(slave.rst_n);
+   pullup(slave.irq_n[0]);
+   pullup(slave.irq_n[1]);
+   pullup(slave.irq_n[2]);
+   pullup(slave.irq_n[3]);
+   pullup(slave.irq_n[4]);
+   pullup(slave.irq_n[5]);
+   pullup(slave.irq_n[6]);
+   pullup(slave.iack_n);
+   pullup(slave.dtack_n);
+   pullup(slave.retry_n);
+   pullup(slave.ds_n[1]);
+   pullup(slave.ds_n[0]);
+   pullup(slave.lword_n);
+   pullup(slave.berr_n);
+   pullup(slave.write_n);
+   pulldown(slave.bbsy_n);
+   pullup(slave.iackin_n);
+   pullup(slave.iackout_n);
+
+   
+   genvar        i;
+   generate
+      for(i=0;i<6;i++)
+        assign slave.irq_n[i] = (VME_IRQ_n_i[i] ? 1'b0 : 1'bz);
+   endgenerate
+   
+   
+          
+   
+   assign VME_RST_n_o = slave.rst_n;
+   
+   assign VME_AS_n_o     = slave.as_n;
+   assign VME_GA_o     = slave.ga;
+   assign VME_WRITE_n_o  = slave.write_n;
+   assign VME_AM_o = slave.am;
+   assign VME_DS_n_o = slave.ds_n;
+   assign VME_BBSY_n_o = slave.bbsy_n;
+   assign VME_IACKIN_n_o = slave.iackin_n;
+   assign VME_IACK_n_o = slave.iack_n;
+
+   bidir_buf #(1)  b0 (slave.lword_n, VME_LWORD_n_b, VME_ADDR_DIR_i, VME_ADDR_OE_N_i);
+   bidir_buf #(31) b1 (slave.addr, VME_ADDR_b, VME_ADDR_DIR_i, VME_ADDR_OE_N_i);
+   bidir_buf #(33) b2 (slave.data, VME_DATA_b, VME_DATA_DIR_i, VME_DATA_OE_N_i);
+
+   pulldown(VME_BERR_i);
+   pulldown(VME_ADDR_DIR_i);
+   pulldown(VME_ADDR_OE_N_i);
+   pulldown(VME_DATA_DIR_i);
+   pulldown(VME_DATA_OE_N_i);
+   
+   
+   assign slave.dtack_n = VME_DTACK_n_i;
+   assign slave.berr_n = ~VME_BERR_i;
+   assign slave.retry_n = VME_RETRY_n_i;
+   assign slave.iackout_n = VME_IACKOUT_n_i;
+   
+endmodule
+
+
+`define DECLARE_VME_BUFFERS(iface) \
+    wire VME_AS_n;\
+    wire VME_RST_n;\
+    wire VME_WRITE_n;\
+    wire [5:0] VME_AM;\
+    wire [1:0] VME_DS_n;\
+    wire VME_BERR;\
+    wire VME_DTACK_n;\
+    wire VME_RETRY_n;\
+    wire VME_RETRY_OE;\
+    wire VME_LWORD_n;\
+    wire [31:1]VME_ADDR;\
+    wire [31:0]VME_DATA;\
+    wire VME_BBSY_n;\
+    wire [6:0]VME_IRQ_n;\
+    wire VME_IACKIN_n,VME_IACK_n;\
+    wire VME_IACKOUT_n;\
+    wire VME_DTACK_OE;\
+    wire VME_DATA_DIR;\
+    wire VME_DATA_OE_N;\
+    wire VME_ADDR_DIR;\
+    wire VME_ADDR_OE_N;\
+    svec_vme_buffers U_VME_Bufs ( \
+    .VME_AS_n_o(VME_AS_n),\
+    .VME_RST_n_o(VME_RST_n),\
+    .VME_WRITE_n_o(VME_WRITE_n),\
+    .VME_AM_o(VME_AM),\
+    .VME_DS_n_o(VME_DS_n),\
+    .VME_BERR_i(VME_BERR),\
+    .VME_DTACK_n_i(VME_DTACK_n),\
+    .VME_RETRY_n_i(VME_RETRY_n),\
+    .VME_RETRY_OE_i(VME_RETRY_OE),\
+    .VME_LWORD_n_b(VME_LWORD_n),\
+    .VME_ADDR_b(VME_ADDR),\
+    .VME_DATA_b(VME_DATA),\
+    .VME_BBSY_n_o(VME_BBSY_n),\
+    .VME_IRQ_n_i(VME_IRQ_n),\
+    .VME_IACK_n_o(VME_IACK_n),\
+    .VME_IACKIN_n_o(VME_IACKIN_n),\
+    .VME_IACKOUT_n_i(VME_IACKOUT_n),\
+    .VME_DTACK_OE_i(VME_DTACK_OE),\
+    .VME_DATA_DIR_i(VME_DATA_DIR),\
+    .VME_DATA_OE_N_i(VME_DATA_OE_N),\
+    .VME_ADDR_DIR_i(VME_ADDR_DIR),\
+    .VME_ADDR_OE_N_i(VME_ADDR_OE_N),\
+    .slave(iface)\
+    );
+
+function automatic bit[5:0] _gen_ga(int slot);
+     bit[4:0] slot_id = slot;
+     return {^slot_id, ~slot_id};
+endfunction // _gen_ga
+
+   
+		
+`define WIRE_VME_PINS(slot_id) \
+    .VME_AS_n_i(VME_AS_n),\
+    .VME_RST_n_i(VME_RST_n),\
+    .VME_WRITE_n_i(VME_WRITE_n),\
+    .VME_AM_i(VME_AM),\
+    .VME_DS_n_i(VME_DS_n),\
+    .VME_GA_i(_gen_ga(slot_id)),\
+    .VME_BERR_o(VME_BERR),\
+    .VME_DTACK_n_o(VME_DTACK_n),\
+    .VME_RETRY_n_o(VME_RETRY_n),\
+    .VME_RETRY_OE_o(VME_RETRY_OE),\
+    .VME_LWORD_n_b(VME_LWORD_n),\
+    .VME_ADDR_b(VME_ADDR),\
+    .VME_DATA_b(VME_DATA),\
+    .VME_BBSY_n_i(VME_BBSY_n),\
+    .VME_IRQ_n_o(VME_IRQ_n),\
+    .VME_IACK_n_i(VME_IACK_n),\
+    .VME_IACKIN_n_i(VME_IACKIN_n),\
+    .VME_IACKOUT_n_o(VME_IACKOUT_n),\
+    .VME_DTACK_OE_o(VME_DTACK_OE),\
+    .VME_DATA_DIR_o(VME_DATA_DIR),\
+    .VME_DATA_OE_N_o(VME_DATA_OE_N),\
+    .VME_ADDR_DIR_o(VME_ADDR_DIR),\
+    .VME_ADDR_OE_N_o(VME_ADDR_OE_N)
+
+
+		
\ No newline at end of file
--- a/hdl/testbench/include/vme64x_bfm/vme64x_bfm.svh
+++ b/hdl/testbench/include/vme64x_bfm/vme64x_bfm.svh
+`ifndef __VME64X_BFM_SVH
+ `define __VME64X_BFM_SVH 1
+
+`timescale 1ns/1ps
+
+`include "simdrv_defs.svh"
+
+`define assert_wait(name, condition, timeout) \
+begin\
+   time t=$time;\
+   while(!(condition)) begin\
+      #1ns;\
+      if($time - t > timeout) begin\
+         $display("Wait timeout : ", `"name`"); \
+        //   $stop;\
+           break;\
+             end\
+      end\
+end
+
+
+
+
+
+interface IVME64X ( input sys_rst_n_i );
+
+   wire as_n;
+   wire rst_n;
+   wire write_n;
+   wire [5:0] am;
+   wire [1:0] ds_n;
+   wire [5:0] ga;
+   wire berr_n, dtack_n;
+   wire retry_n;
+   wire lword_n;
+   wire [31:1] addr;
+   wire [31:0] data;
+   wire bbsy_n;
+   wire [6:0]  irq_n;
+   wire iackin_n, iackout_n, iack_n;
+
+   logic q_as_n = 1'bz;
+   logic q_rst_n = 1'bz;
+   logic q_write_n = 1'bz;
+   logic [5:0] q_am = 6'bz;
+   logic [1:0] q_ds_n = 2'bz;
+   logic [5:0] q_ga = 6'bz;
+   logic q_berr_n = 1'bz, q_dtack_n = 1'bz;
+   logic q_retry_n = 1'bz;
+   logic q_lword_n = 1'bz;
+   logic [31:1] q_addr = 31'bz;
+   logic [31:0] q_data = 32'bz;
+   logic q_bbsy_n = 1'bz;
+   logic [6:0] q_irq_n = 7'bz;
+   logic q_iackin_n = 1'bz, q_iackout_n = 1'bz, q_iack_n = 1'bz;
+
+
+   /* SystemVerilog does not allow pullups inside interfaces or on logic type */
+   
+   assign as_n = q_as_n;
+   assign rst_n = q_rst_n;
+   assign write_n = q_write_n;
+   assign am = q_am;
+   assign ds_n = q_ds_n;
+   assign ga = q_ga;
+   assign berr_n = q_berr_n;
+   assign dtack_n = q_dtack_n;
+   assign retry_n = q_retry_n;
+   assign lword_n = q_lword_n;
+   assign addr = q_addr;
+   assign data = q_data;
+   assign bbsy_n = q_bbsy_n;
+   assign irq_n = q_irq_n;
+   assign iackin_n = q_iackin_n;
+   assign iackout_n = q_iackout_n;
+   assign iack_n = q_iack_n;
+   
+ //  VME Master
+   modport tb
+     (
+      output as_n, 
+      output rst_n, 
+      output write_n, 
+      output am, 
+      output ds_n, 
+      output ga, 
+      output bbsy_n,
+      output iackin_n,
+      output iack_n,
+      input  berr_n, 
+      input  irq_n, 
+      input  iackout_n,
+      inout  addr,
+      inout  data, 
+      inout  lword_n, 
+      inout  retry_n, 
+      inout  dtack_n,
+
+      input q_as_n, 
+      input q_rst_n, 
+      input q_write_n, 
+      input q_am, 
+      input q_ds_n, 
+      input q_ga, 
+      input q_bbsy_n,
+      input q_iackin_n,
+      input q_iack_n,
+      input  q_berr_n, 
+      input  q_irq_n, 
+      input  q_iackout_n,
+      input  q_addr,
+      input  q_data, 
+      input  q_lword_n, 
+      input  q_retry_n, 
+      input  q_dtack_n
+      );
+
+    modport master
+     (
+      output as_n, 
+      output rst_n, 
+      output write_n, 
+      output am, 
+      output ds_n, 
+      output ga, 
+      output bbsy_n,
+      output iackin_n,
+      output iack_n,
+      input  berr_n, 
+      input  irq_n, 
+      input  iackout_n,
+      inout  addr,
+      inout  data, 
+      inout  lword_n, 
+      inout  retry_n, 
+      inout  dtack_n);
+   
+   
+   //  VME Slave
+   modport slave
+     (
+      input  as_n, 
+      input  rst_n, 
+      input  write_n, 
+      input  am, 
+      input  ds_n, 
+      input  ga, 
+      input  bbsy_n, 
+      input  iackin_n,
+      input iack_n,
+      output berr_n, 
+      output irq_n, 
+      output iackout_n,
+      inout  addr, 
+      inout  data, 
+      inout  lword_n, 
+      inout  retry_n, 
+      inout  dtack_n
+      );
+
+   initial forever begin
+      @(posedge sys_rst_n_i);
+      #100ns;
+      q_rst_n = 0;
+      #100ns;
+      q_rst_n = 1;
+   end
+   
+   
+
+endinterface // IVME64x
+
+
+
+const uint64_t CSR_BAR             = 'h7FFFF;
+const uint64_t CSR_BIT_SET_REG     = 'h7FFFB;
+const uint64_t CSR_BIT_CLR_REG     = 'h7FFF7;
+const uint64_t CSR_CRAM_OWNER      = 'h7FFF3;
+const uint64_t CSR_USR_BIT_SET_REG = 'h7FFEF;
+const uint64_t CSR_USR_BIT_CLR_REG = 'h7FFEB;
+
+typedef enum { DONT_CARE = 'h100, 
+               A16       = 'h200, 
+               A24       = 'h300, 
+               A32       = 'h400, 
+               A64       = 'h500 
+               } vme_addr_size_t;
+
+typedef enum { 
+               SINGLE = 'h10, CR_CSR='h20, MBLT='h30, BLT='h40, LCK='h50, TwoeVME='h60, TwoeSST='h70, IACK = 'h80 } vme_xfer_type_t;
+
+typedef enum { D08Byte0='h1, D08Byte1='h2, D08Byte2='h3, D08Byte3='h4, D16Byte01='h5, D16Byte23='h6, D32='h7 } vme_data_type_t ;
+   
+class CBusAccessor_VME64x extends CBusAccessor;
+
+   const bit [3:0] dt_map [vme_data_type_t] =
+                   '{
+                     D08Byte0  : 4'b0101,	
+                     D08Byte1  : 4'b1001,
+                     D08Byte2  : 4'b0111,	
+                     D08Byte3  : 4'b1011,
+                     D16Byte01 : 4'b0001,
+                     D16Byte23 : 4'b0011,
+                     D32       : 4'b0000};
+   
+   protected bit [7:0] m_ba;
+   protected bit [4:0] m_ga;
+   virtual             IVME64X.tb vme;
+
+
+   
+   function new(virtual IVME64X.tb _vme);
+      vme = _vme;
+      m_ga = 6'b010111;
+      vme.q_ga = m_ga;
+   endfunction // new
+
+
+
+   protected task acknowledge_irq(int level, ref int vector);
+      `assert_wait(tmo_rws_bus_free, vme.dtack_n && vme.berr_n, 10us)
+      release_bus();
+      #40ns;
+
+      vme.q_addr[3:1] = level;
+      vme.q_iackin_n = 1'b0;
+      vme.q_iack_n = 1'b0;
+      vme.q_am = 'h29;
+      #100ns;
+      
+      vme.q_as_n = 1'b0;
+      #100ns;
+      vme.q_ds_n[0] = 1'b0;
+      
+      `assert_wait(tmo_rws_bus_idle, !vme.dtack_n || !vme.berr_n, 4us)
+      if(!vme.berr_n)
+        $error("[rw_simple_generic]: VME bus error.");
+
+      vector = vme.data;
+      
+      vme.q_iackin_n = 1'b1;
+      vme.q_iack_n = 1'b1;
+      #100ns;
+      release_bus();
+   endtask
+   
+
+   protected task set_address(uint64_t addr_in, vme_addr_size_t asize, vme_xfer_type_t xtype);
+      bit[63:0] a = addr_in;
+      bit [31:0] a_out;
+
+     const bit [5:0] am_map [int] = 
+                      '{
+                        A32 | CR_CSR : 6'b101111,
+                        A24 | CR_CSR : 6'b101111,
+                        A16 | SINGLE: 6'b101001,
+                        A16 | LCK : 6'b101100,
+                        A24 | SINGLE: 6'b111001,
+                        A24 | BLT : 6'b111011,
+                        A24 | MBLT : 6'b111000,
+                        A24 | LCK : 6'b110010,
+                        A32 | SINGLE: 6'b001001,
+                        A32 | BLT : 6'b001011,
+                        A32 | MBLT : 6'b001000,
+                        A32 | LCK : 6'b000101,
+                        A64 | SINGLE: 6'b000001,
+                        A64 | BLT : 6'b000011,
+                        A64 | MBLT : 6'b000000,
+                        A64 | LCK : 6'b001000,
+                        A32 | TwoeVME : 6'b100000,
+                        A64 | TwoeVME : 6'b100000,
+                        A32 | TwoeSST : 6'b100000,
+                        A64 | TwoeSST : 6'b100000};
+
+      vme.q_am = am_map[asize|xtype];
+
+      
+      if(xtype == CR_CSR)
+        a_out = {8'h0, ~m_ga[4:0], a[18:0]};
+      else case(asize)
+        A16: 
+                   a_out = {16'h0, a[15:2], 2'b00};
+        A24: 
+          a_out = {8'h0, a[23:2], 2'b00};
+        A32:
+          a_out = { a[31:2], 2'b00};
+      endcase // case (xtype)
+
+      vme.q_addr[31:2] = a_out[31:2];
+      
+   endtask // set_address
+
+   
+   protected task release_bus();
+      vme.q_as_n = 1'bz;
+      vme.q_write_n = 1'bz;
+      vme.q_ds_n = 2'bzz;
+      vme.q_lword_n = 1'bz;
+      vme.q_addr = 0;
+      vme.q_data = 32'bz;
+   endtask // release_bus
+   
+
+/* Simple generic VME read/write: single, BLT and CSR xfers */
+   protected task rw_generic(bit write, uint64_t _addr, ref uint64_t _data[], input vme_addr_size_t asize, input vme_xfer_type_t xtype, vme_data_type_t dtype);
+      bit[3:0] dt;
+      int      i;
+      
+      `assert_wait(tmo_rws_bus_free, vme.dtack_n && vme.berr_n, 10us)
+      release_bus();
+      #40ns;
+
+      set_address(_addr, asize, xtype);
+      dt = dt_map[dtype];
+
+      vme.q_lword_n = dt[0];
+      vme.q_addr[1] = dt[1];
+      vme.q_write_n = !write;
+      
+      #100ns;
+      
+      vme.q_as_n = 0;
+      #40ns;
+
+//      $display("RWG %x\n", _data.size());
+      
+      
+      for(i=0;i<_data.size();i++)
+        begin
+           
+           if(write)
+             vme.q_data = (dtype == D08Byte0 || dtype == D08Byte2) ? (_data[i] << 8) : (_data[i]);
+
+           #100ns;
+           vme.q_ds_n = dt[3:2]; 
+
+           `assert_wait(tmo_rws_bus_idle, !vme.dtack_n || !vme.berr_n, 4us)
+           if(!vme.berr_n)
+             $error("[rw_simple_generic]: VME bus error.");
+
+           if(!write)
+             _data[i] = (dtype == D08Byte0 || dtype == D08Byte2) ? (vme.data >> 8) : (vme.data);
+           #40ns;
+           
+           end // for (i=0;i<_data.size();i++)
+      
+      release_bus();
+   endtask // rw_generic
+
+   protected task extract_xtype(int s, ref vme_xfer_type_t xtype, vme_addr_size_t asize, vme_data_type_t dtype);
+      xtype = vme_xfer_type_t'( s & 'h0f0);
+      asize = vme_addr_size_t'( s & 'hf00);
+      dtype = vme_data_type_t'( s & 'h00f);
+   endtask // extract_xtype
+
+   protected int m_default_modifiers = A32 | SINGLE | D32;
+   
+   
+   task set_default_modifiers(int mods);
+      m_default_modifiers = mods;
+   endtask // set_default_modifiers
+   
+   
+   task writem(uint64_t addr[], uint64_t data[], input int size = m_default_modifiers, ref int result);
+      int    i;
+      vme_addr_size_t asize;
+      vme_data_type_t dtype;
+      vme_xfer_type_t xtype;
+      
+      extract_xtype(size, xtype, asize, dtype);
+      if(xtype == SINGLE || xtype == CR_CSR)
+        for(i=0;i<addr.size();i++)
+          begin
+             uint64_t tmp[];
+             tmp = new[1];
+             tmp[0] = data[i];
+             rw_generic(1, addr[i], tmp, asize, xtype, dtype);
+          end
+      else if (xtype == BLT)
+           rw_generic(1, addr[0], data, asize, xtype, dtype);
+      
+   endtask // writem
+   
+   task readm(uint64_t addr[], ref uint64_t data[], input int size = m_default_modifiers, ref int result);
+      int    i;
+
+      vme_addr_size_t asize;
+      vme_data_type_t dtype;
+      vme_xfer_type_t xtype;
+      
+      extract_xtype(size, xtype, asize, dtype);
+      if(xtype == SINGLE || xtype == CR_CSR)
+        for(i=0;i<addr.size();i++)
+          begin
+             uint64_t tmp[];
+             tmp=new[1];
+             
+             rw_generic(0, addr[i], tmp, asize, xtype, dtype);
+             data[i] = tmp[0];
+          end
+
+   endtask // readm
+
+   task read(uint64_t addr, ref uint64_t data, input int size = m_default_modifiers, ref int result = _null);
+      int res;
+      uint64_t aa[1], da[];
+
+      //$display("AM=%x", size);
+      
+      
+      da= new[1];
+      
+      aa[0]  = addr;
+      readm(aa, da, size, res);
+      data  = da[0];
+   endtask
+
+   task write(uint64_t addr, uint64_t data, input int size = m_default_modifiers, ref int result = _null);
+      uint64_t aa[], da[];
+      aa=new[1];
+      da=new[1];
+
+//      $display("VMEWrite s %x", size);
+      
+      
+      aa[0]  = addr;
+      da[0]  = data;
+
+      
+      writem(aa, da, size, result);
+   endtask
+
+   task handle_irqs(ref int done);
+      done = 0;
+      
+      if(vme.irq_n != 7'h7f) 
+        begin
+           int i,level, vector;
+           for(i=6;i>=0;i--)
+             if(!vme.irq_n[i])
+               begin
+                  level = i+1;
+                  break;
+               end
+           $display("vme64x_bfm: got irq level %d", level);
+           
+           acknowledge_irq(level, vector);
+           $display("vme64x_bfm: vector %x", vector);
+           done = 1;
+           
+        end
+   endtask // handle_irqs
+   
+
+      
+  
+endclass // CBusAccessor_VME64x
+
+  
+
+
+   
+`endif //  `ifndef __VME64X_BFM_SVH
--- a/hdl/testbench/svec/Manifest.py
+++ b/hdl/testbench/svec/Manifest.py
 action = "simulation"
 target = "xilinx"
 fetchto = "../../ip_cores"
-vlog_opt="+incdir+../../sim/wb +incdir+../../sim/vme64x_bfm +incdir+../../sim"
+vlog_opt="+incdir+../../sim +incdir+../include/vme64x_bfm +incdir+../include "

 files = [ "main.sv" ]

-modules = { "local" :  [ "../../top/svec" ] }
+modules = { "local" :  [ "../../top/svec/with_wrabbit" ] }

--- a/hdl/testbench/svec/main.sv
+++ b/hdl/testbench/svec/main.sv
+`include "simdrv_defs.svh"
 `include "vme64x_bfm.svh"
 `include "svec_vme_buffers.svh"

 module main;

   reg rst_n = 0;
-   reg clk_125m = 0, clk_20m = 0, acam_refclk = 0;
+   reg clk_125m = 0, clk_20m = 0;

   always #4ns clk_125m <= ~clk_125m;
-   always #16ns acam_refclk <= ~acam_refclk;
   always #25ns clk_20m <= ~clk_20m;
-
-   
   
   initial begin
      repeat(20) @(posedge clk_125m);
      rst_n = 1;
   end
-   
+
   IVME64X VME(rst_n);

   `DECLARE_VME_BUFFERS(VME.slave);

-   reg acam_ef =1;
-   wire acam_rd;
+   reg tdc_ef1 = 1;
+   reg tdc_pulse = 0;
+   wire tdc_rd_n;
+
+
+   always@(posedge tdc_pulse) begin
+      #100ns;
+      tdc_ef1 <= 0;
+      while(tdc_rd_n != 0)
+	#1ns;
+      #10ns;
+      tdc_ef1 <= 1;
+   end
+
+   reg clk_acam = 0;
+   reg clk_62m5 = 0;
   
+
+   always@(posedge clk_125m)
+     clk_62m5 <= ~clk_62m5;
+
+   always@(posedge clk_62m5)
+     clk_acam <= ~clk_acam;
   
-   top_tdc #(
-              .values_for_simul(1)
+   
+   wr_svec_tdc #(
+              .g_with_wr_phy(0),	
+              .g_simulation(1)
              ) DUT (
+		     .clk_125m_pllref_p_i(clk_125m),
+		     .clk_125m_pllref_n_i(~clk_125m),
+		     .clk_125m_gtp_p_i(clk_125m),
+		     .clk_125m_gtp_n_i(~clk_125m),
+
+
+		     .tdc1_125m_clk_p_i(clk_125m),
+		     .tdc1_125m_clk_n_i(~clk_125m),
+
+		     .tdc1_acam_refclk_p_i(clk_acam),
+		     .tdc1_acam_refclk_n_i(~clk_acam),
+
 		     .clk_20m_vcxo_i(clk_20m),
-                     .por_n_i (rst_n),
-                     
-                     .ft0_tdc_125m_clk_p_i(clk_125m),
-                     .ft0_tdc_125m_clk_n_i(~clk_125m),
-                     .ft0_acam_refclk_p_i(acam_refclk),
-                     .ft0_acam_refclk_n_i(~acam_refclk),
-                     .ft0_pll_status_i(1'b1),
-                     .ft0_rd_n_o(acam_rd),
-                     .ft0_ef1_i(acam_ef),
-                     .ft0_ef2_i(1'b1),
-                     
-                     .ft1_tdc_125m_clk_p_i(clk_125m),
-                     .ft1_tdc_125m_clk_n_i(~clk_125m),
-                     .ft1_pll_status_i(1'b1),
+                     .tdc1_pll_status_i(1'b1),
+		     .por_n_i(rst_n),
+
+		     .tdc1_ef1_i(tdc_ef1),
+		     .tdc1_ef2_i(1'b1),
+		     .tdc1_err_flag_i(1'b0),
+		     .tdc1_int_flag_i(1'b0),
+		     .tdc1_rd_n_o(tdc_rd_n),
+		     .tdc1_in_fpga_1_i(tdc_pulse),
+		     .tdc1_in_fpga_2_i(1'b0),
+		     .tdc1_in_fpga_3_i(1'b0),
+		     .tdc1_in_fpga_4_i(1'b0),
+		     .tdc1_in_fpga_5_i(1'b0),
+		     .tdc1_data_bus_io(28'hcafebab),
 		     
+
 		     `WIRE_VME_PINS(8)
-	         );
+		     );
+   

-   initial begin
-      #500us;
-      forever begin
-      acam_ef = 0;
-      wait(!acam_rd);
-      #10ns;
-      acam_ef = 1;
-      #50us;
-         
-      end
-   end
+   
+   
   

+  task automatic config_vme_function(ref CBusAccessor_VME64x acc, input int func, uint64_t base, int am);
+      uint64_t addr = 'h7ff63 + func * 'h10;
+      uint64_t val = (base) | (am << 2);
+
+      $display("Func%d ADER=0x%x", func, val);
+
+     if(am == 0)
+       val = 1;
+      
+      acc.write(addr + 0, (val >> 24) & 'hff, CR_CSR|A32|D08Byte3);
+      acc.write(addr + 4, (val >> 16) & 'hff, CR_CSR|A32|D08Byte3);
+      acc.write(addr + 8, (val >> 8)  & 'hff, CR_CSR|A32|D08Byte3);
+      acc.write(addr + 12, (val >> 0) & 'hff, CR_CSR|A32|D08Byte3);
+ 
+      
+   endtask // config_vme_function
+   
+   
   task automatic init_vme64x_core(ref CBusAccessor_VME64x acc);
+      uint64_t rv;
+
+
      /* map func0 to 0x80000000, A32 */
-      acc.write('h7ff63, 'h80, A32|CR_CSR|D08Byte3);
-      acc.write('h7ff67, 0, CR_CSR|A32|D08Byte3);
-      acc.write('h7ff6b, 0, CR_CSR|A32|D08Byte3);
-      acc.write('h7ff6f, 36, CR_CSR|A32|D08Byte3);
+//      config_vme_function(acc, 0, 'h80000000, 'h09);
+      /* map func1 to 0xc00000, A24 */
+      config_vme_function(acc, 1, 'hc00000, 'h39);
+      config_vme_function(acc, 0, 0, 0);
+
      acc.write('h7ff33, 1, CR_CSR|A32|D08Byte3);
      acc.write('h7fffb, 'h10, CR_CSR|A32|D08Byte3); /* enable module (BIT_SET = 0x10) */

+      acc.set_default_modifiers(A24 | D32 | SINGLE);
   endtask // init_vme64x_core
   
+
+   reg force_irq = 0;
+   
   initial begin
      CBusAccessor_VME64x acc = new(VME.master);
      CBusAccessor acc_casted = CBusAccessor'(acc);
-      uint64_t d;

-      #30us;
+      uint64_t d;
+      const uint64_t tdc1_base = 'h30000;
+      
+      #100us;

      init_vme64x_core(acc);
-      acc_casted.set_default_xfer_size(A32|SINGLE|D32);
+      acc_casted.set_default_xfer_size(A24|SINGLE|D32);
+ 
+      #15us;
+
+
+      $display("Un-reset FMCs...");
      
-      acc.read('h80000000, d, D32|A32|SINGLE);
-      $display("Master SDB 0 = %x. Un-resetting TDC cores.", d);
+      acc.write('hc2000c, 'h3); 

-      acc.write('h80020008, 'hff , D32|A32|SINGLE);
+      #500us;
+      
+      acc.read('hc40000, d); 
+      $display("TDC SDB ID : %x", d);

-      // wait for the PLLs to settle up
-      #300us;

+      acc.write('hc510a0, 1234);  // set UTC
+      acc.write('hc510fc, 1<<9); // load UTC

-      acc.read('h80040000, d, D32|A32|SINGLE);
-      $display("SDB core 0 = %x", d);
-      acc.read('h80060000, d, D32|A32|SINGLE);
-      $display("SDB core 1 = %x", d);
+      acc.write('hc52004, 'hf); // enable EIC irq

-      acc.write('h800500fc, 1, D32|A32|SINGLE); // init acquisition
-   
-      forever begin
-         acc.read('h800500a8, d, D32|A32|SINGLE); // init acquisition
-         $display("wr-ptr %x", d);
-         #10us;
+      acc.write('hc51084, 'h1f); // enable all ACAM inputs
+      acc.write('hc510fc, (1<<0)); // start acquisition
+      
         
+      #300us;
+      forever begin
+	 tdc_pulse <= 1;
+	 #1000ns;
+	 tdc_pulse <= 0;
+	 #10ns;
      end
      
-   end // initial begin
+     
+      
+     
+   end
+ 
   

  

--- a/hdl/testbench/svec/run.do
+++ b/hdl/testbench/svec/run.do
-vlog -sv main.sv +incdir+. +incdir+../../sim/wb +incdir+../../sim/vme64x_bfm +incdir+../../sim
-vsim work.main -voptargs=+acc
+vlog -sv main.sv +incdir+../../sim +incdir+../include/vme64x_bfm +incdir+../include
+vsim -L unisim work.main -voptargs=+acc

 set StdArithNoWarnings 1
 set NumericStdNoWarnings 1

 do wave.do
 radix -hexadecimal
-run 100us
\ No newline at end of file
+run 1ms
\ No newline at end of file
--- a/hdl/testbench/svec/wave.do
+++ b/hdl/testbench/svec/wave.do
 onerror {resume}
 quietly WaveActivateNextPane {} 0
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/clk_i
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/rst_i
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/tdc_config_wb_adr_i
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/tdc_config_wb_cyc_i
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/tdc_config_wb_dat_i
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/tdc_config_wb_stb_i
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/tdc_config_wb_we_i
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_config_rdbk_i
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_status_i
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_ififo1_i
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_ififo2_i
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_start01_i
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/wr_index_i
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/local_utc_i
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/core_status_i
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/irq_code_i
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/tdc_config_wb_ack_o
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/tdc_config_wb_dat_o
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_config_o
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/activate_acq_p_o
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/deactivate_acq_p_o
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_wr_config_p_o
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_rdbk_config_p_o
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_rst_p_o
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_rdbk_status_p_o
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_rdbk_ififo1_p_o
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_rdbk_ififo2_p_o
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_rdbk_start01_p_o
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/dacapo_c_rst_p_o
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/send_dac_word_p_o
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/dac_word_o
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/load_utc_p_o
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/starting_utc_o
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/irq_tstamp_threshold_o
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/irq_time_threshold_o
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/one_hz_phase_o
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_inputs_en_o
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/start_phase_o
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_config
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/reg_adr
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/reg_adr_pipe0
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/starting_utc
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/acam_inputs_en
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/start_phase
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/ctrl_reg
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/one_hz_phase
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/irq_tstamp_threshold
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/irq_time_threshold
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/clear_ctrl_reg
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/send_dac_word_p
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/dac_word
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/pulse_extender_en
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/pulse_extender_c
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/dat_out
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/dat_out_pipe0
-add wave -noupdate /main/DUT/cmp_tdc_board0/tdc_core/reg_control_block/tdc_config_wb_ack_o_pipe0
+add wave -noupdate -expand -group VME /main/VME/sys_rst_n_i
+add wave -noupdate -expand -group VME /main/VME/as_n
+add wave -noupdate -expand -group VME /main/VME/rst_n
+add wave -noupdate -expand -group VME /main/VME/write_n
+add wave -noupdate -expand -group VME /main/VME/am
+add wave -noupdate -expand -group VME /main/VME/ds_n
+add wave -noupdate -expand -group VME /main/VME/ga
+add wave -noupdate -expand -group VME /main/VME/berr_n
+add wave -noupdate -expand -group VME /main/VME/dtack_n
+add wave -noupdate -expand -group VME /main/VME/retry_n
+add wave -noupdate -expand -group VME /main/VME/lword_n
+add wave -noupdate -expand -group VME /main/VME/addr
+add wave -noupdate -expand -group VME /main/VME/data
+add wave -noupdate -expand -group VME /main/VME/bbsy_n
+add wave -noupdate -expand -group VME /main/VME/irq_n
+add wave -noupdate -expand -group VME /main/VME/iackin_n
+add wave -noupdate -expand -group VME /main/VME/iackout_n
+add wave -noupdate -expand -group VME /main/VME/iack_n
+add wave -noupdate -group Top /main/DUT/por_n_i
+add wave -noupdate -group Top /main/DUT/clk_20m_vcxo_i
+add wave -noupdate -group Top /main/DUT/clk_125m_pllref_p_i
+add wave -noupdate -group Top /main/DUT/clk_125m_pllref_n_i
+add wave -noupdate -group Top /main/DUT/clk_125m_gtp_p_i
+add wave -noupdate -group Top /main/DUT/clk_125m_gtp_n_i
+add wave -noupdate -group Top /main/DUT/sfp_txp_o
+add wave -noupdate -group Top /main/DUT/sfp_txn_o
+add wave -noupdate -group Top /main/DUT/sfp_rxp_i
+add wave -noupdate -group Top /main/DUT/sfp_rxn_i
+add wave -noupdate -group Top /main/DUT/sfp_mod_def0_b
+add wave -noupdate -group Top /main/DUT/sfp_mod_def1_b
+add wave -noupdate -group Top /main/DUT/sfp_mod_def2_b
+add wave -noupdate -group Top /main/DUT/sfp_rate_select_b
+add wave -noupdate -group Top /main/DUT/sfp_tx_fault_i
+add wave -noupdate -group Top /main/DUT/sfp_tx_disable_o
+add wave -noupdate -group Top /main/DUT/sfp_los_i
+add wave -noupdate -group Top /main/DUT/pll20dac_din_o
+add wave -noupdate -group Top /main/DUT/pll20dac_sclk_o
+add wave -noupdate -group Top /main/DUT/pll20dac_sync_n_o
+add wave -noupdate -group Top /main/DUT/pll25dac_din_o
+add wave -noupdate -group Top /main/DUT/pll25dac_sclk_o
+add wave -noupdate -group Top /main/DUT/pll25dac_sync_n_o
+add wave -noupdate -group Top /main/DUT/uart_rxd_i
+add wave -noupdate -group Top /main/DUT/uart_txd_o
+add wave -noupdate -group Top /main/DUT/carrier_onewire_b
+add wave -noupdate -group Top /main/DUT/pcb_ver_i
+add wave -noupdate -group Top /main/DUT/tdc1_prsntm2c_n_i
+add wave -noupdate -group Top /main/DUT/tdc2_prsntm2c_n_i
+add wave -noupdate -group Top /main/DUT/fp_led_line_oen_o
+add wave -noupdate -group Top /main/DUT/fp_led_line_o
+add wave -noupdate -group Top /main/DUT/fp_led_column_o
+add wave -noupdate -group Top /main/DUT/VME_AS_n_i
+add wave -noupdate -group Top /main/DUT/VME_RST_n_i
+add wave -noupdate -group Top /main/DUT/VME_WRITE_n_i
+add wave -noupdate -group Top /main/DUT/VME_AM_i
+add wave -noupdate -group Top /main/DUT/VME_DS_n_i
+add wave -noupdate -group Top /main/DUT/VME_GA_i
+add wave -noupdate -group Top /main/DUT/VME_BERR_o
+add wave -noupdate -group Top /main/DUT/VME_DTACK_n_o
+add wave -noupdate -group Top /main/DUT/VME_RETRY_n_o
+add wave -noupdate -group Top /main/DUT/VME_RETRY_OE_o
+add wave -noupdate -group Top /main/DUT/VME_LWORD_n_b
+add wave -noupdate -group Top /main/DUT/VME_ADDR_b
+add wave -noupdate -group Top /main/DUT/VME_DATA_b
+add wave -noupdate -group Top /main/DUT/VME_BBSY_n_i
+add wave -noupdate -group Top /main/DUT/VME_IRQ_n_o
+add wave -noupdate -group Top /main/DUT/VME_IACK_n_i
+add wave -noupdate -group Top /main/DUT/VME_IACKIN_n_i
+add wave -noupdate -group Top /main/DUT/VME_IACKOUT_n_o
+add wave -noupdate -group Top /main/DUT/VME_DTACK_OE_o
+add wave -noupdate -group Top /main/DUT/VME_DATA_DIR_o
+add wave -noupdate -group Top /main/DUT/VME_DATA_OE_N_o
+add wave -noupdate -group Top /main/DUT/VME_ADDR_DIR_o
+add wave -noupdate -group Top /main/DUT/VME_ADDR_OE_N_o
+add wave -noupdate -group Top /main/DUT/tdc1_pll_sclk_o
+add wave -noupdate -group Top /main/DUT/tdc1_pll_sdi_o
+add wave -noupdate -group Top /main/DUT/tdc1_pll_cs_n_o
+add wave -noupdate -group Top /main/DUT/tdc1_pll_dac_sync_n_o
+add wave -noupdate -group Top /main/DUT/tdc1_pll_sdo_i
+add wave -noupdate -group Top /main/DUT/tdc1_pll_status_i
+add wave -noupdate -group Top /main/DUT/tdc1_125m_clk_p_i
+add wave -noupdate -group Top /main/DUT/tdc1_125m_clk_n_i
+add wave -noupdate -group Top /main/DUT/tdc1_acam_refclk_p_i
+add wave -noupdate -group Top /main/DUT/tdc1_acam_refclk_n_i
+add wave -noupdate -group Top /main/DUT/tdc1_start_from_fpga_o
+add wave -noupdate -group Top /main/DUT/tdc1_err_flag_i
+add wave -noupdate -group Top /main/DUT/tdc1_int_flag_i
+add wave -noupdate -group Top /main/DUT/tdc1_start_dis_o
+add wave -noupdate -group Top /main/DUT/tdc1_stop_dis_o
+add wave -noupdate -group Top /main/DUT/tdc1_data_bus_io
+add wave -noupdate -group Top /main/DUT/tdc1_address_o
+add wave -noupdate -group Top /main/DUT/tdc1_cs_n_o
+add wave -noupdate -group Top /main/DUT/tdc1_oe_n_o
+add wave -noupdate -group Top /main/DUT/tdc1_rd_n_o
+add wave -noupdate -group Top /main/DUT/tdc1_wr_n_o
+add wave -noupdate -group Top /main/DUT/tdc1_ef1_i
+add wave -noupdate -group Top /main/DUT/tdc1_ef2_i
+add wave -noupdate -group Top /main/DUT/tdc1_enable_inputs_o
+add wave -noupdate -group Top /main/DUT/tdc1_term_en_1_o
+add wave -noupdate -group Top /main/DUT/tdc1_term_en_2_o
+add wave -noupdate -group Top /main/DUT/tdc1_term_en_3_o
+add wave -noupdate -group Top /main/DUT/tdc1_term_en_4_o
+add wave -noupdate -group Top /main/DUT/tdc1_term_en_5_o
+add wave -noupdate -group Top /main/DUT/tdc1_onewire_b
+add wave -noupdate -group Top /main/DUT/tdc1_scl_b
+add wave -noupdate -group Top /main/DUT/tdc1_sda_b
+add wave -noupdate -group Top /main/DUT/tdc1_led_status_o
+add wave -noupdate -group Top /main/DUT/tdc1_led_trig1_o
+add wave -noupdate -group Top /main/DUT/tdc1_led_trig2_o
+add wave -noupdate -group Top /main/DUT/tdc1_led_trig3_o
+add wave -noupdate -group Top /main/DUT/tdc1_led_trig4_o
+add wave -noupdate -group Top /main/DUT/tdc1_led_trig5_o
+add wave -noupdate -group Top /main/DUT/tdc1_in_fpga_1_i
+add wave -noupdate -group Top /main/DUT/tdc1_in_fpga_2_i
+add wave -noupdate -group Top /main/DUT/tdc1_in_fpga_3_i
+add wave -noupdate -group Top /main/DUT/tdc1_in_fpga_4_i
+add wave -noupdate -group Top /main/DUT/tdc1_in_fpga_5_i
+add wave -noupdate -group Top /main/DUT/tdc2_pll_sclk_o
+add wave -noupdate -group Top /main/DUT/tdc2_pll_sdi_o
+add wave -noupdate -group Top /main/DUT/tdc2_pll_cs_n_o
+add wave -noupdate -group Top /main/DUT/tdc2_pll_dac_sync_n_o
+add wave -noupdate -group Top /main/DUT/tdc2_pll_sdo_i
+add wave -noupdate -group Top /main/DUT/tdc2_pll_status_i
+add wave -noupdate -group Top /main/DUT/tdc2_125m_clk_p_i
+add wave -noupdate -group Top /main/DUT/tdc2_125m_clk_n_i
+add wave -noupdate -group Top /main/DUT/tdc2_acam_refclk_p_i
+add wave -noupdate -group Top /main/DUT/tdc2_acam_refclk_n_i
+add wave -noupdate -group Top /main/DUT/tdc2_start_from_fpga_o
+add wave -noupdate -group Top /main/DUT/tdc2_err_flag_i
+add wave -noupdate -group Top /main/DUT/tdc2_int_flag_i
+add wave -noupdate -group Top /main/DUT/tdc2_start_dis_o
+add wave -noupdate -group Top /main/DUT/tdc2_stop_dis_o
+add wave -noupdate -group Top /main/DUT/tdc2_data_bus_io
+add wave -noupdate -group Top /main/DUT/tdc2_address_o
+add wave -noupdate -group Top /main/DUT/tdc2_cs_n_o
+add wave -noupdate -group Top /main/DUT/tdc2_oe_n_o
+add wave -noupdate -group Top /main/DUT/tdc2_rd_n_o
+add wave -noupdate -group Top /main/DUT/tdc2_wr_n_o
+add wave -noupdate -group Top /main/DUT/tdc2_ef1_i
+add wave -noupdate -group Top /main/DUT/tdc2_ef2_i
+add wave -noupdate -group Top /main/DUT/tdc2_enable_inputs_o
+add wave -noupdate -group Top /main/DUT/tdc2_term_en_1_o
+add wave -noupdate -group Top /main/DUT/tdc2_term_en_2_o
+add wave -noupdate -group Top /main/DUT/tdc2_term_en_3_o
+add wave -noupdate -group Top /main/DUT/tdc2_term_en_4_o
+add wave -noupdate -group Top /main/DUT/tdc2_term_en_5_o
+add wave -noupdate -group Top /main/DUT/tdc2_onewire_b
+add wave -noupdate -group Top /main/DUT/tdc2_scl_b
+add wave -noupdate -group Top /main/DUT/tdc2_sda_b
+add wave -noupdate -group Top /main/DUT/tdc2_led_status_o
+add wave -noupdate -group Top /main/DUT/tdc2_led_trig1_o
+add wave -noupdate -group Top /main/DUT/tdc2_led_trig2_o
+add wave -noupdate -group Top /main/DUT/tdc2_led_trig3_o
+add wave -noupdate -group Top /main/DUT/tdc2_led_trig4_o
+add wave -noupdate -group Top /main/DUT/tdc2_led_trig5_o
+add wave -noupdate -group Top /main/DUT/tdc2_in_fpga_1_i
+add wave -noupdate -group Top /main/DUT/tdc2_in_fpga_2_i
+add wave -noupdate -group Top /main/DUT/tdc2_in_fpga_3_i
+add wave -noupdate -group Top /main/DUT/tdc2_in_fpga_4_i
+add wave -noupdate -group Top /main/DUT/tdc2_in_fpga_5_i
+add wave -noupdate -group Top /main/DUT/clk_20m_vcxo_buf
+add wave -noupdate -group Top /main/DUT/clk_20m_vcxo
+add wave -noupdate -group Top /main/DUT/clk_62m5_sys
+add wave -noupdate -group Top /main/DUT/pllout_clk_sys
+add wave -noupdate -group Top /main/DUT/pllout_clk_sys_fb
+add wave -noupdate -group Top /main/DUT/sys_locked
+add wave -noupdate -group Top /main/DUT/tdc1_125m_clk
+add wave -noupdate -group Top /main/DUT/tdc1_send_dac_word_p
+add wave -noupdate -group Top /main/DUT/tdc1_dac_word
+add wave -noupdate -group Top /main/DUT/tdc2_125m_clk
+add wave -noupdate -group Top /main/DUT/tdc2_send_dac_word_p
+add wave -noupdate -group Top /main/DUT/tdc2_dac_word
+add wave -noupdate -group Top /main/DUT/pllout_clk_dmtd
+add wave -noupdate -group Top /main/DUT/pllout_clk_fb_dmtd
+add wave -noupdate -group Top /main/DUT/pllout_clk_fb_pllref
+add wave -noupdate -group Top /main/DUT/clk_125m_pllref
+add wave -noupdate -group Top /main/DUT/clk_125m_gtp
+add wave -noupdate -group Top /main/DUT/clk_dmtd
+add wave -noupdate -group Top /main/DUT/por_rst_n_a
+add wave -noupdate -group Top /main/DUT/powerup_rst_cnt
+add wave -noupdate -group Top /main/DUT/rst_n_sys
+add wave -noupdate -group Top /main/DUT/tdc1_soft_rst_n
+add wave -noupdate -group Top /main/DUT/tdc2_soft_rst_n
+add wave -noupdate -group Top /main/DUT/carrier_info_fmc_rst
+add wave -noupdate -group Top /main/DUT/carrier_info_stat_reserv
+add wave -noupdate -group Top /main/DUT/VME_DATA_b_out
+add wave -noupdate -group Top /main/DUT/VME_ADDR_b_out
+add wave -noupdate -group Top /main/DUT/VME_LWORD_n_b_out
+add wave -noupdate -group Top /main/DUT/VME_DATA_DIR_int
+add wave -noupdate -group Top /main/DUT/VME_ADDR_DIR_int
+add wave -noupdate -group Top /main/DUT/tm_link_up
+add wave -noupdate -group Top /main/DUT/tm_time_valid
+add wave -noupdate -group Top /main/DUT/tm_utc
+add wave -noupdate -group Top /main/DUT/tm_cycles
+add wave -noupdate -group Top /main/DUT/tm_clk_aux_lock_en
+add wave -noupdate -group Top /main/DUT/tm_clk_aux_locked
+add wave -noupdate -group Top /main/DUT/tm_dac_value
+add wave -noupdate -group Top /main/DUT/tm_dac_wr_p
+add wave -noupdate -group Top /main/DUT/phy_tx_data
+add wave -noupdate -group Top /main/DUT/phy_rx_data
+add wave -noupdate -group Top /main/DUT/phy_tx_k
+add wave -noupdate -group Top /main/DUT/phy_tx_disparity
+add wave -noupdate -group Top /main/DUT/phy_rx_k
+add wave -noupdate -group Top /main/DUT/phy_tx_enc_err
+add wave -noupdate -group Top /main/DUT/phy_rx_rbclk
+add wave -noupdate -group Top /main/DUT/phy_rx_enc_err
+add wave -noupdate -group Top /main/DUT/phy_rst
+add wave -noupdate -group Top /main/DUT/phy_loopen
+add wave -noupdate -group Top /main/DUT/phy_rx_bitslide
+add wave -noupdate -group Top /main/DUT/dac_hpll_load_p1
+add wave -noupdate -group Top /main/DUT/dac_dpll_load_p1
+add wave -noupdate -group Top /main/DUT/dac_hpll_data
+add wave -noupdate -group Top /main/DUT/dac_dpll_data
+add wave -noupdate -group Top /main/DUT/wrc_scl_out
+add wave -noupdate -group Top /main/DUT/wrc_scl_in
+add wave -noupdate -group Top /main/DUT/wrc_sda_out
+add wave -noupdate -group Top /main/DUT/wrc_sda_in
+add wave -noupdate -group Top /main/DUT/sfp_scl_out
+add wave -noupdate -group Top /main/DUT/sfp_scl_in
+add wave -noupdate -group Top /main/DUT/sfp_sda_out
+add wave -noupdate -group Top /main/DUT/sfp_sda_in
+add wave -noupdate -group Top /main/DUT/wrc_owr_en
+add wave -noupdate -group Top /main/DUT/wrc_owr_in
+add wave -noupdate -group Top /main/DUT/cnx_master_out
+add wave -noupdate -group Top /main/DUT/cnx_master_in
+add wave -noupdate -group Top /main/DUT/cnx_slave_out
+add wave -noupdate -group Top /main/DUT/cnx_slave_in
+add wave -noupdate -group Top /main/DUT/irq_to_vmecore
+add wave -noupdate -group Top /main/DUT/tdc1_irq
+add wave -noupdate -group Top /main/DUT/tdc2_irq
+add wave -noupdate -group Top /main/DUT/tdc1_scl_oen
+add wave -noupdate -group Top /main/DUT/tdc1_scl_in
+add wave -noupdate -group Top /main/DUT/tdc1_sda_oen
+add wave -noupdate -group Top /main/DUT/tdc1_sda_in
+add wave -noupdate -group Top /main/DUT/tdc2_scl_oen
+add wave -noupdate -group Top /main/DUT/tdc2_scl_in
+add wave -noupdate -group Top /main/DUT/tdc2_sda_oen
+add wave -noupdate -group Top /main/DUT/tdc2_sda_in
+add wave -noupdate -group Top /main/DUT/carrier_owr_en
+add wave -noupdate -group Top /main/DUT/carrier_owr_i
+add wave -noupdate -group Top /main/DUT/led_state
+add wave -noupdate -group Top /main/DUT/tdc1_ef
+add wave -noupdate -group Top /main/DUT/tdc2_ef
+add wave -noupdate -group Top /main/DUT/led_tdc1_ef
+add wave -noupdate -group Top /main/DUT/led_tdc2_ef
+add wave -noupdate -group Top /main/DUT/led_vme_access
+add wave -noupdate -group Top /main/DUT/led_clk_62m5_divider
+add wave -noupdate -group Top /main/DUT/led_clk_62m5_aux
+add wave -noupdate -group Top /main/DUT/led_clk_62m5
+add wave -noupdate -group Top /main/DUT/wrabbit_led_red
+add wave -noupdate -group Top /main/DUT/wrabbit_led_green
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/clk_sys_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/rst_sys_n_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/rst_n_a_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/pll_sclk_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/pll_sdi_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/pll_cs_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/pll_dac_sync_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/pll_sdo_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/pll_status_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_clk_125m_p_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_clk_125m_n_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/acam_refclk_p_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/acam_refclk_n_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/start_from_fpga_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/err_flag_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/int_flag_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/start_dis_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/stop_dis_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/data_bus_io
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/address_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/cs_n_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/oe_n_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/rd_n_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/wr_n_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/ef1_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/ef2_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/enable_inputs_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/term_en_1_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/term_en_2_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/term_en_3_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/term_en_4_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/term_en_5_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_led_status_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_led_trig1_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_led_trig2_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_led_trig3_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_led_trig4_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_led_trig5_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_in_fpga_1_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_in_fpga_2_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_in_fpga_3_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_in_fpga_4_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_in_fpga_5_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/mezz_scl_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/mezz_sda_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/mezz_scl_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/mezz_sda_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/mezz_one_wire_b
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tm_link_up_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tm_time_valid_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tm_cycles_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tm_tai_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tm_clk_aux_lock_en_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tm_clk_aux_locked_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tm_clk_dmtd_locked_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tm_dac_value_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tm_dac_wr_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/slave_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/slave_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/direct_slave_i
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/direct_slave_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/irq_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/clk_125m_tdc_o
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/clk_125m_mezz
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/rst_125m_mezz_n
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/rst_125m_mezz
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/acam_refclk_r_edge_p
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/send_dac_word_p
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/dac_word
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/pll_sclk
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/pll_sdi
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/pll_dac_sync
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/fmc_eic_irq
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/fmc_eic_irq_synch
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_scl_out
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_scl_oen
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_sda_out
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_sda_oen
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/direct_timestamp
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/direct_timestamp_wr
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/cnx_master_in
+add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/cnx_master_out
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/clk_i
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/rst_i
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/activate_acq_p_i
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/deactivate_acq_p_i
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_wr_config_p_i
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_rst_p_i
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_rdbk_config_p_i
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_rdbk_status_p_i
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_rdbk_ififo1_p_i
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_rdbk_ififo2_p_i
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_rdbk_start01_p_i
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_config_i
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ef1_i
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ef1_meta_i
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ef2_i
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ef2_meta_i
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ack_i
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_dat_i
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/start_from_fpga_i
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/state_active_p_o
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_adr_o
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_cyc_o
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_stb_o
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_dat_o
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_we_o
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_config_rdbk_o
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ififo1_o
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ififo2_o
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_start01_o
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_tstamp1_o
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_tstamp2_o
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_tstamp1_ok_p_o
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_tstamp2_ok_p_o
+add wave -noupdate -group DataEngine1 -height 16 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/engine_st
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/nxt_engine_st
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_cyc
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_stb
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_we
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_adr
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/config_adr_c
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_config_rdbk
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/reset_word
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_config_reg4
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/time_c_full_p
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/time_c_en
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/time_c_rst
+add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/time_c
+add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/clk_i
+add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/rst_i
+add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/acam_refclk_r_edge_p_i
+add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/utc_p_i
+add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/state_active_p_i
+add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/activate_acq_p_i
+add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/deactivate_acq_p_i
+add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/err_flag_i
+add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/int_flag_i
+add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/start_from_fpga_o
+add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/stop_dis_o
+add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/acam_errflag_r_edge_p_o
+add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/acam_errflag_f_edge_p_o
+add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/acam_intflag_f_edge_p_o
+add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/int_flag_synch
+add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/err_flag_synch
+add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/acam_intflag_f_edge_p
+add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/start_pulse
+add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/wait_for_utc
+add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/rst_n
+add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/wait_for_state_active
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/clk_i
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/rst_i
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/acam_refclk_r_edge_p_i
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/clk_period_i
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/load_utc_p_i
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/starting_utc_i
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/pulse_delay_i
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/local_utc_o
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/local_utc_p_o
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/local_utc
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/one_hz_p_pre
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/one_hz_p_post
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/onesec_counter_en
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/total_delay
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/clk_sys_i
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/rst_n_sys_i
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/clk_tdc_i
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/rst_tdc_i
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/slave_i
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/slave_o
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_config_rdbk_i
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_ififo1_i
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_ififo2_i
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_start01_i
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wr_index_i
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/local_utc_i
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/core_status_i
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_code_i
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wrabbit_status_reg_i
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_config_o
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/activate_acq_p_o
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/deactivate_acq_p_o
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_wr_config_p_o
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_config_p_o
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rst_p_o
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_status_p_o
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_ififo1_p_o
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_ififo2_p_o
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_start01_p_o
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dacapo_c_rst_p_o
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/deactivate_chan_o
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/send_dac_word_p_o
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dac_word_o
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/load_utc_p_o
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/starting_utc_o
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_tstamp_threshold_o
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_time_threshold_o
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/one_hz_phase_o
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_inputs_en_o
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wrabbit_ctrl_reg_o
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/start_phase_o
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_config
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr_pipe0
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/starting_utc
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_inputs_en
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/start_phase
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/ctrl_reg
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/one_hz_phase
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_tstamp_threshold
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_time_threshold
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/clear_ctrl_reg
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/send_dac_word_p
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dac_word
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/pulse_extender_en
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/pulse_extender_c
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wrabbit_ctrl_reg
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/deactivate_chan
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/ack_out_pipe0
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/ack_out_pipe1
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_comb0
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_comb1
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_comb2
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_comb3
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_pipe0
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_pipe1
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_pipe2
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_pipe3
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/cyc_in_progress
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wb_in
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wb_out
+add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/rst_n_tdc
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/clk_sys_i
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/rst_n_sys_i
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/clk_tdc_i
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/rst_tdc_i
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/slave_i
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/slave_o
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_config_rdbk_i
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_ififo1_i
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_ififo2_i
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_start01_i
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wr_index_i
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/local_utc_i
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/core_status_i
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_code_i
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wrabbit_status_reg_i
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_config_o
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/activate_acq_p_o
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/deactivate_acq_p_o
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_wr_config_p_o
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_config_p_o
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rst_p_o
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_status_p_o
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_ififo1_p_o
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_ififo2_p_o
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_start01_p_o
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dacapo_c_rst_p_o
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/deactivate_chan_o
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/send_dac_word_p_o
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dac_word_o
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/load_utc_p_o
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/starting_utc_o
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_tstamp_threshold_o
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_time_threshold_o
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/one_hz_phase_o
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_inputs_en_o
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wrabbit_ctrl_reg_o
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/start_phase_o
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_config
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr_pipe0
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/starting_utc
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_inputs_en
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/start_phase
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/ctrl_reg
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/one_hz_phase
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_tstamp_threshold
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_time_threshold
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/clear_ctrl_reg
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/send_dac_word_p
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dac_word
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/pulse_extender_en
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/pulse_extender_c
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wrabbit_ctrl_reg
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/deactivate_chan
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/ack_out_pipe0
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/ack_out_pipe1
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_comb0
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_comb1
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_comb2
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_comb3
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_pipe0
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_pipe1
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_pipe2
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_pipe3
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/cyc_in_progress
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wb_in
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wb_out
+add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/rst_n_tdc
+add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/clk_tdc_i
+add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/clk_sys_i
+add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/rst_n_sys_i
+add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tstamp_wr_rst_i
+add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tstamp_wr_stb_i
+add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tstamp_wr_cyc_i
+add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tstamp_wr_we_i
+add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tstamp_wr_adr_i
+add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tstamp_wr_dat_i
+add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tdc_mem_wb_rst_i
+add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tdc_mem_wb_stb_i
+add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tdc_mem_wb_cyc_i
+add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tdc_mem_wb_we_i
+add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tdc_mem_wb_adr_i
+add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tdc_mem_wb_dat_i
+add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tstamp_wr_ack_p_o
+add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tstamp_wr_dat_o
+add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tdc_mem_wb_ack_o
+add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tdc_mem_wb_dat_o
+add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tdc_mem_wb_stall_o
+add wave -noupdate -expand -group CircBuf1 -height 16 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tstamp_rd_wb_st
+add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/nxt_tstamp_rd_wb_st
+add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tstamp_wr_ack_p
+add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tstamp_rd_we
+add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tstamp_wr_we
+add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/mb_data
+add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/adr_d0
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_sys_i
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rst_n_sys_i
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_tdc_i
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rst_tdc_i
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_refclk_r_edge_p_i
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/send_dac_word_p_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/dac_word_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/start_from_fpga_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/err_flag_i
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/int_flag_i
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/start_dis_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/stop_dis_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_bus_io
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/address_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/cs_n_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/oe_n_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rd_n_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wr_n_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/ef1_i
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/ef2_i
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/enable_inputs_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_1_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_2_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_3_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_4_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_5_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_status_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig1_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig2_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig3_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig4_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig5_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_1_i
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_2_i
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_3_i
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_4_i
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_5_i
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_tstamp_p_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_time_p_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_acam_err_p_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_status_reg_i
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_ctrl_reg_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_synched_i
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_tai_p_i
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_tai_i
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/cfg_slave_i
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/cfg_slave_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/mem_slave_i
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/mem_slave_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/direct_timestamp_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/direct_timestamp_stb_o
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_adr
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_cyc
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_stb
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_we
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_ack
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_dat_r
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_dat_w
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef1
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef2
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef1_meta
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef2_meta
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_errflag_f_edge_p
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_errflag_r_edge_p
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_intflag_f_edge_p
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp1
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp2
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp1_ok_p
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp2_ok_p
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/activate_acq_p
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/deactivate_acq_p
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/load_acam_config
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_acam_config
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_acam_status
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_ififo1
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_ififo2
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_start01
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reset_acam
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/load_utc
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clear_dacapo_counter
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/roll_over_incr_recent
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/deactivate_chan
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/pulse_delay
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/window_delay
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_period
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/starting_utc
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_inputs_en
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ififo1
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ififo2
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_start01
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_tstamp_threshold
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_time_threshold
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_utc
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wr_index
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_config
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_config_rdbk
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tstamp_wr_p
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/start_from_fpga
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/state_active_p
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_i_cycles_offset
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/roll_over_nb
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/retrig_nb_offset
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_utc_p
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/current_retrig_nb
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/utc_p
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/utc
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_ctrl_reg
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circ_buff_class_adr
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circ_buff_class_stb
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circ_buff_class_cyc
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circ_buff_class_we
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circ_buff_class_ack
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circ_buff_class_data_wr
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circ_buff_class_data_rd
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_channel
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_1
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_2
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_3
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_4
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_5
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp_channel
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rst_sys
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/CONTROL
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/CLK
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/TRIG0
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/TRIG1
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/TRIG2
+add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/TRIG3
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {505599788 ps} 0}
+WaveRestoreCursors {{Cursor 1} {943109721 ps} 0}
 configure wave -namecolwidth 177
 configure wave -valuecolwidth 100
 configure wave -justifyvalue left
@@ -72,4 +723,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {441541177 ps} {657429313 ps}
+WaveRestoreZoom {919925540 ps} {1035495170 ps}