top/svec: cleanup indentation and remove unused signals

4c7d3f56 · Grzegorz Daniluk · 6185eb76 · 4c7d3f56
Commit 4c7d3f56 authored Dec 08, 2017 by Grzegorz Daniluk
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Showing with 239 additions and 247 deletions

wr_svec_tdc.vhd hdl/top/svec/wr_svec_tdc.vhd +239 -247

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--- a/hdl/top/svec/wr_svec_tdc.vhd
+++ b/hdl/top/svec/wr_svec_tdc.vhd
@@ -135,10 +135,8 @@ use work.synthesis_descriptor.all;
 --=================================================================================================
 entity wr_svec_tdc is
  generic (
-     g_simulation           : boolean := false;
-     g_with_wr_phy : boolean := true);
-  port
-    (-- SVEC carrier
+    g_simulation           : boolean := false);
+  port (
    -- VCXO clock, PoR
    por_n_i                : in    std_logic;        -- PoR
    clk_20m_vcxo_i         : in    std_logic;        -- 20 MHz VCXO
@@ -418,14 +416,9 @@ architecture rtl of wr_svec_tdc is
  -- Clocks
  -- CLOCK DOMAIN: 62.5 MHz system clock derived from clk_20m_vcxo_i by a Xilinx PLL: clk_62m5_sys
  signal clk_sys_62m5  : std_logic;
-  -- CLOCK DOMAIN: 125 MHz clock from PLL on TDC1: tdc1_125m_clk
+  -- CLOCK DOMAIN: 125 MHz clock from PLL on TDC1 and TDC2
  signal tdc1_125m_clk : std_logic;
-  signal tdc1_send_dac_word_p                 : std_logic;
-  signal tdc1_dac_word                        : std_logic_vector(23 downto 0);
-  -- CLOCK DOMAIN: 125 MHz clock from PLL on TDC2: tdc2_125m_clk
  signal tdc2_125m_clk : std_logic;
-  signal tdc2_send_dac_word_p                 : std_logic;
-  signal tdc2_dac_word                        : std_logic_vector(23 downto 0);

 ---------------------------------------------------------------------------------------------------
  -- Resets
@@ -436,7 +429,6 @@ architecture rtl of wr_svec_tdc is
  signal tdc1_soft_rst_n      : std_logic; -- driven by carrier CSR reserved bit 0
  signal tdc2_soft_rst_n      : std_logic; -- driven by carrier CSR reserved bit 1
  signal carrier_info_fmc_rst : std_logic_vector(30 downto 0);
-  signal carrier_info_stat_reserv             : std_logic_vector(27 downto 0);

 ---------------------------------------------------------------------------------------------------
 -- VME interface