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FMC TDC 1ns 5cha - Gateware
Commit 552710a7 authored by penacoba's avatar penacoba
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New preliminary modules after design specification review 


git-svn-id: http://svn.ohwr.org/fmc-tdc@39 85dfdc96-de2c-444c-878d-45b388be74a9
parent a4e6cbd1
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Showing with 236 additions and 147 deletions
hdl/spec/src/rtl/acam_databus_interface.vhd
View file @ 552710a7
......@@ -174,11 +174,7 @@ begin
end case;
end process;
ef1 <= ef1_i;
ef2 <= ef2_i;
lf1 <= lf1_i;
lf2 <= lf2_i;
-- inputs from other blocks
clk <= clk_i;
reset <= reset_i;
......@@ -188,13 +184,22 @@ begin
stb <= stb_i;
we <= we_i;
-- outputs to other blocks
ack_o <= ack;
dat_o <= ef1 & ef2 & lf1 & lf2 & data_bus_io;
-- inputs from the ACAM
ef1 <= ef1_i;
ef2 <= ef2_i;
lf1 <= lf1_i;
lf2 <= lf2_i;
-- outputs to the ACAM
address_o <= adr(3 downto 0);
cs_n_o <= not(cs);
oe_n_o <= '1';
rd_n_o <= not(rd);
wr_n_o <= not(wr);
ack_o <= ack;
dat_o <= ef1 & ef2 & lf1 & lf2 & data_bus_io;
end rtl;
----------------------------------------------------------------------------------------------------
......
hdl/spec/src/rtl/acam_timecontrol_interface.vhd
View file @ 552710a7
......@@ -34,11 +34,12 @@ entity acam_timecontrol_interface is
int_flag_i : in std_logic;
start_dis_o : out std_logic;
start_from_fpga_o : out std_logic;
stop_dis_o : out std_logic;
-- signals internal to the chip: interface with other modules
clk_i : in std_logic;
one_hz_p_i : in std_logic;
start_trig_i : in std_logic;
reset_i : in std_logic;
acam_errflag_p_o : out std_logic;
......@@ -68,12 +69,13 @@ architecture rtl of acam_timecontrol_interface is
signal clk : std_logic;
signal counter_reset : std_logic;
signal one_hz_p : std_logic;
signal start_trig : std_logic;
signal reset : std_logic;
signal s_int_flag : unsigned(2 downto 0);
signal s_err_flag : unsigned(2 downto 0);
signal start_dis : std_logic;
signal start_from_fpga : std_logic;
signal start_window : std_logic;
signal window_inverted : std_logic;
......@@ -137,14 +139,18 @@ begin
);
start_window <= not(window_inverted);
counter_reset <= reset or one_hz_p;
counter_reset <= reset or start_trig;
start_from_fpga <= start_trig;
-- inputs
clk <= clk_i;
one_hz_p <= one_hz_p_i;
start_trig <= start_trig_i;
reset <= reset_i;
-- outputs
start_dis_o <= start_dis;
stop_dis_o <= '0';
start_from_fpga_o <= start_from_fpga;
end rtl;
----------------------------------------------------------------------------------------------------
......
hdl/spec/src/rtl/data_polling.vhd → hdl/spec/src/rtl/data_engine.vhd
View file @ 552710a7
......@@ -2,7 +2,7 @@
-- CERN-BE-CO-HT
----------------------------------------------------------------------------------------------------
--
-- unit name : data polling engine (data_polling)
-- unit name : data polling engine (data_engine)
-- author : G. Penacoba
-- date : June 2011
-- version : Revision 1
......@@ -15,18 +15,19 @@
----------------------------------------------------------------------------------------------------
-- last changes:
----------------------------------------------------------------------------------------------------
-- to do: empty FIFO signals from Acam are missing (maybe putting them in the data?)
-- other Acam configuration registers maybe...
-- to do:
--
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.tdc_core_pkg.all;
----------------------------------------------------------------------------------------------------
-- entity declaration for data_polling
-- entity declaration for data_engine
----------------------------------------------------------------------------------------------------
entity data_polling is
entity data_engine is
generic(
g_width : integer :=32
);
......@@ -41,22 +42,28 @@ entity data_polling is
we_o : out std_logic;
-- signals internal to the chip: interface with other modules
acam_config_reg_i : in config_vector;
clk_i : in std_logic;
load_acam_config_i : in std_logic;
one_hz_p_i : in std_logic;
reset_i : in std_logic;
start_timer_reg_i : in std_logic_vector(7 downto 0);
acam_start01_o : out std_logic_vector(16 downto 0);
acam_timestamp_o : out std_logic_vector(28 downto 0);
acam_timestamp_valid_o : out std_logic
);
end acam_databus_interface;
end data_engine;
----------------------------------------------------------------------------------------------------
-- architecture declaration for data_polling
-- architecture declaration for data_engine
----------------------------------------------------------------------------------------------------
architecture rtl of data_polling is
architecture rtl of data_engine is
type engine_state_ty is (wr_config, rest_wr, rd_timestamp, rest_rd);
signal engine_st, nxt_engine_st : engine_state_ty;
signal ef1 : std_logic;
signal ef2 : std_logic;
----------------------------------------------------------------------------------------------------
-- architecture begins
......
hdl/spec/src/rtl/start_nb_offset_gen.vhd → hdl/spec/src/rtl/start_retrigger_control.vhd
View file @ 552710a7
......@@ -2,11 +2,13 @@
-- CERN-BE-CO-HT
----------------------------------------------------------------------------------------------------
--
-- unit name : internal start number offset generator (start_nb_offset_gen)
-- unit name : start retrigger control and internal start number offset generator
-- (start_retrigger_control)
-- author : G. Penacoba
-- date : May 2011
-- date : July 2011
-- version : Revision 1
-- description : generates the offset to be added to the start number provided by tha Acam
-- description : launches the start pulses and the ACAM generates the internal start retriggers.
-- Also generates the offset to be added to the start number provided by tha Acam
-- by counting the number of times the 1-Byte counter of the Acam is overloaded.
-- The result is then multiplied by 256 (shifted by 8).
-- dependencies:
......@@ -24,9 +26,9 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
----------------------------------------------------------------------------------------------------
-- entity declaration for start_nb_offset_gen
-- entity declaration for start_retrigger_control
----------------------------------------------------------------------------------------------------
entity start_nb_offset_gen is
entity start_retrigger_control is
generic(
g_width : integer :=32
);
......@@ -35,15 +37,16 @@ entity start_nb_offset_gen is
clk_i : in std_logic;
one_hz_p_i : in std_logic;
reset_i : in std_logic;
start_nb_offset_o : out std_logic_vector(g_width-1 downto 0)
start_nb_offset_o : out std_logic_vector(g_width-1 downto 0);
start_trig_o : out std_logic
);
end start_nb_offset_gen;
end start_retrigger_control;
----------------------------------------------------------------------------------------------------
-- architecture declaration for start_nb_offset_gen
-- architecture declaration for start_retrigger_control
----------------------------------------------------------------------------------------------------
architecture rtl of start_nb_offset_gen is
architecture rtl of start_retrigger_control is
component incr_counter
generic(
......@@ -67,6 +70,8 @@ signal offset_value : std_logic_vector(g_width-1 downto 0);
signal offset_to_shift : unsigned(g_width-1 downto 0);
signal one_hz_p : std_logic;
signal reset : std_logic;
signal start_nb_offset : std_logic_vector(g_width-1 downto 0);
signal start_trig : std_logic;
----------------------------------------------------------------------------------------------------
-- architecture begins
......@@ -89,12 +94,18 @@ begin
counter_reset <= reset or one_hz_p;
offset_to_shift <= unsigned(offset_value);
start_nb_offset_o <= std_logic_vector(shift_left(offset_to_shift,8));
start_nb_offset <= std_logic_vector(shift_left(offset_to_shift,8));
start_trig <= one_hz_p;
-- inputs
acam_intflag_p <= acam_intflag_p_i;
clk <= clk_i;
one_hz_p <= one_hz_p_i;
reset <= reset_i;
-- outputs
start_nb_offset_o <= start_nb_offset;
start_trig_o <= start_trig;
end rtl;
----------------------------------------------------------------------------------------------------
......
hdl/spec/src/rtl/tdc_core_pkg.vhd
View file @ 552710a7
......@@ -78,6 +78,10 @@ constant spec_led_period_syn : std_logic_vector(data_width-1 downto 0):=x"013
constant blink_length_syn : std_logic_vector(data_width-1 downto 0):=x"00BEBC20"; -- 100 ms at 125 MHz
constant blink_length_sim : std_logic_vector(data_width-1 downto 0):=x"000004E2"; -- 10 us at 125 MHz
subtype config_register is std_logic_vector(27 downto 0);
type config_vector is array (10 downto 0) of config_register;
end tdc_core_pkg;
----------------------------------------------------------------------------------------------------
......
hdl/spec/src/rtl/top_tdc.vhd
View file @ 552710a7
......@@ -57,6 +57,7 @@ entity top_tdc is
p_rd_d_rdy_i: in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
spare_o : out std_logic;
-- interface signals with PLL circuit on TDC mezzanine
acam_refclk_i : in std_logic;
......@@ -140,55 +141,59 @@ architecture rtl of top_tdc is
);
end component;
-- component start_nb_offset_gen is
-- generic(
-- g_width : integer :=32
-- );
-- port(
-- acam_intflag_p_i : in std_logic;
-- clk_i : in std_logic;
-- one_hz_p_i : in std_logic;
-- reset_i : in std_logic;
--
-- start_nb_offset_o : out std_logic_vector(g_width-1 downto 0)
-- );
-- end component;
--
-- component data_formatting
-- generic(
-- g_width : integer :=32
-- );
-- port(
-- acam_start01_i : in std_logic_vector(16 downto 0);
-- acam_timestamp_i : in std_logic_vector(28 downto 0);
-- acam_timestamp_valid_i : in std_logic;
-- clk_i : in std_logic;
-- reset_i : in std_logic;
-- start_nb_offset_i : in std_logic_vector(g_width-1 downto 0);
-- utc_current_time_i : in std_logic_vector(g_width-1 downto 0);
--
-- full_timestamp_o : out std_logic_vector(3*g_width-1 downto 0);
-- full_timestamp_valid_o : out std_logic
-- );
-- end component;
component start_retrigger_control is
generic(
g_width : integer :=32
);
port(
acam_intflag_p_i : in std_logic;
clk_i : in std_logic;
one_hz_p_i : in std_logic;
reset_i : in std_logic;
start_nb_offset_o : out std_logic_vector(g_width-1 downto 0);
start_trig_o : out std_logic
);
end component;
component acam_timecontrol_interface
component data_formatting
generic(
g_width : integer :=32
);
port(
err_flag_i : in std_logic;
int_flag_i : in std_logic;
start_dis_o : out std_logic;
stop_dis_o : out std_logic;
acam_start01_i : in std_logic_vector(16 downto 0);
acam_timestamp_i : in std_logic_vector(28 downto 0);
acam_timestamp_valid_i : in std_logic;
clk_i : in std_logic;
one_hz_p_i : in std_logic;
reset_i : in std_logic;
start_nb_offset_i : in std_logic_vector(g_width-1 downto 0);
utc_current_time_i : in std_logic_vector(g_width-1 downto 0);
full_timestamp_o : out std_logic_vector(3*g_width-1 downto 0);
full_timestamp_valid_o : out std_logic
);
end component;
component acam_timecontrol_interface
generic(
g_width : integer :=32
);
port(
-- signals external to the chip: interface with acam
err_flag_i : in std_logic;
int_flag_i : in std_logic;
start_dis_o : out std_logic;
start_from_fpga_o : out std_logic;
stop_dis_o : out std_logic;
-- signals internal to the chip: interface with other modules
clk_i : in std_logic;
start_trig_i : in std_logic;
reset_i : in std_logic;
acam_errflag_p_o : out std_logic;
acam_intflag_p_o : out std_logic
acam_errflag_p_o : out std_logic;
acam_intflag_p_o : out std_logic
);
end component;
......@@ -224,6 +229,10 @@ architecture rtl of top_tdc is
end component;
component clk_rst_managr
generic(
nb_of_reg : integer:=68;
values_for_simulation : boolean:=FALSE
);
port(
acam_refclk_i : in std_logic;
pll_ld_i : in std_logic;
......@@ -331,14 +340,15 @@ architecture rtl of top_tdc is
);
end component;
constant sim_clock_period : std_logic_vector(g_width-1 downto 0):=x"0001E848"; -- 1 ms
constant syn_clock_period : std_logic_vector(g_width-1 downto 0):=x"07735940"; -- 1 s
--used to generate the one_hz_p pulse
constant sim_clock_period : std_logic_vector(g_width-1 downto 0):=x"0001E848"; -- 1 ms at 125 MHz (tdc board clock)
constant syn_clock_period : std_logic_vector(g_width-1 downto 0):=x"07735940"; -- 1 s at 125 MHz (tdc board clock)
signal tdc_led_period : std_logic_vector(g_width-1 downto 0);
signal spec_led_count_done : std_logic;
signal spec_led_period : std_logic_vector(g_width-1 downto 0);
signal tdc_led_count_done : std_logic;
signal spec_led_count_done : std_logic;
signal tdc_led_period : std_logic_vector(g_width-1 downto 0);
signal visible_blink_length : std_logic_vector(g_width-1 downto 0);
-- will be registers of the core
signal pulse_delay : std_logic_vector(g_width-1 downto 0);
......@@ -346,29 +356,27 @@ signal clock_period : std_logic_vector(g_width-1 downto 0);
signal gnum_reset : std_logic;
signal pll_cs : std_logic;
signal spec_clk : std_logic;
signal tdc_led_status : std_logic:='0';
signal spec_led_green : std_logic;
signal spec_led_red : std_logic;
signal tdc_led_status : std_logic;
signal tdc_led_trig1 : std_logic:='0';
signal tdc_led_trig2 : std_logic:='0';
signal tdc_led_trig3 : std_logic:='0';
signal tdc_led_trig4 : std_logic:='0';
signal tdc_led_trig5 : std_logic:='0';
signal spec_led_green : std_logic:='0';
signal spec_led_red : std_logic:='0';
signal acam_errflag_p : std_logic;
signal acam_intflag_p : std_logic;
signal acam_refclk : std_logic;
signal acam_start01 : std_logic_vector(16 downto 0);
signal acam_timestamp : std_logic_vector(28 downto 0);
signal acam_timestamp_valid : std_logic;
signal clk : std_logic;
signal full_timestamp : std_logic_vector(3*g_width-1 downto 0);
signal full_timestamp_valid : std_logic;
signal general_reset : std_logic;
signal one_hz_p : std_logic;
signal start_nb_offset : std_logic_vector(g_width-1 downto 0);
signal start_trig : std_logic;
signal start_timer_reg : std_logic_vector(7 downto 0);
signal utc_current_time : std_logic_vector(g_width-1 downto 0);
......@@ -402,6 +410,10 @@ signal dma_dat_o : std_logic_vector(31 downto 0);
signal dma_ack : std_logic;
signal dma_stall : std_logic;
signal acam_refclk : std_logic;
signal clk : std_logic;
signal spec_clk : std_logic;
----------------------------------------------------------------------------------------------------
-- architecture begins
----------------------------------------------------------------------------------------------------
......@@ -421,35 +433,36 @@ begin
one_hz_p_o => one_hz_p
);
-- start_nb_block: start_nb_offset_gen
-- generic map(
-- g_width => g_width
-- )
-- port map(
-- acam_intflag_p_i => acam_intflag_p,
-- clk_i => clk,
-- one_hz_p_i => one_hz_p,
-- reset_i => general_reset,
--
-- start_nb_offset_o => start_nb_offset
-- );
start_retrigger_block: start_retrigger_control
generic map(
g_width => g_width
)
port map(
acam_intflag_p_i => acam_intflag_p,
clk_i => clk,
one_hz_p_i => one_hz_p,
reset_i => general_reset,
start_nb_offset_o => start_nb_offset,
start_trig_o => start_trig
);
-- data_formatting_block: data_formatting
-- generic map(
-- g_width => g_width
-- )
-- port map(
-- acam_start01_i => acam_start01,
-- acam_timestamp_i => acam_timestamp,
-- acam_timestamp_valid_i => acam_timestamp_valid,
-- clk_i => clk_i,
-- reset_i => general_reset,
-- start_nb_offset_i => start_nb_offset,
-- utc_current_time_i => utc_current_time,
--
-- full_timestamp_o => full_timestamp,
-- full_timestamp_valid_o => full_timestamp_valid
-- );
data_formatting_block: data_formatting
generic map(
g_width => g_width
)
port map(
acam_start01_i => acam_start01,
acam_timestamp_i => acam_timestamp,
acam_timestamp_valid_i => acam_timestamp_valid,
clk_i => clk,
reset_i => general_reset,
start_nb_offset_i => start_nb_offset,
utc_current_time_i => utc_current_time,
full_timestamp_o => full_timestamp,
full_timestamp_valid_o => full_timestamp_valid
);
acam_timing_block: acam_timecontrol_interface
generic map(
......@@ -461,14 +474,13 @@ begin
int_flag_i => int_flag_i,
-- this is the config for acam test, in normal application connect the outputs
start_dis_o => open,
stop_dis_o => open,
-- start_dis_o => start_dis_o,
-- stop_dis_o => stop_dis_o,
start_dis_o => start_dis_o,
start_from_fpga_o => start_from_fpga_o,
stop_dis_o => stop_dis_o,
-- signals internal to the chip: interface with other modules
clk_i => clk,
one_hz_p_i => one_hz_p,
start_trig_i => start_trig,
reset_i => general_reset,
acam_errflag_p_o => acam_errflag_p,
......@@ -563,7 +575,11 @@ begin
dma_stall_i => dma_stall
);
clocks_and_resets_management_block: clk_rst_managr
clks_rsts_mgment: clk_rst_managr
generic map(
nb_of_reg => 68,
values_for_simulation => values_for_simulation
)
port map(
acam_refclk_i => acam_refclk_i,
pll_ld_i => pll_ld_i,
......@@ -577,7 +593,7 @@ begin
acam_refclk_o => acam_refclk,
general_reset_o => general_reset,
pll_cs_o => pll_cs,
pll_cs_o => pll_cs_o,
pll_dac_sync_o => pll_dac_sync_o,
pll_sdi_o => pll_sdi_o,
pll_sclk_o => pll_sclk_o,
......@@ -596,19 +612,6 @@ begin
current_value => open
);
spec_led_period <= spec_led_period_sim when values_for_simulation
else spec_led_period_syn;
spec_led: process
begin
if spec_led_count_done ='1' then
spec_led_red <= not(spec_led_red);
end if;
wait until spec_clk ='1';
end process;
spec_led_green <= pll_ld_i;
tdc_led_counter: countdown_counter
port map(
clk => clk,
......@@ -620,12 +623,51 @@ begin
current_value => open
);
tdc_led_status <= not(tdc_led_count_done);
spec_led: process
begin
if gnum_reset ='1' then
spec_led_red <= '0';
elsif spec_led_count_done ='1' then
spec_led_red <= not(spec_led_red);
end if;
wait until spec_clk ='1';
end process;
tdc_led: process
begin
if one_hz_p ='1' then
tdc_led_status <= '1';
elsif tdc_led_count_done = '1' then
tdc_led_status <= '0';
end if;
wait until clk ='1';
end process;
-- two_seconds: process
-- begin
-- if gnum_reset ='1' then
-- tdc_led_trig5 <= '0';
-- elsif one_hz_p ='1' then
-- tdc_led_trig5 <= not(tdc_led_trig5);
-- end if;
-- wait until clk ='1';
-- end process;
-- inputs
gnum_reset <= not(rst_n_a_i);
-- tdc_led_period <= tdc_led_period_sim when values_for_simulation
-- else tdc_led_period_syn;
spec_led_period <= spec_led_period_sim when values_for_simulation
else spec_led_period_syn;
visible_blink_length <= blink_length_sim when values_for_simulation
else blink_length_syn;
clock_period <= sim_clock_period when values_for_simulation
else syn_clock_period;
-- internal signals
spec_led_green <= pll_ld_i;
acm_adr(19) <= '0';
acm_adr(18 downto 0) <= csr_adr;
acm_cyc <= csr_cyc(0);
......@@ -635,28 +677,42 @@ begin
csr_ack(0) <= acm_ack;
csr_dat_r <= acm_dat_r;
clock_period <= sim_clock_period when values_for_simulation
else syn_clock_period;
pulse_delay <= x"00000000";
-- inputs
gnum_reset <= not(rst_n_a_i) or not(spec_aux1_i);
-- outputs
pll_cs_o <= pll_cs;
spec_led_green_o <= spec_led_green;
spec_led_red_o <= spec_led_red;
tdc_led_status_o <= tdc_led_status;
tdc_led_trig1_o <= tdc_led_trig1;
tdc_led_trig2_o <= tdc_led_trig2;
tdc_led_trig3_o <= tdc_led_trig3;
tdc_led_trig4_o <= tdc_led_trig4;
tdc_led_trig5_o <= tdc_led_trig5;
spec_led_green_o <= spec_led_green;
spec_led_red_o <= spec_led_red;
-- this is the config for acam test...
start_dis_o <= '0';
stop_dis_o <= '0';
start_from_fpga_o <= one_hz_p when spec_aux1_i ='0' else not(spec_aux0_i);
spec_aux2_o <= spec_aux0_i;
spec_aux3_o <= spec_aux1_i;
-- these will evolve as we implement all the features
mute_inputs_o <= '1';
term_en_1_o <= '1';
term_en_2_o <= '1';
term_en_3_o <= '1';
term_en_4_o <= '1';
term_en_5_o <= '1';
spec_aux5_o <= spec_aux0_i;
spec_aux4_o <= spec_aux1_i;
button_with_spec_clk: process
begin
spec_aux3_o <= spec_aux0_i;
wait until spec_clk ='1';
end process;
button_with_tdc_clk: process
begin
spec_aux2_o <= spec_aux0_i;
wait until clk ='1';
end process;
end rtl;
----------------------------------------------------------------------------------------------------
......
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