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FMC TDC 1ns 5cha - Gateware
Commit 552710a7 authored by penacoba's avatar penacoba
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New preliminary modules after design specification review 


git-svn-id: http://svn.ohwr.org/fmc-tdc@39 85dfdc96-de2c-444c-878d-45b388be74a9
parent a4e6cbd1
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Showing with 236 additions and 147 deletions
hdl/spec/src/rtl/acam_databus_interface.vhd
View file @ 552710a7
...@@ -174,11 +174,7 @@ begin ...@@ -174,11 +174,7 @@ begin
end case; end case;
end process; end process;
ef1 <= ef1_i; -- inputs from other blocks
ef2 <= ef2_i;
lf1 <= lf1_i;
lf2 <= lf2_i;
clk <= clk_i; clk <= clk_i;
reset <= reset_i; reset <= reset_i;
...@@ -188,13 +184,22 @@ begin ...@@ -188,13 +184,22 @@ begin
stb <= stb_i; stb <= stb_i;
we <= we_i; we <= we_i;
-- outputs to other blocks
ack_o <= ack;
dat_o <= ef1 & ef2 & lf1 & lf2 & data_bus_io;
-- inputs from the ACAM
ef1 <= ef1_i;
ef2 <= ef2_i;
lf1 <= lf1_i;
lf2 <= lf2_i;
-- outputs to the ACAM
address_o <= adr(3 downto 0); address_o <= adr(3 downto 0);
cs_n_o <= not(cs); cs_n_o <= not(cs);
oe_n_o <= '1'; oe_n_o <= '1';
rd_n_o <= not(rd); rd_n_o <= not(rd);
wr_n_o <= not(wr); wr_n_o <= not(wr);
ack_o <= ack;
dat_o <= ef1 & ef2 & lf1 & lf2 & data_bus_io;
end rtl; end rtl;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
......
hdl/spec/src/rtl/acam_timecontrol_interface.vhd
View file @ 552710a7
...@@ -34,11 +34,12 @@ entity acam_timecontrol_interface is ...@@ -34,11 +34,12 @@ entity acam_timecontrol_interface is
int_flag_i : in std_logic; int_flag_i : in std_logic;
start_dis_o : out std_logic; start_dis_o : out std_logic;
start_from_fpga_o : out std_logic;
stop_dis_o : out std_logic; stop_dis_o : out std_logic;
-- signals internal to the chip: interface with other modules -- signals internal to the chip: interface with other modules
clk_i : in std_logic; clk_i : in std_logic;
one_hz_p_i : in std_logic; start_trig_i : in std_logic;
reset_i : in std_logic; reset_i : in std_logic;
acam_errflag_p_o : out std_logic; acam_errflag_p_o : out std_logic;
...@@ -68,12 +69,13 @@ architecture rtl of acam_timecontrol_interface is ...@@ -68,12 +69,13 @@ architecture rtl of acam_timecontrol_interface is
signal clk : std_logic; signal clk : std_logic;
signal counter_reset : std_logic; signal counter_reset : std_logic;
signal one_hz_p : std_logic; signal start_trig : std_logic;
signal reset : std_logic; signal reset : std_logic;
signal s_int_flag : unsigned(2 downto 0); signal s_int_flag : unsigned(2 downto 0);
signal s_err_flag : unsigned(2 downto 0); signal s_err_flag : unsigned(2 downto 0);
signal start_dis : std_logic; signal start_dis : std_logic;
signal start_from_fpga : std_logic;
signal start_window : std_logic; signal start_window : std_logic;
signal window_inverted : std_logic; signal window_inverted : std_logic;
...@@ -137,14 +139,18 @@ begin ...@@ -137,14 +139,18 @@ begin
); );
start_window <= not(window_inverted); start_window <= not(window_inverted);
counter_reset <= reset or one_hz_p; counter_reset <= reset or start_trig;
start_from_fpga <= start_trig;
-- inputs
clk <= clk_i; clk <= clk_i;
one_hz_p <= one_hz_p_i; start_trig <= start_trig_i;
reset <= reset_i; reset <= reset_i;
-- outputs
start_dis_o <= start_dis; start_dis_o <= start_dis;
stop_dis_o <= '0'; stop_dis_o <= '0';
start_from_fpga_o <= start_from_fpga;
end rtl; end rtl;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
......
hdl/spec/src/rtl/data_polling.vhd → hdl/spec/src/rtl/data_engine.vhd
View file @ 552710a7
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
-- CERN-BE-CO-HT -- CERN-BE-CO-HT
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- --
-- unit name : data polling engine (data_polling) -- unit name : data polling engine (data_engine)
-- author : G. Penacoba -- author : G. Penacoba
-- date : June 2011 -- date : June 2011
-- version : Revision 1 -- version : Revision 1
...@@ -15,18 +15,19 @@ ...@@ -15,18 +15,19 @@
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- last changes: -- last changes:
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- to do: empty FIFO signals from Acam are missing (maybe putting them in the data?) -- to do:
-- other Acam configuration registers maybe... --
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
library IEEE; library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all; use IEEE.numeric_std.all;
use work.tdc_core_pkg.all;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- entity declaration for data_polling -- entity declaration for data_engine
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
entity data_polling is entity data_engine is
generic( generic(
g_width : integer :=32 g_width : integer :=32
); );
...@@ -41,22 +42,28 @@ entity data_polling is ...@@ -41,22 +42,28 @@ entity data_polling is
we_o : out std_logic; we_o : out std_logic;
-- signals internal to the chip: interface with other modules -- signals internal to the chip: interface with other modules
acam_config_reg_i : in config_vector;
clk_i : in std_logic; clk_i : in std_logic;
load_acam_config_i : in std_logic;
one_hz_p_i : in std_logic; one_hz_p_i : in std_logic;
reset_i : in std_logic; reset_i : in std_logic;
start_timer_reg_i : in std_logic_vector(7 downto 0);
acam_start01_o : out std_logic_vector(16 downto 0); acam_start01_o : out std_logic_vector(16 downto 0);
acam_timestamp_o : out std_logic_vector(28 downto 0); acam_timestamp_o : out std_logic_vector(28 downto 0);
acam_timestamp_valid_o : out std_logic acam_timestamp_valid_o : out std_logic
); );
end acam_databus_interface; end data_engine;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- architecture declaration for data_polling -- architecture declaration for data_engine
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
architecture rtl of data_polling is architecture rtl of data_engine is
type engine_state_ty is (wr_config, rest_wr, rd_timestamp, rest_rd);
signal engine_st, nxt_engine_st : engine_state_ty;
signal ef1 : std_logic;
signal ef2 : std_logic;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- architecture begins -- architecture begins
......
hdl/spec/src/rtl/start_nb_offset_gen.vhd → hdl/spec/src/rtl/start_retrigger_control.vhd
View file @ 552710a7
...@@ -2,11 +2,13 @@ ...@@ -2,11 +2,13 @@
-- CERN-BE-CO-HT -- CERN-BE-CO-HT
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- --
-- unit name : internal start number offset generator (start_nb_offset_gen) -- unit name : start retrigger control and internal start number offset generator
-- (start_retrigger_control)
-- author : G. Penacoba -- author : G. Penacoba
-- date : May 2011 -- date : July 2011
-- version : Revision 1 -- version : Revision 1
-- description : generates the offset to be added to the start number provided by tha Acam -- description : launches the start pulses and the ACAM generates the internal start retriggers.
-- Also generates the offset to be added to the start number provided by tha Acam
-- by counting the number of times the 1-Byte counter of the Acam is overloaded. -- by counting the number of times the 1-Byte counter of the Acam is overloaded.
-- The result is then multiplied by 256 (shifted by 8). -- The result is then multiplied by 256 (shifted by 8).
-- dependencies: -- dependencies:
...@@ -24,9 +26,9 @@ use IEEE.std_logic_1164.all; ...@@ -24,9 +26,9 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all; use IEEE.numeric_std.all;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- entity declaration for start_nb_offset_gen -- entity declaration for start_retrigger_control
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
entity start_nb_offset_gen is entity start_retrigger_control is
generic( generic(
g_width : integer :=32 g_width : integer :=32
); );
...@@ -35,15 +37,16 @@ entity start_nb_offset_gen is ...@@ -35,15 +37,16 @@ entity start_nb_offset_gen is
clk_i : in std_logic; clk_i : in std_logic;
one_hz_p_i : in std_logic; one_hz_p_i : in std_logic;
reset_i : in std_logic; reset_i : in std_logic;
start_nb_offset_o : out std_logic_vector(g_width-1 downto 0) start_nb_offset_o : out std_logic_vector(g_width-1 downto 0);
start_trig_o : out std_logic
); );
end start_nb_offset_gen; end start_retrigger_control;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- architecture declaration for start_nb_offset_gen -- architecture declaration for start_retrigger_control
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
architecture rtl of start_nb_offset_gen is architecture rtl of start_retrigger_control is
component incr_counter component incr_counter
generic( generic(
...@@ -67,6 +70,8 @@ signal offset_value : std_logic_vector(g_width-1 downto 0); ...@@ -67,6 +70,8 @@ signal offset_value : std_logic_vector(g_width-1 downto 0);
signal offset_to_shift : unsigned(g_width-1 downto 0); signal offset_to_shift : unsigned(g_width-1 downto 0);
signal one_hz_p : std_logic; signal one_hz_p : std_logic;
signal reset : std_logic; signal reset : std_logic;
signal start_nb_offset : std_logic_vector(g_width-1 downto 0);
signal start_trig : std_logic;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- architecture begins -- architecture begins
...@@ -89,12 +94,18 @@ begin ...@@ -89,12 +94,18 @@ begin
counter_reset <= reset or one_hz_p; counter_reset <= reset or one_hz_p;
offset_to_shift <= unsigned(offset_value); offset_to_shift <= unsigned(offset_value);
start_nb_offset_o <= std_logic_vector(shift_left(offset_to_shift,8)); start_nb_offset <= std_logic_vector(shift_left(offset_to_shift,8));
start_trig <= one_hz_p;
-- inputs
acam_intflag_p <= acam_intflag_p_i; acam_intflag_p <= acam_intflag_p_i;
clk <= clk_i; clk <= clk_i;
one_hz_p <= one_hz_p_i; one_hz_p <= one_hz_p_i;
reset <= reset_i; reset <= reset_i;
-- outputs
start_nb_offset_o <= start_nb_offset;
start_trig_o <= start_trig;
end rtl; end rtl;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
......
hdl/spec/src/rtl/tdc_core_pkg.vhd
View file @ 552710a7
...@@ -78,6 +78,10 @@ constant spec_led_period_syn : std_logic_vector(data_width-1 downto 0):=x"013 ...@@ -78,6 +78,10 @@ constant spec_led_period_syn : std_logic_vector(data_width-1 downto 0):=x"013
constant blink_length_syn : std_logic_vector(data_width-1 downto 0):=x"00BEBC20"; -- 100 ms at 125 MHz constant blink_length_syn : std_logic_vector(data_width-1 downto 0):=x"00BEBC20"; -- 100 ms at 125 MHz
constant blink_length_sim : std_logic_vector(data_width-1 downto 0):=x"000004E2"; -- 10 us at 125 MHz constant blink_length_sim : std_logic_vector(data_width-1 downto 0):=x"000004E2"; -- 10 us at 125 MHz
subtype config_register is std_logic_vector(27 downto 0);
type config_vector is array (10 downto 0) of config_register;
end tdc_core_pkg; end tdc_core_pkg;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
......
hdl/spec/src/rtl/top_tdc.vhd
View file @ 552710a7
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