Commit 5765c94d authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

hdl: SPEC top level with refurbished TDC core

parent caaf87ad
gn4124-core @ ffea5479
Subproject commit e0dcb3f9a3e6804f64c544743bdf46b5fcbbefab
Subproject commit ffea5479190c09938cbba9b7076953c5c41645f3
vme64x-core @ d8ae9867
Subproject commit e98eb58ca8757be8fdf4117d0d1d1c8bb2e238bc
Subproject commit d8ae98675b15a5dc6bf5cc9e7e3fcbdd266187f7
target = "xilinx"
action = "synthesis"
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "wr_spec_tdc"
syn_project = "wr_spec_tdc.xise"
syn_tool = "ise"
top_module = "wr_spec_tdc"
modules = { "local" : [ "../../top/spec" ] }
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Release 13.4 Map O.87xd (nt)
Xilinx Map Application Log File for Design 'spec_tdc'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol
high -xe c -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir
off -pr b -lc off -power off -o spec_tdc_map.ncd spec_tdc.ngd spec_tdc.pcf
Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Jul 08 10:27:13 2014
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 21 secs
Total CPU time at the beginning of Placer: 17 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:de9a1ea9) REAL time: 37 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:de9a1ea9) REAL time: 38 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:de9a1ea9) REAL time: 38 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:46e77852) REAL time: 1 mins 9 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:46e77852) REAL time: 1 mins 9 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:46e77852) REAL time: 1 mins 9 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:46e77852) REAL time: 1 mins 10 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:46e77852) REAL time: 1 mins 10 secs
Phase 9.8 Global Placement
..................................
........................................................
........................................................
..........................
Phase 9.8 Global Placement (Checksum:a3a2a52d) REAL time: 1 mins 42 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:a3a2a52d) REAL time: 1 mins 42 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:8078f7ee) REAL time: 1 mins 58 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:8078f7ee) REAL time: 1 mins 58 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:d7bfac99) REAL time: 1 mins 59 secs
Total REAL time to Placer completion: 2 mins 6 secs
Total CPU time to Placer completion: 1 mins 47 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc_mezz/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_227_o_Mux_41_o
is sourced by a combinatorial pin. This is not good design practice. Use the
CE pin to control the loading of data into the flip-flop.
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 1
Slice Logic Utilization:
Number of Slice Registers: 3,584 out of 54,576 6%
Number used as Flip Flops: 3,559
Number used as Latches: 2
Number used as Latch-thrus: 0
Number used as AND/OR logics: 23
Number of Slice LUTs: 3,881 out of 27,288 14%
Number used as logic: 3,781 out of 27,288 13%
Number using O6 output only: 2,251
Number using O5 output only: 328
Number using O5 and O6: 1,202
Number used as ROM: 0
Number used as Memory: 2 out of 6,408 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 2
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 98
Number with same-slice register load: 53
Number with same-slice carry load: 45
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,510 out of 6,822 22%
Nummber of MUXCYs used: 1,284 out of 13,644 9%
Number of LUT Flip Flop pairs used: 4,827
Number with an unused Flip Flop: 1,538 out of 4,827 31%
Number with an unused LUT: 946 out of 4,827 19%
Number of fully used LUT-FF pairs: 2,343 out of 4,827 48%
Number of unique control sets: 129
Number of slice register sites lost
to control set restrictions: 309 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 134 out of 296 45%
Number of LOCed IOBs: 134 out of 134 100%
IOB Flip Flops: 55
Specific Feature Utilization:
Number of RAMB16BWERs: 11 out of 116 9%
Number of RAMB8BWERs: 0 out of 232 0%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 60 out of 376 15%
Number used as ILOGIC2s: 40
Number used as ISERDES2s: 20
Number of IODELAY2/IODRP2/IODRP2_MCBs: 2 out of 376 1%
Number used as IODELAY2s: 2
Number used as IODRP2s: 0
Number used as IODRP2_MCBs: 0
Number of OLOGIC2/OSERDES2s: 35 out of 376 9%
Number used as OLOGIC2s: 15
Number used as OSERDES2s: 20
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 1 out of 8 12%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 58 0%
Number of GTPA1_DUALs: 0 out of 2 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 4 25%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.70
Peak Memory Usage: 355 MB
Total REAL time to MAP completion: 2 mins 11 secs
Total CPU time to MAP completion: 1 mins 52 secs
Mapping completed.
See MAP report file "spec_tdc_map.mrp" for details.
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sim_tool = "modelsim"
top_module="main"
syn_device="xc6slx45t"
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
include_dirs=[ "../../sim", "../include", "../../ip_cores/gn4124-core/hdl/gn4124core/sim/gn4124_bfm" ]
files = [ "main.sv" ]
modules = { "local" : [ "../../top/spec", "../../ip_cores/gn4124-core/hdl/gn4124core/sim/gn4124_bfm" ] }
`include "simdrv_defs.svh"
`include "gn4124_bfm.svh"
`include "timestamp_fifo_regs.vh"
module fake_acam(
input [3:0] addr,
output reg [27:0] data,
input wr,
input rd,
output reg ef1,
output reg ef2
);
typedef struct {
int channel;
time ts;
} acam_fifo_entry;
acam_fifo_entry fifo1[$], fifo2[$];
task pulse(int channel, time ts);
acam_fifo_entry ent;
ent.channel = channel % 4;
ent.ts = ts;
if (channel >= 0 && channel <= 3)
fifo1.push_back(ent);
else
fifo2.push_back(ent);
#100ns;
if(fifo1.size())
ef1 = 0;
if(fifo2.size())
ef2 = 0;
endtask // pulse
initial begin
ef1 = 1;
ef2 = 1;
data = 28'bz;
end
always@(negedge rd) begin
if (addr == 8) begin
acam_fifo_entry ent;
ent=fifo1.pop_front();
data <= ent.ts | (ent.channel << 26) | (1<<17);
end else if (addr == 9) begin
acam_fifo_entry ent;
ent=fifo2.pop_front();
data <= ent.ts | (ent.channel << 26) | (1<<17);
end else
data <= 28'bz;
#10ns;
ef1 <= (fifo1.size() ? 0 : 1);
ef2 <= (fifo2.size() ? 0 : 1);
end
endmodule
module main;
reg rst_n = 0;
reg clk_125m = 0, clk_20m = 0;
always #4ns clk_125m <= ~clk_125m;
always #25ns clk_20m <= ~clk_20m;
initial begin
repeat(20) @(posedge clk_125m);
rst_n = 1;
end
reg clk_acam = 0;
reg clk_62m5 = 0;
always@(posedge clk_125m)
clk_62m5 <= ~clk_62m5;
always@(posedge clk_62m5)
clk_acam <= ~clk_acam;
wire [3:0] tdc_addr;
wire [27:0] tdc_data;
IGN4124PCIMaster I_Gennum ();
wr_spec_tdc #(
.g_with_wr_phy(0),
.g_simulation(1)
) DUT (
.clk_125m_pllref_p_i(clk_125m),
.clk_125m_pllref_n_i(~clk_125m),
.clk_125m_gtp_p_i(clk_125m),
.clk_125m_gtp_n_i(~clk_125m),
.tdc_clk_125m_p_i(clk_125m),
.tdc_clk_125m_n_i(~clk_125m),
.acam_refclk_p_i(clk_acam),
.acam_refclk_n_i(~clk_acam),
.clk_20m_vcxo_i(clk_20m),
.pll_status_i(1'b1),
.ef1_i(tdc_ef1),
.ef2_i(tdc_ef2),
.err_flag_i(1'b0),
.int_flag_i(1'b0),
.rd_n_o(tdc_rd_n),
.data_bus_io(tdc_data),
.address_o(tdc_addr),
`GENNUM_WIRE_SPEC_PINS(I_Gennum)
);
fake_acam ACAM(
.addr(tdc_addr),
.data(tdc_data),
.wr(1'b0),
.rd(tdc_rd_n),
.ef1(tdc_ef1),
.ef2(tdc_ef2)
);
reg force_irq = 0;
initial begin
CBusAccessor acc;
const uint64_t tdc1_base = 'h40000;
uint64_t d;
acc = I_Gennum.get_accessor();
#100us;
$display("Accessor: %x", acc);
$display("Un-reset FMCs...");
acc.write('h02000c, 'h3);
#500us;
acc.read('h040000, d);
$display("TDC SDB ID : %x", d);
acc.write('h420a0, 1234); // set UTC
acc.write('h420fc, 1<<9); // load UTC
acc.write('h43004, 'hf); // enable EIC irq
acc.write('h42084, 'h1f0000); // enable all ACAM inputs
acc.write('h420fc, (1<<0)); // start acquisition
acc.write('h420fc, (1<<0)); // start acquisition
acc.write('h42090, 2); // thr = 2 ts
acc.write('h42094, 10); // thr = 10 ms
#300us;
fork
forever begin
acc.read('h45000 + `ADDR_TSF_CSR, d);
$display("TSF CSR %x", d);
if(d&1) begin
uint64_t t0,t1,t2,t3;
acc.write('h45000 + `ADDR_TSF_CSR, 0);
acc.read('h45000 + `ADDR_TSF_LTS0, t0);
acc.read('h45000 + `ADDR_TSF_LTS1, t1);
acc.read('h45000 + `ADDR_TSF_LTS2, t2);
acc.read('h45000 + `ADDR_TSF_LTS3, t3);
$display("Last: %08x %08x %08x %08x",t0,t1,t2,t3);
end
acc.read('h45000 + `ADDR_TSF_FIFO_CSR, d);
// $display("FIFO CSR %x", d);
/* -----\/----- EXCLUDED -----\/-----
if(!(d&`TSF_FIFO_CSR_EMPTY)) begin
uint64_t t0,t1,t2,t3;
acc.read('hc15000 + `ADDR_TSF_FIFO_R0, t0);
acc.read('hc15000 + `ADDR_TSF_FIFO_R1, t1);
acc.read('hc15000 + `ADDR_TSF_FIFO_R2, t2);
acc.read('hc15000 + `ADDR_TSF_FIFO_R3, t3);
$display("Fifo: %08x %08x %08x %08x",t0,t1,t2,t3);
end
-----/\----- EXCLUDED -----/\----- */
end
forever begin
$display("Pulse!");
ACAM.pulse(0, 0);
ACAM.pulse(1, 0);
ACAM.pulse(2, 0);
#10us;
end
join
end
endmodule // main
vsim -t 1ps -L unisim work.main -voptargs=+acc
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
radix -hexadecimal
run 1ms
\ No newline at end of file
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sim_tool = "modelsim"
top_module="main"
syn_device="xc6slx150t"
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
vlog_opt="+incdir+../../sim +incdir+../include/vme64x_bfm +incdir+../include "
include_dirs=[ "../../sim", "../include", "../../ip_cores/vme64x-core/hdl/vme64x-core/sim/vme64x_bfm" ]
files = [ "main.sv" ]
......
files = ["synthesis_descriptor.vhd",
"wr_spec_tdc.ucf",
"wr_spec_tdc.vhd"];
fetchto = "../../ip_cores"
modules = {
"local" : [ "../../rtl/",
"../../ip_cores/gn4124-core",
"../../ip_cores/general-cores",
"../../ip_cores/wr-cores"
]
}
#!/bin/bash
wbgen2 -D 1.html -V fmc_tdc_direct_readout_slave.vhd -H record -p fmc_tdc_direct_readout_slave_pkg.vhd -K regs.vh -s defines -C fmctdc-direct.h fmc_tdc_direct_readout_slave.wb
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity spec_reset_gen is
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end spec_reset_gen;
architecture behavioral of spec_reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal button_synced_n : std_logic;
signal pcie_synced_n : std_logic;
signal powerup_n : std_logic := '0';
begin -- behavioral
U_EdgeDet_PCIe : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_pcie_n_a_i,
ppulse_o => pcie_synced_n);
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_button_n_a_i,
synced_o => button_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
end behavioral;
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......@@ -25,18 +25,14 @@
-- All these cores communicate with the VME core through the WISHBONE. |
-- The SDB crossbar is mapping the different slaves into the WISHBONE address space. |
-- |
-- The speed for the VME core is 62.5 MHz. The TDC mezzanine cores however operate at|
-- 125 MHz (like this the TDC core can keep up to speed with the maximum speed the |
-- ACAM can be receiving timestamps). The crossing from the 62.5 MHz world to the |
-- 125 MHz world takes place through dedicated clock_crossing modules. |
-- The speed for the VME core is 62.5 MHz. The TDC mezzanine cores
-- internally operate at 125 MHz, but the wishbone bus works still
-- at system-wide 62.5 MHz clock.
-- |
-- The 62.5 MHz clock comes from an internal Xilinx FPGA PLL, using the 20MHz VCXO of|
-- the SVEC board. |
-- |
-- The 125 MHz clock for each TDC mezzanine comes from the PLL located on it. |
-- A clks_rsts_manager unit is responsible for automatically configuring the PLL upon|
-- the FPGA startup, using the 62.5 MHz clock. The clks_rsts_manager is keeping the |
-- the TDC mezzanine core under reset until the respective PLL gets locked. |
-- |
-- Upon powering up of the FPGA as well as after a VME reset, the whole logic gets |
-- reset (FMC1 125 MHz, FMC2 125 MHz and 62.5 MHz). This also triggers a |
......@@ -53,23 +49,23 @@
-- | | |____________________________| \ | | | |
-- | 62.5MHz \ | | | |
-- | | ____________________________ \| | _____ | |
-- | | | ____________ _______ | | | | | | |
-- | |---|->| | | clk | | | | | | | |
-- | | | | TDC mezz 1 | | cross | | | | | | | |
-- FMC1 | | | |____________| |_______| |\ | | | | | |
-- | | | FMC1 125MHz | \ | | | | | |
-- | | | ___________________ | \ | | | | | |
-- | |---|--->|_clks_rsts_manager_| | \ | | | | | |
-- | | | | | | | | | |
-- | |---| | | | | | | |
-- | | | | | | | | | |
-- FMC1 | | | TDC mezzanine 1 |\ | | | | | |
-- | | | wrapper | \ | | | | | |
-- | | | | \ | | | | | |
-- | |---| | \ | | | | | |
-- | | |____________________________| \| | | | | |
-- | | | | | | | |
-- | | ____________________________ | | | | | |
-- | | | ____________ _______ | | | | | | |
-- | | | | | | clk | | | | | | | |
-- | |---|->| TDC mezz 2 | | cross | | | S | | V | | |
-- FMC2 | | | |____________| |_______| | ---- | | | | | |
-- | | | FMC2 125MHz | | | | | | |
-- | | | ___________________ | | | | | | |
-- | |---|--->|_clks_rsts_manager_| | | | | | | |
-- | | | | | | | | | |
-- | | | | | | | | | |
-- | |---| | | S | | V | | |
-- FMC2 | | | TDC mezzanine 2 | ---- | | | | | |
-- | | | wrapper | | | | | | |
-- | | | | | | | | | |
-- | |---| | | | | | | |
-- | |____________________________| | D | <--> | M | | |
-- | | | | | | |
-- | ____________________________ | | | | | |
......@@ -137,10 +133,8 @@ use work.synthesis_descriptor.all;
-- Entity declaration for top_tdc
--=================================================================================================
entity wr_svec_tdc is
generic
(g_span : integer := 32; -- address span in bus interfaces
g_width : integer := 32; -- data width in bus interfaces
g_simulation : boolean := false;
generic (
g_simulation : boolean := false;
g_with_wr_phy : boolean := true);
port
(-- SVEC carrier
......@@ -324,6 +318,15 @@ end wr_svec_tdc;
--=================================================================================================
architecture rtl of wr_svec_tdc is
function f_bool2int (x : boolean) return integer is
begin
if(x) then
return 1;
else
return 0;
end if;
end f_bool2int;
component spec_serial_dac is
generic (
g_num_data_bits : integer;
......@@ -664,7 +667,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
U_WR_CORE : xwr_core
generic map
(g_simulation => 0,
(g_simulation => f_bool2int(g_simulation),
g_phys_uart => true,
g_virtual_uart => true,
g_with_external_clock_input => false,
......
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