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FMC TDC 1ns 5cha - Gateware
Commit 6185eb76 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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top/svec: reorganized to use WRPC Board wrapper

parent e665f6c1
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hdl/top/svec/Manifest.py
View file @ 6185eb76
......@@ -8,7 +8,13 @@ modules = {
"local" : [ "../../rtl/",
"../../ip_cores/vme64x-core",
"../../ip_cores/general-cores",
"../../ip_cores/wr-cores"
]
"../../ip_cores/wr-cores",
"../../ip_cores/wr-cores/board/svec"
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/vme64x-core.git",
"git://ohwr.org/hdl-core-lib/etherbone-core.git",
],
}
hdl/top/svec/wr_svec_tdc.ucf
View file @ 6185eb76
......@@ -600,7 +600,7 @@ NET "sfp_rxp_i" LOC = D22;
NET "sfp_rxn_i" LOC = C22;
NET "sfp_los_i" LOC = W25;
NET "sfp_mod_def0_b" LOC = Y26;
NET "sfp_mod_def0_i" LOC = Y26;
NET "sfp_mod_def1_b" LOC = Y27;
NET "sfp_mod_def2_b" LOC = AA24;
#NET "sfp_rate_select_o" LOC = W24;
......@@ -608,7 +608,7 @@ NET "sfp_tx_disable_o" LOC = AA25;
NET "sfp_tx_fault_i" LOC = AA27;
NET "sfp_los_i" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def0_b" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def0_i" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def1_b" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def2_b" IOSTANDARD = LVCMOS33;
#NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS33";
......@@ -649,7 +649,7 @@ NET "por_n_i" IOSTANDARD = LVCMOS33;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
# 62.5MHz Xilinx PLL clock/reset
NET "clk_62m5_sys" TNM_NET = "clk_62m5_sys";
NET "clk_sys_62m5" TNM_NET = "clk_sys_62m5";
# 125MHz PLL ref
NET "clk_125m_pllref_n_i" LOC = AB30;
......@@ -681,24 +681,23 @@ NET "tdc2_125m_clk_n_i" TNM_NET = "tdc2_125m_clk_n_i";
TIMESPEC TS_tdc2_tdc_125m_clk_n_i = PERIOD "tdc2_125m_clk_n_i" 8 ns HIGH 50 %;
# TS_IGNORE
TIMESPEC ts_ignore_xclock1 = FROM "clk_62m5_sys" TO "tdc2_125m_clk" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock1 = FROM "clk_62m5_sys" TO "tdc2_125m_clk" 20 ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock2 = FROM "tdc2_125m_clk" TO "clk_62m5_sys" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock2 = FROM "tdc2_125m_clk" TO "clk_62m5_sys" 20 ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock3 = FROM "clk_62m5_sys" TO "tdc2_125m_clk" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock3 = FROM "clk_62m5_sys" TO "tdc2_125m_clk" 20 ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "tdc2_125m_clk" TO "clk_62m5_sys" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "clk_20m_vcxo_i" TO "clk_62m5_sys" 200ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "clk_62m5_sys" TO "clk_20m_vcxo_i" 200ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "clk_62m5_sys" TO "clk_20m_vcxo_i" 200 ns DATAPATHONLY;
#Created by Constraints Editor (xc6slx150t-fgg900-3) - 2015/03/31
NET "gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>;
TIMESPEC TS_gen_with_wr_phy_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50 %;
TIMESPEC ts_ignore_xclock1 = FROM "clk_sys_62m5" TO "tdc2_125m_clk" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock1 = FROM "clk_sys_62m5" TO "tdc2_125m_clk" 20 ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock2 = FROM "tdc2_125m_clk" TO "clk_sys_62m5" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock2 = FROM "tdc2_125m_clk" TO "clk_sys_62m5" 20 ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock3 = FROM "clk_sys_62m5" TO "tdc2_125m_clk" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock3 = FROM "clk_sys_62m5" TO "tdc2_125m_clk" 20 ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "tdc2_125m_clk" TO "clk_sys_62m5" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "clk_20m_vcxo_i" TO "clk_sys_62m5" 200ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "clk_sys_62m5" TO "clk_20m_vcxo_i" 200ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "clk_sys_62m5" TO "clk_20m_vcxo_i" 200 ns DATAPATHONLY;
#TIMESPEC TS_gen_with_wr_phy_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50 %;
#Created by Constraints Editor (xc6slx150t-fgg900-3) - 2017/12/06
NET "cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>;
TIMESPEC TS_cmp_xwrc_board_svec_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch1_gtp_clkout_int_1_ = PERIOD "cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
# PlanAhead Generated miscellaneous constraints
NET "tdc1_address_o[3]" SLEW = FAST;
NET "tdc1_address_o[2]" SLEW = FAST;
NET "tdc1_address_o[1]" SLEW = FAST;
......@@ -768,3 +767,9 @@ INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_skew_limit = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
# Force PPS output to always be placed as IOB register
INST "cmp_xwrc_board_svec/cmp_board_common/cmp_xwr_core/wrpc/pps_gen/wrapped_ppsgen/pps_out_o" IOB = FORCE;
# External async reset
NET "por_n_i" TIG;
NET "vme_rst_n_i" TIG;
hdl/top/svec/wr_svec_tdc.vhd
View file @ 6185eb76
......@@ -87,6 +87,7 @@
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Grzegorz Daniluk (Grzegorz.Daniluk@cern.ch)
-- Date 05/2014 |
-- Version v2 |
-- Depends on |
......@@ -95,6 +96,7 @@
-- Last changes |
-- 08/2013 v1 EG design for SVEC; two cores; synchronizer between vme and the cores |
-- 05/2014 v2 EG added White Rabbit |
-- 12/2017 v7 GD Top file reorganized to benefit from WRPC Board wrapper.
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -119,10 +121,9 @@ use IEEE.numeric_std.all;
use work.tdc_core_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.wr_xilinx_pkg.all;
use work.vme64x_pkg.all;
use work.wr_board_pkg.all;
use work.wr_svec_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
......@@ -152,7 +153,7 @@ entity wr_svec_tdc is
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic := '0';
sfp_rxn_i : in std_logic := '1';
sfp_mod_def0_b : in std_logic; -- SFP detect pin
sfp_mod_def0_i : in std_logic; -- SFP detect pin
sfp_mod_def1_b : inout std_logic; -- SFP scl
sfp_mod_def2_b : inout std_logic; -- SFP sda
sfp_rate_select_b : inout std_logic := '0';
......@@ -412,36 +413,24 @@ architecture rtl of wr_svec_tdc is
-- Signals --
---------------------------------------------------------------------------------------------------
signal areset_n : std_logic;
-- Clocks
-- CLOCK DOMAIN: 20 MHz VCXO clock on SVEC carrier board: clk_20m_vcxo_i
signal clk_20m_vcxo_buf, clk_20m_vcxo : std_logic;
-- CLOCK DOMAIN: 62.5 MHz system clock derived from clk_20m_vcxo_i by a Xilinx PLL: clk_62m5_sys
signal clk_62m5_sys, pllout_clk_sys : std_logic;
signal pllout_clk_sys_fb, sys_locked : std_logic;
signal clk_sys_62m5 : std_logic;
-- CLOCK DOMAIN: 125 MHz clock from PLL on TDC1: tdc1_125m_clk
signal tdc1_125m_clk : std_logic;
signal tdc1_125m_clk : std_logic;
signal tdc1_send_dac_word_p : std_logic;
signal tdc1_dac_word : std_logic_vector(23 downto 0);
-- CLOCK DOMAIN: 125 MHz clock from PLL on TDC2: tdc2_125m_clk
signal tdc2_125m_clk : std_logic;
signal tdc2_send_dac_word_p : std_logic;
signal tdc2_dac_word : std_logic_vector(23 downto 0);
-- WHITE RABBIT CLOCKS:
signal pllout_clk_dmtd, pllout_clk_fb_dmtd : std_logic;
signal pllout_clk_fb_pllref : std_logic;
signal clk_125m_pllref, clk_125m_gtp : std_logic;
signal clk_dmtd : std_logic;
attribute buffer_type : string; --" {bufgdll | ibufg | bufgp | ibuf | bufr | none}";
attribute buffer_type of clk_125m_pllref : signal is "BUFG";
---------------------------------------------------------------------------------------------------
-- Resets
-- asynchronous reset from the FPGA inputs VME_RST_n_i and por_n_i
signal por_rst_n_a : std_logic;
signal powerup_rst_cnt : unsigned(7 downto 0) := "00000000";
-- system reset, synched with 62.5 MHz clock,driven by the VME reset and power-up reset pins.
signal rst_n_sys : std_logic;
signal rst_sys_62m5_n : std_logic;
-- reset input to the clks_rsts_manager units of the two TDC cores;
-- this reset initiates the configuration of the mezzanines PLL
signal tdc1_soft_rst_n : std_logic; -- driven by carrier CSR reserved bit 0
......@@ -462,21 +451,12 @@ architecture rtl of wr_svec_tdc is
---------------------------------------------------------------------------------------------------
-- White Rabbit signals to TDC mezzanine
signal tm_link_up, tm_time_valid : std_logic;
signal tm_utc : std_logic_vector(39 downto 0);
signal tm_tai : std_logic_vector(39 downto 0);
signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_clk_aux_lock_en, tm_clk_aux_locked: std_logic_vector(1 downto 0);
-- White Rabbit signals to clks_rsts_manager
signal tm_dac_value : std_logic_vector(23 downto 0);
signal tm_dac_wr_p : std_logic_vector(1 downto 0);
-- White Rabbit PHY
signal phy_tx_data, phy_rx_data : std_logic_vector(7 downto 0);
signal phy_tx_k, phy_rx_k : std_logic_vector(0 downto 0);
signal phy_tx_enc_err, phy_rx_rbclk,phy_tx_disparity : std_logic;
signal phy_rx_enc_err, phy_rst, phy_loopen : std_logic;
signal phy_rx_bitslide : std_logic_vector(3 downto 0);
-- White Rabbit serial DAC
signal dac_hpll_load_p1, dac_dpll_load_p1 : std_logic;
signal dac_hpll_data, dac_dpll_data : std_logic_vector(15 downto 0);
-- White Rabbit to mezzanine EEPROM
signal wrc_scl_out, wrc_scl_in : std_logic;
signal wrc_sda_out, wrc_sda_in : std_logic;
......@@ -484,7 +464,7 @@ architecture rtl of wr_svec_tdc is
signal sfp_scl_out, sfp_scl_in : std_logic;
signal sfp_sda_out, sfp_sda_in : std_logic;
-- White Rabbit Carrier 1-Wire
signal wrc_owr_en, wrc_owr_in : std_logic_vector(1 downto 0);
signal wrc_owr_oe, wrc_owr_data : std_logic;
---------------------------------------------------------------------------------------------------
-- Crossbar
......@@ -494,6 +474,7 @@ architecture rtl of wr_svec_tdc is
-- WISHBONE to crossbar slave port
signal cnx_slave_out : t_wishbone_slave_out_array (c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array (c_NUM_WB_SLAVES-1 downto 0);
signal vme_wb_out : t_wishbone_master_out;
signal vme_wb_in : t_wishbone_master_in;
---------------------------------------------------------------------------------------------------
......@@ -508,339 +489,21 @@ architecture rtl of wr_svec_tdc is
signal tdc2_scl_oen, tdc2_scl_in : std_logic;
signal tdc2_sda_oen, tdc2_sda_in : std_logic;
signal carrier_owr_en, carrier_owr_i : std_logic_vector(c_FMC_ONEWIRE_NB - 1 downto 0);
-- LEDs
signal led_state : std_logic_vector(15 downto 0);
signal tdc1_ef, tdc2_ef, led_tdc1_ef : std_logic;
signal led_tdc2_ef, led_vme_access : std_logic;
signal wrabbit_led_red, wrabbit_led_green : std_logic;
signal wr_led_act, wr_led_link : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- 62.5 MHz system clock --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
svec_clk_ibuf : IBUFG
port map
(I => clk_20m_vcxo_i,
O => clk_20m_vcxo_buf);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_sys_clk_pll : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8, -- 125 MHz x 8 = 1 GHz
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16, -- 125 MHz, not used
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 16,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
port map
(CLKFBOUT => pllout_clk_sys_fb,
CLKOUT0 => pllout_clk_sys,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => sys_locked,
RST => '0',
CLKFBIN => pllout_clk_sys_fb,
CLKIN => clk_125m_pllref);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_clk_sys_buf : BUFG
port map
(O => clk_62m5_sys,
I => pllout_clk_sys);
---------------------------------------------------------------------------------------------------
-- 62.5 MHz Reset --
---------------------------------------------------------------------------------------------------
-- SVEC power-up reset in the clk_62m5_sys domain: rst_n_sys is asserted asynchronously upon VME
-- reset or SVEC AFPGA power-on reset. If none of these signals is asserted at startup, the process
-- waits for the system clock PLL to lock + additional 256 clk_62m5_sys cycles before de-asserting
-- the reset.
p_powerup_reset : process(clk_62m5_sys, por_rst_n_a)
begin
if(por_rst_n_a = '0') then
rst_n_sys <= '0';
elsif rising_edge(clk_62m5_sys) then
if sys_locked = '1' then
if(powerup_rst_cnt = "11111111") then
rst_n_sys <= '1';
else
rst_n_sys <= '0';
powerup_rst_cnt <= powerup_rst_cnt + 1;
end if;
else
rst_n_sys <= '0';
powerup_rst_cnt <= "00000000";
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
por_rst_n_a <= VME_RST_n_i and por_n_i;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
tdc1_soft_rst_n <= carrier_info_fmc_rst(0) and rst_n_sys;
tdc2_soft_rst_n <= carrier_info_fmc_rst(1) and rst_n_sys;
---------------------------------------------------------------------------------------------------
-- 62.5 MHz DMTD clock --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_dmtd_clk_pll : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16, -- not used
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map
(CLKFBOUT => pllout_clk_fb_dmtd,
CLKOUT0 => pllout_clk_dmtd,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => '0',
CLKFBIN => pllout_clk_fb_dmtd,
CLKIN => clk_20m_vcxo_buf);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_clk_dmtd_buf : BUFG
port map
(O => clk_dmtd,
I => pllout_clk_dmtd);
---------------------------------------------------------------------------------------------------
-- 125 MHz clk for White Rabbit core --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
U_Buf_CLK_PLL : IBUFGDS
generic map
(DIFF_TERM => true,
IBUF_LOW_PWR => true) -- Low power (TRUE) vs. performance (FALSE) setting for referenced
port map
(O => clk_125m_pllref, -- Buffer output
I => clk_125m_pllref_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i); -- Diff_n buffer input (connect directly to top-level port)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
U_Buf_CLK_GTP : IBUFDS
generic map
(DIFF_TERM => true,
IBUF_LOW_PWR => false)
port map
(O => clk_125m_gtp,
I => clk_125m_gtp_p_i,
IB => clk_125m_gtp_n_i);
---------------------------------------------------------------------------------------------------
-- White Rabbit Core + PHY --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
U_WR_CORE : xwr_core
generic map
(g_simulation => f_bool2int(g_simulation),
g_phys_uart => true,
g_virtual_uart => true,
g_with_external_clock_input => false,
g_board_name => "SVEC",
g_aux_clks => 2,
g_ep_rxbuf_size => 1024,
g_dpram_initf => "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram",
g_dpram_size => 131072/4,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_softpll_enable_debugger => false,
g_pcs_16bit => false,
g_records_for_phy => false)
port map
(clk_sys_i => clk_62m5_sys,
clk_dmtd_i => clk_dmtd,
clk_ref_i => clk_125m_pllref,
clk_aux_i(0) => tdc1_125m_clk,
clk_aux_i(1) => tdc2_125m_clk,
rst_n_i => rst_n_sys,
-- DAC
dac_hpll_load_p1_o => dac_hpll_load_p1,
dac_hpll_data_o => dac_hpll_data,
dac_dpll_load_p1_o => dac_dpll_load_p1,
dac_dpll_data_o => dac_dpll_data,
-- PHY
phy_ref_clk_i => clk_125m_pllref,
phy_tx_data_o => phy_tx_data,
phy_tx_k_o => phy_tx_k,
phy_tx_disparity_i => phy_tx_disparity,
phy_tx_enc_err_i => phy_tx_enc_err,
phy_rx_data_i => phy_rx_data,
phy_rx_rbclk_i => phy_rx_rbclk,
phy_rx_k_i => phy_rx_k,
phy_rx_enc_err_i => phy_rx_enc_err,
phy_rx_bitslide_i => phy_rx_bitslide,
phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen,
-- SPEC LEDs
led_act_o => wrabbit_led_red,
led_link_o => wrabbit_led_green,
-- SFP
scl_o => wrc_scl_out,
scl_i => wrc_scl_in,
sda_o => wrc_sda_out,
sda_i => wrc_sda_in,
sfp_scl_o => sfp_scl_out,
sfp_scl_i => sfp_scl_in,
sfp_sda_o => sfp_sda_out,
sfp_sda_i => sfp_sda_in,
sfp_det_i => sfp_mod_def0_b,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
-- 1-wire
owr_en_o => wrc_owr_en,
owr_i => wrc_owr_in,
-- WISHBONE
slave_i => cnx_master_out(c_SLAVE_WRCORE),
slave_o => cnx_master_in(c_SLAVE_WRCORE),
-- Timimg info for TDC core
tm_link_up_o => tm_link_up,
tm_dac_value_o => tm_dac_value,
tm_dac_wr_o => tm_dac_wr_p,
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en,
tm_clk_aux_locked_o => tm_clk_aux_locked,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_utc,
tm_cycles_o => tm_cycles,
-- SPI Flash
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
-- not used
btn1_i => '0',
btn2_i => '0',
pps_p_o => fp_gpio1_o,
-- aux reset
rst_aux_n_o => open);
gen_with_wr_phy: if g_with_wr_phy generate
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
U_GTP : wr_gtp_phy_spartan6
generic map
(g_simulation => 0,
g_enable_ch0 => 0,
g_enable_ch1 => 1)
port map
(gtp_clk_i => clk_125m_gtp,
ch0_ref_clk_i => clk_125m_pllref,
ch0_tx_data_i => x"00",
ch0_tx_k_i => '0',
ch0_tx_disparity_o => open,
ch0_tx_enc_err_o => open,
ch0_rx_rbclk_o => open,
ch0_rx_data_o => open,
ch0_rx_k_o => open,
ch0_rx_enc_err_o => open,
ch0_rx_bitslide_o => open,
ch0_rst_i => '1',
ch0_loopen_i => '0',
ch1_ref_clk_i => clk_125m_pllref,
ch1_tx_data_i => phy_tx_data,
ch1_tx_k_i => phy_tx_k(0),
ch1_tx_disparity_o => phy_tx_disparity,
ch1_tx_enc_err_o => phy_tx_enc_err,
ch1_rx_data_o => phy_rx_data,
ch1_rx_rbclk_o => phy_rx_rbclk,
ch1_rx_k_o => phy_rx_k(0),
ch1_rx_enc_err_o => phy_rx_enc_err,
ch1_rx_bitslide_o => phy_rx_bitslide,
ch1_rst_i => phy_rst,
ch1_loopen_i => '0', -- phy_loopen,
pad_txn0_o => open,
pad_txp0_o => open,
pad_rxn0_i => '0',
pad_rxp0_i => '0',
pad_txn1_o => sfp_txn_o,
pad_txp1_o => sfp_txp_o,
pad_rxn1_i => sfp_rxn_i,
pad_rxp1_i => sfp_rxp_i);
end generate gen_with_wr_phy;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
U_DAC_Helper : spec_serial_dac
generic map
(g_num_data_bits => 16,
g_num_extra_bits => 8,
g_num_cs_select => 1)
port map
(clk_i => clk_62m5_sys,
rst_n_i => rst_n_sys,
value_i => dac_hpll_data,
cs_sel_i => "1",
load_i => dac_hpll_load_p1,
sclk_divsel_i => "010",
dac_cs_n_o(0) => pll20dac_sync_n_o,
dac_sclk_o => pll20dac_sclk_o,
dac_sdata_o => pll20dac_din_o,
xdone_o => open);
U_DAC_Main : spec_serial_dac
generic map
(g_num_data_bits => 16,
g_num_extra_bits => 8,
g_num_cs_select => 1)
port map
(clk_i => clk_62m5_sys,
rst_n_i => rst_n_sys,
value_i => dac_dpll_data,
cs_sel_i => "1",
load_i => dac_dpll_load_p1,
sclk_divsel_i => "010",
dac_cs_n_o(0) => pll25dac_sync_n_o,
dac_sclk_o => pll25dac_sclk_o,
dac_sdata_o => pll25dac_din_o,
xdone_o => open);
areset_n <= vme_rst_n_i and por_n_i;
tdc1_soft_rst_n <= carrier_info_fmc_rst(0) and rst_sys_62m5_n;
tdc2_soft_rst_n <= carrier_info_fmc_rst(1) and rst_sys_62m5_n;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Tristates for mezzanine EEPROM
......@@ -848,21 +511,81 @@ begin
tdc2_scl_b <= '0' when (tdc2_scl_oen = '0') else 'Z';
tdc2_sda_b <= '0' when (tdc2_sda_oen = '0') else 'Z';
---------------------------------------------------------------------------------------------------
-- SVEC Board Wrapper --
---------------------------------------------------------------------------------------------------
cmp_xwrc_board_svec : xwrc_board_svec
generic map (
g_simulation => f_bool2int(g_simulation),
g_with_external_clock_input => FALSE,
g_dpram_initf => "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram",
g_fabric_iface => plain,
g_aux_clks => 2)
port map (
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_aux_i(0) => tdc1_125m_clk,
clk_aux_i(1) => tdc2_125m_clk,
areset_n_i => areset_n,
clk_sys_62m5_o => clk_sys_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n,
pll20dac_din_o => pll20dac_din_o,
pll20dac_sclk_o => pll20dac_sclk_o,
pll20dac_sync_n_o => pll20dac_sync_n_o,
pll25dac_din_o => pll25dac_din_o,
pll25dac_sclk_o => pll25dac_sclk_o,
pll25dac_sync_n_o => pll25dac_sync_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_det_i => sfp_mod_def0_i,
sfp_sda_i => sfp_sda_in,
sfp_sda_o => sfp_sda_out,
sfp_scl_i => sfp_scl_in,
sfp_scl_o => sfp_scl_out,
sfp_rate_select_o => sfp_rate_select_b,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
eeprom_sda_i => wrc_sda_in,
eeprom_sda_o => wrc_sda_out,
eeprom_scl_i => wrc_scl_in,
eeprom_scl_o => wrc_scl_out,
onewire_i => wrc_owr_data,
onewire_oen_o => wrc_owr_oe,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
wb_slave_o => cnx_master_in(c_SLAVE_WRCORE),
wb_slave_i => cnx_master_out(c_SLAVE_WRCORE),
tm_link_up_o => tm_link_up,
tm_dac_value_o => tm_dac_value,
tm_dac_wr_o => tm_dac_wr_p,
tm_clk_aux_lock_en_i=> tm_clk_aux_lock_en,
tm_clk_aux_locked_o => tm_clk_aux_locked,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai,
tm_cycles_o => tm_cycles,
pps_p_o => fp_gpio1_o,
led_link_o => wr_led_link,
led_act_o => wr_led_act);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
carrier_onewire_b <= '0' when wrc_owr_en(0) = '1' else 'Z';
wrc_owr_in(0) <= carrier_onewire_b;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The SFP is permanently enabled.
sfp_tx_disable_o <= '0';
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
-- Tristates for 1-wire thermometer
carrier_onewire_b <= '0' when wrc_owr_oe = '1' else 'Z';
wrc_owr_data <= carrier_onewire_b;
---------------------------------------------------------------------------------------------------
-- CSR WISHBONE CROSSBAR --
......@@ -884,8 +607,8 @@ begin
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
port map
(clk_sys_i => clk_62m5_sys,
rst_n_i => rst_n_sys,
(clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
......@@ -905,8 +628,8 @@ begin
g_REVISION_ID => c_SVEC_REVISION_ID,
g_PROGRAM_ID => c_SVEC_PROGRAM_ID)
port map
(clk_i => clk_62m5_sys,
rst_n_i => rst_n_sys,
(clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
vme_i.as_n => vme_as_n_i,
vme_i.rst_n => vme_rst_n_i,
vme_i.write_n => vme_write_n_i,
......@@ -932,36 +655,47 @@ begin
vme_o.data_oe_n => vme_data_oe_n_o,
vme_o.addr_dir => vme_addr_dir_int,
vme_o.addr_oe_n => vme_addr_oe_n_o,
wb_o => cnx_slave_in (c_MASTER_VME),
wb_i => cnx_slave_out(c_MASTER_VME)); --vme_wb_in);
wb_o => vme_wb_out,
wb_i => vme_wb_in);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
vme_berr_o <= not vme_berr_n;
vme_irq_o <= not vme_irq_n;
-- Shift address for byte addressing.
cnx_slave_in(c_MASTER_VME).cyc <= vme_wb_out.cyc;
cnx_slave_in(c_MASTER_VME).stb <= vme_wb_out.stb;
cnx_slave_in(c_MASTER_VME).adr <= vme_wb_out.adr(29 downto 0) & "00";
cnx_slave_in(c_MASTER_VME).sel <= vme_wb_out.sel;
cnx_slave_in(c_MASTER_VME).we <= vme_wb_out.we;
cnx_slave_in(c_MASTER_VME).dat <= vme_wb_out.dat;
-- Drive inject also IRQ to the WB interface.
vme_wb_in.ack <= cnx_slave_out(c_MASTER_VME).ack;
vme_wb_in.err <= cnx_slave_out(c_MASTER_VME).err;
vme_wb_in.rty <= cnx_slave_out(c_MASTER_VME).rty;
vme_wb_in.stall <= cnx_slave_out(c_MASTER_VME).stall;
vme_wb_in.dat <= cnx_slave_out(c_MASTER_VME).dat;
vme_wb_in.int <= irq_to_vmecore;
-- VME tri-state bufferes
vme_data_b <= vme_data_b_out when vme_data_dir_int = '1' else (others => 'Z');
vme_addr_b <= vme_addr_b_out when vme_addr_dir_int = '1' else (others => 'Z');
vme_lword_n_b <= vme_lword_n_b_out when vme_addr_dir_int = '1' else 'Z';
vme_addr_dir_o <= vme_addr_dir_int;
vme_data_dir_o <= vme_data_dir_int;
vme_berr_o <= not vme_berr_n;
vme_irq_o <= not vme_irq_n;
---------------------------------------------------------------------------------------------------
-- TDC BOARDS --
---------------------------------------------------------------------------------------------------
cmp_tdc_mezzanine_1: fmc_tdc_wrapper
generic map (
g_simulation => g_simulation,
g_with_direct_readout => false )
port map (
clk_sys_i => clk_62m5_sys,
rst_sys_n_i => rst_n_sys,
clk_sys_i => clk_sys_62m5,
rst_sys_n_i => rst_sys_62m5_n,
rst_n_a_i => tdc1_soft_rst_n,
pll_sclk_o => tdc1_pll_sclk_o,
pll_sdi_o => tdc1_pll_sdi_o,
......@@ -1013,7 +747,7 @@ begin
tm_link_up_i => tm_link_up,
tm_time_valid_i => tm_time_valid,
tm_cycles_i => tm_cycles,
tm_tai_i => tm_utc,
tm_tai_i => tm_tai,
tm_clk_aux_lock_en_o => tm_clk_aux_lock_en(0),
tm_clk_aux_locked_i => tm_clk_aux_locked(0),
tm_clk_dmtd_locked_i => '1',
......@@ -1039,8 +773,8 @@ begin
g_simulation => g_simulation,
g_with_direct_readout => false )
port map (
clk_sys_i => clk_62m5_sys,
rst_sys_n_i => rst_n_sys,
clk_sys_i => clk_sys_62m5,
rst_sys_n_i => rst_sys_62m5_n,
rst_n_a_i => tdc2_soft_rst_n,
pll_sclk_o => tdc2_pll_sclk_o,
pll_sdi_o => tdc2_pll_sdi_o,
......@@ -1092,7 +826,7 @@ begin
tm_link_up_i => tm_link_up,
tm_time_valid_i => tm_time_valid,
tm_cycles_i => tm_cycles,
tm_tai_i => tm_utc,
tm_tai_i => tm_tai,
tm_clk_aux_lock_en_o => tm_clk_aux_lock_en(1),
tm_clk_aux_locked_i => tm_clk_aux_locked(1),
tm_clk_dmtd_locked_i => '1',
......@@ -1123,8 +857,8 @@ begin
g_num_interrupts => 2,
g_init_vectors => c_VIC_VECTOR_TABLE)
port map
(clk_sys_i => clk_62m5_sys,
rst_n_i => rst_n_sys,
(clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_master_out(c_SLAVE_VIC),
slave_o => cnx_master_in(c_SLAVE_VIC),
irqs_i(0) => tdc1_irq,
......@@ -1138,8 +872,8 @@ begin
-- Also added software resets for the clks_rsts_manager units
cmp_carrier_info : carrier_info
port map
(rst_n_i => rst_n_sys,
clk_sys_i => clk_62m5_sys,
(rst_n_i => rst_sys_62m5_n,
clk_sys_i => clk_sys_62m5,
wb_adr_i => cnx_master_out(c_SLAVE_SVEC_INFO).adr(3 downto 2),
wb_dat_i => cnx_master_out(c_SLAVE_SVEC_INFO).dat,
wb_dat_o => cnx_master_in(c_SLAVE_SVEC_INFO).dat,
......@@ -1154,7 +888,9 @@ begin
carrier_info_carrier_type_i => c_CARRIER_TYPE,
carrier_info_stat_fmc_pres_i => tdc1_prsntm2c_n_i,
carrier_info_stat_p2l_pll_lck_i => '0',
carrier_info_stat_sys_pll_lck_i => sys_locked,
-- SVEC board wrapper releases rst_sys_62m5_n only when system clock pll is
-- locked. Therefore we report here '1' - pll locked
carrier_info_stat_sys_pll_lck_i => '1',
carrier_info_stat_ddr3_cal_done_i => '0',
carrier_info_stat_reserved_i(27 downto 1) => (others => '1'),
......@@ -1185,8 +921,8 @@ begin
g_CLK_FREQ => 62500000, -- in Hz
g_REFRESH_RATE => 250) -- in Hz
port map
(rst_n_i => rst_n_sys,
clk_i => clk_62m5_sys,
(rst_n_i => rst_sys_62m5_n,
clk_i => clk_sys_62m5,
led_intensity_i => "1100100", -- in %
led_state_i => led_state,
column_o => fp_led_column_o,
......@@ -1199,9 +935,9 @@ begin
-- fp led number : | 5 | 6 | 7 | 8 | 1 | 2 | 3 | 4 |
-- LED 1: White Rabbit act
led_state(7 downto 6) <= c_LED_RED when wrabbit_led_red = '1' else c_LED_OFF;
led_state(7 downto 6) <= c_LED_RED when wr_led_act = '1' else c_LED_OFF;
-- LED 2: White Rabbit link
led_state(5 downto 4) <= c_LED_GREEN when wrabbit_led_green = '1' else c_LED_OFF;
led_state(5 downto 4) <= c_LED_GREEN when wr_led_link = '1' else c_LED_OFF;
-- LED 3: TDC1 empty flag
led_state(3 downto 2) <= c_LED_GREEN when led_tdc1_ef = '1' else c_LED_OFF;
-- LED 4: TDC2 empty flag
......@@ -1220,8 +956,8 @@ begin
generic map
(g_width => 5000000)
port map
(clk_i => clk_62m5_sys,
rst_n_i => rst_n_sys,
(clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
pulse_i => cnx_slave_in(c_MASTER_VME).cyc,
extended_o => led_vme_access);
......@@ -1230,8 +966,8 @@ begin
generic map
(g_width => 5000000)
port map
(clk_i => clk_62m5_sys,
rst_n_i => rst_n_sys,
(clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
pulse_i => tdc1_ef,
extended_o => led_tdc1_ef);
-- -- -- -- -- -- --
......@@ -1242,8 +978,8 @@ begin
generic map
(g_width => 5000000)
port map
(clk_i => clk_62m5_sys,
rst_n_i => rst_n_sys,
(clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
pulse_i => tdc2_ef,
extended_o => led_tdc2_ef);
-- -- -- -- -- -- --
......
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