updated submodules

66d5ae61 · Evangelia Gousiou · f238ebb5 · 4c3ac537 · 66d5ae61 · 66d5ae61
Commit 66d5ae61 authored Jun 16, 2020 by Evangelia Gousiou
6 changed files
--- a/spec @ 4c3ac537
+++ b/spec @ 4c3ac537
-Subproject commit 44e9007a2953f91c686bcabf38b92d2f6ecfb217
+Subproject commit 4c3ac537b70fef0190d57f91844581f906959e27
--- a/hdl/syn/spec/syn_extra_steps.tcl
+++ b/hdl/syn/spec/syn_extra_steps.tcl
@@ -27,7 +27,7 @@ xilinx::project set "Register Balancing" "Yes"


 xilinx::project set "Placer Effort Level Map" "High"
-xilinx::project set "Placer Extra Effort Map" "Normal"
+xilinx::project set "Placer Extra Effort Map" "Continue on Impossible"
 xilinx::project set "Extra Effort (Highest PAR level only)" "Continue on Impossible"

 xilinx::project save

--- a/hdl/syn/spec/wr_spec_tdc.xise
+++ b/hdl/syn/spec/wr_spec_tdc.xise
--- a/hdl/syn/svec/wr_svec_tdc.xise
+++ b/hdl/syn/svec/wr_svec_tdc.xise
--- a/hdl/testbench/spec/buildinfo_pkg.vhd
+++ b/hdl/testbench/spec/buildinfo_pkg.vhd
-- Buildinfo for project main
--
-- This file was automatically generated; do not edit
-
-package buildinfo_pkg is
-  constant buildinfo : string :=
-       "buildinfo:1" & LF
-     & "module:main" & LF
-     & "commit:745e912cee76d4ee9e8c3fded1c9ee9b5e694cdd" & LF
-     & "syntool:modelsim" & LF
-     & "syndate:2020-04-24, 22:37 CEST" & LF
-     & "synauth:Tomasz Wlostowski" & LF;
-end buildinfo_pkg;
--- a/hdl/testbench/spec/wave.do
+++ b/hdl/testbench/spec/wave.do