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FMC TDC 1ns 5cha - Gateware
Commit 66dc31d3 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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added bit for identifying which tdc core is connected to which mezzanine (makes sense for svec)

parent fdef93de
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Showing with 27 additions and 9 deletions
hdl/rtl/fmc_tdc_core.vhd
View file @ 66dc31d3
......@@ -225,7 +225,9 @@ entity fmc_tdc_core is
channel_enable_o : out std_logic_vector(4 downto 0);
irq_threshold_o : out std_logic_vector(9 downto 0);
irq_timeout_o : out std_logic_vector(9 downto 0)
irq_timeout_o : out std_logic_vector(9 downto 0);
fmc_id_i : in std_logic
);
end fmc_tdc_core;
......@@ -301,7 +303,8 @@ begin
core_status(0) <= '1' when g_with_dma_readout else '0';
core_status(1) <= '1' when g_with_fifo_readout else '0';
core_status(31 downto 2) <= (others => '0');
core_status(2) <= fmc_id_i;
core_status(31 downto 3) <= (others => '0');
reg_control_block : entity work.reg_ctrl
generic map
......
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ 66dc31d3
......@@ -124,6 +124,8 @@ entity fmc_tdc_mezzanine is
clk_tdc_i : in std_logic; -- 125 MHz clock
rst_tdc_n_i : in std_logic; -- reset for 125 MHz logic
fmc_id_i : in std_logic;
acam_refclk_r_edge_p_i : in std_logic;
send_dac_word_p_o : out std_logic;
dac_word_o : out std_logic_vector(23 downto 0);
......@@ -390,6 +392,8 @@ begin
direct_timestamp_valid_o => direct_timestamp_valid_o,
direct_timestamp_o => direct_timestamp_o,
fmc_id_i => fmc_id_i,
irq_threshold_o => irq_threshold,
irq_timeout_o => irq_timeout,
channel_enable_o => channel_enable
......
hdl/rtl/fmc_tdc_wrapper.vhd
View file @ 66dc31d3
......@@ -142,6 +142,8 @@ entity fmc_tdc_wrapper is
rst_sys_n_i : in std_logic;
rst_n_a_i : in std_logic;
fmc_id_i : in std_logic;
-- Interface with the PLL AD9516 and DAC AD5662 on TDC mezzanine
pll_sclk_o : out std_logic; -- SPI clock
pll_sdi_o : out std_logic; -- data line for PLL and DAC
......@@ -414,7 +416,8 @@ begin
-- 125M clk and reset
clk_tdc_i => clk_125m_mezz,
rst_tdc_n_i => rst_125m_mezz_n,
-- FMC slot identification
fmc_id_i => fmc_id_i,
-- Wishbone
slave_i => cnx_master_out(c_slave_regs),
slave_o => cnx_master_in(c_slave_regs),
......
hdl/rtl/reg_ctrl.vhd
View file @ 66dc31d3
......@@ -543,7 +543,7 @@ begin
starting_utc when c_STARTING_UTC_ADR,
acam_inputs_en when c_ACAM_INPUTS_EN_ADR,
start_phase when c_START_PHASE_ADR,
one_hz_phase when c_ONE_HZ_PHASE_ADR,
x"C000FFEE" when c_ONE_HZ_PHASE_ADR, -- ref for test
irq_tstamp_threshold when c_IRQ_TSTAMP_THRESH_ADR,
irq_time_threshold when c_IRQ_TIME_THRESH_ADR,
x"00" & dac_word when c_DAC_WORD_ADR,
......
hdl/rtl/tdc_core_pkg.vhd
View file @ 66dc31d3
......@@ -336,8 +336,8 @@ package tdc_core_pkg is
-- corresponds to:
constant c_STARTING_UTC_ADR : std_logic_vector(7 downto 0) := x"20"; -- address 0x51080 of GN4124 BAR 0
constant c_ACAM_INPUTS_EN_ADR : std_logic_vector(7 downto 0) := x"21"; -- address 0x51084 of GN4124 BAR 0
constant c_FMC_ID_ADR : std_logic_vector(7 downto 0) := x"22"; -- address 0x51088 of GN4124 BAR 0
constant c_SPARE_ADR : std_logic_vector(7 downto 0) := x"23"; -- address 0x5108C of GN4124 BAR 0
constant c_START_PHASE_ADR : std_logic_vector(7 downto 0) := x"22"; -- address 0x51088 of GN4124 BAR 0
constant c_ONE_HZ_PHASE_ADR : std_logic_vector(7 downto 0) := x"23"; -- address 0x5108C of GN4124 BAR 0
constant c_IRQ_TSTAMP_THRESH_ADR: std_logic_vector(7 downto 0) := x"24"; -- address 0x51090 of GN4124 BAR 0
constant c_IRQ_TIME_THRESH_ADR : std_logic_vector(7 downto 0) := x"25"; -- address 0x51094 of GN4124 BAR 0
......@@ -436,7 +436,10 @@ package tdc_core_pkg is
clk_tdc_i : in std_logic; -- 125 MHz clock
rst_tdc_i : in std_logic; -- reset for 125 MHz logic
-- WISHBONE interface with the GN4124/VME_core (clk_sys)
-- Identification of the FMC core; '0' for SPEC, '0' and '1' for each of SVEC cores
fmc_id_i : in std_logic;
-- WISHBONE interface with the GN4124/VME_core (clk_sys)
-- for the core configuration | timestamps retrieval | core interrupts | 1Wire | I2C
slave_i: in t_wishbone_slave_in;
......@@ -515,6 +518,7 @@ package tdc_core_pkg is
rst_n_sys_i : in std_logic;
clk_tdc_i : in std_logic;
rst_tdc_i : in std_logic;
fmc_id_i : in std_logic;
acam_refclk_r_edge_p_i : in std_logic;
send_dac_word_p_o : out std_logic;
dac_word_o : out std_logic_vector(23 downto 0);
......@@ -887,6 +891,7 @@ package tdc_core_pkg is
clk_sys_i : in std_logic;
rst_sys_n_i : in std_logic;
rst_n_a_i : in std_logic;
fmc_id_i : in std_logic;
pll_sclk_o : out std_logic;
pll_sdi_o : out std_logic;
pll_cs_o : out std_logic;
......
hdl/rtl/tdc_ts_addsub.vhd
View file @ 66dc31d3
......@@ -44,6 +44,7 @@ use ieee.numeric_std.all;
use work.tdc_core_pkg.all;
-- adds q = a + b, b can be a NEGATIVE timestamp (i.e. a negative offset)
entity tdc_ts_addsub is
generic(
g_frac_range : integer := 4096;
......
hdl/rtl/tdc_ts_sub.vhd
View file @ 66dc31d3
......@@ -44,6 +44,7 @@ use ieee.numeric_std.all;
use work.tdc_core_pkg.all;
--subtracts q = b - a, both b and a are POSITIVE timestamps
entity tdc_ts_sub is
port(
......
hdl/testbench/spec/buildinfo_pkg.vhd
View file @ 66dc31d3
......@@ -6,8 +6,8 @@ package buildinfo_pkg is
constant buildinfo : string :=
"buildinfo:1" & LF
& "module:main" & LF
& "commit:7d68c05fc60844172732a01f54f436f71e7d76c6" & LF
& "commit:fdef93deaa461521b973a709efa4e9b9103592c5" & LF
& "syntool:modelsim" & LF
& "syndate:2019-09-26, 17:01 CEST" & LF
& "syndate:2019-09-30, 10:33 CEST" & LF
& "synauth:Evangelia Gousiou" & LF;
end buildinfo_pkg;
hdl/top/spec/wr_spec_tdc.vhd
View file @ 66dc31d3
......@@ -672,6 +672,7 @@ begin
clk_sys_i => clk_sys_62m5,
rst_sys_n_i => rst_sys_62m5_n,
rst_n_a_i => rst_sys_62m5_n, ------------ to be removed
fmc_id_i => '0', -- '0' for SPEC; '0' and '1' for each of the TDCs of SVEC
pll_sclk_o => fmc0_tdc_pll_sclk_o,
pll_sdi_o => fmc0_tdc_pll_sdi_o,
pll_cs_o => fmc0_tdc_pll_cs_o,
......
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