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FMC TDC 1ns 5cha - Gateware
Commits
6b2e87d4
Commit
6b2e87d4
authored
Aug 09, 2018
by
Tomasz Wlostowski
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spec: use FmcAdc's DMA EIC as an interrupt adapter between GN4124 core and the VIC
parent
52b43d93
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Showing
4 changed files
with
391 additions
and
9 deletions
+391
-9
Manifest.py
hdl/rtl/Manifest.py
+2
-1
dma_eic.vhd
hdl/rtl/dma_eic.vhd
+321
-0
dma_eic.wb
hdl/rtl/wbgen/dma_eic.wb
+21
-0
wr_spec_tdc.vhd
hdl/top/spec/wr_spec_tdc.vhd
+47
-8
No files found.
hdl/rtl/Manifest.py
View file @
6b2e87d4
...
...
@@ -30,6 +30,7 @@ files = [
"tdc_buffer_control_regs.vhd"
,
"tdc_buffer_control_regs_wbgen2_pkg.vhd"
,
"tdc_ts_sub.vhd"
,
"wbgen2_eic_nomask.vhd"
"wbgen2_eic_nomask.vhd"
,
"dma_eic.vhd"
];
hdl/rtl/dma_eic.vhd
0 → 100644
View file @
6b2e87d4
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for GN4124 DMA enhanced interrupt controller
---------------------------------------------------------------------------------------
-- File : ../rtl/dma_eic.vhd
-- Author : auto-generated by wbgen2 from dma_eic.wb
-- Created : Wed Dec 4 09:51:41 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dma_eic.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
wbgen2_pkg
.
all
;
entity
dma_eic
is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
wb_int_o
:
out
std_logic
;
irq_dma_done_i
:
in
std_logic
;
irq_dma_error_i
:
in
std_logic
);
end
dma_eic
;
architecture
syn
of
dma_eic
is
signal
eic_idr_int
:
std_logic_vector
(
1
downto
0
);
signal
eic_idr_write_int
:
std_logic
;
signal
eic_ier_int
:
std_logic_vector
(
1
downto
0
);
signal
eic_ier_write_int
:
std_logic
;
signal
eic_imr_int
:
std_logic_vector
(
1
downto
0
);
signal
eic_isr_clear_int
:
std_logic_vector
(
1
downto
0
);
signal
eic_isr_status_int
:
std_logic_vector
(
1
downto
0
);
signal
eic_irq_ack_int
:
std_logic_vector
(
1
downto
0
);
signal
eic_isr_write_int
:
std_logic
;
signal
irq_inputs_vector_int
:
std_logic_vector
(
1
downto
0
);
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
bwsel_reg
:
std_logic_vector
(
3
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
1
downto
0
);
signal
ack_in_progress
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
rd_int
:
std_logic
;
signal
allones
:
std_logic_vector
(
31
downto
0
);
signal
allzeros
:
std_logic_vector
(
31
downto
0
);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg
<=
wb_dat_i
;
bwsel_reg
<=
wb_sel_i
;
rd_int
<=
wb_cyc_i
and
(
wb_stb_i
and
(
not
wb_we_i
));
wr_int
<=
wb_cyc_i
and
(
wb_stb_i
and
wb_we_i
);
allones
<=
(
others
=>
'1'
);
allzeros
<=
(
others
=>
'0'
);
--
-- Main register bank access process.
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
ack_sreg
<=
"0000000000"
;
ack_in_progress
<=
'0'
;
rddata_reg
<=
"00000000000000000000000000000000"
;
eic_idr_write_int
<=
'0'
;
eic_ier_write_int
<=
'0'
;
eic_isr_write_int
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
-- advance the ACK generator shift register
ack_sreg
(
8
downto
0
)
<=
ack_sreg
(
9
downto
1
);
ack_sreg
(
9
)
<=
'0'
;
if
(
ack_in_progress
=
'1'
)
then
if
(
ack_sreg
(
0
)
=
'1'
)
then
eic_idr_write_int
<=
'0'
;
eic_ier_write_int
<=
'0'
;
eic_isr_write_int
<=
'0'
;
ack_in_progress
<=
'0'
;
else
end
if
;
else
if
((
wb_cyc_i
=
'1'
)
and
(
wb_stb_i
=
'1'
))
then
case
rwaddr_reg
(
1
downto
0
)
is
when
"00"
=>
if
(
wb_we_i
=
'1'
)
then
eic_idr_write_int
<=
'1'
;
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"01"
=>
if
(
wb_we_i
=
'1'
)
then
eic_ier_write_int
<=
'1'
;
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"10"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
1
downto
0
)
<=
eic_imr_int
(
1
downto
0
);
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"11"
=>
if
(
wb_we_i
=
'1'
)
then
eic_isr_write_int
<=
'1'
;
end
if
;
rddata_reg
(
1
downto
0
)
<=
eic_isr_status_int
(
1
downto
0
);
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
others
=>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
end
case
;
end
if
;
end
if
;
end
if
;
end
process
;
-- Drive the data output bus
wb_dat_o
<=
rddata_reg
;
-- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int
(
1
downto
0
)
<=
wrdata_reg
(
1
downto
0
);
-- extra code for reg/fifo/mem: Interrupt enable register
eic_ier_int
(
1
downto
0
)
<=
wrdata_reg
(
1
downto
0
);
-- extra code for reg/fifo/mem: Interrupt status register
eic_isr_clear_int
(
1
downto
0
)
<=
wrdata_reg
(
1
downto
0
);
-- extra code for reg/fifo/mem: IRQ_CONTROLLER
eic_irq_controller_inst
:
entity
work
.
wbgen2_eic_nomask
generic
map
(
g_num_interrupts
=>
2
,
g_irq00_mode
=>
0
,
g_irq01_mode
=>
0
,
g_irq02_mode
=>
0
,
g_irq03_mode
=>
0
,
g_irq04_mode
=>
0
,
g_irq05_mode
=>
0
,
g_irq06_mode
=>
0
,
g_irq07_mode
=>
0
,
g_irq08_mode
=>
0
,
g_irq09_mode
=>
0
,
g_irq0a_mode
=>
0
,
g_irq0b_mode
=>
0
,
g_irq0c_mode
=>
0
,
g_irq0d_mode
=>
0
,
g_irq0e_mode
=>
0
,
g_irq0f_mode
=>
0
,
g_irq10_mode
=>
0
,
g_irq11_mode
=>
0
,
g_irq12_mode
=>
0
,
g_irq13_mode
=>
0
,
g_irq14_mode
=>
0
,
g_irq15_mode
=>
0
,
g_irq16_mode
=>
0
,
g_irq17_mode
=>
0
,
g_irq18_mode
=>
0
,
g_irq19_mode
=>
0
,
g_irq1a_mode
=>
0
,
g_irq1b_mode
=>
0
,
g_irq1c_mode
=>
0
,
g_irq1d_mode
=>
0
,
g_irq1e_mode
=>
0
,
g_irq1f_mode
=>
0
)
port
map
(
clk_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_i
,
irq_i
=>
irq_inputs_vector_int
,
irq_ack_o
=>
eic_irq_ack_int
,
reg_imr_o
=>
eic_imr_int
,
reg_ier_i
=>
eic_ier_int
,
reg_ier_wr_stb_i
=>
eic_ier_write_int
,
reg_idr_i
=>
eic_idr_int
,
reg_idr_wr_stb_i
=>
eic_idr_write_int
,
reg_isr_o
=>
eic_isr_status_int
,
reg_isr_i
=>
eic_isr_clear_int
,
reg_isr_wr_stb_i
=>
eic_isr_write_int
,
wb_irq_o
=>
wb_int_o
);
irq_inputs_vector_int
(
0
)
<=
irq_dma_done_i
;
irq_inputs_vector_int
(
1
)
<=
irq_dma_error_i
;
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o
<=
ack_sreg
(
0
);
end
syn
;
hdl/rtl/wbgen/dma_eic.wb
0 → 100644
View file @
6b2e87d4
peripheral {
name = "GN4124 DMA enhanced interrupt controller";
description = "Enhanced interrrupt controller for GN4124 DMA.";
hdl_entity = "dma_eic";
prefix = "dma_eic";
irq {
name = "DMA done interrupt";
description = "DMA done interrupt line (rising edge sensitive).";
prefix = "dma_done";
trigger = EDGE_RISING;
};
irq {
name = "DMA error interrupt";
description = "DMA error interrupt line (rising edge sensitive).";
prefix = "dma_error";
trigger = EDGE_RISING;
};
};
hdl/top/spec/wr_spec_tdc.vhd
View file @
6b2e87d4
...
...
@@ -442,12 +442,13 @@ architecture rtl of wr_spec_tdc is
-- Note: All address in sdb and crossbar are BYTE addresses!
-- Master ports on the wishbone crossbar
constant
c_NUM_WB_MASTERS
:
integer
:
=
5
;
constant
c_NUM_WB_MASTERS
:
integer
:
=
6
;
constant
c_WB_SLAVE_SPEC_INFO
:
integer
:
=
0
;
-- Info on SPEC control and status registers
constant
c_WB_SLAVE_VIC
:
integer
:
=
1
;
-- Interrupt controller
constant
c_WB_SLAVE_TDC
:
integer
:
=
2
;
-- TDC core configuration
constant
c_WB_SLAVE_DMA
:
integer
:
=
3
;
constant
c_WB_SLAVE_WRC
:
integer
:
=
4
;
-- White Rabbit PTP core
constant
c_WB_SLAVE_DMA_EIC
:
integer
:
=
4
;
constant
c_WB_SLAVE_WRC
:
integer
:
=
5
;
-- White Rabbit PTP core
-- SDB header address
constant
c_SDB_ADDRESS
:
t_wishbone_address
:
=
x"00000000"
;
...
...
@@ -475,15 +476,32 @@ architecture rtl of wr_spec_tdc is
date
=>
x"20121116"
,
name
=>
"WB-DMA.Control "
)));
constant
c_wb_dma_eic_sdb
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"01"
,
wbd_endian
=>
c_sdb_endian_big
,
wbd_width
=>
x"4"
,
-- 32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"000000000000003F"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"12000661"
,
version
=>
x"00000001"
,
date
=>
x"20121116"
,
name
=>
"WB-DMA.InterruptCtr"
)));
constant
c_INTERCONNECT_LAYOUT
:
t_sdb_record_array
(
6
downto
0
)
:
=
constant
c_INTERCONNECT_LAYOUT
:
t_sdb_record_array
(
7
downto
0
)
:
=
(
0
=>
f_sdb_embed_device
(
c_SPEC_INFO_SDB_DEVICE
,
x"00020000"
),
1
=>
f_sdb_embed_device
(
c_xwb_vic_sdb
,
x"00030000"
),
-- c_xwb_vic_sdb described in the wishbone_pkg
2
=>
f_sdb_embed_bridge
(
c_FMC_TDC_SDB_BRIDGE
,
x"00040000"
),
3
=>
f_sdb_embed_device
(
c_wb_dma_ctrl_sdb
,
x"00050000"
),
4
=>
f_sdb_embed_bridge
(
c_WRCORE_BRIDGE_SDB
,
x"00080000"
),
5
=>
f_sdb_embed_repo_url
(
c_SDB_REPO_URL
),
6
=>
f_sdb_embed_synthesis
(
c_sdb_synthesis_info
));
4
=>
f_sdb_embed_device
(
c_wb_dma_eic_sdb
,
x"00060000"
),
5
=>
f_sdb_embed_bridge
(
c_WRCORE_BRIDGE_SDB
,
x"00080000"
),
6
=>
f_sdb_embed_repo_url
(
c_SDB_REPO_URL
),
7
=>
f_sdb_embed_synthesis
(
c_sdb_synthesis_info
));
---------------------------------------------------------------------------------------------------
...
...
@@ -559,7 +577,7 @@ architecture rtl of wr_spec_tdc is
signal
ddr3_calib_done
:
std_logic
;
signal
dma_irq
:
std_logic_vector
(
1
downto
0
);
signal
ddr_wr_fifo_empty
:
std_logic
;
signal
dma_eic_irq
:
std_logic
;
component
chipscope_icon
port
(
...
...
@@ -898,12 +916,33 @@ begin
slave_i
=>
cnx_master_out
(
c_WB_SLAVE_VIC
),
slave_o
=>
cnx_master_in
(
c_WB_SLAVE_VIC
),
irqs_i
(
0
)
=>
tdc0_irq
,
irqs_i
(
1
)
=>
dma_
irq
(
0
)
,
irqs_i
(
1
)
=>
dma_
eic_irq
,
irq_master_o
=>
irq_to_gn4124
);
gn_gpio
(
0
)
<=
irq_to_gn4124
;
gn_gpio
(
1
)
<=
irq_to_gn4124
;
------------------------------------------------------------------------------
-- GN4124 DMA interrupt controller
------------------------------------------------------------------------------
cmp_dma_eic
:
entity
work
.
dma_eic
port
map
(
rst_n_i
=>
rst_sys_62m5_n
,
clk_sys_i
=>
clk_sys_62m5
,
wb_adr_i
=>
cnx_master_out
(
c_WB_SLAVE_DMA_EIC
)
.
adr
(
3
downto
2
),
-- cnx_master_out.adr is byte address
wb_dat_i
=>
cnx_master_out
(
c_WB_SLAVE_DMA_EIC
)
.
dat
,
wb_dat_o
=>
cnx_master_in
(
c_WB_SLAVE_DMA_EIC
)
.
dat
,
wb_cyc_i
=>
cnx_master_out
(
c_WB_SLAVE_DMA_EIC
)
.
cyc
,
wb_sel_i
=>
cnx_master_out
(
c_WB_SLAVE_DMA_EIC
)
.
sel
,
wb_stb_i
=>
cnx_master_out
(
c_WB_SLAVE_DMA_EIC
)
.
stb
,
wb_we_i
=>
cnx_master_out
(
c_WB_SLAVE_DMA_EIC
)
.
we
,
wb_ack_o
=>
cnx_master_in
(
c_WB_SLAVE_DMA_EIC
)
.
ack
,
wb_stall_o
=>
cnx_master_in
(
c_WB_SLAVE_DMA_EIC
)
.
stall
,
wb_int_o
=>
dma_eic_irq
,
irq_dma_done_i
=>
dma_irq
(
0
),
irq_dma_error_i
=>
dma_irq
(
1
)
);
---------------------------------------------------------------------------------------------------
-- Carrier CSR information --
---------------------------------------------------------------------------------------------------
...
...
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