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FMC TDC 1ns 5cha - Gateware
Commit 745fe32b authored by egousiou's avatar egousiou
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spec: removed dma; timestamps to be retrieved through wishbone (not stable yet;… 

spec: removed dma; timestamps to be retrieved through wishbone (not stable yet; code needs bit of cleaning!)

git-svn-id: http://svn.ohwr.org/fmc-tdc@147 85dfdc96-de2c-444c-878d-45b388be74a9
parent ff2c1b3a
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hdl/rtl/clks_rsts_manager.vhd
View file @ 745fe32b
......@@ -231,8 +231,8 @@ architecture rtl of clks_rsts_manager is
signal tdc_clk_buf : std_logic;
signal sclk, tdc_clk, acam_refclk : std_logic;
-- Resets
signal internal_rst, interf_rst, rst, vme_rst : std_logic;
signal rst_cnt, vme_rst_cnt : unsigned(7 downto 0) := "00000000";
signal rst : std_logic;
signal rst_cnt : unsigned(7 downto 0) := "00000000";
--=================================================================================================
......
hdl/rtl/data_formatting.vhd
View file @ 745fe32b
......@@ -136,7 +136,7 @@ architecture rtl of data_formatting is
signal acam_start_nb : std_logic_vector(7 downto 0);
-- timestamp manipulations
signal un_acam_start_nb, un_clk_i_cycles_offset : unsigned(31 downto 0);
signal un_roll_over, un_nb_of_retrig, un_retrig_nb_offset : unsigned(31 downto 0);
signal un_nb_of_retrig, un_retrig_nb_offset : unsigned(31 downto 0);
signal un_nb_of_cycles, un_retrig_from_roll_over : unsigned(31 downto 0);
signal acam_start_nb_32 : std_logic_vector(31 downto 0);
-- final timestamp fields
......@@ -148,8 +148,6 @@ architecture rtl of data_formatting is
signal dacapo_counter : unsigned(19 downto 0);
signal wr_index : unsigned(7 downto 0);
-- coarse time calculations
signal tstamp_on_first_retrig_case1 : std_logic;
signal tstamp_on_first_retrig_case2 : std_logic;
signal un_previous_clk_i_cycles_offset : unsigned(31 downto 0);
signal un_previous_retrig_nb_offset : unsigned(31 downto 0);
signal un_previous_roll_over_nb : unsigned(31 downto 0);
......
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ 745fe32b
......@@ -183,11 +183,12 @@ architecture rtl of fmc_tdc_mezzanine is
---------------------------------------------------------------------------------------------------
-- Note: All address in sdb and crossbar are BYTE addresses!
-- Master ports on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 4;
constant c_NUM_WB_MASTERS : integer := 5;
constant c_WB_SLAVE_TDC_CORE_CONFIG : integer := 0; -- TDC core configuration registers
constant c_WB_SLAVE_TDC_ONEWIRE : integer := 1; -- TDC mezzanine board UnidueID&Thermometer 1-wire
constant c_WB_SLAVE_TDC_EIC : integer := 2; -- TDC interrupts
constant c_WB_SLAVE_TDC_SYS_I2C : integer := 3; -- TDC mezzanine board system EEPROM I2C
constant c_WB_SLAVE_TSTAMP_MEM : integer := 4; -- Access to TDC core timestamps memory
-- Slave port on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 1;
......@@ -196,11 +197,12 @@ architecture rtl of fmc_tdc_mezzanine is
-- sdb header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- WISHBONE crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(3 downto 0) :=
(0 => f_sdb_embed_device(c_TDC_CONFIG_SDB_DEVICE, x"00001000"),
1 => f_sdb_embed_device(c_ONEWIRE_SDB_DEVICE, x"00001100"),
2 => f_sdb_embed_device(c_TDC_EIC_DEVICE, x"00001200"),
3 => f_sdb_embed_device(c_I2C_SDB_DEVICE, x"00001300"));
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(4 downto 0) :=
(0 => f_sdb_embed_device(c_TDC_CONFIG_SDB_DEVICE, x"00010000"),
1 => f_sdb_embed_device(c_ONEWIRE_SDB_DEVICE, x"00011000"),
2 => f_sdb_embed_device(c_TDC_EIC_DEVICE, x"00012000"),
3 => f_sdb_embed_device(c_I2C_SDB_DEVICE, x"00013000"),
4 => f_sdb_embed_device(c_TDC_MEM_SDB_DEVICE, x"00014000"));
---------------------------------------------------------------------------------------------------
......@@ -217,7 +219,6 @@ architecture rtl of fmc_tdc_mezzanine is
-- WISHBONE addresses
signal tdc_core_wb_adr : std_logic_vector(31 downto 0);
signal tdc_mem_wb_adr : std_logic_vector(31 downto 0);
signal dummy_core_wb_adr : std_logic_vector(31 downto 0);
-- 1-wire
signal mezz_owr_en, mezz_owr_i : std_logic_vector(0 downto 0);
-- I2C
......@@ -339,19 +340,21 @@ begin
tdc_config_wb_dat_o => cnx_master_in(c_WB_SLAVE_TDC_CORE_CONFIG).dat,
tdc_config_wb_ack_o => cnx_master_in(c_WB_SLAVE_TDC_CORE_CONFIG).ack,
-- WISHBONE for timestamps transfer
tdc_mem_wb_adr_i => wb_tdc_mem_adr_i,
tdc_mem_wb_dat_i => wb_tdc_mem_dat_i,
tdc_mem_wb_stb_i => wb_tdc_mem_stb_i,
tdc_mem_wb_we_i => wb_tdc_mem_we_i,
tdc_mem_wb_cyc_i => wb_tdc_mem_cyc_i,
tdc_mem_wb_ack_o => wb_tdc_mem_ack_o,
tdc_mem_wb_dat_o => wb_tdc_mem_dat_o,
tdc_mem_wb_stall_o => wb_tdc_mem_stall_o);
tdc_mem_wb_adr_i => tdc_mem_wb_adr,--wb_tdc_mem_adr_i,
tdc_mem_wb_dat_i => cnx_master_out(c_WB_SLAVE_TSTAMP_MEM).dat,--wb_tdc_mem_dat_i,
tdc_mem_wb_stb_i => cnx_master_out(c_WB_SLAVE_TSTAMP_MEM).stb,--wb_tdc_mem_stb_i,
tdc_mem_wb_we_i => cnx_master_out(c_WB_SLAVE_TSTAMP_MEM).we,--wb_tdc_mem_we_i,
tdc_mem_wb_cyc_i => cnx_master_out(c_WB_SLAVE_TSTAMP_MEM).cyc,--wb_tdc_mem_cyc_i,
tdc_mem_wb_ack_o => cnx_master_in(c_WB_SLAVE_TSTAMP_MEM).ack,--wb_tdc_mem_ack_o,
tdc_mem_wb_dat_o => cnx_master_in(c_WB_SLAVE_TSTAMP_MEM).dat,--wb_tdc_mem_dat_o,
tdc_mem_wb_stall_o => cnx_master_in(c_WB_SLAVE_TSTAMP_MEM).stall);--wb_tdc_mem_stall_o);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Convert byte address into word address
tdc_core_wb_adr <= "00" & cnx_master_out(c_WB_SLAVE_TDC_CORE_CONFIG).adr(31 downto 2);
tdc_mem_wb_adr <= "00" & cnx_master_out(c_WB_SLAVE_TSTAMP_MEM).adr(31 downto 2);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_TDC_CORE_CONFIG).err <= '0';
......@@ -359,6 +362,10 @@ begin
cnx_master_in(c_WB_SLAVE_TDC_CORE_CONFIG).stall <= '0';
cnx_master_in(c_WB_SLAVE_TDC_CORE_CONFIG).int <= '0';
wb_tdc_mem_ack_o <= '0';
wb_tdc_mem_dat_o <= (others => '0');
wb_tdc_mem_stall_o <= '0';
---------------------------------------------------------------------------------------------------
-- TDC Mezzanine Board EEPROM I2C --
......
hdl/syn/spec/syn_tdc.edf
View file @ 745fe32b
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hdl/syn/spec/tdc.bin
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hdl/syn/spec/tdc.bit
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hdl/syn/spec/tdc_par_script.tcl
View file @ 745fe32b
......@@ -5,4 +5,4 @@ trce -v 32 -u par_tdc.ncd syn_tdc.pcf -o timing_report
#bitgen -w par_tdc.ncd tdc
bitgen -w -g Binary:Yes par_tdc.ncd tdc
ngdbuild -uc synplicity.ucf syn_tdc.edf;map -detail -w -timing -ol high syn_tdc.ngd;par -w -ol high syn_tdc.ncd par_tdc.ncd syn_tdc.pcf;bitgen -w -g Binary:Yes par_tdc.ncd tdc
\ No newline at end of file
ngdbuild -uc synplicity.ucf syn_tdc.edf;map -detail -w -timing -ol -pr b high syn_tdc.ngd;par -w -ol high syn_tdc.ncd par_tdc.ncd syn_tdc.pcf;bitgen -w -g Binary:Yes par_tdc.ncd tdc
hdl/top/spec/tdc_core_pkg.vhd
View file @ 745fe32b
......@@ -237,6 +237,22 @@ package tdc_core_pkg is
date => x"20130429",
name => "WB-TDC-Core-Config ")));
constant c_TDC_MEM_SDB_DEVICE : t_sdb_device :=
(abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component =>
(addr_first => x"0000000000000000",
addr_last => x"0000000000000FFF",
product =>
(vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000601",
version => x"00000001",
date => x"20121116",
name => "WB-TDC-MEM ")));
---------------------------------------------------------------------------------------------------
-- Constants regarding 1 Hz pulse generation --
......
hdl/top/spec/top_tdc.vhd
View file @ 745fe32b
......@@ -104,8 +104,8 @@ entity top_tdc is
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
irq_p_o : inout std_logic; -- Interrupt request pulse to GN4124 GPIO 8
irq_aux_p_o : inout std_logic; -- Interrupt request pulse to GN4124 GPIO 9, aux signal
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO 8
irq_aux_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO 9, aux signal
-- Signals for the interface with the PLL AD9516 and DAC AD5662 on TDC mezzanine
pll_sclk_o : out std_logic; -- SPI clock
......@@ -200,15 +200,15 @@ architecture rtl of top_tdc is
constant c_SLAVE_DMA_EIC : integer := 4; -- DMA interrupt controller
constant c_SLAVE_TDC : integer := 5; -- TDC core configuration
constant c_FMC_TDC_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001FFF", x"00000000");
constant c_FMC_TDC_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0001FFFF", x"00000000");
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(8 downto 0) :=
(0 => f_sdb_embed_device (c_DMA_SDB_DEVICE, x"00001000"),
1 => f_sdb_embed_device (c_ONEWIRE_SDB_DEVICE, x"00001100"),
2 => f_sdb_embed_device (c_SPEC_CSR_SDB_DEVICE,x"00001200"),
3 => f_sdb_embed_device (c_xwb_vic_sdb, x"00001300"), -- c_xwb_vic_sdb described in the wishbone_pkg
4 => f_sdb_embed_device (c_DMA_EIC_SDB, x"00001400"),
5 => f_sdb_embed_bridge (c_FMC_TDC_SDB_BRIDGE, x"00002000"),
(0 => f_sdb_embed_device (c_DMA_SDB_DEVICE, x"00010000"),
1 => f_sdb_embed_device (c_ONEWIRE_SDB_DEVICE, x"00020000"),
2 => f_sdb_embed_device (c_SPEC_CSR_SDB_DEVICE,x"00030000"),
3 => f_sdb_embed_device (c_xwb_vic_sdb, x"00040000"), -- c_xwb_vic_sdb described in the wishbone_pkg
4 => f_sdb_embed_device (c_DMA_EIC_SDB, x"00050000"),
5 => f_sdb_embed_bridge (c_FMC_TDC_SDB_BRIDGE, x"00060000"),
6 => f_sdb_embed_repo_url (c_SDB_REPO_URL),
7 => f_sdb_embed_synthesis (c_SDB_SYNTHESIS),
8 => f_sdb_embed_integration(c_SDB_INTEGRATION));
......@@ -216,13 +216,13 @@ architecture rtl of top_tdc is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- VIC default vector setting
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 1) :=
(0 => x"00003200",
(0 => x"00002000",
1 => x"00001400");
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- clocks and resets
signal clk, general_rst_n, general_rst, clk_125m : std_logic;
signal clk_20m_vcxo_buf, clk_20m_vcxo, acam_refclk_r_edge_p : std_logic;
signal general_rst_n, general_rst, clk_125m : std_logic;
signal clk_20m_vcxo_buf, acam_refclk_r_edge_p : std_logic;
-- DAC configuration
signal send_dac_word_p : std_logic;
signal dac_word : std_logic_vector(23 downto 0);
......@@ -242,27 +242,12 @@ architecture rtl of top_tdc is
signal irq_to_gn4124 : std_logic;
signal irq_acam_err_p, irq_tstamp_p, irq_time_p : std_logic;
signal dma_irq : std_logic_vector(1 downto 0);
signal irq_sources : std_logic_vector(g_width-1 downto 0);
-- Carrier CSR info
signal gn4124_status : std_logic_vector(31 downto 0);
signal mezz_pll_status : std_logic_vector(11 downto 0);
-- Mezzanine 1-wire
signal mezz_owr_pwren, mezz_owr_en, mezz_owr_i : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
-- Carrier 1-wire
signal carrier_owr_en, carrier_owr_i : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
-- Mezzanine system I2C for EEPROM
signal sys_scl_in, sys_scl_out, sys_scl_oe_n : std_logic;
signal sys_sda_in, sys_sda_out, sys_sda_oe_n : std_logic;
signal led_clk_20m_divider : unsigned(22 downto 0);
signal led_clk_20m_aux : std_logic_vector(7 downto 0) :="01111111";
signal led_clk_20m : std_logic;
signal led_clk_125m_divider : unsigned(22 downto 0);
signal led_clk_125m_aux : std_logic_vector(7 downto 0):="01111111";
signal led_clk_125m : std_logic;
signal led_clk_125m2_divider : unsigned(22 downto 0);
signal led_clk_125m2_aux : std_logic_vector(7 downto 0);
signal led_clk_125m2 : std_logic;
signal dma_eic_irq, fmc_eic_irq : std_logic;
......
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