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FMC TDC 1ns 5cha - Gateware
Commit 757b8fff authored by penacoba's avatar penacoba
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Improved models for testbench 


git-svn-id: http://svn.ohwr.org/fmc-tdc@52 85dfdc96-de2c-444c-878d-45b388be74a9
parent 320d75f0
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Showing with 22 additions and 12 deletions
hdl/spec/src/test_bench/acam_data_model.vhd
View file @ 757b8fff
...@@ -152,8 +152,8 @@ begin ...@@ -152,8 +152,8 @@ begin
interface_fifo1: acam_fifo_model interface_fifo1: acam_fifo_model
generic map( generic map(
size => 256, size => 256,
full_threshold => 20, full_threshold => 10,
empty_threshold => 10 empty_threshold => 1
) )
port map( port map(
data_input => timestamp_for_fifo1, data_input => timestamp_for_fifo1,
...@@ -167,8 +167,8 @@ begin ...@@ -167,8 +167,8 @@ begin
interface_fifo2: acam_fifo_model interface_fifo2: acam_fifo_model
generic map( generic map(
size => 256, size => 256,
full_threshold => 20, full_threshold => 10,
empty_threshold => 10 empty_threshold => 1
) )
port map( port map(
data_input => timestamp_for_fifo2, data_input => timestamp_for_fifo2,
......
hdl/spec/src/test_bench/acam_fifo_model.vhd
View file @ 757b8fff
...@@ -31,6 +31,8 @@ end acam_fifo_model; ...@@ -31,6 +31,8 @@ end acam_fifo_model;
architecture behavioral of acam_fifo_model is architecture behavioral of acam_fifo_model is
constant ts_ef : time:= 11800 ps; -- maximum empty flag set time
subtype index is natural range size-1 downto 0; subtype index is natural range size-1 downto 0;
subtype memory_cell is std_logic_vector(27 downto 0); subtype memory_cell is std_logic_vector(27 downto 0);
type memory_block is array (natural range size-1 downto 0) of memory_cell; type memory_block is array (natural range size-1 downto 0) of memory_cell;
...@@ -59,15 +61,22 @@ begin ...@@ -59,15 +61,22 @@ begin
begin begin
if rising_edge(rd_fifo) then if rising_edge(rd_fifo) then
data_output <= fifo(rd_pointer); data_output <= fifo(rd_pointer);
end if;
if falling_edge(rd_fifo) then
if rd_pointer = size-1 then if rd_pointer = size-1 then
rd_pointer <= 0; rd_pointer <= 0 after ts_ef;
else else
rd_pointer <= rd_pointer + 1; rd_pointer <= rd_pointer + 1 after ts_ef;
end if; end if;
end if; end if;
-- if falling_edge(rd_fifo) then
-- if rd_pointer = size-1 then
-- rd_pointer <= 0;
-- else
-- rd_pointer <= rd_pointer + 1;
-- end if;
-- end if;
end process; end process;
flags: process(level) flags: process(level)
......
hdl/spec/src/test_bench/gnum_model/cmd_router.vhd
View file @ 757b8fff
...@@ -68,7 +68,7 @@ end component; -- cmd_router1 ...@@ -68,7 +68,7 @@ end component; -- cmd_router1
type boolean_vector is array (natural range <>) of boolean; type boolean_vector is array (natural range <>) of boolean;
constant MAX_FILES : integer := 10; constant MAX_FILES : integer := 10;
constant FILENAMES : FILE_ARRAY(0 to MAX_FILES-1) := (others=>"data_vectors/acam_test_cmd0.vec"); constant FILENAMES : FILE_ARRAY(0 to MAX_FILES-1) := (others=>"data_vectors/atdc_test_cmd0.vec");
-- , "data_vectors/acam_test_cmd1.vec"); -- , "data_vectors/acam_test_cmd1.vec");
-- "data_vectors/acam_test_cmd2.vec", "data_vectors/acam_test_cmd3.vec", -- "data_vectors/acam_test_cmd2.vec", "data_vectors/acam_test_cmd3.vec",
-- "data_vectors/acam_test_cmd4.vec", "data_vectors/acam_test_cmd5.vec", -- "data_vectors/acam_test_cmd4.vec", "data_vectors/acam_test_cmd5.vec",
......
hdl/spec/src/test_bench/tb_tdc.vhd
View file @ 757b8fff
...@@ -271,7 +271,7 @@ constant spec_clk_period : time:= 50 ns; ...@@ -271,7 +271,7 @@ constant spec_clk_period : time:= 50 ns;
-- Number of Models receiving commands -- Number of Models receiving commands
constant N_BFM : integer := 1; -- 0 : GN412X_BFM in Model Mode constant N_BFM : integer := 1; -- 0 : GN412X_BFM in Model Mode
-- -- 1 : GN412X_BFM in DUT mode -- -- 1 : GN412X_BFM in DUT mode
-- Number of files to feed BFMs -- Number of files to feed BFMs
constant N_FILES : integer := 1; constant N_FILES : integer := 1;
-- --
...@@ -320,6 +320,7 @@ signal tstop2 : std_logic; ...@@ -320,6 +320,7 @@ signal tstop2 : std_logic;
signal tstop3 : std_logic; signal tstop3 : std_logic;
signal tstop4 : std_logic; signal tstop4 : std_logic;
signal tstop5 : std_logic; signal tstop5 : std_logic;
signal dummy_tstop5 : std_logic;
signal tdc_in_fpga_5 : std_logic; signal tdc_in_fpga_5 : std_logic;
...@@ -482,7 +483,7 @@ begin ...@@ -482,7 +483,7 @@ begin
tstop2_i => tstop2, tstop2_i => tstop2,
tstop3_i => tstop3, tstop3_i => tstop3,
tstop4_i => tstop4, tstop4_i => tstop4,
tstop5_i => tstop5, tstop5_i => dummy_tstop5,
startdis_i => start_dis_o, startdis_i => start_dis_o,
stopdis_i => stop_dis_o, stopdis_i => stop_dis_o,
......
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